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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
commit e76462eeb7
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1
sdk/include/app_version.h Normal file
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#define APP_VERSION 0

35
sdk/include/basic_include.h Normal file
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#ifndef _HUGEIC_BASIC_INCLUDE_H_
#define _HUGEIC_BASIC_INCLUDE_H_
#include "typesdef.h"
#include "list.h"
#include "dev.h"
#include "devid.h"
#include "errno.h"
#include "osal/atomic.h"
#include "osal/ffs.h"
#include "osal/irq.h"
#include "osal/msgqueue.h"
#include "osal/mutex.h"
#include "osal/semaphore.h"
#include "osal/sleep.h"
#include "osal/string.h"
#include "osal/task.h"
#include "osal/timer.h"
#include "osal/time.h"
#include "osal/work.h"
#include "osal/event.h"
#include "hal/gpio.h"
#include "hal/dma.h"
#include "hal/crc.h"
#include "hal/uart.h"
#include "lib/common/common.h"
#include "lib/common/sysevt.h"
#include "lib/common/rbuffer.h"
#include "lib/heap/sysheap.h"
#include "lib/syscfg/syscfg.h"
#endif

140
sdk/include/chip/arch/csky/byteshift.h Normal file
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#ifndef _LINUX_UNALIGNED_BYTESHIFT_H
#define _LINUX_UNALIGNED_BYTESHIFT_H
#ifdef __cplusplus
extern "C" {
#endif
static inline uint16 __get_unaligned_le16(const uint8 *p)
{
return p[0] | p[1] << 8;
}
static inline uint32 __get_unaligned_le32(const uint8 *p)
{
return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
}
static inline uint64 __get_unaligned_le64(const uint8 *p)
{
return (uint64)__get_unaligned_le32(p + 4) << 32 |
__get_unaligned_le32(p);
}
static inline void __put_unaligned_le16(uint16 val, uint8 *p)
{
*p++ = val;
*p++ = val >> 8;
}
static inline void __put_unaligned_le32(uint32 val, uint8 *p)
{
__put_unaligned_le16(val >> 16, p + 2);
__put_unaligned_le16(val, p);
}
static inline void __put_unaligned_le64(uint64 val, uint8 *p)
{
__put_unaligned_le32(val >> 32, p + 4);
__put_unaligned_le32(val, p);
}
static inline uint16 get_unaligned_le16(const void *p)
{
return __get_unaligned_le16((const uint8 *)p);
}
static inline uint32 get_unaligned_le32(const void *p)
{
return __get_unaligned_le32((const uint8 *)p);
}
static inline uint64 get_unaligned_le64(const void *p)
{
return __get_unaligned_le64((const uint8 *)p);
}
static inline void put_unaligned_le16(uint16 val, void *p)
{
__put_unaligned_le16(val, (uint8 *)p);
}
static inline void put_unaligned_le32(uint32 val, void *p)
{
__put_unaligned_le32(val, (uint8 *)p);
}
static inline void put_unaligned_le64(uint64 val, void *p)
{
__put_unaligned_le64(val, (uint8 *)p);
}
static inline uint16 __get_unaligned_be16(const uint8 *p)
{
return p[0] << 8 | p[1];
}
static inline uint32 __get_unaligned_be32(const uint8 *p)
{
return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
}
static inline uint64 __get_unaligned_be64(const uint8 *p)
{
return (uint64)__get_unaligned_be32(p) << 32 |
__get_unaligned_be32(p + 4);
}
static inline void __put_unaligned_be16(uint16 val, uint8 *p)
{
*p++ = val >> 8;
*p++ = val;
}
static inline void __put_unaligned_be32(uint32 val, uint8 *p)
{
__put_unaligned_be16(val >> 16, p);
__put_unaligned_be16(val, p + 2);
}
static inline void __put_unaligned_be64(uint64 val, uint8 *p)
{
__put_unaligned_be32(val >> 32, p);
__put_unaligned_be32(val, p + 4);
}
static inline uint16 get_unaligned_be16(const void *p)
{
return __get_unaligned_be16((const uint8 *)p);
}
static inline uint32 get_unaligned_be32(const void *p)
{
return __get_unaligned_be32((const uint8 *)p);
}
static inline uint64 get_unaligned_be64(const void *p)
{
return __get_unaligned_be64((const uint8 *)p);
}
static inline void put_unaligned_be16(uint16 val, void *p)
{
__put_unaligned_be16(val, (uint8 *)p);
}
static inline void put_unaligned_be32(uint32 val, void *p)
{
__put_unaligned_be32(val, (uint8 *)p);
}
static inline void put_unaligned_be64(uint64 val, void *p)
{
__put_unaligned_be64(val, (uint8 *)p);
}
#ifdef __cplusplus
}
#endif
#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */

45
sdk/include/chip/arch/csky/defs.h Normal file
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#ifndef _ARCH_CSKY_DEFS_H_
#define _ARCH_CSKY_DEFS_H_
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/////////////////////////////////////////////////////////////////////////////////
#define RETURN_ADDR() __builtin_return_address(0)
#define cpu_dcache_disable() csi_dcache_clean_invalid(); csi_dcache_disable();
#define cpu_dcache_enable() csi_dcache_enable()
typedef signed char int8;
typedef signed short int16;
typedef signed int int32;
typedef signed long long int64;
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
typedef unsigned long long uint64;
typedef unsigned long ulong;
#ifndef _SIZE_T_DECLARED
typedef unsigned int size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef _SSIZE_T_DECLARED
#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
typedef int ssize_t;
#else
typedef long ssize_t;
#endif
#define _SSIZE_T_DECLARED
#endif
/////////////////////////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#endif

29
sdk/include/chip/arch/csky/string.h Normal file
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#ifndef __ARCH_CSKY_STDLIB_H_
#define __ARCH_CSKY_STDLIB_H_
#include <ctype.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#ifdef __cplusplus
extern "C" {
#endif
#define os_htons(x) ((((x) & (uint16)0x00ffUL) << 8) | (((x) & (uint16)0xff00UL) >> 8))
#define os_ntohs(x) os_htons(x)
#define os_htonl(x) ((((x) & (uint32)0x000000ffUL) << 24) | \
(((x) & (uint32)0x0000ff00UL) << 8) | \
(((x) & (uint32)0x00ff0000UL) >> 8) | \
(((x) & (uint32)0xff000000UL) >> 24))
#define os_ntohl(x) os_htonl(x)
int strncasecmp(const char *s1, const char *s2, size_t n);
int strcasecmp(const char *s1, const char *s2);
#ifdef __cplusplus
}
#endif
#endif

103
sdk/include/chip/arch/csky/time.h Normal file
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#ifndef __ARCH_CSKY_OS_TIME_H_
#define __ARCH_CSKY_OS_TIME_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <time.h>
#include <sys/time.h>
#ifdef __NEWLIB__
#include <sys/timespec.h>
#if !defined(__time_t_defined) && !defined(_TIME_T_DECLARED)
typedef uint64 time_t;
#define __time_t_defined
#define _TIME_T_DECLARED
#endif
#endif
#ifndef _USECONDS_T_DECLARED
typedef unsigned long useconds_t; /* microseconds (unsigned) */
#define _USECONDS_T_DECLARED
#endif
#if !defined(_CLOCKID_T_DECLARED)
typedef unsigned long clockid_t;
#define __clockid_t_defined
#define _CLOCKID_T_DECLARED
#endif
#if !defined(__timer_t_defined) && !defined(_TIMER_T_DECLARED)
typedef unsigned long timer_t;
#define __timer_t_defined
#define _TIMER_T_DECLARED
#endif
#ifndef _SYS_TIMESPEC_H_
struct itimerspec {
struct timespec it_interval; /**< Timer period. */
struct timespec it_value; /**< Timer expiration. */
};
#endif
/*struct timeval */
/* Convenience macros for operations on timevals.
NOTE: `timercmp' does not work for >= or <=. */
#ifndef timerisset
#define timerisset(tvp) ((tvp)->tv_sec || (tvp)->tv_usec)
#endif
#ifndef timerclear
#define timerclear(tvp) ((tvp)->tv_sec = (tvp)->tv_usec = 0)
#endif
#ifndef timercmp
#define timercmp(a, b, CMP) \
(((a)->tv_sec == (b)->tv_sec) ? \
((a)->tv_usec CMP (b)->tv_usec) : \
((a)->tv_sec CMP (b)->tv_sec))
#endif
#if 1 //see: posix/timer.c
#ifndef timeradd
#define timeradd(a, b, result) \
do { \
(result)->tv_sec = (a)->tv_sec + (b)->tv_sec; \
(result)->tv_usec = (a)->tv_usec + (b)->tv_usec; \
if ((result)->tv_usec >= 1000000) \
{ \
++(result)->tv_sec; \
(result)->tv_usec -= 1000000; \
} \
} while (0)
#endif
#ifndef timersub
#define timersub(a, b, result) \
do { \
(result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \
(result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \
if ((result)->tv_usec < 0) { \
--(result)->tv_sec; \
(result)->tv_usec += 1000000; \
} \
} while (0)
#endif
#endif
extern int settimeofday(const struct timeval *tv, const struct timezone *tz);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/chip/soc.h Normal file
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#ifndef __SOC_H__
#define __SOC_H__
#include "tx_platform.h"
#define CONFIG_KERNEL_RHINO 1
#endif

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sdk/include/chip/tx_platform.h Normal file
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#ifndef _HUGE_IC_PLATFORM_H_
#define _HUGE_IC_PLATFORM_H_
#define PRO_TYPE_LMAC 1
#define PRO_TYPE_UMAC 2
#define PRO_TYPE_WNB 3
#define PRO_TYPE_UAV 4
#define PRO_TYPE_FMAC 5
#define PRO_TYPE_IOT 6
#define PRO_TYPE_FPV 7
#define PRO_TYPE_MCU 8
#define PRO_TYPE_VIDEO 9
#define PRO_TYPE_QA 66
#define PRO_TYPE_QC 88
#ifdef TXW81X
#include "txw81x/txw81x.h"
#include "txw81x/pin_names.h"
#include "txw81x/io_function.h"
#include "txw81x/adc_voltage_type.h"
#include "txw81x/sysctrl.h"
#include "txw81x/pmu.h"
#include "txw81x/misc.h"
#include "txw81x/boot_lib.h"
#include "txw81x/test_atcmd.h"
#include "txw81x/byteshift.h"
#endif
#ifdef TXW82X
#include "txw82x/txw82x.h"
#include "txw82x/pin_names.h"
#include "txw82x/io_function.h"
#include "txw82x/adc_voltage_type.h"
#include "txw82x/sysctrl.h"
#include "txw82x/pmu.h"
#include "txw82x/rpc.h"
#include "txw82x/misc.h"
#include "txw82x/boot_lib.h"
#include "txw82x/test_atcmd.h"
#endif
#endif

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sdk/include/chip/txw82x/adc_voltage_type.h Normal file
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/**
******************************************************************************
* @file sdk\include\chip\txw80x\adc_voltage_type.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2022-03-18
* @brief This file contains all the adc_voltage_type.
* @copyright Copyright (c) 2016-2022 HUGE-IC
******************************************************************************
* @attention
* Only used for txw80x.
*
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ADC_VOLTAGE_TYPE_H
#define __ADC_VOLTAGE_TYPE_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Docxygenid_ADC_voltage_type_enum
* @{
*/
/**
* @brief Enumeration constant for ADC voltage type.
* @note
* Enum number start from 0x101.
*/
enum adc_voltage_type {
/*! RF temperature
*/
ADC_CHANNEL_RF_TEMPERATURE = 0x101,
/*! Vtune电压
*/
ADC_CHANNEL_VTUNE = 0x102,
/*!
* VCO VDD电压
*/
ADC_CHANNEL_VCO_VDD = 0x103,
/*!
* VDD DIV电压
*/
ADC_CHANNEL_VDD_DIV = 0x104,
/*!
* VDDI电压
*/
ADC_CHANNEL_VDDI = 0x105,
/*!
* PMU temperature
*/
ADC_CHANNEL_PMU_TEMPERATURE = 0x106,
/*!
* vdd core
*/
ADC_CHANNEL_CORE_VDD = 0x107,
};
/** @} Docxygenid_ADC_voltage_type_enum_enum*/
#ifdef __cplusplus
}
#endif
#endif
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/

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sdk/include/chip/txw82x/boot_lib.h Normal file
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#ifndef __BOOT_LIB_H
#define __BOOT_LIB_H
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
uint32 get_boot_loader_addr();
void save_boot_loader_addr();
uint32 get_boot_total_size();
uint32 get_boot_version();
void increase_boot_version();
void set_boot_msg(uint8 *msg);
uint32 get_boot_svn_version();
uint8_t get_psram_status();
void set_psram_status(uint8_t res);
uint32 get_boot_loader_offset();
//返回 0:是代表检查通过 -1:输入长度过短 -2:头部校验不过 -3:头部crc校验不过
//注意:返回-2或者-3,crc都会被写入一个值(但不一定有效)
int16 get_code_crc(uint8 *buf,uint32 len,uint16 *crc);//返回ota代码的crc(只需要前面256byte)
uint16 get_code_crc16(); //获取当前代码的crc
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/chip/txw82x/cld_cache.h Normal file
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/*
* Copyright (C) 2024 ZHUHAI TAIXIN Co., Ltd. All rights reserved.
*
*/
/******************************************************************************
* @file cld_cahce.h
* @brief cldache Access Layer Header File
* @version V1.0
* @date 2024.5.29
******************************************************************************/
#ifndef __CLD_CACHE_H_GENERIC
#define __CLD_CACHE_H_GENERIC
#include <stdint.h>
#include <csi_gcc.h>
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* definitions
******************************************************************************/
/**
\ingroup
@{
*/
/* definitions */
typedef struct
{
__I uint32_t HWPARAMS; //0x000
__I uint32_t reserve0[3]; //0x004-0x00c
__IO uint32_t CTRL; //0x010
__I uint32_t NSEC_ACCESS; //0x014
__I uint32_t reserve1[2]; //0x018-0x01c
__O uint32_t MAINT_CTRL_ALL; //0x020
__O uint32_t MAINT_CTRL_LINES; //0x024
__I uint32_t MAINT_STATUS; //0x028
__I uint32_t reserve2[53]; //0x02c-0x0fc
__I uint32_t SECIRQSTAT; //0x100;
__O uint32_t SECIRQSCLR; //0x104;
__IO uint32_t SECIRQEN; //0x108;
__I uint32_t SECIRQINFO1; //0x10C;
__I uint32_t SECIRQINFO2; //0x110;
__I uint32_t reserve3[11]; //0x114-0x13c
__I uint32_t NSECIRQSTAT; //0x140;
__O uint32_t NSECIRQSCLR; //0x144;
__IO uint32_t NSECIRQEN; //0x148;
__I uint32_t NSECIRQINFO1; //0x14C;
__I uint32_t NSECIRQINFO2; //0x150;
__I uint32_t reserve4[107]; //0x154-0x2fc
__I uint32_t SECHIT; //0x300;
__I uint32_t SECMISS; //0x304;
__IO uint32_t SECSTATCTRL; //0x308;
__I uint32_t reserve5[1]; //0x30c
__I uint32_t NSECHIT; //0x310;
__I uint32_t NSECMISS; //0x314;
__IO uint32_t NSECSTATCTRL; //0x318;
__I uint32_t reserve6[813]; //0x31c-0xFCC
__I uint32_t PIDR4; //0xFD0;
__I uint32_t PIDR5; //0xFD4;
__I uint32_t PIDR6; //0xFD8;
__I uint32_t PIDR7; //0xFDC;
__I uint32_t PIDR0; //0xFE0;
__I uint32_t PIDR1; //0xFE4;
__I uint32_t PIDR2; //0xFE8;
__I uint32_t PIDR3; //0xFEC;
__I uint32_t CIDR0; //0xFF0;
__I uint32_t CIDR1; //0xFF4;
__I uint32_t CIDR2; //0xFF8;
__I uint32_t CIDR3; //0xFFC;
} DCACHE_CTRL_TypeDef;
#define DCACHE_CTRL_BASE2 ((uint32_t)0x50000000)
#define DCACHE_CTRL ((DCACHE_CTRL_TypeDef *) DCACHE_CTRL_BASE2)
/* THE memory is forced non-sec */
#define DCACHE_MAINT_NO_SEC ((uint32_t)0x00000004)
#define DCACHE_STA_ENABLE ((uint32_t)0x00000001)
#define DCACHE_STA_ONGOING_EN ((uint32_t)0x00000002)
#define DCACHE_STA_ONGOING_MAINT ((uint32_t)0x00000004)
#define DCACHE_STA_ONGOING_PWR_MAINT ((uint32_t)0x00000008)
#define DCACHE_STA_IS_CLEAN ((uint32_t)0x00000010)
static inline uint32_t cld_cache_get_status(void)
{
return DCACHE_CTRL->MAINT_STATUS;
}
static inline uint32_t cld_cache_is_maint_done(void)
{
return (0x4 == (DCACHE_CTRL->SECIRQSTAT & 0xC));
}
static inline uint32_t cld_cache_is_maint_ignore(void)
{
return (DCACHE_CTRL->SECIRQSTAT & 0x8);
}
static inline void cld_cache_clr_maint_done(void)
{
DCACHE_CTRL->SECIRQSCLR = 0x4;
}
static inline void cld_cache_clr_maint_ignore(void)
{
DCACHE_CTRL->SECIRQSCLR = 0x8;
}
static inline void cld_cache_clr_all_pending(void)
{
DCACHE_CTRL->SECIRQSCLR = 0xFF;
}
static inline uint32_t cld_cache_is_enable(void)
{
return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ENABLE;
}
static inline uint32_t cld_cache_is_clean(void)
{
return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_IS_CLEAN;
}
static inline uint32_t cld_cache_is_ongoing_enable(void)
{
return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_EN;
}
static inline uint32_t cld_cache_is_ongoing_maint(void)
{
return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_MAINT;
}
static inline uint32_t cld_cache_is_ongoing_pwr_maint(void)
{
return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_PWR_MAINT;
}
static inline uint32_t cld_cache_is_ongoing(void)
{
return DCACHE_CTRL->MAINT_STATUS & (DCACHE_STA_ONGOING_PWR_MAINT | DCACHE_STA_ONGOING_MAINT | DCACHE_STA_ONGOING_EN);
}
static inline void cld_cache_force_write_through(void)
{
DCACHE_CTRL->CTRL |= 1UL << 1;
}
/* TXW82x S_NS ONLY */
#define CLD_CACHE_MAINT_OPT_ATOMIC(opt)\
do {\
uint32 __disable_irq(void);\
void __enable_irq(void);\
uint32 flag = __disable_irq();\
cld_cache_clr_all_pending();\
opt;\
while (!cld_cache_is_maint_done());\
if(!flag) __enable_irq();\
} while (0);
#define CLD_CACHE_MAINT_OPT(opt)\
do {\
cld_cache_clr_all_pending();\
opt;\
while (!cld_cache_is_maint_done());\
} while (0);
#define CLD_CACHE_MAINT_OPT_WAIT() //do { while (cld_cache_is_ongoing_maint()); } while (0)
#define CLD_CACHE_MAINT_FB_KICKOFF()\
do {\
extern uint32 psram_rsv_addr;\
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = (psram_rsv_addr & 0xFFFFFFE0) | 0x2 | DCACHE_MAINT_NO_SEC;);\
*(uint32 volatile*)((uint32_t)psram_rsv_addr);\
} while(0)
static inline void cld_cache_clean_all(void)
{
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 1;);
}
static inline void cld_cache_invalidate_all(void)
{
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 2;);
}
static inline void cld_cache_clean_invalidate_all(void)
{
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 3;);
}
static inline void cld_cache_disable(void)
{
__DSB();
cld_cache_invalidate_all();
DCACHE_CTRL->CTRL &= ~(1UL << 0);
while (cld_cache_is_enable());
while (cld_cache_is_ongoing_maint());
}
static inline void cld_cache_enable(void)
{
cld_cache_disable();
/* deny powerdown \ enable nsec stat、 maintain lines */
DCACHE_CTRL->CTRL |= 1UL << 0 | 0x10 | 0x70000;
while (!cld_cache_is_enable());
}
static inline void cld_cache_irq_enable(void)
{
/* ONLY ERROR : XOM_ERR(not support) & TR_ERR */
DCACHE_CTRL->SECIRQEN = 0x90;
}
static inline void cld_cache_clean_line(uint32_t addr)
{
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = ((uint32_t)addr & (0xFFFFFFFF << 5)) | 0x1 | DCACHE_MAINT_NO_SEC;);
CLD_CACHE_MAINT_OPT_WAIT();
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
static inline void cld_cache_clean_range (uint32_t *addr, int32_t dsize)
{
int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
int32_t linesize = 32;
op_addr |= 0x1 | DCACHE_MAINT_NO_SEC;
while (op_size > 0) {
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
CLD_CACHE_MAINT_OPT_WAIT();
}
__DSB();
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
static inline void cld_cache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
int32_t linesize = 32;
op_addr |= 0x3 | DCACHE_MAINT_NO_SEC;
while (op_size > 0) {
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
CLD_CACHE_MAINT_OPT_WAIT();
}
__DSB();
}
/**
\brief D-Cache Invalidate by address
\details Cleans and invalidates D_Cache for the given address
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
static inline void cld_cache_invalid_range (uint32_t *addr, int32_t dsize)
{
int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
int32_t linesize = 32;
op_addr |= 0x2 | DCACHE_MAINT_NO_SEC;
CLD_CACHE_MAINT_FB_KICKOFF();
while (op_size > 0) {
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
CLD_CACHE_MAINT_OPT_WAIT();
}
__DSB();
}
static inline uint32_t cld_cache_get_nsec_hits(void)
{
return DCACHE_CTRL->NSECHIT;
}
static inline uint32_t cld_cache_get_nsec_miss(void)
{
return DCACHE_CTRL->NSECMISS;
}
static inline void cld_cache_reset_profile(void)
{
DCACHE_CTRL->NSECSTATCTRL |= 0x2;
}
static inline void cld_cache_enable_profile(void)
{
while (cld_cache_is_ongoing());
DCACHE_CTRL->NSECSTATCTRL |= 0x1;
}
static inline void cld_cache_disable_profile(void)
{
DCACHE_CTRL->NSECSTATCTRL &= ~ 0x1;
}
#ifdef __cplusplus
}
#endif
#endif /* __CLD_CACHE_H_GENERIC */

660
sdk/include/chip/txw82x/io_function.h Normal file
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@@ -0,0 +1,660 @@
/**
******************************************************************************
* @file sdk\include\chip\txw80x\io_function.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2022-01-11
* @brief This file contains all the GPIO functions.
* @copyright Copyright (c) 2016-2022 HUGE-IC
******************************************************************************
* @attention
* Only used for txw80x.
*
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IO_FUNCTION_H
#define __IO_FUNCTION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "typesdef.h"
#define REG_GPIO_DIR_CLR(port, n) \
(*(volatile unsigned int*)(port+0x00)) &= ~(3<<((n)<<1))
#define REG_GPIO_DIR_INPUT(port, n) \
do { \
REG_GPIO_DIR_CLR(port, n); \
(*(volatile unsigned int*)(port+0x00)) |= (0<<((n)<<1)); \
} while(0)
#define REG_GPIO_DIR_OUTPUT(port, n) \
do { \
REG_GPIO_DIR_CLR(port, n); \
(*(volatile unsigned int*)(port+0x00)) |= (1<<((n)<<1)); \
} while(0)
#define REG_GPIO_OTYPE_CLR(port, n) \
(*(volatile unsigned int*)(port+0x04)) &= ~(1<<(n));
#define REG_GPIO_OPEN_DRAIN(port, n) \
do { \
REG_GPIO_OTYPE_CLR(port, n); \
(*(volatile unsigned int*)(port+0x04)) |= (1<<(n));\
} while(0)
#define REG_GPIO_PUSH_PULL(port, n) \
do { \
REG_GPIO_OTYPE_CLR(port, n); \
(*(volatile unsigned int*)(port+0x04)) |= (0<<(n));\
} while(0)
#define REG_GPIO_PUL_100(port, n) \
(*(volatile unsigned int*)(port+0x10)) |= BIT((((n)-0)<<2))
#define REG_GPIO_PUH_100(port, n) \
(*(volatile unsigned int*)(port+0x14)) |= BIT((((n)-8)<<2))
#define REG_GPIO_PDL_100(port, n) \
(*(volatile unsigned int*)(port+0x18)) |= BIT((((n)-0)<<2))
#define REG_GPIO_PDH_100(port, n) \
(*(volatile unsigned int*)(port+0x1C)) |= BIT((((n)-8)<<2))
#define REG_GPIO_SET(port, n) \
(*(volatile unsigned int*)(port+0x24)) = \
((*(volatile unsigned int*)(port+0x24)) & ~BIT(n)) | BIT(n)
#define REG_GPIO_RESET(port, n) \
(*(volatile unsigned int*)(port+0x24)) = \
((*(volatile unsigned int*)(port+0x24)) & ~BIT(n))
/** @addtogroup Docxygenid_GPIO_enum
* @{
*/
/**
* @brief Enumeration constant for GPIO command.
* @note
* Enum number start from 0x101.
*/
enum gpio_cmd {
/*! GPIO cmd afio set
*/
GPIO_CMD_AFIO_SET = 0x101,
/*! GPIO cmd iomap output
*/
GPIO_CMD_IOMAP_OUT_FUNC,
/*! GPIO cmd iomap input
*/
GPIO_CMD_IOMAP_IN_FUNC,
/*! GPIO cmd iomap inout
*/
GPIO_CMD_IOMAP_INOUT_FUNC,
/*! GPIO pin driver strength config
*/
GPIO_CMD_DRIVER_STRENGTH,
};
/**
* @brief Enumeration constant for GPIO afio set.
*/
enum gpio_afio_set{
/*! gpio cmd afio 0
*/
GPIO_AF_0 = 0,
/*! gpio cmd afio 1
*/
GPIO_AF_1 ,
/*! gpio cmd afio 2
*/
GPIO_AF_2 ,
/*! gpio cmd afio 3
*/
GPIO_AF_3 ,
};
/**
* @breif : Enumeration constant for GPIO pull level.
*/
enum gpio_pull_level {
/*! gpio pull level : NONE
*/
GPIO_PULL_LEVEL_NONE = 0,
/*! gpio pull level : 4.7K
*/
GPIO_PULL_LEVEL_4_7K ,
/*! gpio pull level : 100k
*/
GPIO_PULL_LEVEL_100K ,
};
/**
* @breif : Enumeration constant for GPIO driver strength
*/
enum pin_driver_strength {
/**
*对于81x, 分别对应4, 12, 20, 28mA
*对于82x, 分别对应4, 8, 16, 20mA. 对于PB12/PD8/PD14/PE1, 则分别是8, 20, 32, 60mA
*/
GPIO_DS_G0,
GPIO_DS_G1,
GPIO_DS_G2,
GPIO_DS_G3,
};
/** @defgroup GPIO IO map output function selection
* @{
*/
//除了GPIO_IOMAP_OUTPUT， 不能同时存在两个及以上 [ (枚举值+4)/5 ]相同的GPIO OUTPUT MAPPING 配置，下表已经分好类了
enum gpio_iomap_out_func{
GPIO_IOMAP_OUTPUT = 0,
GPIO_IOMAP_OUT_OSPI_CS_IO = 0x1,
GPIO_IOMAP_OUT_DBGPATH_DBGO_8 = 0x2,
GPIO_IOMAP_OUT_LCD_DE_OR_ERD = 0x3,
GPIO_IOMAP_OUT_COMP_DOUT_DIG0 = 0x5,
GPIO_IOMAP_OUT_LCD_DATA_O_0 = 0x6,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_0 = 0x7,
GPIO_IOMAP_OUT_DBGPATH_DBGO_9 = 0x8,
GPIO_IOMAP_OUT_COMP_DOUT_DIG1 = 0xA,
GPIO_IOMAP_OUT_LCD_DE_OR_ERD1 = 0xB,
GPIO_IOMAP_OUT_ANTENNA_SEL = 0xF,
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC = 0x10,
GPIO_IOMAP_OUT_PA_EN = 0x14,
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS0 = 0x15,
GPIO_IOMAP_OUT_RF_EXT_LNA_EN = 0x19,
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR0 = 0x1A,
GPIO_IOMAP_OUT_RF_SWITCH_EN1 = 0x1B,
GPIO_IOMAP_OUT_RF_TX_EN_FEM = 0x1E,
GPIO_IOMAP_OUT_RF_SWITCH_EN0 = 0x1F,
GPIO_IOMAP_OUT_DVP_MCLK_OUT = 0x20,
GPIO_IOMAP_OUT_RF_RX_EN_FEM = 0x23,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_1 = 0x24,
GPIO_IOMAP_OUT_RF_TRX_SW_FEM = 0x25,
GPIO_IOMAP_OUT_LCD_DATA_O_1 = 0x28,
GPIO_IOMAP_OUT_DAC_PDM_OUT = 0x29,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_2 = 0x2A,
GPIO_IOMAP_OUT_RF_PA_EN_FEM = 0x2B,
GPIO_IOMAP_OUT_LCD_DATA_O_2 = 0x2D,
GPIO_IOMAP_OUT_LCD_DATA_O_3 = 0x2E,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_3 = 0x2F,
GPIO_IOMAP_OUT_DBGPATH_DBGO_0 = 0x30,
GPIO_IOMAP_OUT_UART1_RTS_RE_O = 0x32,
GPIO_IOMAP_OUT_LCD_DATA_O_4 = 0x33,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_4 = 0x34,
GPIO_IOMAP_OUT_DBGPATH_DBGO_1 = 0x35,
GPIO_IOMAP_OUT_UART1_CTS_DE_OUT = 0x37,
GPIO_IOMAP_OUT_LCD_DATA_O_5 = 0x38,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_5 = 0x39,
GPIO_IOMAP_OUT_UART1_OUT = 0x3C,
GPIO_IOMAP_OUT_DBGPATH_DBGO_2 = 0x3D,
GPIO_IOMAP_OUT_UART0_RTS_RE_O = 0x41,
GPIO_IOMAP_OUT_DBGPATH_DBGO_3 = 0x42,
GPIO_IOMAP_OUT_UART0_CTS_DE_OUT = 0x46,
GPIO_IOMAP_OUT_UART0_OUT = 0x4B,
GPIO_IOMAP_OUT_LCD_DATA_O_6 = 0x4C,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_6 = 0x4D,
GPIO_IOMAP_OUT_STMR3_PWM_OUT = 0x50,
GPIO_IOMAP_OUT_LCD_DATA_O_7 = 0x51,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_7 = 0x52,
GPIO_IOMAP_OUT_STMR2_PWM_OUT = 0x55,
GPIO_IOMAP_OUT_LCD_DATA_O_8 = 0x56,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_8 = 0x57,
GPIO_IOMAP_OUT_STMR1_PWM_OUT = 0x5A,
GPIO_IOMAP_OUT_LCD_DATA_O_9 = 0x5B,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_9 = 0x5C,
GPIO_IOMAP_OUT_STMR0_PWM_OUT = 0x5F,
GPIO_IOMAP_OUT_LCD_DATA_O_10 = 0x60,
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_10 = 0x61,
GPIO_IOMAP_OUT_STMR4_PWM_OUT = 0x64,
GPIO_IOMAP_OUT_LCD_DATA_O_11 = 0x65,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_6 = 0x66,
GPIO_IOMAP_OUT_STMR5_PWM_OUT = 0x69,
GPIO_IOMAP_OUT_SPI0_IO3_OUT = 0x6A,
GPIO_IOMAP_OUT_SDHOST_SCLK_O = 0x6E,
GPIO_IOMAP_OUT_SPI0_IO2_OUT = 0x6F,
GPIO_IOMAP_OUT_TMR3_PWM_OUT = 0x73,
GPIO_IOMAP_OUT_SPI0_IO1_OUT = 0x74,
GPIO_IOMAP_OUT_TMR2_PWM_OUT = 0x78,
GPIO_IOMAP_OUT_SPI1_NSS_OUT = 0x79,
GPIO_IOMAP_OUT_TMR1_PWM_OUT = 0x7D,
GPIO_IOMAP_OUT_LCD_DATA_O_12 = 0x7E,
GPIO_IOMAP_OUT_TMR0_PWM_OUT = 0x82,
GPIO_IOMAP_OUT_DBGPATH_DBGO_4 = 0x83,
GPIO_IOMAP_OUT_SDHOST1_DAT1_OUT = 0x84,
GPIO_IOMAP_OUT_DUAL_ORG_FSYNC = 0x85,
GPIO_IOMAP_OUT_LED_TMR0_PWM_OUT = 0x87,
GPIO_IOMAP_OUT_LCD_DATA_O_13 = 0x88,
GPIO_IOMAP_OUT_DBGPATH_DBGO_5 = 0x89,
GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT = 0x8C,
GPIO_IOMAP_OUT_LCD_DATA_O_14 = 0x8D,
GPIO_IOMAP_OUT_DBGPATH_DBGO_6 = 0x8E,
GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT = 0x91,
GPIO_IOMAP_OUT_LCD_DATA_O_15 = 0x92,
GPIO_IOMAP_OUT_DBGPATH_DBGO_7 = 0x93,
GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT = 0x96,
GPIO_IOMAP_OUT_CAN_TXD = 0x97,
GPIO_IOMAP_OUT_CPU1_JTG_TMS = 0x98,
GPIO_IOMAP_OUT_PDM_MCLK = 0x9B,
GPIO_IOMAP_OUT_OSPI_CS_IO1 = 0x9C,
GPIO_IOMAP_OUT_QSPI_NSS1_OUT = 0xA0,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_0 = 0xA1,
GPIO_IOMAP_OUT_GRANT_BLE = 0xA2,
GPIO_IOMAP_OUT_SPI0_NSS_OUT = 0xA5,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_1 = 0xA6,
GPIO_IOMAP_OUT_GRANT_BLE_SWITCH_O = 0xA7,
GPIO_IOMAP_OUT_SPI0_SCK_OUT = 0xAA,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_2 = 0xAB,
GPIO_IOMAP_OUT_GRANT_WIFI_SWITCH_O = 0xAC,
GPIO_IOMAP_OUT_SPI0_IO0_OUT = 0xAF,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_3 = 0xB0,
GPIO_IOMAP_OUT_SPARE0 = 0xB4,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_4 = 0xB5,
GPIO_IOMAP_OUT_SPARE1 = 0xB9,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_5 = 0xBA,
GPIO_IOMAP_OUT_SPARE2 = 0xBE,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_7 = 0xBF,
GPIO_IOMAP_OUT_SPARE3 = 0xC3,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_8 = 0xC4,
GPIO_IOMAP_OUT_SPI1_SCK_OUT = 0xC8,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_9 = 0xC9,
GPIO_IOMAP_OUT_SPI1_IO0_OUT = 0xCD,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_10 = 0xCE,
GPIO_IOMAP_OUT_SPI1_IO1_OUT = 0xD2,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_11 = 0xD3,
GPIO_IOMAP_OUT_LCD_DATA_O_16 = 0xD7,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_12 = 0xD8,
GPIO_IOMAP_OUT_LCD_DATA_O_17 = 0xDC,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_13 = 0xDD,
GPIO_IOMAP_OUT_LCD_DATA_O_18 = 0xDE,
GPIO_IOMAP_OUT_SPI2_NSS_OUT = 0xE1,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_14 = 0xE2,
GPIO_IOMAP_OUT_SDHOST1_SCLK_O = 0xE3,
GPIO_IOMAP_OUT_SPI2_SCK_OUT = 0xE6,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_15 = 0xE7,
GPIO_IOMAP_OUT_SDHOST1_DAT0_OUT = 0xE8,
GPIO_IOMAP_OUT_SPI2_IO0_OUT = 0xEB,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_16 = 0xEC,
GPIO_IOMAP_OUT_LCD_DATA_O_19 = 0xED,
GPIO_IOMAP_OUT_SDHOST1_CMD_OUT = 0xEE,
GPIO_IOMAP_OUT_SPI2_IO1_OUT = 0xF0,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_17 = 0xF1,
GPIO_IOMAP_OUT_LCD_DATA_O_20 = 0xF2,
GPIO_IOMAP_OUT_SDHOST1_DAT2_OUT = 0xF3,
GPIO_IOMAP_OUT_SPI2_IO2_OUT = 0xF5,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_18 = 0xF6,
GPIO_IOMAP_OUT_LCD_DATA_O_21 = 0xF7,
GPIO_IOMAP_OUT_SDHOST1_DAT3_OUT = 0xF8,
GPIO_IOMAP_OUT_SPI2_IO3_OUT = 0xFA,
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_19 = 0xFB,
GPIO_IOMAP_OUT_SDHOST_CMD_OUT = 0xFF,
GPIO_IOMAP_OUT_UART6_TX = 0x100,
GPIO_IOMAP_OUT_SDHOST_DAT0_OUT = 0x104,
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR1 = 0x105,
GPIO_IOMAP_OUT_SDHOST_DAT1_OUT = 0x109,
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS1 = 0x10A,
GPIO_IOMAP_OUT_SDHOST_DAT2_OUT = 0x10E,
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC1 = 0x10F,
GPIO_IOMAP_OUT_SDHOST_DAT3_OUT = 0x113,
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR2 = 0x114,
GPIO_IOMAP_OUT_IO2IO_CHANNAL3 = 0x115,
GPIO_IOMAP_OUT_IIS0_MCLK_OUT = 0x118,
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS2 = 0x119,
GPIO_IOMAP_OUT_IO2IO_CHANNAL2 = 0x11A,
GPIO_IOMAP_OUT_IIS0_WSCLK_OUT = 0x11D,
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC2 = 0x11E,
GPIO_IOMAP_OUT_IO2IO_CHANNAL1 = 0x11F,
GPIO_IOMAP_OUT_IIS0_BCLK_OUT = 0x122,
GPIO_IOMAP_OUT_LCD_DE_OR_ERD2 = 0x123,
GPIO_IOMAP_OUT_IO2IO_CHANNAL0 = 0x124,
GPIO_IOMAP_OUT_IIS0_DO = 0x127,
GPIO_IOMAP_OUT_UART5_TX = 0x128,
GPIO_IOMAP_OUT_LCD_DATA_O_22 = 0x129,
GPIO_IOMAP_OUT_IIS1_MCLK_OUT = 0x12C,
GPIO_IOMAP_OUT_LCD_DATA_O_23 = 0x12D,
GPIO_IOMAP_OUT_NFC_TX_GATE_N = 0x12E,
GPIO_IOMAP_OUT_IIS1_WSCLK_OUT = 0x131,
GPIO_IOMAP_OUT_SPI1_IO2_OUT = 0x132,
GPIO_IOMAP_OUT_NFC_TX_N = 0x133,
GPIO_IOMAP_OUT_IIS1_BCLK_OUT = 0x136,
GPIO_IOMAP_OUT_SPI1_IO3_OUT = 0x137,
GPIO_IOMAP_OUT_NFC_TX_GATE_P = 0x138,
GPIO_IOMAP_OUT_IIS1_DO = 0x13B,
GPIO_IOMAP_OUT_UART4_TX = 0x13C,
GPIO_IOMAP_OUT_NFC_TX_P = 0x13D,
GPIO_IOMAP_OUT_CLK_TO_IO = 0x140,
};
/** @defgroup Enumeration constant for GPIO IO map input function selection
* @{
*/
enum gpio_iomap_in_func{
GPIO_IOMAP_INPUT = 0xF000,
GPIO_IOMAP_IN_SPARE_IO1 = 0x0000,
GPIO_IOMAP_IN_SPARE_IO2,
GPIO_IOMAP_IN_SPARE_IO3,
GPIO_IOMAP_IN_TMR2_CAP_IN,
GPIO_IOMAP_IN_TMR3_CAP_IN,
GPIO_IOMAP_IN_PDM_DATA_IN_EPWM_TZ1_M3_2,
GPIO_IOMAP_IN_PTA_REQ_IN_EPWM_TZ2_M3_3,
GPIO_IOMAP_IN_PTA_PRI_IN_EPWM_TZ3_M3_4,
GPIO_IOMAP_IN_FREQ_IND_IN_EPWM_TZ4_M3_5,
GPIO_IOMAP_IN_STMR0_CAP_IN_LCD_D3_IN_M1_22_EPWM_SYNC_IO_M3_6,
GPIO_IOMAP_IN_STMR1_CAP_IN_LCD_D4_IN_M1_23,
GPIO_IOMAP_IN_STMR2_CAP_IN_LCD_D5_IN_M1_24,
GPIO_IOMAP_IN_STMR3_CAP_IN_LCD_D6_IN_M1_25,
GPIO_IOMAP_IN_PORT_WKUP_IN0 = 13,
GPIO_IOMAP_IN_TMR0_CAP_IN = 13,
GPIO_IOMAP_IN_PORT_WKUP_IN1_LCD_D7_IN_M1_26 = 14,
GPIO_IOMAP_IN_TMR0_SYNCI = 14,
GPIO_IOMAP_IN_EXT_RFSWITCH_EN0 = 14,
GPIO_IOMAP_IN_PORT_WKUP_IN2_LCD_D8_IN_M1_27 = 15,
GPIO_IOMAP_IN_TMR1_CAP_IN = 15,
GPIO_IOMAP_IN_PORT_WKUP_IN3_LCD_TE_M0_10,
GPIO_IOMAP_IN_UART0_IN,
GPIO_IOMAP_IN_UART0_CTS_DE_IN,
GPIO_IOMAP_IN_UART1_IN_LCD_D9_IN_M1_28,
GPIO_IOMAP_IN_UART1_CTS_DE_IN_LCD_D10_IN_M1_29,
GPIO_IOMAP_IN_FB_IN_EXT_PA_EN_SYS_NMI_CAN_RXD,
GPIO_IOMAP_IN_UART4_IN,
GPIO_IOMAP_IN_LCD_D0_IN_M1_19,
GPIO_IOMAP_IN_SPI0_NSS_IN,
GPIO_IOMAP_IN_SPI0_SCK_IN,
GPIO_IOMAP_IN_SPI0_IO0_IN,
GPIO_IOMAP_IN_SPI0_IO1_IN,
GPIO_IOMAP_IN_SPI0_IO2_IN,
GPIO_IOMAP_IN_SPI0_IO3_IN,
GPIO_IOMAP_IN_SPI1_NSS_IN_LCD_D11_IN_M1_30,
GPIO_IOMAP_IN_SPI1_SCK_IN,
GPIO_IOMAP_IN_SPI1_IO0_IN,
GPIO_IOMAP_IN_SPI1_IO1_IN_LCD_D12_IN_M1_31,
GPIO_IOMAP_IN_LCD_D1_IN_M1_20,
GPIO_IOMAP_IN_LCD_D2_IN_M1_21,
GPIO_IOMAP_IN_SPI2_NSS_IN_LCD_D13_IN_M2_0,
GPIO_IOMAP_IN_SPI2_SCK_IN,
GPIO_IOMAP_IN_SPI2_IO0_IN,
GPIO_IOMAP_IN_SPI2_IO1_IN_LCD_D14_IN_M2_1,
GPIO_IOMAP_IN_SPI2_IO2_IN_LCD_D15_IN_M2_2,
GPIO_IOMAP_IN_SPI2_IO3_IN_LCD_D16_IN_M2_3,
GPIO_IOMAP_IN_STMR4_CAP_IN_LCD_D17_IN_M2_4,
GPIO_IOMAP_IN_STMR5_CAP_IN_LCD_D18_IN_M2_5,
GPIO_IOMAP_IN_SDHOST_CMD_IN,
GPIO_IOMAP_IN_SDHOST_DAT0_IN,
GPIO_IOMAP_IN_SDHOST_DAT1_IN,
GPIO_IOMAP_IN_SDHOST_DAT2_IN,
GPIO_IOMAP_IN_SDHOST_DAT3_IN,
GPIO_IOMAP_IN_IIS0_MCLK_IN_LCD_D19_IN_M2_6,
GPIO_IOMAP_IN_IIS0_WSCLK_IN_LCD_D20_IN_M2_7,
GPIO_IOMAP_IN_IIS0_BCLK_IN_LCD_D21_IN_M2_8,
GPIO_IOMAP_IN_IIS0_DAT_IN_UART6_RX_M3_9,
GPIO_IOMAP_IN_IIS1_MCLK_IN_Uart5_IN_LCD_D22_IN_M2_9,
GPIO_IOMAP_IN_IIS1_WSCLK_IN_LCD_D23_IN_M2_10,
GPIO_IOMAP_IN_SPI1_IO2_IN_IIS1_BCLK_IN,
GPIO_IOMAP_IN_SPI1_IO3_IN_IIS1_DAT_IN_UART6_RX_M3_9,
};
/** @defgroup Enumeration constant for GPIO spare iomap function
* @{ 选择一个IO连接到备用的功能点上， 解决同组MAP无法复用的问题
*
*/
enum smap_node{
SMAP_OUT_0 = 0,
SMAP_OUT_1,
SMAP_OUT_2,
SMAP_OUT_3,
SMAP_IN_1,
SMAP_IN_2,
SMAP_IN_3,
};
enum smap_output{
SMAP_OUT_RF_EXT_LNA_EN ,
SMAP_OUT_RF_TX_EN_FEM ,
SMAP_OUT_RF_SWITCH_EN1 ,
SMAP_OUT_RF_RX_EN_FEM ,
SMAP_OUT_RF_SWITCH_EN0 ,
SMAP_OUT_RF_TRX_SW_FEM ,
SMAP_OUT_RF_PA_EN_FEM ,
SMAP_OUT_GRANT_BLE ,
SMAP_OUT_GRANT_BLE_SWITCH_O ,
SMAP_OUT_GRANT_WIFI_SWITCH_O ,
SMAP_OUT_UART0_RTS_RE_O ,
SMAP_OUT_UART0_CTS_DE_OUT ,
SMAP_OUT_UART0_OUT ,
SMAP_OUT_UART1_RTS_RE_O ,
SMAP_OUT_UART1_CTS_DE_OUT ,
SMAP_OUT_UART1_OUT ,
SMAP_OUT_UART4_TX ,
SMAP_OUT_UART5_TX ,
SMAP_OUT_UART6_TX ,
SMAP_OUT_VIDEO_PAR_DATA_O_0 ,
SMAP_OUT_VIDEO_PAR_DATA_O_1 ,
SMAP_OUT_VIDEO_PAR_DATA_O_2 ,
SMAP_OUT_VIDEO_PAR_DATA_O_3 ,
SMAP_OUT_VIDEO_PAR_DATA_O_4 ,
SMAP_OUT_VIDEO_PAR_DATA_O_5 ,
SMAP_OUT_VIDEO_PAR_DATA_O_6 ,
SMAP_OUT_VIDEO_PAR_DATA_O_7 ,
SMAP_OUT_VIDEO_PAR_DATA_O_8 ,
SMAP_OUT_VIDEO_PAR_DATA_O_9 ,
SMAP_OUT_DBGPATH_DBGO_0 ,
SMAP_OUT_DBGPATH_DBGO_1 ,
SMAP_OUT_DBGPATH_DBGO_2 ,
SMAP_OUT_DBGPATH_DBGO_3 ,
SMAP_OUT_DBGPATH_DBGO_4 ,
SMAP_OUT_DBGPATH_DBGO_5 ,
SMAP_OUT_DBGPATH_DBGO_6 ,
SMAP_OUT_DBGPATH_DBGO_7 ,
SMAP_OUT_DBGPATH_DBGO_8 ,
SMAP_OUT_DBGPATH_DBGO_9 ,
SMAP_OUT_STMR0_PWM_OUT ,
SMAP_OUT_STMR1_PWM_OUT ,
SMAP_OUT_STMR2_PWM_OUT ,
SMAP_OUT_STMR3_PWM_OUT ,
SMAP_OUT_STMR4_PWM_OUT ,
SMAP_OUT_STMR5_PWM_OUT ,
SMAP_OUT_TMR3_PWM_OUT ,
SMAP_OUT_TMR2_PWM_OUT ,
SMAP_OUT_TMR1_PWM_OUT ,
SMAP_OUT_TMR0_PWM_OUT ,
SMAP_OUT_LED_TMR0_PWM_OUT ,
SMAP_OUT_LED_TMR1_PWM_OUT ,
SMAP_OUT_LED_TMR2_PWM_OUT ,
SMAP_OUT_LED_TMR3_PWM_OUT ,
SMAP_OUT_OSPI_CS_IO ,
SMAP_OUT_QSPI_NSS1_OUT ,
SMAP_OUT_QSPI_OSPI_MNT_O_0 ,
SMAP_OUT_QSPI_OSPI_MNT_O_1 ,
SMAP_OUT_QSPI_OSPI_MNT_O_2 ,
SMAP_OUT_QSPI_OSPI_MNT_O_3 ,
SMAP_OUT_QSPI_OSPI_MNT_O_4 ,
SMAP_OUT_QSPI_OSPI_MNT_O_5 ,
SMAP_OUT_QSPI_OSPI_MNT_O_6 ,
SMAP_OUT_QSPI_OSPI_MNT_O_7 ,
SMAP_OUT_QSPI_OSPI_MNT_O_8 ,
SMAP_OUT_QSPI_OSPI_MNT_O_9 ,
SMAP_OUT_QSPI_OSPI_MNT_O_10 ,
SMAP_OUT_QSPI_OSPI_MNT_O_11 ,
SMAP_OUT_QSPI_OSPI_MNT_O_12 ,
SMAP_OUT_QSPI_OSPI_MNT_O_13 ,
SMAP_OUT_QSPI_OSPI_MNT_O_14 ,
SMAP_OUT_QSPI_OSPI_MNT_O_15 ,
SMAP_OUT_QSPI_OSPI_MNT_O_16 ,
SMAP_OUT_QSPI_OSPI_MNT_O_17 ,
SMAP_OUT_QSPI_OSPI_MNT_O_18 ,
SMAP_OUT_QSPI_OSPI_MNT_O_19 ,
SMAP_OUT_SDHOST1_CMD_OUT ,
SMAP_OUT_SDHOST1_SCLK_O ,
SMAP_OUT_SDHOST1_DAT0_OUT,
SMAP_OUT_SDHOST1_DAT1_OUT,
SMAP_OUT_SDHOST1_DAT2_OUT,
SMAP_OUT_SDHOST1_DAT3_OUT,
SMAP_OUT_SDHOST_SCLK_O ,
SMAP_OUT_SDHOST_CMD_OUT ,
SMAP_OUT_SDHOST_DAT0_OUT ,
SMAP_OUT_SDHOST_DAT1_OUT ,
SMAP_OUT_SDHOST_DAT2_OUT ,
SMAP_OUT_SDHOST_DAT3_OUT ,
SMAP_OUT_IO2IO_CHANNAL3 ,
SMAP_OUT_IO2IO_CHANNAL2 ,
SMAP_OUT_IO2IO_CHANNAL1 ,
SMAP_OUT_IO2IO_CHANNAL0 ,
SMAP_OUT_IIS1_WSCLK_OUT ,
SMAP_OUT_IIS1_BCLK_OUT ,
SMAP_OUT_IIS1_DO ,
SMAP_OUT_IIS1_MCLK_OUT ,
SMAP_OUT_IIS0_MCLK_OUT ,
SMAP_OUT_IIS0_WSCLK_OUT ,
SMAP_OUT_IIS0_BCLK_OUT ,
SMAP_OUT_IIS0_DO ,
SMAP_OUT_LCD_DATA_O_0 ,
SMAP_OUT_LCD_DATA_O_1 ,
SMAP_OUT_LCD_DATA_O_2 ,
SMAP_OUT_LCD_DATA_O_3 ,
SMAP_OUT_LCD_DATA_O_4 ,
SMAP_OUT_LCD_DATA_O_5 ,
SMAP_OUT_LCD_DATA_O_6 ,
SMAP_OUT_LCD_DATA_O_7 ,
SMAP_OUT_LCD_DATA_O_8 ,
SMAP_OUT_LCD_DATA_O_9 ,
SMAP_OUT_LCD_DATA_O_10 ,
SMAP_OUT_LCD_DATA_O_11 ,
SMAP_OUT_LCD_DATA_O_12 ,
SMAP_OUT_LCD_DATA_O_13 ,
SMAP_OUT_LCD_DATA_O_14 ,
SMAP_OUT_LCD_DATA_O_15 ,
SMAP_OUT_LCD_DATA_O_16 ,
SMAP_OUT_LCD_DATA_O_17 ,
SMAP_OUT_LCD_DATA_O_18 ,
SMAP_OUT_LCD_DATA_O_19 ,
SMAP_OUT_LCD_DATA_O_20 ,
SMAP_OUT_LCD_DATA_O_21 ,
SMAP_OUT_LCD_DATA_O_22 ,
SMAP_OUT_LCD_DATA_O_23 ,
SMAP_OUT_LCD_DOTCLK_OR_RWR ,
SMAP_OUT_LCD_VSYNC_OR_CS ,
SMAP_OUT_LCD_HSYNC_OR_DC ,
SMAP_OUT_LCD_DE_OR_ERD ,
SMAP_OUT_SPI0_NSS_OUT ,
SMAP_OUT_SPI0_SCK_OUT ,
SMAP_OUT_SPI0_IO0_OUT ,
SMAP_OUT_SPI0_IO1_OUT ,
SMAP_OUT_SPI0_IO2_OUT ,
SMAP_OUT_SPI0_IO3_OUT ,
SMAP_OUT_SPI1_SCK_OUT ,
SMAP_OUT_SPI1_NSS_OUT ,
SMAP_OUT_SPI1_IO0_OUT ,
SMAP_OUT_SPI1_IO1_OUT ,
SMAP_OUT_SPI1_IO2_OUT ,
SMAP_OUT_SPI1_IO3_OUT ,
SMAP_OUT_SPI2_NSS_OUT ,
SMAP_OUT_SPI2_SCK_OUT ,
SMAP_OUT_SPI2_IO0_OUT ,
SMAP_OUT_SPI2_IO1_OUT ,
SMAP_OUT_SPI2_IO2_OUT ,
SMAP_OUT_SPI2_IO3_OUT ,
SMAP_OUT_NFC_TX_GATE_N ,
SMAP_OUT_NFC_TX_N ,
SMAP_OUT_NFC_TX_GATE_P ,
SMAP_OUT_NFC_TX_P ,
SMAP_OUT_COMP_DOUT_DIG0 ,
SMAP_OUT_COMP_DOUT_DIG1 ,
SMAP_OUT_ANTENNA_SEL ,
SMAP_OUT_LIN_TX ,
SMAP_OUT_LIN1_TX ,
SMAP_OUT_PA_EN ,
SMAP_OUT_DVP_MCLK_OUT ,
SMAP_OUT_DAC_PDM_OUT ,
SMAP_OUT_DUAL_ORG_FSYNC ,
SMAP_OUT_PDM_MCLK ,
SMAP_OUT_CAN_TXD ,
SMAP_OUT_CLK_TO_IO ,
};
enum smap_input{
SMAP_IN_IO2IO_CH0 = 1,
SMAP_IN_IO2IO_CH1,
SMAP_IN_IO2IO_CH2,
SMAP_IN_IO2IO_CH3,
SMAP_IN_LCD_DAT_3 =5,
SMAP_IN_LCD_DAT_4,
SMAP_IN_LCD_DAT_5,
SMAP_IN_LCD_DAT_6,
SMAP_IN_LCD_DAT_7,
SMAP_IN_LCD_DAT_8 = 10,
SMAP_IN_EX_RFSWI_EN0 = 11,
SMAP_IN_LCD_DAT_9 = 12,
SMAP_IN_LCD_DAT_10,
SMAP_IN_FB_IN = 14,
SMAP_IN_EX_RF_PA_EN = 15,
SMAP_IN_LCD_DAT_11 = 16,
SMAP_IN_LCD_DAT_12,
SMAP_IN_SDHOST1_DAT3,
SMAP_IN_LCD_DAT_13,
SMAP_IN_SDHOST1_DAT0,
SMAP_IN_SDHOST1_CMD,
SMAP_IN_LCD_DAT_14,
SMAP_IN_SDHOST1_DAT2,
SMAP_IN_LCD_DAT_15,
SMAP_IN_SPI2_IO3,
SMAP_IN_LCD_DAT_16,
SMAP_IN_LCD_DAT_17,
SMAP_IN_LCD_DAT_18,
SMAP_IN_LCD_DAT_19,
SMAP_IN_LCD_DAT_20,
SMAP_IN_LCD_DAT_21,
SMAP_IN_UART5_RX = 32,
SMAP_IN_LCD_DAT_22,
SMAP_IN_LCD_DAT_23,
SMAP_IN_SPI_IO2,
SMAP_IN_SPI_IO3,
SMAP_IN_UART6_RX,
};
/** @} Docxygenid_IO_function_enum*/
int32 gpio_driver_strength(uint32 pin, enum pin_driver_strength strength);
int32 gpio_set_altnt_func(uint32 pin, enum gpio_afio_set afio);
int32 gpio_iomap_output(uint32 pin, enum gpio_iomap_out_func func_sel);
int32 gpio_iomap_input(uint32 pin, enum gpio_iomap_in_func func_sel);
int32 gpio_iomap_inout(uint32 pin, enum gpio_iomap_in_func in_func_sel, enum gpio_iomap_out_func out_func_sel);
int lmac_fem_pin_func(int request);
#ifdef __cplusplus
}
#endif
#endif
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/

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/**
******************************************************************************
* @file misc.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2021.01.14
* @brief This file contains all the PowerDomain firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
*
*
* Revision History
* V1.0.0 2021.01.14 First Release, move from sysctrl
*
******************************************************************************
*/
#ifndef __MISC_H__
#define __MISC_H__
#include "typesdef.h"
#include "cld_cache.h"
#include "lib/common/rbuffer.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef VENUS_END
/*******************************************************************/
/* Venus to be continue */
/*******************************************************************/
#endif
/**
* @}
*/
///** @defgroup SYSMONITOR MACRO-DEF & Exported_Functions
// * @{
// */
typedef struct
{
__IO uint32 CHx_LMT_L;
__IO uint32 CHx_LMT_H;
__IO uint32 CHx_ERR_ADR;
// uint32 RESERVEDx;
} SYS_MNT_CH_TypeDef;
typedef struct
{
__IO uint32 CTRL;
__IO uint32 PND;
__IO uint32 CLR;
__IO uint32 RD;
__IO uint32 WR;
__IO uint32 rev[4];
SYS_MNT_CH_TypeDef SYS_MNT_CH[2];
} SYS_MNT_TypeDef;
#define SYSMNT ((SYS_MNT_TypeDef *) SYS_MNT_BASE)
/**
* @}
*/
/**
* @brief CPU1_MNT
*/
typedef struct
{
__IO uint32 R0;
__IO uint32 R1;
__IO uint32 R2;
__IO uint32 R3;
__IO uint32 R4;
__IO uint32 R5;
__IO uint32 R6;
__IO uint32 R7;
__IO uint32 R8;
__IO uint32 R9;
__IO uint32 R10;
__IO uint32 R11;
__IO uint32 R12;
__IO uint32 R13;
__IO uint32 R14;
__IO uint32 R15; //0x40
uint32 reserved_0x44[12];
__IO uint32 R28;
uint32 reserved_0x70[19];
__IO uint32 EXPC; //0xc0
__IO uint32 PSR;
__IO uint32 EPC;
__IO uint32 EPSR;
__IO uint32 FCR;
__IO uint32 FESR;
__IO uint32 CPU1_DBGON;
__IO uint32 CPU0_DBGON;
__IO uint32 CPU1_SFTPND;
} CPU1_MNT_TypeDef;
#define CPU1_MNT ((CPU1_MNT_TypeDef *) 0x4000A100 )
/** @addtogroup Template_Project
* @{
*/
#define LL_SYSMONITOR_CHN_EN(n) (BIT(n))
#define LL_SYSMONITOR_CHN_CAP_RANGE_INTER(n) (BIT(n+4))
#define LL_SYSMONITOR_CHN_CAP_RANGE_OUTER(n) (0)
#define LL_SYSMONITOR_CAP_PC_EN (1UL << 6)
#define LL_SYSMONITOR_INT_EN (1UL << 7)
#define LL_SYSMONITOR_CH0_SEL(n) (((n) & 0x1F) << 8)
#define LL_SYSMONITOR_CH0_SEL_MSK ((0x1F) << 8)
#define LL_SYSMONITOR_CH0_CAP_READ ((1UL) << 18)
#define LL_SYSMONITOR_CH0_CAP_WRITE ((1UL) << 19)
#define LL_SYSMONITOR_CH0_CAP_MODE(n) ((((n) & 0x3)) << 18)
#define LL_SYSMONITOR_CH1_SEL(n) (((n) & 0x1F) << 13)
#define LL_SYSMONITOR_CH1_SEL_MSK ((0x1F) << 13)
#define LL_SYSMONITOR_CH1_CAP_READ ((1UL) << 20)
#define LL_SYSMONITOR_CH1_CAP_WRITE ((1UL) << 21)
#define LL_SYSMONITOR_CH1_CAP_MODE(n) ((((n) & 0x3)) << 20)
#define LL_SYSMONITOR_CLEAR_REGISTER() do { SYSMNT->CLR = 1 | 2; } while(0)
/** @addtogroup XXX
* @{
*/
typedef enum {
//CHANNEL 1
LL_SYSMONITOR_CHN_M2M0_RD = (0) | (1<<8),
LL_SYSMONITOR_CHN_M2M0_WR = (1) | (1<<8),
LL_SYSMONITOR_CHN_M2M1_RD = (2) | (1<<8),
LL_SYSMONITOR_CHN_M2M1_WR = (3) | (1<<8),
LL_SYSMONITOR_CHN_CPU0_ICODE = (4) | (1<<8),
LL_SYSMONITOR_CHN_CPU0_DCODE = (5) | (1<<8),
LL_SYSMONITOR_CHN_USB_20 = (6) | (1<<8),
LL_SYSMONITOR_CHN_USB_11 = (7) | (1<<8),
//CHANNEL 0
LL_SYSMONITOR_CHN_CPU1_ICODE = (6) | (0<<8),
LL_SYSMONITOR_CHN_CPU1_DCODE = (7) | (0<<8),
LL_SYSMONITOR_CHN_OSPI = (8) | (0<<8),
LL_SYSMONITOR_CHN_QSPI = (9) | (0<<8),
LL_SYSMONITOR_CHN_GMAC_RX = (10) | (0<<8),
LL_SYSMONITOR_CHN_GMAC_TX = (11) | (0<<8),
} TYPE_ENUM_LL_SYSMONITOR_CH;
/** @addtogroup XXX
* @{
*/
typedef enum {
LL_SYSMONITOR_CAP_RANGE_INTER = (0),
LL_SYSMONITOR_CAP_RANGE_OUTER = (1),
} TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE;
/** @addtogroup XXX
* @{
*/
typedef enum {
LL_SYSMONITOR_CAP_MODE_READ = (1),
LL_SYSMONITOR_CAP_MODE_WRITE = (2),
LL_SYSMONITOR_CAP_MODE_READ_OR_WRITE = (3),
} TYPE_ENUM_LL_SYSMONITOR_CAP_MODE;
typedef struct __ll_sysmonitor_cfg {
/*! System monitor interrupt enable
*/
bool int_en;
/*! System monitor sub channel : [0, 20]
*/
TYPE_ENUM_LL_SYSMONITOR_CH ch;
/*! capture mode
*/
TYPE_ENUM_LL_SYSMONITOR_CAP_MODE cap_mode;
/*! capture range
*/
TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE cap_range;
/*! Chx low limited address
*/
uint32 chx_limit_low;
/*! Chx high limited address
*/
uint32 chx_limit_high;
/* IRQ handle
*/
void (*cb)(void *);
} TYPE_SYSMONITOR_CFG;
void sys_monitor_config(TYPE_SYSMONITOR_CFG *p_cfg);
void sys_monitor_reset(void);
/*******************************************************************/
/* OSPI_EFF */
/*******************************************************************/
struct HW_EFF {
volatile uint32_t CON;
volatile uint32_t PERIOD;
volatile uint32_t RD_CNT;
volatile uint32_t WR_CNT;
};
#define OSPI_EFF ((struct HW_EFF *) 0x40020214)
#define EFF_CNT_CLEAR (1<<6)
#define EFF_INTR_PEND (1<<5)
#define EFF_CH_SHIFT (2)
#define EFF_CH_MASK (7<<2)
#define EFF_INTR_EN (1<<1)
#define EFF_MODU_EN (1<<0)
#define OSPI_EFF_MSG_SIZE (5)
enum EFF_CH {
EFF_CPU0_DBUS,
EFF_CPU0_IBUS,
EFF_CPU1_DBUS,
EFF_CPU1_IBUS,
EFF_H264,
EFF_SCHED,
EFF_CH_OTHER,
EFF_CH_END,
};
struct eff_msg {
uint32_t rd_cnt[EFF_CH_END];
uint32_t wr_cnt[EFF_CH_END];
};
struct eff_mgr {
RBUFFER_DEF(rb, struct eff_msg, OSPI_EFF_MSG_SIZE);
};
/*统计period_ms时间内PSRAM的请求数， MAX值是0xffffffff / CPU_CLK * 1000*/
int eff_start(uint32_t period_ms);
void eff_stop();
/*输出最近一次统计到的信息*/
int eff_printf();
int eff_read(struct eff_msg *msg);
/*******************************************************************/
/* EFUSE */
/*******************************************************************/
/**
* @}
*/
#define CHIP_PACKID_KL928 0x01
#define CHIP_PACKID_TXW825_824 0x02
#define CHIP_PACKID_TXW826_824 0x10
#define CHIP_PACKID_TXW826_824C 0x11
#define CHIP_PACKID_TXW827_C08 0x20
#define CHIP_PACKID_TXW828_C08FL 0x30
#define CHIP_PACKID_TXW828_E08FL 0x31
#define CHIP_PACKID_TXW828_E016FL 0x32
#define CHIP_PACKID_TXW828_J016FL 0x33
#define CHIP_PACKID_TXM609_800 0x40
#define CHIP_PACKID_TXM609_804 0x41
#define CHIP_PACKID_TXM609_H016 0x42
/** @defgroup EFUSE MACRO-DEF & Exported_Functions
* @{
*/
typedef struct
{
__IO uint32 EFUSE_CON;
__IO uint32 EFUSE_TIME_CON0;
__IO uint32 EFUSE_TIME_CON1;
__IO uint32 EFUSE_TIME_CON2;
__IO uint32 EFUSE_STATUS;
__IO uint32 EFUSE_ADDR_CNT;
__IO uint32 EFUSE_DATA;
} EFUSE_TypeDef;
#define EFUSE ((EFUSE_TypeDef *) EFUSE_BASE)
/* efuse timing define */
#define LL_EFUSE_POWER_FREQ 100000 /* 10us */
#define LL_EFUSE_PROGRAM_FREQ 100000 /* 10us (9~11uS) */
#define LL_EFUSE_READ_FREQ 10000000 /* 100ns ( > 36ns) */
uint16 sysctrl_efuse_config_and_read(uint32 addr, uint8 *p_buf, uint16 len);
void rf_para_efuse_check_valid(void);
void sysctrl_efuse_mac_addr_calc(uint8 *addr_buf);
uint16 sysctrl_efuse_get_customer_id(void);
uint8 sysctrl_efuse_get_chip_package(void);
uint32 sysctrl_efuse_get_smt_dat(void);
int32 tsensor_meas(uint8 sensor_idx);
/*******************************************************************/
/* RFADC */
/*******************************************************************/
typedef struct {
__IO uint32 RFADCDIGCON;
} RFADCDIG_TypeDef;
#define RFADCDIG ((RFADCDIG_TypeDef *) RFADCDIG_BASE)
#define RFADCDIGCON_ACS_ON_MSK BIT(0)
#define RFADCDIGCON_ACS_RW_MSK BIT(1)
#define RFADCDIGCON_ACS_ADDR_SHIFT 2
#define RFADCDIGCON_ACS_ADDR_MSK (0x1f<<RFADCDIGCON_ACS_ADDR_SHIFT)
#define RFADCDIGCON_ACS_DATA_SHIFT 7
#define RFADCDIGCON_ACS_DATA_MSK (0x3fffff<<RFADCDIGCON_ACS_DATA_SHIFT)
#define ADCOUTSEL 0 // 0: output data after calibration; 1: output data before calibration
/*******************************************************************/
/* RFADC */
/*******************************************************************/
enum lf_clk_src {
FROM_HOSC = 0,
FROM_RC32K = 2,
FROM_PB0 = 3,
};
enum lf_clk_count {
_1024_CYCLE = 0,
_512_CYCLE = 1,
_256_CYCLE = 2,
_128_CYCLE = 3,
_64_CYCLE = 4,
_32_CYCLE = 5,
_16_CYCLE = 6,
_8_CYCLE = 7,
};
enum dac_default_state {
POWER_OFF = 0,
SLEEP = 1,
STAND_BY = 2,
POWER_ON = 3
};
enum rf_bw {
BW_1M = 0,
BW_2M = 1,
BW_4M = 2,
BW_8M = 3
};
enum rf_parameter_type {
RF_EFUSE_ALL_SIM = 0,
ADC_CALIB_VAL = 1,
ADDA_TIM_OFFSET = 2,
TXDCOC_CALIB_VAL = 3,
TXIMB_CALIB_VAL = 4,
RXDCOC_CALIB_VAL = 5,
RXIMB_CALIB_VAL = 6
};
int32 tx_digi_gain_store(uint16 tx_digi_gain);
int32 sysctrl_internal_rf_sel_lo_freq(uint8 lo_freq_idx);
int32 is_xo_cs_calibed(void);
int32 is_xo_cto_calibed(void);
int32 xo_cs_store(uint8 xo_cs_val);
int32 sysctrl_get_xo_drcs(void);
int32 sysctrl_set_xo_drcs(uint16 xo_drcs);
void adc_cfg_reg_wr(uint8 addr, uint32 data);
uint32 adc_cfg_reg_rd(uint8 addr);
int32 is_adc_calibed(void);
void adc_init(void);
int32 adc_calib_res_store(void);
void adc_calib_res_restore(void);
void rfadc_calib_mode_soft_test(void);
int32 sysctrl_err_resp_icode_bus(uint8 enable);
int32 sysctrl_err_resp_dcode_bus(uint8 enable);
int32 sysctrl_err_resp_ahb2dma_bus(uint8 enable);
int32 sysctrl_err_resp_sdiodevice_bus(uint8 enable);
int32 sysctrl_err_resp_disable(void);
int32 sysctrl_get_chip_flash_size(void);
int32 sysctrl_is_chipdcn_compid(void);
/* 速率：x Bps */
uint32_t sys_dma2ahb_bw_static(int32 printf_en);
/* miss rate : 万分之x */
uint32_t sys_csi_cache_static(int32 core_id, int32 printf_en);
uint32_t sys_cld_cache_static(int32 printf_en);
uint32_t sys_psram_eff_static(int32 printf_en);
int32 sys_get_cpu_dcache_maint_both(void);
int32 sys_get_cpu_dcache_enable(void);
/** use when DMA source is psram
* usage( this -> DMA kick)
*/
void sys_dcache_clean_range (uint32_t *addr, int32_t dsize);
/* usefor TCPIP CHKSUM */
void sys_dcache_clean_range_unaligned (uint32_t *addr, int32_t dsize);
/** use when DMA destination is PSRAM
* usage : ( this -> DMA) ;
*/
void sys_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize);
void sys_dcache_clean_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
/** use when DMA destination is PSRAM
* Note：this function will auto writeback data head & tail (16/32byte unaligned)
* 1.usage : ( DMA done-> this) ;
* 2.Precondition: dma buffer addr & size is 16/32byte aligned
* 3.DMA buffer size is not checked
*/
void sys_dcache_invalid_range (uint32_t *addr, int32_t dsize);
/** use when DMA destination is PSRAM
* Note：this function will auto writeback data head & tail (16/32byte unaligned)
*/
void sys_dcache_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
#ifdef __cplusplus
}
#endif
#endif //__MISC_H__
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/

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/**
******************************************************************************
* @file pmu.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2021.01.14
* @brief This file contains all the PowerDomain firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
*
*
* Revision History
* V1.0.0 2021.01.14 First Release, move from sysctrl
*
******************************************************************************
*/
#ifndef __PMU_H__
#define __PMU_H__
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CORE_LVD_CON (0x00>>0)
#define CORE_LVD_CON1 (0x04>>0)
#define CORE_LVD_CON2 (0x08>>0)
#define CORE_PMUCON0 (0x10>>0)
#define CORE_PMUCON1 (0x14>>0)
#define CORE_PMUCON2 (0x18>>0)
#define CORE_PMUCON3 (0x1c>>0)
#define CORE_PMUCON4 (0x20>>0)
#define CORE_PMUCON5 (0x24>>0)
#define CORE_RFCON0 (0x28>>0)
#define CORE_RFCON1 (0x2c>>0)
#define CORE_PMUCON6 (0x30>>0)
#define CORE_PMUCON7 (0x34>>0)
#define CORE_PMUCON8 (0x38>>0)
#define CORE_PMUCON9 (0x3c>>0)
#define CORE_PMUCON10 (0x40>>0)
#define CORE_PMUCON11 (0x44>>0)
#define CORE_PMUCON12 (0x48>>0)
#define CORE_PMUCON13 (0x4c>>0)
#define CORE_PNDCLR (0x50>>0)
//-------------RTC part1 start---------------
#define CORE_RTCWPR (0x54>>0) //54
#define CORE_RTCCTR (0x58>>0) //58
#define CORE_RTCPDR (0x5c>>0) //5c
#define CORE_RTCISR (0x60>>0) //60
#define CORE_RTCSSR (0x64>>0) //64
#define CORE_RTCTMR (0x68>>0) //68
#define CORE_RTCDAR (0x6c>>0) //6c
#define CORE_RTCALR0R (0x70>>0) //70
#define CORE_RTCWUTR (0x74>>0) //74
#define CORE_RTCTSSSR (0x78>>0) //78
#define CORE_RTCTSTMR (0x7c>>0) //7c
//-------------RTC part1 end---------------
#define CORE_TMRCON (0x80>>0)
#define CORE_TMRPR (0x84>>0)
#define CORE_TMRRPT (0x88>>0)
#define CORE_TMRTRIM (0x8c>>0)
#define CORE_TMRPR2 (0x90>>0)
//-------------RTC part2 start---------------
//#define CORE_TMRRTCC (0x94>>0)
#define CORE_RTCTSDAR (0x94>>0) //94
#define CORE_RTCCALR (0x98>>0) //98
#define CORE_RTCSSSR (0x9c>>0) //9c
//-------------RTC part2 start---------------
#define CORE_WKCON (0xa0>>0)
#define CORE_WKCON1 (0xa4>>0)
#define CORE_WKCON2 (0xa8>>0)
#define CORE_SECCON (0xb0>>0)
#define CORE_SECDAT (0xb4>>0)
#define CORE_SECADR (0xb8>>0)
#define CORE_SECKEY (0xbc>>0)
#define CORE_CMPCON (0xc0>>0)
#define CORE_CMPCON1 (0xc4>>0)
#if 0 //vernus
#define CORE_TMR0CON (0xd0>>0)
#define CORE_TMR1CON (0xd4>>0)
#define CORE_TMR2CON (0xd8>>0)
#define CORE_TMR3CON (0xdc>>0)
#else //vernus200= eagle v2
#define CORE_PMUCON14 (0xc8>>0)
#define CORE_PMUCON15 (0xcc>>0)
#define CORE_TMR_CON (0xd0>>0)
#define CORE_TMR0CON (0xd4>>0)
#define CORE_TMR1CON (0xd8>>0)
#define CORE_TMR2CON (0xdc>>0)
#define CORE_TMR3CON (0xe0>>0)
#define CORE_WDTCON (0xe4>>0)
#define CORE_WDTKEY (0xe8>>0)
#endif
typedef struct
{
__IO uint32 LVD_CON;
__IO uint32 LVD_CON1;
__IO uint32 LVD_CON2;
__IO uint32 TMRAOCNTL;
__IO uint32 PMUCON0;
__IO uint32 PMUCON1;
__IO uint32 PMUCON2;
__IO uint32 PMUCON3;
__IO uint32 PMUCON4;
__IO uint32 PMUCON5;
__IO uint32 RFCON0;
__IO uint32 RFCON1;
__IO uint32 PMUCON6;
__IO uint32 PMUCON7;
__IO uint32 PMUCON8;
__IO uint32 PMUCON9;
__IO uint32 PMUCON10; //40
__IO uint32 PMUCON11;
__IO uint32 PMUCON12;
__IO uint32 PMUCON13;
__IO uint32 PNDCLR; //50
__IO uint32 RTCWPR; //54
__IO uint32 RTCCTR; //58
__IO uint32 RTCPDR; //5c
__IO uint32 RTCISR; //60
__IO uint32 RTCSSR; //64
__IO uint32 RTCTMR; //68
__IO uint32 RTCDAR; //6c
__IO uint32 RTCALR0R; //70
__IO uint32 RTCWUTR; //74
__IO uint32 RTCTSSSR; //78
__IO uint32 RTCTSTMR; //7c
__IO uint32 TMRCON; //80
__IO uint32 TMRPR;
__IO uint32 TMRRPT;
__IO uint32 TMRTRIM;
__IO uint32 TMRPR2; //90
__IO uint32 RTCTSDAR; //94
__IO uint32 RTCCALR; //98
__IO uint32 RTCSSSR; //9c
__IO uint32 WKCON; //a0
__IO uint32 WKCON1;
__IO uint32 WKCON2;
__IO uint32 TMRAOCNTH;
__IO uint32 SECCON; //b0
__IO uint32 SECDAT;
__IO uint32 SECADDR;
__IO uint32 SECKEY;
__IO uint32 CMPCON; //c0
__IO uint32 CMPCON1; //c4
__IO uint32 PMUCON14; //c8
__IO uint32 PMUCON15; //cc
__IO uint32 TMR_CON; //d0
__IO uint32 TMR0CON0; //d4
__IO uint32 TMR1CON0; //d8
__IO uint32 TMR2CON0; //dc
__IO uint32 TMR3CON0; //e0
__IO uint32 WDTCON; //e4
__IO uint32 WDTKEY; //e8
__IO uint32 PMUCON16; //ec
__IO uint32 RTC_VCCHVD_CON; //f0
__IO uint32 RTC_VCCHVD_PND; //f4
} PMU_TypeDef;
#define PMU ((PMU_TypeDef *) PMU_BASE)
#define PMU_REG_SET_BITS(reg, bits) do { pmu_reg_write((uint32)&reg, (reg)|(bits)); } while(0)
#define PMU_REG_CLR_BITS(reg, bits) do { pmu_reg_write((uint32)&reg, (reg) & ~(bits)); } while(0)
#define PMU_REG_SET_VALUE(reg, bit_mask, val, bit_pos) do { pmu_reg_write((uint32)&reg, ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)) ); } while(0)
#define PMU_REG_BIT_FUN(fun_name, reg, bits)\
__STATIC_INLINE void fun_name##_en(void) { PMU_REG_SET_BITS(reg, bits); }\
__STATIC_INLINE void fun_name##_dis(void) { PMU_REG_CLR_BITS(reg, bits); }
/* lvdcon */
#define pmu_vcam_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(31))
#define pmu_vcam_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(31))
#define PMU_VCAM_OC_PENDING (PMU->LVD_CON & BIT(30))
#define PMU_V15_OC_PENDING (PMU->LVD_CON & BIT(29))
#define PMU_VDD_OC_PENDING (PMU->LVD_CON & BIT(28))
#define PMU_VDD_LV_PENDING (PMU->LVD_CON & BIT(27))
#define PMU_VCC_LV_PENDING (PMU->LVD_CON & BIT(26))
#define PMU_VCC1_LV_PENDING (PMU->LVD_CON & BIT(25)) //?
#define PMU_VCC15_LV_PENDING (PMU->LVD_CON & BIT(24))
#define pmu_vcc1_lv_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(23))
#define pmu_vcc1_lv_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(23))
#define pmu_vcc15_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(22))
#define pmu_vcc15_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(22))
#define pmu_lvd_oe_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(21))
#define pmu_lvd_oe_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(21))
#define pmu_vdd_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(20))
#define pmu_vdd_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(20))
#define pmu_vdd_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(19))
#define pmu_vdd_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(19))
#define pmu_vcc_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(18))
#define pmu_vcc_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(18))
#define pmu_vcc15_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(17))
#define pmu_vcc15_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(17))
enum vcc15_oc_level {
VCC15_OC_200MA = 0,
VCC15_OC_90MA = 0x3,
VCC15_OC_70MA,
VCC15_OC_60MA,
VCC15_OC_50MA,
};
#define pmu_vcc15_oc_level_set(vcc15_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x0001c000, vcc15_oc_level, 14)
enum vdd_oc_level {
VDD_OC_50MA,
VDD_OC_100MA,
VDD_OC_150MA,
VDD_OC_200MA,
};
#define pmu_vdd_oc_level_set(vdd_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00003000, vdd_oc_level, 12)
enum vcc15_lv_level {
VCC15_LV_0V86_T_0V90,
VCC15_LV_1V00_T_1V05,
VCC15_LV_1V14_T_1V19,
VCC15_LV_1V29_T_1V35,
};
#define pmu_vcc15_lv_level_set(vcc15_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000c00, vcc15_lv_level, 10)
enum vdd_lv_level {
VDD_LV_0V64_T_0V68,
VDD_LV_0V74_T_0V78,
VDD_LV_0V84_T_0V88,
VDD_LV_0V84_T_0V98,
};
#define pmu_vdd_lv_level_set(vdd_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000300, vdd_lv_level, 8)
enum avcc_lv_level {
AVCC_LV_1V90_T_1V99,
AVCC_LV_2V06_T_2V16,
AVCC_LV_2V21_T_2V31,
AVCC_LV_2V33_T_2V44,
AVCC_LV_2V46_T_2V58,
AVCC_LV_2V62_T_2V74,
AVCC_LV_2V75_T_2V87,
AVCC_LV_2V90_T_3V04,
};
#define pmu_avcc_lv_level_set(avcc_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x000000e0, avcc_lv_level, 5)
enum vcc1_lv_level {
VCC1_LV_2V54_T_2V66,
VCC1_LV_1V46_T_1V53,
};
#define pmu_vcc1_lv_level_set(vcc1_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000010, vcc1_lv_level, 4)
#define pmu_vdd_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(3))
#define pmu_vdd_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(3))
#define pmu_avcc_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(2))
#define pmu_avcc_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(2))
#define pmu_vcc1_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(1))
#define pmu_vcc1_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(1))
#define pmu_vcc15_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(0))
#define pmu_vcc15_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(0))
/* lvdcon1 */
#define PMU_VDD18_OC_PENDING (PMU->LVD_CON1 & BIT(31))
#define PMU_VDD12_OC_PENDING (PMU->LVD_CON1 & BIT(30))
#define pmu_vcc_lv_detect_sync_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(30))
#define pmu_vcc_lv_detect_sync_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(30))
#define pmu_vdd_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(29))
#define pmu_vdd_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(29))
#define pmu_vcc_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(28))
#define pmu_vcc_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(28))
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
/* lvdcon2 */
#define pmu_vdd12_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(31))
#define pmu_vdd12_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(31))
#define pmu_vdd18_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(30))
#define pmu_vdd18_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(30))
#define pmu_vcc1_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(29))
#define pmu_vcc1_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(29))
#define pmu_vcc15_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(28))
#define pmu_vcc15_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(28))
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
/* CORE_PMUCON0 */
#define pmu_ftmclr_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(31))
#define pmu_ftmclr_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(31))
#define pmu_port_wk_auto_dis_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(29))
#define pmu_port_wk_auto_dis_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(29))
#define pmu_mclr_soft_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(28))
#define pmu_mclr_soft_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(28))
#define pmu_led_io_mux_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(27))
#define pmu_led_io_mux_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(27))
enum pd_tmr1_clk_sel {
PD_TMR1_CLK_RC128K,
PD_TMR1_CLK_XOSC,
PD_TMR1_CLK_RC8M,
PD_TMR1_CLK_LX32K,
};
#define pmu_pd_tmr1_clk_sel(pd_tmr1_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x06000000, pd_tmr1_clk_sel, 25)
#define pmu_pd_mem2_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(24))
#define pmu_pd_mem2_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(24))
#define pmu_fls_pg_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(23))
#define pmu_fls_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(23))
#define pmu_pd_mem32k_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(22))
#define pmu_pd_mem32k_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(22))
#define pmu_pd_ulp_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(21))
#define pmu_pd_ulp_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(21))
#define pmu_pd_io_latch_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(20))
#define pmu_pd_io_latch_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(20))
#define pmu_pd_rf_latch_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(19))
#define pmu_pd_rf_latch_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(19))
#define pmu_pd_osc_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(18))
#define pmu_pd_osc_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(18))
#define pmu_pd_osc_hw_trim_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(17))
#define pmu_pd_osc_hw_trim_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(17))
enum pd_tmr_clk_sel {
PD_TMR_CLK_RC128K,
PD_TMR_CLK_XOSC,
PD_TMR_CLK_RC32K,
PD_TMR_CLK_LX32K,
};
#define pmu_pd_tmr_clk_sel(pd_tmr_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00018000, pd_tmr_clk_sel, 15)
#define pmu_io_clk_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(14))
#define pmu_io_clk_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(14))
#define pmu_pd_wdt_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(11))
#define pmu_pd_wdt_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(11))
enum lpvdd_vol_level {
LPVDD_VOL_0V74,
LPVDD_VOL_0V81,
LPVDD_VOL_0V88,
LPVDD_VOL_0V95,
LPVDD_VOL_1V02,
LPVDD_VOL_1V09,
LPVDD_VOL_1V16,
LPVDD_VOL_1V23,
};
#define pmu_lpvdd_vol_set(lpvdd_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00000700, lpvdd_vol_level, 8)
/* CORE_PMUCON1 */
/* CORE_PMUCON2 */
/* CORE_PMUCON3 */
/* CORE_PMUCON4 */
#define pmu_vdd_en() PMU_REG_SET_BITS(PMU->PMUCON4, BIT(9))
#define pmu_vdd_dis() PMU_REG_CLR_BITS(PMU->PMUCON4, BIT(9))
/* CORE_PMUCON5 */
enum vdd15_vol_level {
VDD15_VOL_1V2,
VDD15_VOL_1V3,
VDD15_VOL_1V4,
VDD15_VOL_1V5,
VDD15_VOL_1V6,
VDD15_VOL_1V7,
VDD15_VOL_1V8,
VDD15_VOL_1V9,
VDD15_VOL_2V0,
VDD15_VOL_2V1,
VDD15_VOL_2V2,
VDD15_VOL_2V3,
VDD15_VOL_2V4,
VDD15_VOL_2V5,
};
#define pmu_vdd15_vol_set(vdd15_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON5, 0xF, vdd15_vol_level, 0)
#define pmu_hirc_8mhz_en() PMU_REG_SET_BITS(PMU->PMUCON5, BIT(24))
#define pmu_hirc_8mhz_dis() PMU_REG_CLR_BITS(PMU->PMUCON5, BIT(24))
/* CORE_PMUCON7 */
enum pmu_con7_bits_funcs {
PMU_BOOT_DIRECT_RUN, //0
PMU_APP_DEADCODE_PENDING,
PMU_CP_FAIL_PENDING,
PMU_BOOT_CODE_POS,
PMU_DIRECT_RUN_DISABLE_SIGN, //4
PMU_SKIP_MASTER_BOOT_SIGN,
PMU_SKIP_TEST_MODE_SIGN,
PMU_SKIP_PSRAM_SIGN,
PMU_RSV8, //8
PMU_RSV9,
PMU_RSV10,
PMU_RSV11,
PMU_RSV12,
PMU_RSV13,
PMU_RSV14,
PMU_RSV15,
PMU_DSLEEP_INIT_SIGN, //16
PMU_LPWDT_LOCK_SIGN,
PMU_WDT1_LOCK_SIGN,
PMU_WDT_LOCK_SIGN,
PMU_APP_SOFTRESET_SIGN, //20
PMU_WIFI_TEST_MODE_SIGN,
PMU_RSV22,
PMU_BOOT_DIRECT_RUN_PENDING2,
};
#define pmu_boot_direct_run_en() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(0))
#define pmu_boot_direct_run_dis() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(0))
#define pmu_get_boot_direct_run_pending() ((PMU->PMUCON7 & BIT(0)))
#define pmu_get_deadcode_pending() ((PMU->PMUCON7 & BIT(1)) ? 1 : 0)
#define pmu_clr_deadcode_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(1))
#define pmu_get_cp_fail_pending() ((PMU->PMUCON7 & BIT(2)) ? 1 : 0)
#define pmu_clr_cp_fail_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(2))
#define pmu_get_boot_code_pos() ((PMU->PMUCON7 & BIT(3)) ? 1 : 0)
#define GET_DIRECT_RUN_DISABLE_SIGN() ((PMU->PMUCON7 & BIT(4)) ? 1 : 0)
#define SET_DIRECT_RUN_DISABLE_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(4));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(4));\
} while(0)
#define GET_SKIP_MASTER_BOOT_SIGN() ((PMU->PMUCON7 & BIT(5)) ? 1 : 0)
#define SET_SKIP_MASTER_BOOT_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(5));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(5));\
} while(0)
#define GET_SKIP_TEST_MODE_SIGN() ((PMU->PMUCON7 & BIT(6)))
#define SET_SKIP_TEST_MODE_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(6));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(6));\
} while(0)
#define GET_SKIP_PSRAM_SIGN() ((PMU->PMUCON7 & BIT(7)))
#define SET_SKIP_PSRAM_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(7));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(7));\
} while(0)
/* PMU->PMUCON7[8:19] : not used */
/* PMU->PMUCON7[20] */
#define GET_APP_SOFTRESET_SIGN() ((PMU->PMUCON7 & BIT(20)))
#define SET_APP_SOFTRESET_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(20));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(20));\
} while(0)
/* PMU->PMUCON7[22] */
#define GET_WIFI_TEST_MODE_SIGN() ((PMU->PMUCON7 & BIT(21)))
#define SET_WIFI_TEST_MODE_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(21));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(21));\
} while(0)
#define pmu_get_boot_direct_run_pending2() ((PMU->PMUCON7 & BIT(23)))
#define pmu_set_direct_run_pengding2() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(23))
#define pmu_clr_direct_run_pengding2() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(23))
#define pmu_set_direct_run_addr(addr) PMU_REG_SET_VALUE(PMU->PMUCON7, 0xFF000000, ((addr >> 12) & 0xFF), 24)
/* CORE_PMUCON8 */
#define pmu_jtag_io_en() PMU_REG_SET_BITS(PMU->PMUCON8, BIT(0))
#define pmu_jtag_io_dis() PMU_REG_CLR_BITS(PMU->PMUCON8, BIT(0))
/* CORE_PMUCON11 */
#define VCCFLS_PG_DISABLE()\
do {\
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 & (~ BIT(23))); \
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 | (BIT(17))); \
} while(0)
#define VCCFLS_PG_ENABLE()\
do {\
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 | BIT(23)); \
} while(0)
#define pmu_efuse_program_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(31))
#define pmu_efuse_program_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(31))
#define pmu_vcam_lc_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(29))
#define pmu_vcam_lc_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(29))
#define pmu_vcam_pg_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(16))
#define pmu_vcam_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(16))
#define pmu_vcam_oc_detect_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(15))
#define pmu_vcam_oc_detect_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(15))
#define pmu_vcam_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(14))
#define pmu_vcam_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(14))
#define pmu_vcam_discharge_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(13))
#define pmu_vcam_discharge_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(13))
/* CORE_PNDCLR */
#define pmu_vcam2_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(30))
#define pmu_vcc18_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(29))
#define pmu_vcam_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(22))
#define pmu_vcc15_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(13))
#define pmu_vdd_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(12))
enum vcam_vol_level {
VCAM_VOL_2V50,
VCAM_VOL_2V55,
VCAM_VOL_2V60,
VCAM_VOL_2V65,
VCAM_VOL_2V70,
VCAM_VOL_2V75,
VCAM_VOL_2V80,
VCAM_VOL_2V85,
VCAM_VOL_2V90,
VCAM_VOL_2V95,
VCAM_VOL_3V00,
VCAM_VOL_3V05,
VCAM_VOL_3V10,
VCAM_VOL_3V15,
VCAM_VOL_3V20,
VCAM_VOL_3V25,
};
#define pmu_set_vcam_vol(vcam_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON11, 0x01e00000, vcam_vol_level, 21)
enum vcam_oc_level {
VCAM_OC_750MA,
VCAM_OC_300MA,
VCAM_OC_200MA,
VCAM_OC_100MA,
};
#define pmu_vcam_oc_set(vcam_oc_level) PMU_REG_SET_VALUE(PMU->PMUCON11, 0x00000600, vcam_oc_level, 9)
/* CORE_RFCON0 */
#define pmu_xo_cs_set(xo_cs_vdd) PMU_REG_SET_VALUE(PMU->RFCON0, 0x03f80000, xo_cs_vdd, 19)
#define xo_set_cs_sec(xo_cs_vdd) pmu_xo_cs_set(xo_cs_vdd)
#define pmu_xosc_en() PMU_REG_SET_BITS(PMU->RFCON0, BIT(0))
#define pmu_xosc_dis() PMU_REG_CLR_BITS(PMU->RFCON0, BIT(0))
enum vcc_ldo_vol_level {
VCC_LDO_VOL_1V00,
VCC_LDO_VOL_1V05,
VCC_LDO_VOL_1V10,
VCC_LDO_VOL_1V15,
VCC_LDO_VOL_1V20,
VCC_LDO_VOL_1V25,
VCC_LDO_VOL_1V30,
VCC_LDO_VOL_1V35,
VCC_LDO_VOL_1V40,
VCC_LDO_VOL_1V45,
VCC_LDO_VOL_1V50,
VCC_LDO_VOL_1V55,
VCC_LDO_VOL_1V60,
VCC_LDO_VOL_1V65,
VCC_LDO_VOL_1V70,
VCC_LDO_VOL_1V75,
VCC_LDO_VOL_1V80,
VCC_LDO_VOL_1V85,
VCC_LDO_VOL_1V90,
VCC_LDO_VOL_1V95,
VCC_LDO_VOL_2V00,
VCC_LDO_VOL_2V05,
VCC_LDO_VOL_2V10,
VCC_LDO_VOL_2V15,
VCC_LDO_VOL_2V20,
VCC_LDO_VOL_2V25,
VCC_LDO_VOL_2V30,
VCC_LDO_VOL_2V35,
VCC_LDO_VOL_2V40,
VCC_LDO_VOL_2V45,
VCC_LDO_VOL_2V50,
VCC_LDO_VOL_2V55,
};
struct system_reset_pending_bits {
uint32 srp_mclr : 1, /* mclr pin reset */
srp_soft : 1, /* cpu0 mcu reset */
srp_wdt : 1, /* cpu0 watchdog reset */
srp_lp_wdt : 1, /* lowpower watchdog reset */
srp_wdt1 : 1, /* cpu1 watchdog reset */
srp_soft1 : 1, /* cpu1 mcu reset */
Reserved0 : 2,
srp_lvd : 1, /* vcc lower voltage reset */
srp_lvd_vcam_cur_ov : 1,/* vcam over-current */
srp_lvd_vcc15_cur_ov : 1,/* vcc15 over-current */
srp_lvd_vdd_cur_ov : 1, /* vdd over-current */
srp_lvd_vdd_vol_low : 1, /* vdd voltage low */
srp_lvd_vcc_vol_low : 1, /* vcc voltage low */
srp_lvd_vcc1_vol_low : 1, /* vcc1 voltage low */
srp_lvd_vcc15_vol_low : 1, /* vcc15 voltage low */
srp_deep_sleep : 1,
srp_lvd_vdd18_cur_ov : 1, /* vdd18 over-current */
srp_lvd_vcam2_cur_ov : 1, /* vcam2 over-current */
Reserved : 13;
};
struct system_reset_info {
union {
uint32 system_reset_pending;
struct system_reset_pending_bits system_reset_pending_bits_s;
};
} __attribute__((packed));
extern struct system_reset_info sri;
void pmu_reg_write(uint32 reg_addr, uint32 data) ;
void pmu_dcdc_open(void);
void pmu_vccfls_power_set(uint32 power_on, uint32 suply_3p3v);
/* PC[8:13] power domain : VCC or VCC18 */
void pmu_vccsd_power_set(uint32 power_on, uint32 suply_3p3v);
int32 pmu_vdd18_ldo_en(uint32 en, enum vcc_ldo_vol_level vol);
int pmu_is_vdd18_ldo_en(void);
int pmu_get_vdd18_ldo_vol(void);
/**
* strongly recommend vol same with vcc18 when power for mipi sensor
*/
int32 pmu_vcam2_ldo_en(uint32 en, enum vcc_ldo_vol_level vol);
int pmu_is_vcam2_ldo_en(void);
int pmu_get_vcam2_ldo_vol(void);
void pmu_tsensor_chan_sel_sec(uint8 chan_idx);
void pmu_pd_set_anatop_en_sec(void);
int jtag_map_set(uint8 val);
void tsensor_open(void);
void tsensor_close(void);
void lvd_irq_handler(void *data);
void sys_reset_detect(void);
void sys_reset_pending_clr(void);
void sys_reset_show(void);
void pmu_vdd_core_set(uint32 vddcore);
#ifdef __cplusplus
}
#endif
#endif //__PMU_H__
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/

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#ifndef _TXW82X_RPC_FUNCID_H_
#define _TXW82X_RPC_FUNCID_H_
#define RPC_FUNC_ID(f) RPC_FUNCID_##f
enum CPU0_RPC_FUNCID {
RPC_FUNC_ID(sys_wifi_register) = 2, /*ID 1 空出来*/
RPC_FUNC_ID(sys_wifi_recv),
RPC_FUNC_ID(sys_event_new),
RPC_FUNC_ID(sys_wifi_event_cb),
RPC_FUNC_ID(atcmd_recv),
//BT
RPC_FUNC_ID(hci_host_recv),
//lvgl
RPC_FUNC_ID(lvgl_frame_rotate_rpc_sync),
/////////////////////////////////
CPU0_RPC_FUNCID_NUM,
};
enum CPU1_RPC_FUNCID {
RPC_FUNC_ID(sys_enter_sleep), //SLEEP: 固定为 ID 1
RPC_FUNC_ID(cpu1_run_func),
RPC_FUNC_ID(cpu1_atcmd_recv),
RPC_FUNC_ID(lmac_ioctl_rpc),
RPC_FUNC_ID(skbpool_add_region),
RPC_FUNC_ID(ieee80211_deliver_init),
RPC_FUNC_ID(ieee80211_iface_create_ap),
RPC_FUNC_ID(ieee80211_iface_create_sta),
RPC_FUNC_ID(ieee80211_iface_start),
RPC_FUNC_ID(ieee80211_iface_stop),
RPC_FUNC_ID(ieee80211_pairing),
RPC_FUNC_ID(ieee80211_unpair),
RPC_FUNC_ID(ieee80211_scan),
RPC_FUNC_ID(ieee80211_scatter_tx),
RPC_FUNC_ID(ieee80211_tx),
RPC_FUNC_ID(ieee80211_input),
RPC_FUNC_ID(ieee80211_tx_mgmt),
RPC_FUNC_ID(ieee80211_tx_custmgmt),
RPC_FUNC_ID(ieee80211_tx_ether),
RPC_FUNC_ID(ieee80211_disassoc),
RPC_FUNC_ID(ieee80211_disassoc_all),
RPC_FUNC_ID(ieee80211_hook_ext_data),
RPC_FUNC_ID(ieee80211_cleanup_bsslist),
RPC_FUNC_ID(ieee80211_get_bsslist),
RPC_FUNC_ID(ieee80211_get_stalist),
RPC_FUNC_ID(ieee80211_conf_set_bssbw),
RPC_FUNC_ID(ieee80211_conf_get_bssbw),
RPC_FUNC_ID(ieee80211_conf_set_chanlist),
RPC_FUNC_ID(ieee80211_conf_set_ssid),
RPC_FUNC_ID(ieee80211_conf_get_ssid),
RPC_FUNC_ID(ieee80211_conf_set_keymgmt),
RPC_FUNC_ID(ieee80211_conf_get_keymgmt),
RPC_FUNC_ID(ieee80211_conf_set_psk),
RPC_FUNC_ID(ieee80211_conf_set_passwd),
RPC_FUNC_ID(ieee80211_conf_get_psk),
RPC_FUNC_ID(ieee80211_conf_set_beacon_int),
RPC_FUNC_ID(ieee80211_conf_set_dtim_int),
RPC_FUNC_ID(ieee80211_conf_set_bssid),
RPC_FUNC_ID(ieee80211_conf_get_bssid),
RPC_FUNC_ID(ieee80211_conf_set_channel),
RPC_FUNC_ID(ieee80211_conf_get_channel),
RPC_FUNC_ID(ieee80211_conf_get_mac),
RPC_FUNC_ID(ieee80211_conf_set_mac),
RPC_FUNC_ID(ieee80211_conf_set_bss_max_idle),
RPC_FUNC_ID(ieee80211_conf_get_connstate),
RPC_FUNC_ID(ieee80211_conf_get_wkreason),
RPC_FUNC_ID(ieee80211_conf_wakeup_sta),
RPC_FUNC_ID(ieee80211_conf_get_txpower),
RPC_FUNC_ID(ieee80211_conf_set_heartbeat_int),
RPC_FUNC_ID(ieee80211_conf_set_aplost_time),
RPC_FUNC_ID(ieee80211_conf_set_acs),
RPC_FUNC_ID(ieee80211_conf_set_wmm_enable),
RPC_FUNC_ID(ieee80211_conf_set_use4addr),
RPC_FUNC_ID(ieee80211_conf_get_stainfo),
RPC_FUNC_ID(ieee80211_conf_get_stalist),
RPC_FUNC_ID(ieee80211_conf_get_sta_snr),
RPC_FUNC_ID(ieee80211_conf_get_stacnt),
RPC_FUNC_ID(ieee80211_conf_set_aphide),
RPC_FUNC_ID(ieee80211_conf_get_bgrssi),
RPC_FUNC_ID(ieee80211_conf_set_mcast_txrate),
RPC_FUNC_ID(ieee80211_conf_set_hwmode),
RPC_FUNC_ID(ieee80211_conf_set_psdata_cnt),
RPC_FUNC_ID(ieee80211_conf_set_wmm_param),
RPC_FUNC_ID(ieee80211_conf_get_wmm_param),
RPC_FUNC_ID(ieee80211_conf_set_wpa_group_rekey),
RPC_FUNC_ID(ieee80211_conf_set_datatag),
RPC_FUNC_ID(ieee80211_conf_get_ant_sel),
RPC_FUNC_ID(ieee80211_conf_get_reason_code),
RPC_FUNC_ID(ieee80211_conf_get_status_code),
RPC_FUNC_ID(ieee80211_conf_get_rtc),
RPC_FUNC_ID(ieee80211_conf_get_acs_result),
RPC_FUNC_ID(ieee80211_conf_set_rtc),
RPC_FUNC_ID(ieee80211_conf_set_radio_onoff),
RPC_FUNC_ID(ieee80211_conf_set_isolate),
RPC_FUNC_ID(ieee80211_conf_set_ft),
RPC_FUNC_ID(ieee80211_pair_enable),
RPC_FUNC_ID(hci_controller_recv),
RPC_FUNC_ID(audio_coder_run),
RPC_FUNC_ID(lvgl_frame_rotate_rpc_init),
RPC_FUNC_ID(lvgl_frame_rotate_rpc),
RPC_FUNC_ID(ieee80211_conf_set_pair_ngo),
RPC_FUNC_ID(ieee80211_conf_set_mutl_pair),
RPC_FUNC_ID(ieee80211_conf_set_linkcost_param),
RPC_FUNC_ID(ieee80211_conf_set_pair_channel),
RPC_FUNC_ID(ieee80211_conf_get_tx_mcs),
RPC_FUNC_ID(ieee80211_conf_set_tx_mcs),
RPC_FUNC_ID(cpu1_new_task),
/////////////////////////////////
CPU1_RPC_FUNCID_NUM,
};
#endif

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sdk/include/chip/txw82x/test_atcmd.h Normal file
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#ifndef _TXW82X_TEST_ATCMD_H_
#define _TXW82X_TEST_ATCMD_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 atcmd_reg_rd_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_reg_wt_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_test_start_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_test_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_temp_en_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_type_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_rf_pwr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_pha_amp_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_step_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_cont_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_start_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_trig_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_frm_type_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_mcs_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_lo_freq_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_cw_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_aifs_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_txop_hdl(const char *cmd, char *argv[], uint32 argc);
int32 at_cmd_cfg_rx_agc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_lmac_print_period_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_bss_bw_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 at_cmd_cca_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_wave_dump_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_cca_cert_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_srrc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_dbg_level_hdl(const char *cmd, char *argv[], uint32 argc);
int32 sys_atcmd_reset(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_sleep_dbg_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_sleep_alg_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_sleep_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_dtim_hdl(const char *cmd, char *argv[], uint32 argc);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/chip/txw82x/txw82x.h Normal file
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#ifndef _TXW82X_DEF_H_
#define _TXW82X_DEF_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/////////////////////////////////////////////////////////////////////////////////
#define RETURN_ADDR() __builtin_return_address(0)
#define cpu_dcache_disable() csi_dcache_clean_invalid(); csi_dcache_disable();
#define cpu_dcache_enable() csi_dcache_enable()
typedef signed char int8;
typedef signed short int16;
typedef signed int int32;
typedef signed long long int64;
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
typedef unsigned long long uint64;
typedef unsigned long ulong;
#ifndef _SIZE_T_DECLARED
typedef unsigned int size_t;
#define _SIZE_T_DECLARED
#endif
#ifndef _SSIZE_T_DECLARED
#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
typedef int ssize_t;
#else
typedef long ssize_t;
#endif
#define _SSIZE_T_DECLARED
#endif
/////////////////////////////////////////////////////////////////////////////////
/* ------------------------- Interrupt Number Definition ------------------------ */
enum IRQn {
/****** Peripheral Interrupt Numbers *********************************************************/
USB20DMA_IRQn = 0,
USB20MC_IRQn = 1,
UART0_IRQn = 2,
UART1_IRQn = 3,
LCD_IRQn = 4,
QSPI_IRQn = 5,
SPI0_IRQn = 6,
SPI1_IRQn = 7,
SPI2_IRQn = 8,
OSPI_IRQn = 9,
TIM0_IRQn = 10,
TIM1_IRQn = 11,
TIM2_IRQn = 12,
TIM3_IRQn = 13,
SCALE1_IRQn = 14,
AUDIO_SUBSYS2_IRQn = 15,//Swap the position of number 2 with number 0 ,
AUDIO_SUBSYS1_IRQn = 16,//To keep consist with rtl design
AUDIO_SUBSYS0_IRQn = 17,//
SDIO_IRQn = 18,
SDHOST1_IRQn = 19,
SDHOST_IRQn = 20,
LMAC_IRQn = 21,
GMAC_IRQn = 22,
DUAL_ORG_IRQn = 23,
GEN422_IRQn = 24,
CORET_IRQn = 25, //CPU TIMER
SHA_IRQn = 26, //SHA/SYS_AES
CRC_IRQn = 27,
ADKEY0_IRQn = 28,
PD_TMR_IRQn = 29,
WKPND_IRQn = 30,
PDWKPND_IRQn = 31,
LVD_IRQn = 32,
WDT_IRQn = 33,
SYS_ERR_IRQn = 34,
IIS0_IRQn = 35,
IIS1_IRQn = 36,
GPIOA_IRQn = 37,
LO_MNT_IRQn = 38,
DVP_IRQn = 39,
MJPEG01_IRQn = 40,
H264ENC_IRQn = 41,
VPP_IRQn = 42,
PRC_IRQn = 43,
STMR5_IRQn = 44,
PDM_IRQn = 45,
LED_TMR_IRQn = 46,
SCALE2_IRQn = 47,
GFSK_IRQn = 48,
CMPOUT0_IRQn = 49,
UART6_IRQn = 50,
SCALE3_IRQn = 51,
IMG_ISP_IRQn = 52,
MIPI_CSI2_IRQn = 53,
RF_IRQn = 54,
USB11_MC_IRQn = 55,
USB11_DMA_IRQn = 56,
RTC_VCCHVD_IRQn = 57,
RTC_IRQn = 58,
MIPI_DSI_IRQn = 59,
PARA_OUT_IRQn = 60,
M2M_DMA0_IRQn = 61,
CAN_IRQn = 62,
EXT_DCACHE_IRQn = 63,
CPU_SPINLOCK_IRQn = 64,
CPU_RECV_MAIL_IRQn = 65,
CPU_SEND_MAIL_IRQn = 66,
CPU_DBG_ON_IRQn = 67,
OSPI_FIFO_IRQn = 68,
OSPI_EFF_IRQn = 69,
GEN420_IRQn = 70,
SYS_AES_IRQn = 71,
PKA_IRQn = 72,
WDT1_IRQn = 73,
GPIOB_IRQn = 74,
GPIOC_IRQn = 75,
GPIOD_IRQn = 76,
GPIOE_IRQn = 77,
GPIOF_IRQn = 78,
DVP1_IRQn = 79,
PNG_IRQn = 80,
STMR4_IRQn = 81,
STMR3_IRQn = 82,
STMR2_IRQn = 83,
STMR1_IRQn = 84,
STMR0_IRQn = 85,
CMPOUT1_IRQn = 86,
UART5_IRQn = 87,
UART4_IRQn = 88,
MIPI1_CSI2_IRQn = 89,
DMA2D_IRQn = 90,
CSC_IRQn = 91,
OSD_ENC_IRQn = 92,
USB20PHY_IRQn = 93,
PARA_IN_IRQn = 94,
M2M_DMA1_IRQn = 95,
WKUP_IRQn = 96,
SAM_IRQn = 97,
LIN_IRQn = 98,
LIN1_IRQn = 99,
CPU_SOFT_INT_IRQn = 100,
M2M_DMA2_IRQn = 105,
IRQ_NUM,
};
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the CK804 Processor and Core Peripherals ------- */
#define __CK803_REV 0x0000U /* Core revision r0p0 */
#define __CK804_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0 /* MGU present or not */
#define __VIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include "csi_core.h" /* Processor and core peripherals */
#include "stdint.h"
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define PSRAM_BASE_I ((uint32_t)0x08000000) /*!< SRAM base address in the alias region */
#define PSRAM_END_ADDR_I ((uint32_t)0x10000000) /*!< SRAM end address in the alias region */
#define FLASH_BASE ((uint32_t)0x10000000) /*!< FLASH base address in the alias region */
#define FLASH_END_BASE ((uint32_t)0x20000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define DCACHE_CTRL_BASE ((uint32_t)0x50000000)
#define PSRAM_BASE ((uint32_t)0x28000000) /*!< SRAM base address in the alias region */
#define PSRAM_END_ADDR ((uint32_t)0x30000000) /*!< SRAM end address in the alias region */
/*!< Peripheral memory map */
#define APB0_BASE PERIPH_BASE
#define APB1_BASE (PERIPH_BASE + 0x10000)
#define APB2_BASE (PERIPH_BASE + 0xc0000)
#define AHB_BASE (PERIPH_BASE + 0x20000)
#define GPIO_BASE (PERIPH_BASE + 0xe0000)
#define SYSCTRL_BASE (AHB_BASE + 0x0000)
#define CPUDBG_BASE (AHB_BASE + 0x0280)
#define GPIOA_BASE (GPIO_BASE + 0x0000)
#define GPIOB_BASE (GPIO_BASE + 0x0100)
#define GPIOC_BASE (GPIO_BASE + 0x0200)
#define GPIOD_BASE (GPIO_BASE + 0x0300)
#define GPIOE_BASE (GPIO_BASE + 0x0400)
#define GPIOF_BASE (GPIO_BASE + 0x0500)
#define SYS_MNT_BASE (AHB_BASE + 0x023c)
#define SDHOST_BASE (0x40040048)
#define SDHOST1_BASE (0x40040068)
#define SDIO_HOST_BASE (AHB_BASE + 0x3000) //not used
#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
#define LMAC_BASE (AHB_BASE + 0x42000)
#define USB11S_BASE (PERIPH_BASE + 0x70000)
#define GMAC_BASE (PERIPH_BASE + 0x71000)
#define MODEM_BASE (PERIPH_BASE + 0xd0000)
#define USB20_BASE (PERIPH_BASE + 0xf0000)
//#define DMAC_BASE (AHB_BASE + 0x0000)
//#define GPIOA_BASE (AHB_BASE + 0x2000)
//#define GPIOB_BASE (AHB_BASE + 0x5000)
//#define SYS_MNT_BASE (AHB_BASE + 0x9000)
//-------------------------------------------------------
// APB0 SYNC CLK DOMAIN PERIS
//-------------------------------------------------------
#define QSPI_BASE (APB0_BASE + 0x0000)
#define OSPI_BASE (APB0_BASE + 0x1000)
#define SCHED_BASE (APB0_BASE + 0x2000)
#define UART0_BASE (APB2_BASE + 0x0000)
#define UART1_BASE (APB2_BASE + 0x0100)
#define UART2_BASE (APB2_BASE + 0x0200)
#define UART3_BASE (APB2_BASE + 0x0300)
#define UART4_BASE (APB2_BASE + 0x0b70)
#define UART5_BASE (APB2_BASE + 0x0b90)
#define UART6_BASE (APB2_BASE + 0x0bb0)
#define SPI0_BASE (APB0_BASE + 0x7400)
#define SPI1_BASE (APB0_BASE + 0x7500)
#define SPI2_BASE (APB2_BASE + 0x0600)
#define SPI3_BASE (APB2_BASE + 0x0700)
#define SPI4_BASE (APB2_BASE + 0x0800)
#define SPI5_BASE (APB2_BASE + 0x0b20)
#define SPI6_BASE (APB2_BASE + 0x0b38)
#define LED_BASE (APB0_BASE + 0x4b50)
#define IIC0_BASE (APB0_BASE + 0x7400)
#define IIC1_BASE (APB0_BASE + 0x7500)
#define IIC2_BASE (APB2_BASE + 0x0600)
#define IIC3_BASE (APB2_BASE + 0x0700)
#define IIC4_BASE (APB2_BASE + 0x0800)
#define IIS0_BASE (APB2_BASE + 0x3400)
#define IIS1_BASE (APB2_BASE + 0x3440)
#define PDM_BASE (APB2_BASE + 0x3480)
#define PRC_BASE (APB0_BASE + 0x5000)
#define OF_BASE (APB0_BASE + 0x5020)
#define FT_BASE (APB0_BASE + 0x5040)
#define PALE_BASE (APB0_BASE + 0x5060)
#define VPP_BASE (APB0_BASE + 0x5100)
#define MJPEG0_BASE (APB0_BASE + 0x5200)
#define MJPEG0_DQT_BASE (APB0_BASE + 0x5280)
#define MJPEG1_BASE (APB0_BASE + 0x5300)
#define CSI2_HOST_BASE (APB0_BASE + 0x5700)
#define MJPEG0_TAB_BASE (APB0_BASE + 0x5280)
#define MJPEG1_TAB_BASE (APB0_BASE + 0x5380)
#define MJPEG_HUFF_BASE (APB0_BASE + 0x5400)
#define PARA_OUT_BASE (APB0_BASE + 0x6000)
#define PARA_IN_BASE (APB0_BASE + 0x6040)
#define DVP_BASE (APB0_BASE + 0x6070)
#define DVP1_BASE (APB0_BASE + 0x6088)
#define GEN422_BASE (APB0_BASE + 0x60a0)
#define GEN420_BASE (APB0_BASE + 0x60e0)
#define DUAL_ORG_BASE (APB0_BASE + 0x6110)
#define MIPI_DSI_BASE (APB0_BASE + 0x6200)
#define MIPI_CSI0_BASE (APB0_BASE + 0x6400)
#define MIPI_CSI1_BASE (APB0_BASE + 0x6600)
#define SCALE1_BASE (APB0_BASE + 0x7100)
#define LCDC_BASE (APB0_BASE + 0x7000)
#define ROT_BASE (APB1_BASE + 0xc140)
#define FILL_BASE (APB1_BASE + 0xc180)
#define CSC_BASE (APB1_BASE + 0xc200)
#define OSD_ENC_BASE (APB1_BASE + 0xc240)
#define SHADOW_BASE (APB1_BASE + 0xc280)
#define TRANSFORM_BASE (APB1_BASE + 0xc300)
#define SCALE2_BASE (APB0_BASE + 0x71A0)
#define SCALE3_BASE (APB0_BASE + 0x7200)
#define AUDIO_BASE (APB2_BASE + 0x3000)
#define COMP_BASE (APB0_BASE + 0x9000)
#define EFUSE_BASE (APB0_BASE + 0xa000)
#define LO_MNT_BASE (APB2_BASE + 0x3740)
#define AUDIO_DSP (APB2_BASE + 0x3600)
#define CAN_RBUF_BASE (APB2_BASE + 0x4000)
#define CAN_TBUF_BASE (APB2_BASE + 0x4050)
#define CAN_CTRL_BASE (APB2_BASE + 0x4098)
#define CAN_ACF_BASE (APB2_BASE + 0x40b8)
#define FPGA_DDR_BASE (APB0_BASE + 0xf000)
#define H264_REG_BASE (APB1_BASE + 0x1000)
#define RFADCDIG_BASE (APB1_BASE + 0x4000)
#define WDT_BASE (APB2_BASE + 0x1000)
#define WDT1_BASE (APB2_BASE + 0x1010)
#define TIMER_ALL_BASE (APB2_BASE + 0x1128)
#define TIMER0_BASE (APB2_BASE + 0x1100)
#define TIMER1_BASE (APB2_BASE + 0x1200)
#define TIMER2_BASE (APB2_BASE + 0x1300)
#define TIMER3_BASE (APB2_BASE + 0x1400)
#define TIMER4_BASE (APB2_BASE + 0x1500)
#define SUPTMR_BASE (APB2_BASE + 0x1600)
#define SIMPLE_TIMER0_BASE (APB2_BASE + 0x1b00)
#define SIMPLE_TIMER1_BASE (APB2_BASE + 0x1b10)
#define SIMPLE_TIMER2_BASE (APB2_BASE + 0x1b20)
#define SIMPLE_TIMER3_BASE (APB2_BASE + 0x1b30)
#define SIMPLE_TIMER4_BASE (APB2_BASE + 0x1b40)
#define SIMPLE_TIMER5_BASE (APB2_BASE + 0x1b50)
#define CRC_BASE (APB1_BASE + 0x2000)
#define SYS_AES_BASE (APB1_BASE + 0x2100)
#define SHA_BASE (APB1_BASE + 0X2200)
#define IMAGE_ISP_BASE (APB1_BASE + 0x6000)
#define ISP_LSC_BASE (APB1_BASE + 0x6300)
#define ISP_R_GAMMA_BASE (APB1_BASE + 0x6400)
#define ISP_G_GAMMA_BASE (APB1_BASE + 0x6500)
#define ISP_B_GAMMA_BASE (APB1_BASE + 0x6600)
#define ISP_Y_GAMMA_BASE (APB1_BASE + 0x6700)
#define ISP_R_HIST_BASE (APB1_BASE + 0x6800)
#define ISP_G_HIST_BASE (APB1_BASE + 0x6900)
#define ISP_B_HIST_BASE (APB1_BASE + 0x6a00)
#define ISP_Y_HIST_BASE (APB1_BASE + 0x6b00)
#define PMU_BASE (APB1_BASE + 0x8000)
#define LVD_BASE (APB1_BASE + 0x8000)
#define RTC_BASE (APB1_BASE + 0x8000)
#define RFDIG_BASE (APB1_BASE + 0x9000)
#define ADKEY_BASE (APB2_BASE + 0x2000)
#define CMP_BASE (APB1_BASE + 0xa020)
#define ADKEY1_BASE (APB1_BASE + 0xa024)
#define USB11_BASE (APB1_BASE + 0xb000)
#define DMA2D_BASE (APB1_BASE + 0xc000)
#define DMA2D_FGCLUT_BASE (APB1_BASE + 0xc800)
#define DMA2D_BGCLUT_BASE (APB1_BASE + 0xcc00)
#define RFDIGCAL_BASE (APB1_BASE + 0xd000)
#define NPU_BASE (APB1_BASE + 0xe000)
#define SYSCTRL_BASE (AHB_BASE + 0x0000)
#define GPIOA_BASE (GPIO_BASE + 0x0000)
#define GPIOB_BASE (GPIO_BASE + 0x0100)
#define GPIOC_BASE (GPIO_BASE + 0x0200)
#define GPIOD_BASE (GPIO_BASE + 0x0300)
#define GPIOE_BASE (GPIO_BASE + 0x0400)
#define GPIOF_BASE (GPIO_BASE + 0x0500)
#define AUDIO_CORDIC_BASE (AUDIO_BASE+ 0x500)
#define AUDIO_DSP_FLT_BASE (AUDIO_BASE+ 0x600)
#define AUDIO_EQ_BASE (AUDIO_BASE+ 0x700)
#define AUDIO_ASRC_BASE (AUDIO_BASE+ 0x710)
#define AUDIO_DRC_BASE (AUDIO_BASE+ 0x720)
#define M2M_DMA_BASE (0x40040000)
#define M2M_DMA0_BASE (M2M_DMA_BASE + 0x00)
#define M2M_DMA1_BASE (M2M_DMA_BASE + 0x18)
#define M2M_DMA2_BASE (M2M_DMA_BASE + 0x30)
#define SYS_MNT_BASE (AHB_BASE + 0x023c)
#define SDHOST_BASE (0x40040048)
#define SDHOST1_BASE (0x40040068)
#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
#define MODEM_BASE (PERIPH_BASE + 0xd0000)
#define LMAC_BASE (AHB_BASE + 0x42000)
#define GMAC_BASE (PERIPH_BASE + 0x71000)
#define USB20_BASE (PERIPH_BASE + 0xf0000)
#define FT_USB3_BASE (APB0_BASE + 0x5040)
#define LED_TIMER0_BASE (PMU_BASE + 0x000d0)
#define LED_TIMER1_BASE (PMU_BASE + 0x000d4)
#define LED_TIMER2_BASE (PMU_BASE + 0x000d8)
#define LED_TIMER3_BASE (PMU_BASE + 0x000dc)
#define CPU0_MSGBOX_BASE (0x80001000)
#define CPU0_SPLCK_BASE (0x80001060)
#define CPU1_MSGBOX_BASE (0x80000000)
#define CPU1_SPLCK_BASE (0x80000060)
#define CORESETTING_BASE (0x2006bf00)
typedef enum {
HG_AHB_PT_ALL,
HG_AHB_PT_GPIOA_DEBUNCE,
HG_AHB_PT_GPIOB_DEBUNCE,
HG_AHB_PT_GPIOC_DEBUNCE,
HG_AHB_PT_M2M_DMA,
HG_AHB_PT_SYS_MNT,
HG_AHB_PT_SDMMC,
HG_AHB_PT_SDIO,
HG_AHB_PT_MODEM,
HG_AHB_PT_LMAC,
HG_AHB_PT_GMAC,
HG_AHB0_PT_DISPLAY, //scale0/2/3,rotate,screenshot,osd0,gama,dither,lcd_if,ccm_constrast_saturation,alpha_blend,video
HG_AHB0_PT_VEDIO_IF, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
HG_APB0_PT_ALL,
HG_AHB0_PT_H264, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
HG_APB0_PT_QSPI,
HG_APB0_PT_OSPI,
HG_APB0_PT_UART0,
HG_APB0_PT_UART1,
HG_APB0_PT_UART4,
HG_APB0_PT_UART5,
HG_APB0_PT_UART6,
HG_APB0_PT_SPI0,
HG_APB0_PT_SPI1,
HG_APB0_PT_SPI2,
HG_APB0_PT_SPI3,
HG_APB0_PT_SPI5,
HG_APB0_PT_SPI6,
HG_APB0_PT_LED,
HG_APB0_PT_IIC0,
HG_APB0_PT_IIC1,
HG_APB0_PT_IIC2,
HG_APB0_PT_IIC3,
HG_APB0_PT_IIS0,
HG_APB0_PT_IIS1,
HG_APB0_PT_PDM,
HG_APB0_PT_JPEG,
HG_APB0_PT_DVP,
HG_APB0_PT_CMP,
HG_APB0_PT_EFUSE,
HG_APB1_PT_ALL,
HG_APB1_PT_AES,
HG_APB1_PT_ISP,
HG_APB1_PT_TMR0,
HG_APB1_PT_TMR1,
HG_APB1_PT_TMR2,
HG_APB1_PT_TMR3,
HG_APB1_PT_STMR,
HG_APB1_PT_SUPTMR,
HG_APB1_PT_CRC,
HG_APB1_PT_PMU,
HG_APB1_PT_LVD,
HG_APB1_PT_ADKEY,
HG_ASYNC_APB1_PT_AUDIO_SUB, //adc,dac,iis0/1,pdm,cordic,hs,sync,vad
} HG_Peripheral_Type;
typedef enum {
CPU_SPLOCK_ID_0,
CPU_SPLOCK_ID_1,
CPU_SPLOCK_ID_2,
CPU_SPLOCK_ID_3,
CPU_SPLOCK_ID_4,
CPU_SPLOCK_ID_5,
CPU_SPLOCK_ID_6,
CPU_SPLOCK_ID_7,
CPU_SPLOCK_ID_8,
CPU_SPLOCK_ID_9,
CPU_SPLOCK_ID_10,
CPU_SPLOCK_ID_11,
CPU_SPLOCK_ID_12,
CPU_SPLOCK_ID_13_DMA2D,
CPU_SPLOCK_ID_14_EFUSE,
CPU_SPLOCK_ID_15_DCACHE,
CPU_SPLOCK_ID_MAX,
} CPU_SPLOCK_ID;
#define EFUSE_OFFSET 3
#define JPG_NUM 2
#define OSC_CLK 32000000UL
#define JPG_NUM 2
#define CPU_CYCLE_VALUE() csi_coret_get_value()
#define IS_DCACHE_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
#define IS_PSRAM_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
#define IS_FLASH_ADDR(addr) ((uint32_t)(addr) >= FLASH_BASE && (uint32_t)(addr) < FLASH_END_BASE)
#define IS_SRAM_ADDR(addr) ((uint32_t)(addr) >= SRAM_BASE && (uint32_t)(addr) < PSRAM_BASE)
typedef struct {
uint32_t crc32;
volatile uint8 cpu1_ready;
volatile uint8 soft_int_pending;
uint8_t print_level;
uint8_t disable_print:1, dcache_maint_en:1, afh_en:1, rev:5;
uint8_t vif_maxcnt;
uint8_t bss_maxcnt;
uint16_t dbg_flags;
uint16_t sta_maxcnt;
uint16_t bss_lifetime;
uint32_t dbg_uart_dev;
uint32_t m2m_dma_dev;
uint32_t wdt1_to;
void * wdt1_irq_hdl;
uint32_t adc_dev;
uint32_t cpu_clk;
uint32_t rxbuf_addr;
uint32_t rxbuf_size;
uint32_t heap_addr;
uint32_t heap_size;
uint32_t skbpool_addr;
uint32_t skbpool_size;
uint32_t skbpool_flag;
uint32_t heap_flag;
uint32_t afh_chan_mask;
uint32_t psram_rsv_addr_core0;
} txw82x_CoreSetting;
#define CoreSetting ((txw82x_CoreSetting *) CORESETTING_BASE)
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HUGEIC_DEV_H_
#define _HUGEIC_DEV_H_
#include "osal/atomic.h"
#ifdef __cplusplus
extern "C" {
#endif
struct dev_obj;
struct devobj_ops{
#ifdef CONFIG_SLEEP
int32 (*suspend)(struct dev_obj *obj);
int32 (*resume)(struct dev_obj *obj);
#endif
};
#ifndef OS_BLKLIST
#define OS_BLKLIST
struct os_blklist{
void *hdl;
};
typedef struct os_blklist os_blklist_t;
#endif
struct dev_obj{
uint16 dev_id;
uint8 busy; /* device 被使用状态，由驱动代码设置。
有8bit可用，驱动代码根据 read/write/... 设置不同的bit位 */
uint8 suspend: 1, /* device进入suspend状态，由dev_suspend API设置 */
hotplug: 1, /* 热插拔设备 */
rev: 6;
atomic8_t ref;
struct dev_obj *next;
#ifdef CONFIG_SLEEP
struct os_blklist blklist;
#endif
const struct devobj_ops *ops;
};
/*热插拔设备*/
struct dev_hotplug_obj{
struct dev_hotplug_obj *next;
void *hdl;
uint16 dev_id; //设备ID -> see devid.h
uint16 dev_type; //热插拔设备类型
void *info; //设备信息
};
typedef int32 (*dev_hotplug_walkcb)(const struct dev_hotplug_obj *dev);
int32 dev_hotplug_in(void *hdl, uint16 dev_id, uint16 dev_type, void *info);
int32 dev_hotplug_out(void *hdl);
int32 dev_hotplug_walk(uint16 type, dev_hotplug_walkcb cb);
#define DEV_BUSY(dev, val, set) dev_busy((struct dev_obj *)(dev), val, set)
#define DEV_SUSPENDED(dev, suspend) dev_suspended((struct dev_obj *)(dev), suspend)
#define HALDEV_SUSPENDED(dev) if(dev_suspended((struct dev_obj *)dev, 1)) return RET_ERR
/**
* dev core module initialize
* @return return RET_OK if initialize sucess, else return RET_ERR.
**/
extern int32 dev_init(void);
/**
* get dev by dev_id
* @param[in] dev_id device id
* @return return device object if device exist, else return NULL.
**/
extern struct dev_obj *dev_get(uint16 dev_id);
#define DEV_PUT(dev) dev_put((struct dev_obj *)(dev))
extern void dev_put(struct dev_obj *dev);
/*
* set or clear device busy flag.
*/
extern void dev_busy(struct dev_obj *dev, uint8 busy, uint8 set);
/**
* register device into dev manager.
* @param[in] dev_id device id.
* @param[in] device object to register.
* @return return RET_OK if register sucess, else return RET_ERR.
**/
extern int32 dev_register(uint16 dev_id, struct dev_obj *device);
/**
* unregister device into dev manager.
* @param[in] device object to unregister.
* @return return RET_OK if register sucess, else return RET_ERR.
**/
extern int32 dev_unregister(struct dev_obj *device);
/* 检查指定的device是否已经被suspend，
参数suspend：表示如果device已经被suspend，是否suspend当前task
*/
int32 dev_suspended(struct dev_obj *dev, uint8 suspend);
/**
* device suspend when system enter sleep.
* @param[in] dsleep sleep or deep sleep.
* @return return RET_OK if unregister sucess, else return RET_ERR.
**/
extern int32 dev_suspend(uint16 type);
extern int32 dev_suspend_hook(struct dev_obj *dev, uint16 type);
/**
* device resume when system resume.
* @return return RET_OK if unregister sucess, else return RET_ERR.
**/
extern int32 dev_resume(uint16 type, uint32 wkreason);
extern int32 dev_resume_hook(struct dev_obj *dev, uint16 type, uint32 wkreason);
extern int32 pin_func(uint16 dev_id, int32 request);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HGADC_V0_H
#define _HGADC_V0_H
#include "hal/adc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgadc_v0;
typedef struct _adc_channel_data {
/* pointer of config function */
int32 (*func)(struct hgadc_v0 *dev, uint32 channel, uint32 enable);
/* channel */
uint16 channel;
}adc_channel_data;
typedef struct _adc_channel_node {
/* data type */
adc_channel_data data;
/* for list opreation */
struct _adc_channel_node *next;
/* channel amount */
uint8 channel_amount;
}adc_channel_node;
struct hgadc_v0 {
struct adc_device dev;
uint32 hw;
adc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t adc_lock;
os_semaphore_t adc_done;
adc_channel_node head_node;
uint32 refer_vddi;
uint32 refer_vddi_adc_data;
uint32 refer_tsensor;
uint32 refer_adda_vref;
uint32 rf_vddi_en:1,
opened :1,
irq_en :1;
};
int32 hgadc_v0_attach(uint32 dev_id, struct hgadc_v0 *adc);
#ifdef __cplusplus
}
#endif
#endif

82
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#ifndef _HGADC_V1_H
#define _HGADC_V1_H
#include "hal/adc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgadc_v1;
typedef struct _adc_channel_data {
/* pointer of config function */
int32 (*func)(struct hgadc_v1 *dev, uint32 channel, uint32 enable);
/* channel */
uint16 channel;
/* sel for hw*/
uint32 sel;
uint16 sch_vdd;
}adc_channel_data;
typedef struct _adc_channel_node {
/* data type */
adc_channel_data data;
/* for list opreation */
struct _adc_channel_node *next;
/* channel amount */
uint8 channel_amount;
}adc_channel_node;
struct hgadc_v1 {
struct adc_device dev;
uint32 hw;
adc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t adc_lock;
os_semaphore_t adc_done;
adc_channel_node head_node;
adc_channel_node *cur_node;
uint32 refer_vddi;
uint32 refer_vddi_adc_data;
uint32 refer_tsensor;
uint32 refer_pmu_tsensor;
uint32 refer_adda_vref;
uint32 ref_temp;
int32 adkey_range;
uint32 rf_vddi_en:1,
opened :1,
irq_en :1;
};
struct hgadc_v1_hw;
void saradc_pri_channel_config(struct hgadc_v1_hw *hw, uint8 pri_chanx_en,uint8 pri_chan_sel,uint8 pri_trg_sel);
void saradc_pri_channel_clr_pending(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void saradc_pri_channel_kick(struct hgadc_v1_hw *hw);
uint16 saradc_pri_channel_get_pending(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void saradc_pri_channel_disable(struct hgadc_v1_hw *hw, uint8 pri_chanx_en);
uint16 saradc_pri_channel_get_raw_data(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void sar_adc_sample_one_channel(uint32 channel, uint32 *raw_data);
void saradc_channel_disable(struct hgadc_v1_hw *hw, uint8 chanx_en);
uint16 saradc_one_channel_single_kick(struct hgadc_v1_hw *hw);
uint16 saradc_channel_get_raw_data(struct hgadc_v1_hw *hw, uint8 chan_en);
uint16 saradc_channel_get_pending(struct hgadc_v1_hw *hw, uint8 chan_en);
void saradc_channel_config(struct hgadc_v1_hw *hw, uint8 chanx_en,uint8 smp_mode_sel,uint8 chan_sel,uint8 trg_sel);
void saradc_channel_clr_pending(struct hgadc_v1_hw *hw, uint8 chan_en);
int32 hgadc_v1_attach(uint32 dev_id, struct hgadc_v1 *adc);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _AUSYS_H
#define _AUSYS_H
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------
* AUSYS DA platform APIs
*----------------------------------*/
enum ausys_da_platform {
AUSYS_AUDA,
AUSYS_IIS0,
AUSYS_IIS1,
};
enum ausys_da_msg_type {
//FIFO empty message
AUSYS_DA_MSG_FIFO_FULL = BIT(0),
//FIFO full message
AUSYS_DA_MSG_FIFO_EMPTY = BIT(1),
//DA successfully play once
AUSYS_DA_MSG_PLAY_DONE = BIT(2),
//DA successfully play half
AUSYS_DA_MSG_PLAY_HALF = BIT(3),
};
struct ausys_da_msg_content {
uint32 fifo_next_addr;
uint32 fifo_next_len;
};
struct ausys_da_msg {
enum ausys_da_msg_type type;
struct ausys_da_msg_content da_content;
void *user_content;
};
int32 ausys_da_put(void* buf, uint32 bytes);
int32 ausys_da_play(void);
int32 ausys_da_change_sample_rate(uint32 sample_rate);
int32 ausys_da_change_volume(uint32 percent_0to100);
int32 ausys_da_get_cur_volume(uint32 *percent_0to100);
int32 ausys_da_register_msg(enum ausys_da_msg_type msg_type);
int32 ausys_da_unregister_msg(enum ausys_da_msg_type msg_type);
int32 ausys_da_get_msg(struct ausys_da_msg *msg, uint32 tmo_ms);
int32 ausys_da_ioctl(enum ausys_da_platform platform, uint32 cmd, uint32 arg0, uint32 arg1);
int32 ausys_da_deinit(void);
int32 ausys_da_init(
uint32 sample_rate,
uint32 sample_bits,
uint32 channel,
enum ausys_da_platform platform,
uint32 buf_bytes,
uint32 per_buf_bytes,
uint32 play_null_bytes
);
/*----------------------------------
* AUSYS AD platform APIs
*----------------------------------*/
enum ausys_ad_platform {
AUSYS_AUAD,
AUSYS_PDM,
AUSYS_IIS_SLAVER0,
AUSYS_IIS_SLAVER1,
};
enum ausys_ad_msg_type {
//AD successfully play once
AUSYS_AD_MSG_PLAY_DONE = BIT(0),
//AD successfully play half
AUSYS_AD_MSG_PLAY_HALF = BIT(1),
};
struct ausys_ad_msg_content {
uint32 fifo_next_addr;
uint32 fifo_next_len;
uint32 fifo_cur_addr;
uint32 fifo_cur_len;
};
struct ausys_ad_msg {
enum ausys_ad_msg_type type;
struct ausys_ad_msg_content ad_content;
void *user_content;
};
/*!
* type of user call back handle
*/
typedef void (*type_ausys_ad_user_cb)(void* buf, uint32 bytes, uint32 res);
int32 ausys_ad_record(enum ausys_ad_platform platform);
int32 ausys_ad_register_msg(enum ausys_ad_platform platform, enum ausys_ad_msg_type msg_type);
int32 ausys_ad_unregister_msg(enum ausys_ad_platform platform, enum ausys_ad_msg_type msg_type);
int32 ausys_ad_get_msg(enum ausys_ad_platform platform, struct ausys_ad_msg *msg, uint32 tmo_ms);
int32 ausys_ad_ioctl(enum ausys_ad_platform platform, uint32 cmd, uint32 arg0, uint32 arg1);
int32 ausys_ad_deinit(enum ausys_ad_platform platform);
int32 ausys_ad_init(
enum ausys_ad_platform platform,
uint32 sample_rate,
uint32 sample_bits,
uint32 channel,
uint32 buf_bytes,
uint32 per_buf_bytes,
type_ausys_ad_user_cb user_cb,
uint32 user_data
);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef __AUSYS_AD_H
#define __AUSYS_AD_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

21
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#ifndef __AUSYS_CONFIG_H
#define __AUSYS_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
*
*/
#ifdef __cplusplus
}
#endif
#endif

26
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#ifndef __AUSYS_DA_H
#define __AUSYS_DA_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
* DA platform test mode cmd
*/
enum ausys_da_test {
AUSYS_DA_TEST_OPEN,
AUSYS_DA_TEST_CLOSE,
AUSYS_DA_TEST_PLAY_SINE,
};
int32 ausys_da_test_mode(uint32 cmd, uint32 param1, uint32 param2, uint32 param3);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef __AUSYS_DEBUG_H
#define __AUSYS_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#define AUSYS_DEBUG(fmt, args...) //_os_printf(fmt, ##args)
#define AUSYS_INFO(fmt, ...) \
do{ \
os_printf("ausys info:"fmt,##__VA_ARGS__); \
}while(0);
#define AUSYS_ERR(fmt, ...) \
do{ \
os_printf("ausys err:"fmt,##__VA_ARGS__); \
os_printf("Func:%s Line:%d LR=0x%x\r\n", \
__func__,__LINE__, (uint32)RETURN_ADDR()); \
}while(0);
#define AUSYS_WARNING(fmt, ...) \
do{ \
os_printf("ausys warning:"fmt,##__VA_ARGS__); \
}while(0);
#define AUSYS_ASSERT(expr, info) \
do { \
if (expr) { \
AUSYS_ERR(info); \
return RET_ERR; \
} \
} while(0);
#define AUSYS_PRINT_ARRAY(buf, len) do{\
uint8 *p_print = (uint8 *)buf;\
_os_printf("\r\n");\
for (uint32 __ii=1; __ii<=len; __ii++) {\
_os_printf("%02x ", p_print[__ii-1]);\
if (((__ii)%16 == 0)) _os_printf("\r\n");\
}\
_os_printf("\r\n");\
}while(0);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef __AUSYS_EQ_H
#define __AUSYS_EQ_H
#ifdef __cplusplus
extern "C" {
#endif
#define EQ_COEFF_NUM (50)
extern const int32 eq_coeff_origin[50];
#ifdef __cplusplus
}
#endif
#endif

56
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#ifndef __AUSYS_QUEUE_H
#define __AUSYS_QUEUE_H
#ifdef __cplusplus
extern "C" {
#endif
struct __ausys_queue_elem {
uint32 addr;
uint32 bytes;
};
typedef struct __ausys_queue_ctrl{
uint32 elem_num;
uint16 head;
uint16 tail;
uint16 per_bytes;
uint16 sta_init:1,
sta_none:1;
void *p_malloc;
void *p_use;
struct __ausys_queue_elem *p_queue;
}TYPE_AUSYS_QUEUE;
int32 ausys_queue_create(TYPE_AUSYS_QUEUE *ausys_queue, uint32 total_bytes, uint32 per_bytes);
int32 ausys_queue_destroy(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_elem_ent(TYPE_AUSYS_QUEUE *ausys_queue, void *buf, uint32 bytes, uint32 need_cpy);
int32 ausys_queue_elem_del(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_tail_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_tail_len(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_first_half(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_second_half(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_all(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_head_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_head_len(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_index_addr(TYPE_AUSYS_QUEUE *ausys_queue, uint32 index);
uint32 ausys_queue_get_index_len(TYPE_AUSYS_QUEUE *ausys_queue, uint32 index);
uint32 ausys_queue_get_head_index(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_tail_index(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_headnext_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_headnext_len(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_is_empty(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_is_full(TYPE_AUSYS_QUEUE *ausys_queue);
#ifdef __cplusplus
}
#endif
#endif

20
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#ifndef __AUSYS_TEST_H
#define __AUSYS_TEST_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

208
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#ifndef _AUADC_H
#define _AUADC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUADC sample_rate type
*/
enum auadc_sample_rate {
AUADC_SAMPLE_RATE_8K,
AUADC_SAMPLE_RATE_11_025K,
AUADC_SAMPLE_RATE_16K,
AUADC_SAMPLE_RATE_12K,
AUADC_SAMPLE_RATE_22_05K,
AUADC_SAMPLE_RATE_24K,
AUADC_SAMPLE_RATE_32K,
AUADC_SAMPLE_RATE_44_1K,
AUADC_SAMPLE_RATE_48K,
};
/**
* @brief AUADC irq_flag type
*/
enum auadc_irq_flag {
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUADC ioctl_cmd type
*/
enum auadc_ioctl_cmd {
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUADC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUADC_IOCTL_CMD_SET_ANALOG_GAIN,
};
/* User interrupt handle */
typedef void (*auadc_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUADCC api for user */
struct auadc_device {
struct dev_obj dev;
};
/* AUADC api for user */
struct auadc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32(*close)(struct auadc_device *auadc);
int32(*read)(struct auadc_device *auadc, void* buf, uint32 bytes);
int32(*ioctl)(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
};
/* AUADC API functions */
/**
* @brief auadc_open
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
/**
* @brief auadc_close
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_close(struct auadc_device *auadc);
/**
* @brief auadc_read
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_read(struct auadc_device *auadc, void* buf, uint32 bytes);
/**
* @brief auadc_ioctl
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auadc_request_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auadc_release_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

21
sdk/include/dev/audio/components/ad/hg_auadc_v0.h Normal file
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#ifndef _HG_AUADC_V0_H_
#define _HG_AUADC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auadc_v0_init(struct auadc_device *auadc);
int32 hg_auadc_v0_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32 hg_auadc_v0_close(struct auadc_device *auadc);
int32 hg_auadc_v0_read(struct auadc_device *auadc, void* buf, uint32 bytes);
int32 hg_auadc_v0_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auadc_v0_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auadc_v0_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

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#ifndef _AUALAW_H
#define _AUALAW_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUALAW irq_flag type
*/
enum aualaw_irq_flag {
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUALAW ioctl_cmd type
*/
enum aualaw_ioctl_cmd {
/*!
* @brief:
*
*/
AUALAW_IOCTL_CMD_NONE,
};
/* User interrupt handle */
typedef void (*aualaw_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUALAW api for user */
struct aualaw_device {
struct dev_obj dev;
};
struct aualaw_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aualaw_device *aualaw);
int32(*close)(struct aualaw_device *aualaw);
int32(*encode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*decode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*ioctl)(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
};
/* AUALAW API functions */
/**
* @brief aualaw_open
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_open(struct aualaw_device *aualaw);
/**
* @brief aualaw_close
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_close(struct aualaw_device *aualaw);
/**
* @brief aualaw_encode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_decode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_ioctl
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aualaw_request_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aualaw_release_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

22
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#ifndef _HG_AUALAW_V0_H_
#define _HG_AUALAW_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aualaw_v0_init(void);
int32 hg_aualaw_v0_open(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_close(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aualaw_v0_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aualaw_v0_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

112
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#ifndef _AUASRC_H
#define _AUASRC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUASRC ioctl_cmd type
*/
enum auasrc_ioctl_cmd {
/*!
* @brief:
*
*/
AUASRC_IOCTL_CMD_NONE,
};
/* AUASRC api for user */
struct auasrc_device {
struct dev_obj dev;
};
struct auasrc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auasrc_device *auasrc);
int32(*close)(struct auasrc_device *auasrc);
int32(*run)(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
int32(*ioctl)(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUASRC API functions */
/**
* @brief auasrc_open
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_open(struct auasrc_device *auasrc);
/**
* @brief auasrc_close
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_close(struct auasrc_device *auasrc);
/**
* @brief auasrc_encode
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_run(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
/**
* @brief auasrc_ioctl
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_ioctl(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_AUASRC_V0_H_
#define _HG_AUASRC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auasrc_v0_init(void);
int32 hg_auasrc_v0_open(struct auasrc_device *auasrc);
int32 hg_auasrc_v0_close(struct auasrc_device *auasrc);
int32 hg_auasrc_v0_run(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
int32 hg_auasrc_v0_ioctl(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
void hg_auasrc_v0_adjust_sample_ofs(void);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUASRC_V0_H_ */

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#ifndef _AUDAC_H
#define _AUDAC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUDAC sample_rate type
*/
enum audac_sample_rate {
AUDAC_SAMPLE_RATE_8K,
AUDAC_SAMPLE_RATE_11_025K,
AUDAC_SAMPLE_RATE_12K,
AUDAC_SAMPLE_RATE_16K,
AUDAC_SAMPLE_RATE_22_05K,
AUDAC_SAMPLE_RATE_24K,
AUDAC_SAMPLE_RATE_32K,
AUDAC_SAMPLE_RATE_44_1K,
AUDAC_SAMPLE_RATE_48K,
};
/**
* @brief AUDAC irq_flag type
*/
enum audac_irq_flag {
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUDAC ioctl_cmd type
*/
enum audac_ioctl_cmd {
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUDAC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUDAC_IOCTL_CMD_SET_ANALOG_GAIN,
/*!
* @brief: Soft mute
*
*/
AUDAC_IOCTL_CMD_SOFT_MUTE,
/*!
* @brief: Change sample rate
* @note :
* 1.Ensure DAC is muted by special method
* 2.You should call "audac_write" API after using this cmd
*
*/
AUDAC_IOCTL_CMD_CHANGE_SAMPLE_RATE,
AUDAC_IOCTL_CMD_GET_DIGITAL_GAIN,
};
/* User interrupt handle */
typedef void (*audac_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUDAC api for user */
struct audac_device {
struct dev_obj dev;
};
struct audac_hal_ops {
struct devobj_ops ops;
int32(*open)(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32(*close)(struct audac_device *audac);
int32(*write)(struct audac_device *audac, void* buf, uint32 bytes);
int32(*ioctl)(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag);
};
/* AUDAC API functions */
/**
* @brief audac_open
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
/**
* @brief audac_close
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_close(struct audac_device *audac);
/**
* @brief audac_write
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_write(struct audac_device *audac, void* buf, uint32 bytes);
/**
* @brief audac_ioctl
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief audac_request_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief audac_release_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_AUDAC_V0_H_
#define _HG_AUDAC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_audac_v0_init(struct audac_device *audac);
int32 hg_audac_v0_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32 hg_audac_v0_close(struct audac_device *audac);
int32 hg_audac_v0_write(struct audac_device *audac, void* buf, uint32 bytes);
int32 hg_audac_v0_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_audac_v0_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_audac_v0_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

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#ifndef _AUDRC_H
#define _AUDRC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUDRC ioctl_cmd type
*/
enum audrc_ioctl_cmd {
/*!
* @brief:
*
*/
AUDRC_IOCTL_CMD_NONE,
};
/* AUDRC api for user */
struct audrc_device {
struct dev_obj dev;
};
struct audrc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct audrc_device *audrc);
int32(*close)(struct audrc_device *audrc);
int32(*run)(struct audrc_device *audrc, void *p_content, uint32 bytes);
int32(*ioctl)(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUDRC API functions */
/**
* @brief audrc_open
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_open(struct audrc_device *audrc);
/**
* @brief audrc_close
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_close(struct audrc_device *audrc);
/**
* @brief audrc_encode
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_run(struct audrc_device *audrc, void *p_content, uint32 bytes);
/**
* @brief audrc_ioctl
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_ioctl(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_AUDRC_V0_H_
#define _HG_AUDRC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_audrc_v0_init(void);
int32 hg_audrc_v0_open(struct audrc_device *audrc);
int32 hg_audrc_v0_close(struct audrc_device *audrc);
int32 hg_audrc_v0_run(struct audrc_device *audrc, void *p_content, uint32 bytes);
int32 hg_audrc_v0_ioctl(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUDRC_V0_H_ */

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/**
******************************************************************************
* @file E:\work\venus_v2\SW\trunk\verify\test\audio\dsd1793.h
* @author Troy
* @version V1.0.0
* @date 01-31-2023
* @brief This file contains all the dsd1793 firmware functions.
******************************************************************************
* @attention
*
*
*
*
*
******************************************************************************
*/
#ifndef __DSD1793_H
#define __DSD1793_H
#ifdef __cplusplus
extern "C" {
#endif
#if 1
/*!
* IIC config
*/
//PIN ADDR1, PIN ADDR0
//00, 01, 10, 11
#define DSD1793_PIN_ADDR0 (0)
#define DSD1793_PIN_ADDR1 (0)
#define DSD1793_DSD_MODE (1)
#define DSD1793_PCM_MODE (0)
#define DSD1793_IIC (HG_I2C1_DEVID)
#define DSD1793_IIC_DEVICE_ADDR ((0x4<<4) | (0xC | (DSD1793_PIN_ADDR1) | (DSD1793_PIN_ADDR0)))
#define DSD1793_IIC_SCL_PIN (PC_13)
#define DSD1793_IIC_SDA_PIN (PC_14)
#if 0
//#define DSD1793_IIC_SCL_GPIO_PORT (GPIOC)
//#define DSD1793_IIC_SCL_PIN_NUM (13)
//#define DSD1793_IIC_SDA_GPIO_PORT (GPIOC)
//#define DSD1793_IIC_SDA_PIN_NUM (14)
//#define DSD1793_IIC_SCL_PIN_BIT (BIT(DSD1793_IIC_SCL_PIN_NUM))
//#define DSD1793_IIC_SDA_PIN_BIT (BIT(DSD1793_IIC_SDA_PIN_NUM))
#define SMAPLE_FRQUENCY (48000)
#define OVER_SAMPLE_RATE (192)
#define __SYSCLK (SYS_CLK)
#define SCK_IIS (0)
#define SCK_TIMER (0)
#define DSD1793_SCK_GPIO_PORT (GPIOD)
#define DSD1793_SCK_GPIO_PIN_NUM (14)
#define DSD1793_SCK_GPIO_PIN_BIT (BIT(DSD1793_SCK_GPIO_PIN_NUM))
#define __dsd1793_iic_module_init()\
do{\
TYPE_LL_IIC_INIT _init;\
TYPE_LL_IIC_CFG _cfg;\
memset(&_cfg, 0, sizeof(TYPE_LL_IIC_CFG));\
memset(&_init, 0, sizeof(TYPE_LL_IIC_INIT));\
_cfg.presc = 8;\
_cfg.scldel = 15;\
_cfg.sdadel = 15;\
_cfg.scll = 31;\
_cfg.sclh = 31;\
_cfg.work_mode = LL_IIC_MASTER_MODE;\
ll_iic_init(DSD1793_IIC, &_init);\
ll_iic_config(DSD1793_IIC, &_cfg);\
}while(0);
#define __dsd1793_iic_io_init()\
do{\
ll_gpio_iomap_inout_config(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OUT_SPI2_SCK_OUT,\
LL_GPIO_IN_SPI2_SCK_IN);\
ll_gpio_iomap_inout_config(DSD1793_IIC_SDA_GPIO_PORT, DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OUT_SPI2_IO0_OUT,\
LL_GPIO_IN_SPI2_IO0_IN);\
ll_gpio_ospeed_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OSPEED_3);\
ll_gpio_ospeed_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OSPEED_3);\
ll_gpio_pull_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
ll_gpio_pull_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
ll_gpio_bit_set(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_BIT);\
ll_gpio_bit_set(DSD1793_IIC_SDA_GPIO_PORT,DSD1793_IIC_SDA_PIN_BIT);\
}while(0);
#if (SCK_IIS)
#define __dsd1793_sck_init()\
do{\
TYPE_LL_IIS_INIT _init;\
TYPE_LL_IIS_CFG _cfg;\
memset(&_init, 0, sizeof(TYPE_LL_IIS_INIT));\
memset(&_cfg, 0, sizeof(TYPE_LL_IIS_CFG));\
_cfg.mode = LL_IIS_MASTER_MODE;\
_cfg.work_mode = LL_IIS_SIMPLEX_TX;\
_cfg.channel_mode = LL_IIS_STEREO_MODE;\
_cfg.ws_pol = LL_IIS_LOW_FOR_LEFT_CHANNEL;\
_cfg.bck_pol = LL_IIS_SAMPLE_IN_RISING_EDGE;\
_cfg.data_format = LL_IIS_STANDARD_MODE;\
_cfg.mclk_sel = LL_IIS_MCLK_SEL_SYS_PLL;\
_cfg.mclk_output = LL_IIS_MCLK_OUT_ENABLE;\
_cfg.mclk_div = 16;\
_cfg.baudrate = 29;\
_cfg.ws = 31;\
_cfg.bit = 31;\
ll_gpio_iomap_inout_config(DSD1793_SCK_GPIO_PORT, DSD1793_SCK_GPIO_PIN_NUM, LL_GPIO_OUT_IIS0_MCLK_OUT , LL_GPIO_IN_IIS0_MCLK_IN__LCD_D19_IN_MASK2_6);\
ll_iis_config(IIS0, &_cfg);\
}while(0);
#endif
#if (SCK_TIMER)
#define __dsd1793_sck_init()\
do{\
TYPE_LL_TIMER_CFG _timer_cfg;\
TYPE_LL_TIMER_INIT _timer_init_cfg;\
memset(&_timer_cfg, 0, sizeof(TYPE_LL_TIMER_CFG));\
memset(&_timer_init_cfg, 0, sizeof(TYPE_LL_TIMER_INIT));\
ll_timer_init(TIMER0, &_timer_init_cfg);\
_timer_cfg.work_mode_sel = LL_TIMER_MODE_PWM;\
_timer_cfg.in_src_sel = LL_TIMER_IN_SRC_SYS_CLK;\
_timer_cfg.prescaler_sel = 0;\
_timer_cfg.period_val = (__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE)) - 1;\
_timer_cfg.pwm_val = ((__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE))/2) - 1;\
_timer_cfg.count_val = 0;\
ll_timer_config(TIMER0, &_timer_cfg);;\
ll_gpio_ospeed_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), 7);\
ll_gpio_iomap_output_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), LL_GPIO_OUT_M1_9_LCD_DATA_O_12__TMR0_PWM_OUT);\
ll_timer_start(TIMER0);\
}while(0);
#endif
#define __dsd1793_iic_write_1byte(data)\
do{\
ll_iic_master_tx(DSD1793_IIC, data, LL_IIC_NONE_FLAG);\
}while(0);
#define __dsd1793_iic_read_1byte(data)\
do{\
data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_NONE_FLAG);\
}while(0);
#define __dsd1793_iic_write(reg, p_data, len)\
do{\
uint8 *__p_data = (uint8 *)p_data;\
if(__p_data){\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
__dsd1793_iic_write_1byte(reg);\
if(len){\
for(uint16 __len=0; __len<len-1; __len++){\
__dsd1793_iic_write_1byte(*__p_data++);\
}\
}\
ll_iic_master_tx(DSD1793_IIC, *__p_data, LL_IIC_STOP_FLAG);\
}\
}while(0);
#define __dsd1793_iic_read(reg, p_data, len)\
do{\
uint8 *__p_data = (uint8 *)p_data;\
if(__p_data){\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
__dsd1793_iic_write_1byte(reg);\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 1, LL_IIC_START_FLAG);\
if(len){\
for(uint16 __len=0; __len<len-1; __len++){\
__dsd1793_iic_read_1byte(*__p_data++);\
}\
}\
*__p_data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_STOP_FLAG | LL_IIC_NACK_FLAG);\
}\
}while(0);
#endif
#define __dsd1793_delay_ms(x) os_sleep_ms(x)
/*!
* DSD1793 reg index define
*/
#define DSD1793_REG16 16
#define DSD1793_REG17 17
#define DSD1793_REG18 18
#define DSD1793_REG19 19
#define DSD1793_REG20 20
#define DSD1793_REG21 21
#define DSD1793_REG22 22
void dsd1793_reg_write_l8bit(uint16 reg, uint16 val_l8bit);
void dsd1793_reg_read_l8bit(uint16 reg, uint16 *val_l8bit);
void dsd1793_init(void);
#endif
#ifdef __cplusplus
}
#endif
#endif
/******************************** END OF FILE *****/

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#ifndef _AUEQ_H
#define _AUEQ_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUEQ ioctl_cmd type
*/
enum aueq_ioctl_cmd {
/*!
* @brief:
*
*/
AUEQ_IOCTL_CMD_NONE,
};
/* AUEQ api for user */
struct aueq_device {
struct dev_obj dev;
};
struct aueq_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32(*close)(struct aueq_device *aueq);
int32(*run)(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32(*ioctl)(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUEQ API functions */
/**
* @brief aueq_open
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
/**
* @brief aueq_close
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_close(struct aueq_device *aueq);
/**
* @brief aueq_encode
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
/**
* @brief aueq_ioctl
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

59
sdk/include/dev/audio/components/eq/biquad_filter.h Normal file
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#ifndef BIQUAD_FILTER_H
#define BIQUAD_FILTER_H
typedef int s32, S32;
typedef unsigned int u32, U32, uint;
typedef long long int s64, S64;
typedef unsigned long long u64, U64;
typedef short int s16, S16;
typedef unsigned short int u16, U16;
typedef signed char s8, S8;
typedef unsigned char u8, U8;
//模拟64bit芯片运算
int CLIP_INT24(int in);
int CLIP_INT16(int in);
void ML0(s32 x, s32 y);
void MLA(s32 x, s32 y);
void MSB(s32 x, s32 y);
s32 MLZ(s32 n);
s32 MLZ_QUICK(s32 n);
s32 MLZ_FIX(s32 n);
u32 get_acc_64_high_32(void);
u32 get_acc_64_low_32(void);
typedef struct {
int b[3];
int a[2];
int x[2];
int y[2];
int fixed_point_num;
} TYPE_BIQUAD_FILTER;
int biquad_filter_calc(TYPE_BIQUAD_FILTER *filter_ctl, int x);
//void biquad_filter_ctl_init(TYPE_BIQUAD_FILTER *filter_ctl, int fixed_point_num);
#if 0
void eq_lpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_hpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_bpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_notch_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_apf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_peaking_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_low_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_high_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
#endif
#endif /* BIQUAD_FILTER_H */

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sdk/include/dev/audio/components/eq/coeff_type.h Normal file
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#ifndef _COEFF_TYPE_H
#define _COEFF_TYPE_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
* @brief coefficient configuration
* @note
* only for software.
* a example of coefficient for 5 band:
* struct aueq_cfg cfg[5];
* cfg[0].b[0] = 0.1;
* cfg[0].b[1] = 0.3;
* ...
* cfg[1].b[1] = 0.6;
*/
struct aueq_cfg_5band{
double b[3];
double a[2];
};
/*!
* @brief coefficient configuration
* @note
* only for chip.
*/
struct aueq_cfg_10band{
int32 coeff[50];
};
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/audio/components/eq/eq_coeff.h Normal file
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#ifndef _EQ_COEFF_H
#define _EQ_COEFF_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

19
sdk/include/dev/audio/components/eq/hg_aueq_v0.h Normal file
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#ifndef _HG_AUEQ_V0_H_
#define _HG_AUEQ_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aueq_v0_init(void);
int32 hg_aueq_v0_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v0_close(struct aueq_device *aueq);
int32 hg_aueq_v0_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v0_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUEQ_V0_H_ */

19
sdk/include/dev/audio/components/eq/hg_aueq_v1.h Normal file
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#ifndef _HG_AUEQ_V1_H_
#define _HG_AUEQ_V1_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aueq_v1_init(void);
int32 hg_aueq_v1_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v1_close(struct aueq_device *aueq);
int32 hg_aueq_v1_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v1_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUEQ_V0_H_ */

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sdk/include/dev/audio/components/fade/aufade.h Normal file
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#ifndef _AUFADE_H
#define _AUFADE_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUFADE calculate mode types
*/
enum aufade_mode {
AUFADE_IN = BIT(0),
AUFADE_OUT = BIT(1),
};
/**
* @brief AUFADE irq_flag type
*/
enum aufade_irq_flag {
/*!
* @brief:
*
*/
AUFADE_IRQ_FLAG_NONE = BIT(0),
};
/**
* @brief AUFADE ioctl_cmd type
*/
enum aufade_ioctl_cmd {
AUFADE_IOCTL_CMD_GET_CURRENT_VOL = BIT(0),
AUFADE_IOCTL_CMD_CHECK_IS_DONE = BIT(1),
};
/* User interrupt handle */
typedef void (*aufade_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUFADE api for user */
struct aufade_device {
struct dev_obj dev;
};
struct aufade_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aufade_device *aufade);
int32(*close)(struct aufade_device *aufade);
int32(*start)(struct aufade_device *aufade, uint32 from, uint32 to);
int32(*ioctl)(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
};
/* AUFADE API functions */
/**
* @brief aufade_open
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_open(struct aufade_device *aufade);
/**
* @brief aufade_close
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_close(struct aufade_device *aufade);
/**
* @brief aufade_start
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_start(struct aufade_device *aufade, uint32 from, uint32 to);
/**
* @brief aufade_ioctl
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aufade_request_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aufade_release_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
int32 aufade_get_cur_vol(struct aufade_device *aufade, uint32 *vol);
int32 aufade_check_is_done(struct aufade_device *aufade, uint32 *result);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/audio/components/fade/hg_aufade_v0.h Normal file
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#ifndef _HG_AUFADE_V0_H_
#define _HG_AUFADE_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aufade_v0_init(void);
int32 hg_aufade_v0_open(struct aufade_device *aufade);
int32 hg_aufade_v0_close(struct aufade_device *aufade);
int32 hg_aufade_v0_start(struct aufade_device *aufade, uint32 from, uint32 to);
int32 hg_aufade_v0_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aufade_v0_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aufade_v0_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUFADE_V0_H_ */

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sdk/include/dev/audio/components/hg_audio_v0.h Normal file
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#ifndef _HG_AUDIO_V0_H_
#define _HG_AUDIO_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
/*!
* Type of device
*/
#define AUDIO_TYPE_AUADC BIT(0)
#define AUDIO_TYPE_AUDAC BIT(1)
#define AUDIO_TYPE_AUHS BIT(2)
#define AUDIO_TYPE_AUVAD BIT(3)
#define AUDIO_TYPE_AUALAW BIT(4)
#define AUDIO_TYPE_AUFADE BIT(5)
#define AUDIO_TYPE_AUEQ BIT(6)
#define AUDIO_TYPE_AUASRC BIT(7)
#define AUDIO_TYPE_AUDRC BIT(8)
/** @brief AUDIO operating handle structure
* @{
*/
/*!
* Common dat areas struct
*/
union __comm_dat{
uint32 comm;
struct {
uint32 adc_en :1,
dac_en :1,
hs_en :1,
alaw_en :1,
vad_en :1,
aufade_en :1,
eq_en :1,
asrc_en :1,
drc_en :1,
ana_power_on :1,
ana_power_adc_on :1,
ana_power_dac_on :1,
ana_rc_cali_ok :1,
ana_driver_version :2,
ana_rfb_level :2,
ana_rin_level :2;
} comm_bits;
};
struct hg_audio_v0 {
/* Pointer of device */
struct dev_obj dev;
uint32 hw;
/* common areas */
union __comm_dat comm_dat;
/* Pointer of common areas */
void *p_comm;
void *irq_hdl;
uint32 irq_data;
uint16 irq_num;
/* Type of device */
uint16 dev_type;
};
int32 hg_audio_v0_attach(uint32 dev_id, struct hg_audio_v0 *audio);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

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sdk/include/dev/audio/components/hw/hg_audio_ana_cfg.h Normal file
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#ifndef __HG_AUDIO_ANA_CFG_H
#define __HG_AUDIO_ANA_CFG_H
#ifdef __cplusplus
extern "C" {
#endif
//DAC+PGA
#define DAC_DRIVER_VERSION0 (0x0)
//1bit PWM
#define DAC_DRIVER_VERSION1 (0x1)
//DAC
#define DAC_DRIVER_VERSION2 (0x2)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_44_1K (1)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_48K (2)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_32K (3)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_16K (4)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_8K (5)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_11_025K (6)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_22_05K (7)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_24K (8)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_12K (10)
/*!
* mic type: difference
*/
#define __AUDIO_ADC_ANA_CFG_MIC_TYPE_DIFF (1)
/*!
* mic type: single ended
*/
#define __AUDIO_ADC_ANA_CFG_MIC_TYPE_SINGE (2)
struct __audio_adc_ana_cfg {
uint16 sample_rate;
uint16 mic_type;
uint8 set_rfb;
uint8 set_rin;
};
struct __audio_dac_ana_cfg {
uint16 driver_version;
};
struct __audio_comm_ana_cfg {
union {
uint32 comm;
struct {
uint32 audio_ref1 :6,
audio_ref2 :6,
audio_c2 :6;
}comm_bits;
};
};
struct __audio_dac_digital_cfg {
uint32 target_vol;
};
struct __audio_dac_digital_cfg dac_digital_cfg;
struct __audio_ana_cfg {
struct __audio_adc_ana_cfg adc;
struct __audio_dac_ana_cfg dac;
struct __audio_comm_ana_cfg comm;
};
void audio_ana_config_power_on(void *cfg);
void audio_ana_config_power_off(void *cfg);
void audio_ana_config_adc_on(void *cfg);
void audio_ana_config_adc_off(void *cfg);
void audio_ana_config_dac_on(void *cfg);
void audio_ana_config_dac_off(void *cfg);
void audio_ana_config_dac_voice_off(void *cfg);
void audio_ana_config_dac_voice_on(void *cfg);
void audio_ana_config_rc_cali(void *cfg);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/audio/components/hw/hg_audio_v0_hw.h Normal file
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#ifndef _HG_AUDIO_V0_HW_H
#define _HG_AUDIO_V0_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
*DIGI_PATH_CTL
*/
#define LL_AUDIO_DIGI_PATH_CTL_ADC_MODE(x) (((x)&0x3) << (0x1e))
#define LL_AUDIO_DIGI_PATH_CTL_DAC_MODE(x) (((x)&0x3) << (0x1c))
#define LL_AUDIO_DIGI_PATH_CTL_DRC_DIRECT_EN(x) (((x)&0x1) << (0x1b))
#define LL_AUDIO_DIGI_PATH_CTL_ASRC_DIRECT_EN(x) (((x)&0x1) << (0x1a))
#define LL_AUDIO_DIGI_PATH_CTL_EQ_DIRECT_EN(x) (((x)&0x1) << (0x19))
#define LL_AUDIO_DIGI_PATH_CTL_XU_SET(x) (((x)&0x7) << (0xe ))
#define LL_AUDIO_DIGI_PATH_CTL_ALPHA_SEL(x) (((x)&0x3) << (0xc ))
#define LL_AUDIO_DIGI_PATH_CTL_MXS_DWA_EN(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_DIGI_PATH_CTL_VOLEN(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_DIGI_PATH_CTL_AGCEN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DIGI_PATH_CTL_ADCHP(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_DIGI_PATH_CTL_DACM(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_DIGI_PATH_CTL_ADCEN(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DIGI_PATH_CTL_DACEN(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_CTL
*/
#define LL_AUDIO_DAC_DMA_CTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_DMA_CTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_DMA_CTL_SKIPDATA(x) (((x)&0x3) << (0x6 ))
#define LL_AUDIO_DAC_DMA_CTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DAC_DMA_CTL_DATAMODE(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_DMA_CTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_DMA_CTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_WCTL
*/
#define LL_AUDIO_DAC_DMA_WCTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_DMA_WCTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_DMA_WCTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DAC_DMA_WCTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_DMA_WCTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*ADC_DMA_CTL
*/
#define LL_AUDIO_ADC_DMA_CTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_ADC_DMA_CTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_ADC_DMA_CTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_ADC_DMA_CTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_ADC_DMA_CTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_STADR
*/
#define LL_AUDIO_DAC_DMA_STADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*DAC_DMA_WSTADR
*/
#define LL_AUDIO_DAC_DMA_WSTADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*ADC_DMA_STADR
*/
#define LL_AUDIO_ADC_DMA_STADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*DAC_DMA_LEN
*/
#define LL_AUDIO_DAC_DMA_LEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_DMA_WLEN
*/
#define LL_AUDIO_DAC_DMA_WLEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*ADC_DMA_LEN
*/
#define LL_AUDIO_ADC_DMA_LEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_SAMP_IDX
*/
#define LL_AUDIO_DAC_SAMP_IDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_SAMP_WIDX
*/
#define LL_AUDIO_DAC_SAMP_WIDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*ADC_SAMP_IDX
*/
#define LL_AUDIO_ADC_SAMP_IDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*AUDIO_IP
*/
#define LL_AUDIO_AUDIO_IP_DAC_WR_TH1IP(x) (((x)&0x1) << (0x15))
#define LL_AUDIO_AUDIO_IP_DAC_WR_TH0IP(x) (((x)&0x1) << (0x14))
#define LL_AUDIO_AUDIO_IP_DAC_WR_DONEIP(x) (((x)&0x1) << (0x13))
#define LL_AUDIO_AUDIO_IP_CORDIC_OVIP(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_AUDIO_IP_VOL_OVIP(x) (((x)&0x1) << (0x11))
#define LL_AUDIO_AUDIO_IP_HS_DMAOVIP(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_AUDIO_IP_HS_DMAHFIP(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_AUDIO_IP_CODEC_DMAOVIP(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_AUDIO_IP_CODEC_DMAHFIP(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_AUDIO_IP_VAD_WINOVIP(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_AUDIO_IP_VAD_DMAOVIP(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_AUDIO_IP_VAD_DMAHFIP(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_AUDIO_IP_VAD_ZCRIP(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_AUDIO_IP_VAD_POWER1IP(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_AUDIO_IP_VAD_POWER0IP(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_AUDIO_IP_VADIP(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_AUDIO_IP_ADCTH1IP(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_AUDIO_IP_ADCTH0IP(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_AUDIO_IP_ADCDONEIP(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_AUDIO_IP_DACTH1IP(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_AUDIO_IP_DACTH0IP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_AUDIO_IP_DACDONEIP(x) (((x)&0x1) << (0x0 ))
/*!
*AUDIO_IE
*/
#define LL_AUDIO_AUDIO_IE_CORDIC_OVIE(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_AUDIO_IE_HS_DMAOVIE(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_AUDIO_IE_HS_DMAHFIE(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_AUDIO_IE_CODEC_DMAOVIE(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_AUDIO_IE_CODEC_DMAHFIE(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_AUDIO_IE_VAD_WINOVIE(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_AUDIO_IE_VAD_DMAOVIE(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_AUDIO_IE_VAD_DMAHFIE(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_AUDIO_IE_VAD_ZCRIE(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_AUDIO_IE_VAD_POWER1IE(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_AUDIO_IE_VAD_POWER0IE(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_AUDIO_IE_VADIE(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_AUDIO_IE_ADCTH1IE(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_AUDIO_IE_ADCTH0IE(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_AUDIO_IE_ADCDONEIE(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_AUDIO_IE_DACTH1IE(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_AUDIO_IE_DACTH0IE(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_AUDIO_IE_DACDONEIE(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_FLT_CTL
*/
#define LL_AUDIO_DAC_FLT_CTL_SDM_DC(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_FLT_CTL_SDM_GAIN(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_FLT_CTL_HK_SEL(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_DAC_FLT_CTL_MASH_SEL(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_DAC_FLT_CTL_ANA_CLK_SEL(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_DAC_FLT_CTL_PDM_OUT_EN(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_DAC_FLT_CTL_NOISE_WIDTH(x) (((x)&0x1f) << (0x7 ))
#define LL_AUDIO_DAC_FLT_CTL_NOSIE_EN(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_DAC_FLT_CTL_OSR_SEL(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_FLT_CTL_BAND_SEL(x) (((x)&0x3) << (0x0 ))
/*!
*DAC_MIX_CTL
*/
#define LL_AUDIO_DAC_MIX_CTL_RGAIN(x) (((x)&0xff) << (0x8 ))
#define LL_AUDIO_DAC_MIX_CTL_LGAIN(x) (((x)&0xff) << (0x0 ))
/*!
*DAC_VOL_CTL0
*/
#define LL_AUDIO_DAC_VOL_CTL0_D_VOL(x) (((x)&0x7fff) << (0x11))
#define LL_AUDIO_DAC_VOL_CTL0_S_VOL(x) (((x)&0x7fff) << (0x2 ))
#define LL_AUDIO_DAC_VOL_CTL0_VOL_DIR(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_VOL_CTL0_VOL_KICK(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_VOL_CTL1
*/
#define LL_AUDIO_DAC_VOL_CTL1_DAC_VOL(x) (((x)&0x7fff) << (0x4 ))
#define LL_AUDIO_DAC_VOL_CTL1_VOL_STEP(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_VOL_CTL1_VOL_SAMP(x) (((x)&0x3) << (0x0 ))
/*!
*ADC_FLT_CTL
*/
#define LL_AUDIO_ADC_FLT_CTL_ADCGAIN(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_ADC_FLT_CTL_XU_SET(x) (((x)&0x7) << (0x15))
#define LL_AUDIO_ADC_FLT_CTL_SMP_CYC(x) (((x)&0x3) << (0x13))
#define LL_AUDIO_ADC_FLT_CTL_ANA_CLK_SEL(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_ADC_FLT_CTL_ALPHA_SET(x) (((x)&0x3) << (0x9 ))
#define LL_AUDIO_ADC_FLT_CTL_MXS_DWA_EN(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_ADC_FLT_CTL_MXS_DWA_CLK_EN(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_ADC_FLT_CTL_NOSIE_EN(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_ADC_FLT_CTL_X2_MODE_EN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_ADC_FLT_CTL_OSR_SEL(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_ADC_FLT_CTL_BAND_SEL(x) (((x)&0x3) << (0x0 ))
/*!
*DAC_ANA_CTL
*/
#define LL_AUDIO_DAC_ANA_CTL_TESTEN(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_DAC_ANA_CTL_SELVCM(x) (((x)&0x7f) << (0x14))
#define LL_AUDIO_DAC_ANA_CTL_DAC_EN(x) (((x)&0x1) << (0x13))
#define LL_AUDIO_DAC_ANA_CTL_DACOUTPD(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_DAC_ANA_CTL_EN_COREOP(x) (((x)&0x1) << (0x11))
#define LL_AUDIO_DAC_ANA_CTL_EN_OUTPUTOP(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_DAC_ANA_CTL_EN_VCM(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_DAC_ANA_CTL_MUTE(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_DAC_ANA_CTL_VCMPD(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_DAC_ANA_CTL_GSET(x) (((x)&0x3) << (0xb ))
#define LL_AUDIO_DAC_ANA_CTL_GSEL(x) (((x)&0x7) << (0x8 ))
#define LL_AUDIO_DAC_ANA_CTL_ISET(x) (((x)&0xff) << (0x0 ))
/*!
*ADC_ANA_CTL0
*/
#define LL_AUDIO_ADC_ANA_CTL0_SEL_REFSOURCE(x) (((x)&0x3) << (0x1e))
#define LL_AUDIO_ADC_ANA_CTL0_EN_VCMLPF(x) (((x)&0x1) << (0x1d))
#define LL_AUDIO_ADC_ANA_CTL0_SW_VCM2PAD(x) (((x)&0x1) << (0x1c))
#define LL_AUDIO_ADC_ANA_CTL0_EN_V2I(x) (((x)&0x1) << (0x1b))
#define LL_AUDIO_ADC_ANA_CTL0_EN_LDO27(x) (((x)&0x1) << (0x1a))
#define LL_AUDIO_ADC_ANA_CTL0_EN_BG(x) (((x)&0x1) << (0x19))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VCC27AU(x) (((x)&0x7) << (0x16))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VREF100(x) (((x)&0xf) << (0x12))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VCMAU(x) (((x)&0xf) << (0xe ))
#define LL_AUDIO_ADC_ANA_CTL0_TEST_KICK_P(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_ADC_ANA_CTL0_TEST_KICK_N(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_ADC_ANA_CTL0_SW_PGA2ADC(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_ADC_ANA_CTL0_SW_PAD2ADC(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_ADC_ANA_CTL0_EN_AUADC(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_ADC_ANA_CTL0_EN_AUADCBIAS(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_LDO11VOLT(x) (((x)&0xf) << (0x4 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_SDDIV(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_LDO11R1(x) (((x)&0x3) << (0x0 ))
/*!
*ADC_ANA_CTL1
*/
#define LL_AUDIO_ADC_ANA_CTL1_TEST_OK_N(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_ADC_ANA_CTL1_TEST_OK_P(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_ADC_ANA_CTL1_TEST_EN(x) (((x)&0x1) << (0x0 ))
/*!
*ADC_ANA_CTL2
*/
#define LL_AUDIO_ADC_ANA_CTL2_RESERVED(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*MIC_ANA_CTL0
*/
#define LL_AUDIO_MIC_ANA_CTL0_EN_PGASEM(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_MIC_ANA_CTL0_EN_PGADFM(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_MIC_ANA_CTL0_SATOPGA(x) (((x)&0x7) << (0x4 ))
#define LL_AUDIO_MIC_ANA_CTL0_SEL_PGA2RIN(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_MIC_ANA_CTL0_SEL_PGA1RIN(x) (((x)&0x3) << (0x0 ))
/*!
*MIC_ANA_CTL1
*/
#define LL_AUDIO_MIC_ANA_CTL1_RESERVED(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*VAD_CTL0
*/
#define LL_AUDIO_VAD_CTL0_SIGN_CALC_EN(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_VAD_CTL0_AUTO_CLR_EN(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_VAD_CTL0_WAIT_SPAC_TIME(x) (((x)&0xff) << (0x6 ))
#define LL_AUDIO_VAD_CTL0_ZCR_OV0_EN(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_VAD_CTL0_POWER_OV1_EN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_VAD_CTL0_POWER_OV0_EN(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_VAD_CTL0_AUTO_MODE_EN(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_VAD_CTL0_VAD_KICK(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_VAD_CTL0_VADEN(x) (((x)&0x1) << (0x0 ))
/*!
*VAD_CTL1
*/
#define LL_AUDIO_VAD_CTL1_POWER_TH1(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_VAD_CTL1_POWER_TH0(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_CTL2
*/
#define LL_AUDIO_VAD_CTL2_ZCR_TH0(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_VAD_CTL2_WINDOW_NUM(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_VAD_CTL2_WINDOW_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_DMA_CTL
*/
#define LL_AUDIO_VAD_DMA_CTL_DMA_SHITF(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_DMA_STADR
*/
#define LL_AUDIO_VAD_DMA_STADR_DMA_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*VAD_DMA_CNT
*/
#define LL_AUDIO_VAD_DMA_CNT_ZCR_RES(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_VAD_DMA_CNT_DMA_CNT(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_STA
*/
#define LL_AUDIO_VAD_STA_POWER_RES_DB(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*CORDIC_CTL0
*/
#define LL_AUDIO_CORDIC_CTL0_THETA(x) (((x)&0xffff) << (0x1 ))
#define LL_AUDIO_CORDIC_CTL0_CORDIC_KICK(x) (((x)&0x1) << (0x0 ))
/*!
*CORDIC_STA
*/
#define LL_AUDIO_CORDIC_STA_COS_DATA(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_CORDIC_STA_SIN_DATA(x) (((x)&0xffff) << (0x0 ))
/*!
*EQ_CON0
*/
#define LL_AUDIO_EQ_CON0_EQ_GAIN(x) (((x)&0x1fff) << (0xd ))
#define LL_AUDIO_EQ_CON0_EQ_COEFF_SW(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_EQ_CON0_EQ_ROUND_MODE(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_EQ_CON0_EQ_DSM_EN(x) (((x)&0x3ff) << (0x1 ))
#define LL_AUDIO_EQ_CON0_EQ_EN(x) (((x)&0x1) << (0x0 ))
/*!
*EQ_CON1
*/
#define LL_AUDIO_EQ_CON1_EQ_COEFF_RD(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_WR(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_WDATA(x) (((x)&0x3fffff) << (0x8 ))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_SEL(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_EQ_CON1_EQ_ADDR(x) (((x)&0x7f) << (0x0 ))
/*!
*EQ_CON2
*/
#define LL_AUDIO_EQ_CON2_EQ_DONE(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_EQ_CON2_EQ_SW_DONE(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_EQ_CON2_EQ_COEFF_NUM(x) (((x)&0x1) << (0x1d))
#define LL_AUDIO_EQ_CON2_EQ_COEFF_RDATA(x) (((x)&0x3fffff) << (0x0 ))
/*!
*ASRC_CON0
*/
#define LL_AUDIO_ASRC_CON0_SAMPLE_OFS(x) (((x)&0x3fffff) << (0xa ))
#define LL_AUDIO_ASRC_CON0_SAMPLE_CNT(x) (((x)&0x1ff) << (0x1 ))
#define LL_AUDIO_ASRC_CON0_ASRC_EN(x) (((x)&0x1) << (0x0 ))
/*!
*ASRC_STA
*/
#define LL_AUDIO_ASRC_STA_FIFO_FULL(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_ASRC_STA_FIFO_EMPTY(x) (((x)&0x1) << (0x0 ))
/*!
*DRC_CON0
*/
#define LL_AUDIO_DRC_CON0_KNEE1_OP(x) (((x)&0x7f) << (0x19))
#define LL_AUDIO_DRC_CON0_KNEE1_IP(x) (((x)&0x1f) << (0x14))
#define LL_AUDIO_DRC_CON0_NOISE_SLOPE(x) (((x)&0x3) << (0x12))
#define LL_AUDIO_DRC_CON0_SLOPE1(x) (((x)&0x7) << (0xf ))
#define LL_AUDIO_DRC_CON0_SLOPE0(x) (((x)&0x7) << (0xc ))
#define LL_AUDIO_DRC_CON0_RC_SET(x) (((x)&0x1f) << (0x7 ))
#define LL_AUDIO_DRC_CON0_ATK_SET(x) (((x)&0x1f) << (0x2 ))
#define LL_AUDIO_DRC_CON0_DRC_EN(x) (((x)&0x1) << (0x0 ))
/*!
*DRC_CON1
*/
#define LL_AUDIO_DRC_CON1_NOISE_MIN_GAIN(x) (((x)&0x1f) << (0xf ))
#define LL_AUDIO_DRC_CON1_MAX_GAIN(x) (((x)&0x3) << (0xd ))
#define LL_AUDIO_DRC_CON1_MIN_GAIN(x) (((x)&0x7) << (0xa ))
#define LL_AUDIO_DRC_CON1_KNEE2_OP(x) (((x)&0x1f) << (0x5 ))
#define LL_AUDIO_DRC_CON1_KNEE2_IP(x) (((x)&0x1f) << (0x0 ))
struct hg_audio_hw_v0 {
__IO uint32 DIGI_PATH_CTL ; // 0x0
__IO uint32 DAC_DMA_CTL ; // 0x4
__IO uint32 DAC_DMA_STADR ; // 0x8
__IO uint32 DAC_DMA_LEN ; // 0xc
__IO uint32 DAC_SAMP_IDX ; // 0x10
__IO uint32 DAC_DMA_WCTL ; // 0x14
__IO uint32 DAC_DMA_WSTADR ; // 0x18
__IO uint32 DAC_DMA_WLEN ; // 0x1c
__IO uint32 DAC_SAMP_WIDX ; // 0x20
__IO uint32 DAC_FLT_CTL ; // 0x24
__IO uint32 DAC_MIX_CTL ; // 0x28
__IO uint32 DAC_VOL_CTL0 ; // 0x2c
__IO uint32 DAC_VOL_CTL1 ; // 0x30
__IO uint32 reserve0[51] ; // 0x34-0xfc
__IO uint32 ADC_DMA_CTL ; // 0x100
__IO uint32 ADC_DMA_STADR ; // 0x104
__IO uint32 ADC_DMA_LEN ; // 0x108
__IO uint32 ADC_SAMP_IDX ; // 0x10c
__IO uint32 ADC_FLT_CTL ; // 0x110
__IO uint32 AUDIO_IP ; // 0x114
__IO uint32 AUDIO_IE ; // 0x118
__IO uint32 ADC_RCCAL_CON ; // 0x11c
__IO uint32 ADC_RCCAL_STA ; // 0x120
__IO uint32 reserve1[55] ; // 0x124-0x1fc
__IO uint32 ADC_ANA_CTL0 ; // 0x200
__IO uint32 ADC_ANA_CTL1 ; // 0x204
__IO uint32 AMP_ANA_CTL0 ; // 0x208
__IO uint32 AMP_ANA_CTL1 ; // 0x20c
__IO uint32 DAC_ANA_CTL0 ; // 0x210
__IO uint32 DAC_ANA_CTL1 ; // 0x214
__IO uint32 PA_ANA_CTL0 ; // 0x218
__IO uint32 PA_ANA_CTL1 ; // 0x21c
__IO uint32 BIAS_ANA_CTL0 ; // 0x220
__IO uint32 BIAS_ANA_CTL1 ; // 0x224
__IO uint32 reserve2[54] ; // 0x228-0x2fc
__IO uint32 VAD_CTL0 ; // 0x300
__IO uint32 VAD_CTL1 ; // 0x304
__IO uint32 VAD_CTL2 ; // 0x308
__IO uint32 VAD_DMA_CTL ; // 0x30c
__IO uint32 VAD_DMA_STADR ; // 0x310
__IO uint32 VAD_DMA_CNT ; // 0x314
__IO uint32 VAD_STA ; // 0x318
__IO uint32 reserve3[281] ; // 0x31c-0x77c
__IO uint32 INCGAINTH3_0 ; // 0x780
__IO uint32 INCGAINTH5_4 ; // 0x784
__IO uint32 REDGAINTH3_0 ; // 0x788
__IO uint32 REDGAINTH5_4 ; // 0x78c
__IO uint32 GAINVAL3_0 ; // 0x790
__IO uint32 GAINVAL6_4 ; // 0x794
__IO uint32 AGC_CTL0 ; // 0x798
__IO uint32 AGC_CTL1 ; // 0x79c
__IO uint32 CODEC_CTL ; // 0x7a0
__IO uint32 CODEC_DMA_STADR ; // 0x7a4
__IO uint32 CODEC_DMA_DSTADR ; // 0x7a8
__IO uint32 CODEC_DMA_LEN ; // 0x7ac
__IO uint32 CODEC_DMA_CNT ; // 0x7b0
__IO uint32 HS_CTL0 ; // 0x7b4
__IO uint32 HS_CTL1 ; // 0x7b8
__IO uint32 HS_DMA_STADR ; // 0x7bc
__IO uint32 HS_DMA_DSTADR ; // 0x7c0
__IO uint32 HS_DMA_LEN ; // 0x7c4
__IO uint32 HS_DMA_CNT ; // 0x7c8
};
struct hg_aueq_hw_v0 {
__IO uint32 EQ_CON0;
__IO uint32 EQ_CON1;
__IO uint32 EQ_CON2;
};
struct hg_auasrc_hw_v0 {
__IO uint32 ASRC_CON0;
__IO uint32 ASRC_STA;
};
struct hg_audrc_hw_v0 {
__IO uint32 DRC_CON0;
__IO uint32 DRC_CON1;
};
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUDIO_V0_HW_H */

203
sdk/include/dev/audio/components/vad/auvad.h Normal file
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@@ -0,0 +1,203 @@
#ifndef _AUVAD_H
#define _AUVAD_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUVAD calculate mode types
*/
enum auvad_calc_mode {
AUVAD_CALC_MODE_ENERGY = BIT(0),
AUVAD_CALC_MODE_ZCR = BIT(1),
};
/**
* @brief AUVAD irq_flag type
*/
enum auvad_irq_flag {
/*!
* @brief:
*
*/
NONE = BIT(0),
};
/**
* @brief AUVAD ioctl_cmd type
*/
enum auvad_ioctl_cmd {
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_CALC_MODE,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH0,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH1,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_ZCR,
};
/* User interrupt handle */
typedef void (*auvad_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUVAD api for user */
struct auvad_device {
struct dev_obj dev;
};
struct auvad_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32(*close)(struct auvad_device *auvad);
int32(*calc)(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32(*ioctl)(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
};
/* AUVAD API functions */
/**
* @brief auvad_open
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
/**
* @brief auvad_close
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_close(struct auvad_device *auvad);
/**
* @brief auvad_encode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_encode(struct auvad_device *auvad, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief auvad_decode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
/**
* @brief auvad_ioctl
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auvad_request_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auvad_release_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

21
sdk/include/dev/audio/components/vad/hg_auvad_v0.h Normal file
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#ifndef _HG_AUVAD_V0_H_
#define _HG_AUVAD_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auvad_v0_init(void);
int32 hg_auvad_v0_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32 hg_auvad_v0_close(struct auvad_device *auvad);
int32 hg_auvad_v0_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32 hg_auvad_v0_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auvad_v0_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auvad_v0_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUVAD_V0_H_ */

53
sdk/include/dev/capture/hgcapture_v0.h Normal file
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#ifndef _HGCAPTURE_V0_H
#define _HGCAPTURE_V0_H
#include "hal/capture.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGCAPTURE_MAX_CAPTURE_CHANNEL 4
enum hgcapture_v0_func_cmd {
HGCAPTURE_V0_FUNC_CMD_MASK = BIT(7),
HGCAPTURE_V0_FUNC_CMD_INIT = HGCAPTURE_V0_FUNC_CMD_MASK | 1,
HGCAPTURE_V0_FUNC_CMD_DEINIT = HGCAPTURE_V0_FUNC_CMD_MASK | 2,
HGCAPTURE_V0_FUNC_CMD_START = HGCAPTURE_V0_FUNC_CMD_MASK | 3,
HGCAPTURE_V0_FUNC_CMD_STOP = HGCAPTURE_V0_FUNC_CMD_MASK | 4,
/* IOCTL CMD */
/* IRQ_FLAG */
HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE = HGCAPTURE_V0_FUNC_CMD_MASK | 5,
HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW = HGCAPTURE_V0_FUNC_CMD_MASK | 6,
HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ = HGCAPTURE_V0_FUNC_CMD_MASK | 7,
HGCAPTURE_V0_FUNC_CMD_SUSPEND = HGCAPTURE_V0_FUNC_CMD_MASK | 8,
HGCAPTURE_V0_FUNC_CMD_RESUME = HGCAPTURE_V0_FUNC_CMD_MASK | 9,
};
struct hgcapture_v0_config {
uint32 irq_data;
capture_irq_hdl irq_hdl;
uint16 func_cmd;
/* Only for config REG in lower layer code */
uint16 cap_sel:1,
cap_pol:1;
};
struct hgcapture_v0 {
struct capture_device dev;
void *channel[HGCAPTURE_MAX_CAPTURE_CHANNEL];
uint8 opened[HGCAPTURE_MAX_CAPTURE_CHANNEL];
};
int32 hgcapture_v0_attach(uint32 dev_id, struct hgcapture_v0 *capture);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/crc/hg_crc.h Normal file
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#ifndef _HG_CRC_H_
#define _HG_CRC_H_
#include "hal/crc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_crc {
struct crc_dev dev;
void *hw;
os_mutex_t hold;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
uint16 cookie;
};
int32 hg_crc_attach(uint32 dev_id, struct hg_crc *crc_c);
#ifdef __cplusplus
}
#endif
#endif /* _HG_CRC_H_ */

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sdk/include/dev/csc/hgcsc.h Normal file
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#ifndef HG_CSC_H
#define HG_CSC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/csc.h"
typedef enum {
CSC_DONE_IRQ,
CSC_IRQ_NUM
}CSC_IRQ_E;
struct hgcsc {
struct csc_device dev;
uint32 hw;
csc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hgcsc_attach(uint32 dev_id, struct hgcsc *csc);
#endif

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sdk/include/dev/csi/hgdvp.h Normal file
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#ifndef HG_DVP_H
#define HG_DVP_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dvp.h"
#ifdef TXW80X
typedef enum {
HSIE_ISR = 0,
VSIE_ISR,
SSCIE_EIGHT_ISR,
FHFIE_ISR,
FOVIE_ISR,
SIP_ISR,
JPEG_DONE,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
#ifdef TXW81X
typedef enum {
FOVIE_ISR = 0,
HSIP_ISR,
VSIP_ISR,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
#if TXW82X
typedef enum {
FOVIE_ISR = 0,
HSIP_ISR,
VSIP_ISR,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
struct hgdvp {
struct dvp_device dev;
//struct hgdvp_hw *hw;
uint32 hw;
dvp_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgdvp_attach(uint32 dev_id, struct hgdvp *dvp);
#endif

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#ifndef _DW_DMAC_H_
#define _DW_DMAC_H_
#include "hal/dma.h"
#ifdef __cplusplus
extern "C" {
#endif
/*! max dmac hardware channel
*/
#define DW_DMAC_MAX_DMAC_CHN 4
/*! max dmac hardware channel mask
*/
#define DW_DMAC_MAX_DMAC_CHN_MASK 0xF
/**
* @brief DMAC controller (IP)
*/
struct dw_dmac_hw_ch {
__IO uint32 SARL;
__IO uint32 SARH;
__IO uint32 DARL;
__IO uint32 DARH;
__IO uint32 FIFO0[2]; //LLPL,LLPH, NO USE
__IO uint32 CTLL;
__IO uint32 CTLH;
__IO uint32 FIFO1[8]; //SSTATL,SSTATH,DSTATL,DSTATH,SSTATARL,SSTATARH,DSTATARL,DSTATARH
__IO uint32 CFGL;
__IO uint32 CFGH;
__IO uint32 SGRL;
__IO uint32 SGRH;
__IO uint32 DSRL;
__IO uint32 DSRH;
};
/**
* @brief DMAC
*/
struct hgdma_dw_hw {
struct dw_dmac_hw_ch CH[4];
__IO uint32 FIFO0[22*4];
__IO uint32 RawTfrL;
__IO uint32 RawTfrH;
__IO uint32 RawBlockL;
__IO uint32 RawBlockH;
__IO uint32 RawSrcTranL;
__IO uint32 RawSrcTranH;
__IO uint32 RawDstTranL;
__IO uint32 RawDstTranH;
__IO uint32 RawErrL;
__IO uint32 RawErrH;
__IO uint32 FIFO1[5*2];
__IO uint32 MaskTfrL;
__IO uint32 MaskTfrH;
__IO uint32 MaskBlockL;
__IO uint32 MaskBlockH;
__IO uint32 MaskSrcTranL;
__IO uint32 MaskSrcTranH;
__IO uint32 MaskDstTranL;
__IO uint32 MaskDstTranH;
__IO uint32 MaskErrL;
__IO uint32 MaskErrH;
__IO uint32 ClearTfrL;
__IO uint32 ClearTfrH;
__IO uint32 ClearBlockL;
__IO uint32 ClearBlockH;
__IO uint32 ClearSrcTranL;
__IO uint32 ClearSrcTranH;
__IO uint32 ClearDstTranL;
__IO uint32 ClearDstTranH;
__IO uint32 ClearErrL;
__IO uint32 ClearErrH;
__IO uint32 FIFO2[2];
__IO uint32 ReqSrcRegL;
__IO uint32 ReqSrcRegH;
__IO uint32 ReqDstRegL;
__IO uint32 ReqDstRegH;
__IO uint32 SglReqSrcRegL;
__IO uint32 SglReqSrcRegH;
__IO uint32 SglReqDstRegL;
__IO uint32 SglReqDstRegH;
__IO uint32 LstSrcRegL;
__IO uint32 LstSrcRegH;
__IO uint32 LstDstRegL;
__IO uint32 LstDstRegH;
__IO uint32 DmaCfgRegL;
__IO uint32 DmaCfgRegH;
__IO uint32 ChEnRegL;
__IO uint32 ChEnRegH;
__IO uint32 FIFO3[2];
__IO uint32 DmaTestRegL;
__IO uint32 DmaTestRegH;
};
struct hgdma_dw {
struct dma_device dev;
struct hgdma_dw_hw *hw;
uint32 irq_num;
uint32 opened;
os_semaphore_t mem_chn;
os_semaphore_t dev_chn;
os_mutex_t dev_mutex;
dma_irq_hdl irq_hdl[DW_DMAC_MAX_DMAC_CHN];
uint32 irq_data[DW_DMAC_MAX_DMAC_CHN];
uint32 state[DW_DMAC_MAX_DMAC_CHN];
uint32 chn_used_flag;
};
/** @brief DW DMAC register constant table definition
* @{
*/
/***** DW_PARAMS Register *****/
/*! number of channels
*/
#define DW_DMAC_PARAMS_NR_CHAN 4
/*! number of AHB masters
*/
#define DW_DMAC_PARAMS_NR_MASTER 2
/***** DWC_PARAMS Register *****/
/*! multi block transfer
*/
#define DW_DMACC_PARAMS_MBLK_EN 11
/***** CTLx Register *****/
/*! irqs enabled
*/
#define DW_DMAC_CTLL_INT_EN (1UL << 0)
/*! The size of each element of destination transmission.
*/
#define DW_DMAC_CTLL_DST_WIDTH(n) (((n)&0x7) << 1)
/*! The size of each element of source transmission.
*/
#define DW_DMAC_CTLL_SRC_WIDTH(n) (((n)&0x7) << 4)
/*! Indicates destination address how to change on every source transfer.
*/
#define DW_DMAC_CTLL_DST_DIR(n) (((n)&0x3) << 7)
/*! Indicates source address how to change on every source transfer.
*/
#define DW_DMAC_CTLL_SRC_DIR(n) (((n)&0x3) << 9)
/*! Number of data items to be written to de destination every time.
*/
#define DW_DMAC_CTLL_DST_MSIZE(n) (((n)&0x7) << 11)
/*! Number of data items to be read from the source every time.
*/
#define DW_DMAC_CTLL_SRC_MSIZE(n) (((n)&0x7) << 14)
/*! src gather
*/
#define DW_DMAC_CTLL_S_GATH_EN (1UL << 17)
/* dst scatter
*/
//#define DW_DMAC_CTLL_D_SCAT_EN (1UL << 18)
/*! Transfer type and flow control.
*/
#define DW_DMAC_CTLL_FC(n) (((n)&0x7) << 20)
/*! dst master select : 1 for memory, 0 for peripherals
*/
#define DW_DMAC_CTLL_DMS(n) (((n)&0x3) << 23)
/*! src master select : 1 for memory, 0 for peripherals
*/
#define DW_DMAC_CTLL_SMS(n) (((n)&0x3) << 25)
/* dest block chain
*/
//#define DW_DMAC_CTLL_LLP_D_EN (1UL << 27)
/* src block chain
*/
//#define DW_DMAC_CTLL_LLP_S_EN (1UL << 28)
/***** CTL_HI Register *****/
/*! Block transfer done
*/
#define DW_DMAC_CTLH_DONE (0x00001000)
/*! Block transfer size. The max block size is 4095.
*/
#define DW_DMAC_CTLH_BLOCK_TS_MASK (0x00000FFF)
/***** CFG_LO Register *****/
/*! Channel priority mask
*/
#define DW_DMAC_CFGL_CH_PRIOR_MASK (0x7UL << 5)
/*! Channel priority
*/
#define DW_DMAC_CFGL_CH_PRIOR(n) (((n)&0x7) << 5)
/*! Channle Suspend. Suspends all DMA data transfers from the source until this
* bit is cleared.
*/
#define DW_DMAC_CFGL_CH_SUSP (1UL << 8)
/*! Indicates if there is data left in the channel FIFO.
*/
#define DW_DMAC_CFGL_FIFO_EMPTY (1UL << 9)
/*! Destination software or hardware handshaking select.
*/
#define DW_DMAC_CFGL_HS_DST (1UL << 10)
/*! Source software or hardware handshaking select.
*/
#define DW_DMAC_CFGL_HS_SRC (1UL << 11)
//#define DW_DMAC_CFGL_LOCK_CH_LEVEL(n) (((n)&0x3) << 12)
//#define DW_DMAC_CFGL_LOCK_BUS_LEVEL(n) (((n)&0x3) << 14)
//#define DW_DMAC_CFGL_LOCK_CH (1UL << 16)
//#define DW_DMAC_CFGL_LOCK_BUS (1UL << 17)
/*! Destination handshaking interface polarity.
*/
#define DW_DMAC_CFGL_HS_DST_POL (1UL << 18)
/*! Source handshaking interface polarity.
*/
#define DW_DMAC_CFGL_HS_SRC_POL (1UL << 19)
/*! Maximum AMBA burst length that is used for DMA transfers on this channel.
*/
#define DW_DMAC_CFGL_MAX_BURST(n) (((n)&0x2FF) << 20)
/*! Automatic source reload.
*/
#define DW_DMAC_CFGL_RELOAD_SAR (1UL << 30)
/*! Automatic desination reload.
*/
#define DW_DMAC_CFGL_RELOAD_DAR (1UL << 31)
/***** CFG_HI Register *****/
/*! Flow control mode.
*/
#define DW_DMAC_CFGH_FCMODE (1UL << 0)
/*! FIFO mode select.
*/
#define DW_DMAC_CFGH_FIFO_MODE (1UL << 1)
/*! Protection control.
*/
#define DW_DMAC_CFGH_PROTCTL(n) (((n)&0x7) << 2)
//#define DW_DMAC_CFGH_DS_UPD_EN (1UL << 5)
//#define DW_DMAC_CFGH_SS_UPD_EN (1UL << 6)
/*! Assigns a hardware handshaking interface to the source of channel.
*/
#define DW_DMAC_CFGH_SRC_PER(n) (((n)&0xF) << 7)
/*! Assigns a hardware handshaking interface to the destination of channel.
*/
#define DW_DMAC_CFGH_DST_PER(n) (((n)&0xF) << 11)
/***** SGR Register *****/
/*! Source gather interval.
*/
#define DW_DMAC_SGR_SGI(n) (((n)&0xFFFFF) << 0)
/*! Source gather count.
*/
#define DW_DMAC_SGR_SGC(n) (((n)&0xF) << 20)
/***** DSR Register *****/
//#define DW_DMAC_DSR_DSI(x) (((n)&0xFFFFF) << 0)
//#define DW_DMAC_DSR_DSC(x) (((n)&0xF) << 20)
/***** DmaCfgReg Register *****/
/*! dmac enable.
*/
#define DW_DMAC_CFG_DMA_EN (1UL << 0)
/***** ChEnRegL/MaskTfrL/MaskErrL/MaskDstTranL/MaskSrcTranL/MaskBlockL/ Register *****/
/*! Source gather count.
*/
#define DW_DMAC_WRITE_EN(n) ((1 << (n+8)) | (1 << n))
/*! Source gather count.
*/
#define DW_DMAC_WRITE_DIS(n) (1 << (n+8))
#define DW_DMAC_XFER_DONE(n) (1 << (n))
#define DW_DMAC_XFER_ERR(n) (1 << (n+8))
/**
* @}
*/
/** @brief DW DMAC external constant definition
* @{
*/
/**
* @breif Number of data items to be transferred(of width TR_WIDTH)
*/
enum dw_dmac_msize {
/*! damc data width : 1 TR_WIDTH
*/
DW_DMAC_MSIZE_1,
/*! damc data width : 4 TR_WIDTH
*/
DW_DMAC_MSIZE_4,
/*! damc data width : 8 TR_WIDTH
*/
DW_DMAC_MSIZE_8,
// The following MSIZE is not supported.
// DW_DMAC_MSIZE_16,
// DW_DMAC_MSIZE_32,
// DW_DMAC_MSIZE_64,
// DW_DMAC_MSIZE_128,
// DW_DMAC_MSIZE_256,
};
/**
* @brief The size of each element of destination transmission. The unit is bit.
*/
enum dw_dmac_tr_width {
/*! damc xfer width : 8 bit
*/
DW_DMAC_TR_8,
/*! damc xfer width : 16bit
*/
DW_DMAC_TR_16,
/*! damc xfer width : 32bit
*/
DW_DMAC_TR_32,
// The following TR_WIDTH is not supported.0
// DW_DMAC_TR_64,
// DW_DMAC_TR_128,
// DW_DMAC_TR_256,
};
/**
* @brief Indicates destination address how to change on every source transfer.
*/
enum dw_dmac_addr_dir {
/*! Increment
*/
DW_DMAC_ADDR_INC,
/*! Decrement
*/
DW_DMAC_ADDR_DEC,
/*! No change
*/
DW_DMAC_ADDR_NO_CHANGE,
};
/**
* @breif flow controller
@verbatim
-------------------------------------------------------------------------------
CTLL.TT_FC Field Transfer Type Flow Controller
-------------------------------------------------------------------------------
000 Memory to Memory DW_anb_dmac
001 Memory to Peripheral DW_anb_dmac
010 Peripheral to Memory DW_anb_dmac
011 Peripheral to Peripheral DW_anb_dmac
100 Peripheral to Memory Peripheral
101 Peripheral to Peripheral Source Peripheral
110 Memory to Peripheral Peripheral
111 Peripheral to Peripheral Destination Peripheral
@endverbatim
*/
enum dw_dmac_fc {
/*! Memory to Memory
*/
DW_DMAC_FC_D_M2M,
/*! Memory to Peripheral
*/
DW_DMAC_FC_D_M2P,
/*! Peripheral to Memory
*/
DW_DMAC_FC_D_P2M,
/*! Peripheral to Peripheral
*/
DW_DMAC_FC_D_P2P,
// The following flow control is not supported.
// DW_DMAC_FC_P_P2M,
// DW_DMAC_FC_SP_P2P,
// DW_DMAC_FC_P_M2P,
// DW_DMAC_FC_DP_P2P,
};
/**
* @}
*/
int32 dw_dmac_search_src_id(uint32 addr);
int32 dw_dmac_search_dest_id(uint32 addr);
int32 dw_dmac_attach(uint32 dev_id, struct hgdma_dw *dmac);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dma/hg_m2m_dma.h Normal file
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#ifndef _HG_M2M_DMA_H_
#define _HG_M2M_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef TXW82X
#define HG_M2M_DMA_NUM (CONFI_CORE_M2M_DMA ? 2 : 3)
#define HG_M2M_DMA_MAX_LEN (1<<20)
#else
#define HG_M2M_DMA_NUM 2
#define HG_M2M_DMA_MAX_LEN (64<<10)
#endif
/**
* @brief M2M_DMA
*/
struct mem_dma_ch {
__IO uint32 DMA_CON;
__IO uint32 DMA_SAIE;
__IO uint32 DMA_DATA;
__IO uint32 DMA_SADR;
__IO uint32 DMA_TADR;
__IO uint32 DMA_DLEN;
#ifdef TXW81X
__IO uint32 DMA_ISIZE;
#endif
};
struct mem_dma_hw {
struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
};
struct mem_dma_dev {
struct dma_device dev;
struct mem_dma_hw *hw;
uint32 irq_num[HG_M2M_DMA_NUM];
uint32 busy_flag : 8,
dma1_status : 1,
dma1_mutex : 1,
suspend : 1,
reserved : 21;
struct os_semaphore done[HG_M2M_DMA_NUM];
};
/** @brief M2M DMA register constant table definition
* @{
*/
/***** DMA_CON *****/
#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
#define HG_M2M_DMA_CON_DTE (1UL << 0)
/***** DMA_SAIE *****/
#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
/***** DMA_ISIZE *****/
#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
/***** DMA_DLEN *****/
#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
/**
* @}
*/
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dma/hg_m2m_dma_core1.h Normal file
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#ifndef _HG_M2M_DMA_H_
#define _HG_M2M_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef TXW82X
#define HG_M2M_DMA_NUM 1
#define HG_M2M_DMA_MAX_LEN (1<<20)
#else
#define HG_M2M_DMA_NUM 2
#define HG_M2M_DMA_MAX_LEN (64<<10)
#endif
/**
* @brief M2M_DMA
*/
struct mem_dma_ch {
__IO uint32 DMA_CON;
__IO uint32 DMA_SAIE;
__IO uint32 DMA_DATA;
__IO uint32 DMA_SADR;
__IO uint32 DMA_TADR;
__IO uint32 DMA_DLEN;
#ifdef TXW81X
__IO uint32 DMA_ISIZE;
#endif
};
struct mem_dma_hw {
struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
};
struct mem_dma_dev {
struct dma_device dev;
struct mem_dma_hw *hw;
uint32 irq_num[HG_M2M_DMA_NUM];
uint32 busy_flag : 8,
dma1_status : 1,
dma1_mutex : 1,
suspend : 1,
reserved : 21;
struct os_semaphore done[HG_M2M_DMA_NUM];
};
/** @brief M2M DMA register constant table definition
* @{
*/
/***** DMA_CON *****/
#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
#define HG_M2M_DMA_CON_DTE (1UL << 0)
/***** DMA_SAIE *****/
#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
/***** DMA_ISIZE *****/
#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
/***** DMA_DLEN *****/
#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
/**
* @}
*/
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dma2d/hg_dma2d_v0.h Normal file
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#ifndef _HG_DMA2D_V0_H_
#define _HG_DMA2D_V0_H_
#include "hal/dma2d.h"
#include "osal/mutex.h"
#include "osal/semaphore.h"
#ifdef __cplusplus
extern "C" {
#endif
enum {
DMA2D_COLOR_SIZE_ARGB8888 = 4,
DMA2D_COLOR_SIZE_RGB888 = 3,
DMA2D_COLOR_SIZE_RGB565 = 2,
DMA2D_COLOR_SIZE_ARGB1555 = 2,
DMA2D_COLOR_SIZE_ARGB4444 = 2,
DMA2D_COLOR_SIZE_L8 = 1,
DMA2D_COLOR_SIZE_AL44 = 1,
DMA2D_COLOR_SIZE_AL88 = 2,
DMA2D_COLOR_SIZE_L4 = 0,
DMA2D_COLOR_SIZE_A8 = 1,
DMA2D_COLOR_SIZE_A4 = 0,
};
enum {
DMA2D_MODE_MEMCPY = 0,
DMA2D_MODE_CONVERT = 1,
DMA2D_MODE_MIXTURE = 2,
DMA2D_MODE_MEMSET = 3,
DMA2D_MODE_MIXTURE_BG = 4,
DMA2D_MODE_MIXTURE_FG = 5,
};
enum {
DMA2D_CLUT_FLAG_FG = 0,
DMA2D_CLUT_FLAG_BG,
};
struct hgdma2d_v0 {
struct dma2d_device dev;
uint32 hw;
uint32 fgclut;
uint32 bgclut;
uint32 irq_num;
uint32 irq_data;
uint32 result_status;
dma2d_irq_hdl irq_hdl;
struct os_mutex done_lock;
struct os_semaphore done_sema;
uint32 done : 1,
dsleep : 1,
suspend : 1,
resume : 1,
fg_clut_flag : 1,
bg_clut_flag : 1,
reserved : 26;
};
int32 hgdma2d_v0_attach(uint32 dev_id, struct hgdma2d_v0 *dma2d);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dual/hgdual_org.h Normal file
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#ifndef HG_DUAL_H
#define HG_DUAL_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dual_org.h"
typedef enum {
ORG0_SD_ISR = 0,
ORG1_SD_ISR,
ORG_RD_DONE_IE,
ORG_RD_SLOW_IE,
DORG_IRQ_NUM,
}DORG_IRQ_E;
struct hgdual {
struct dual_device dev;
uint32 hw;
dual_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
uint32 opened:1, use_dma:1, save : 3, change_done : 1;
};
int32 hgdual_attach(uint32 dev_id, struct hgdual *dual);
#endif

92
sdk/include/dev/emac/hg_gmac_eva_v2.h Normal file
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#ifndef _HG_GMAC_EVA_V2_H_
#define _HG_GMAC_EVA_V2_H_
#include "osal/task.h"
#include "lib/net/ethphy/eth_phy.h"
#include "hal/netdev.h"
#ifdef __cplusplus
extern "C" {
#endif
#define gmac_v2_dbg(fmt, ...) os_printf(fmt, ##__VA_ARGS__)
struct hg_gmac_data_v2 {
struct hg_gmac_v2_rx_descriptor volatile *p_rx_des;
struct hg_gmac_v2_tx_descriptor volatile *p_tx_des;
uint8 *p_rx_malloc;
uint8 *p_tx_malloc;
/*! In order not to splicing buf, the buf of the last RX descriptor
* should be able to fill one frame.
*/
/*!
* struct hg_gmac_v2_tx_descriptor rx_des[rx_des_num];
* uint8 rx_buf[rx_des_num-1][HG_GMAC_V2_RX_PER_BUF_SIZE];
* uint8 last_rx_buf[HG_GMAC_V2_RX_FRAME_MAX_SIZE];
*/
uint32 rx_des_num;
struct hg_gmac_v2_rx_descriptor *p_rx_des_buf;
uint8 *p_rx_buf;
/*!
* struct hg_gmac_v2_tx_descriptor tx_des[tx_des_num];
* uint8 tx_buf[tx_des_num][HG_GMAC_V2_TX_PER_BUF_SIZE];
*/
uint32 tx_des_num;
struct hg_gmac_v2_tx_descriptor *p_tx_des_buf;
uint8 *p_tx_buf;
};
struct hg_gmac_eva_v2_statistics {
uint32 tx_cnt;
uint32 rx_cnt;
uint32 ru_pending_cnt;
uint32 rx_err_cnt;
};
struct hg_gmac_eva_v2 {
struct netdev dev;
uint32 hw;
uint32 modbus_devid,
phy_devid,
crc_devid;
struct crc_dev *crcdev;
uint32 mdio_pin;
uint32 mdc_pin;
uint32 irq_num;
uint32 opened:1, tx_nonblock:1, rev:30;
uint32 rgmii_en;
struct hg_gmac_data_v2 ctrl_data;
uint8 mac_addr[6];
netdev_input_cb input_cb;
void *input_priv;
uint32 tx_buf_size;
uint32 rx_buf_size;
os_task_t receive_task;
struct ethernet_phy_device *phydev;
struct ethernet_mdio_bus *mdio_bus;
/* Save link information */
int32 speed;
int32 duplex;
int32 link_status;
os_semaphore_t receive_sema;
os_mutex_t mdio_mutex;
os_mutex_t send_mutex;
struct hg_gmac_eva_v2_statistics statistics;
};
int32 hg_gmac_v2_attach(uint32 dev_id, struct hg_gmac_eva_v2 *gmac);
int32 hg_gmac_v2_has_received_frame(struct netdev *ndev);
int32 hg_gmac_v2_receive_data(struct netdev *emac_dev);
#ifdef __cplusplus
}
#endif
#endif

22
sdk/include/dev/gen/hggen420.h Normal file
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#ifndef HG_GEN420_H
#define HG_GEN420_H
#include "hal/gen420.h"
typedef enum {
GEN420_DONE_ISR = 0,
GEN420_IRQ_NUM,
}GEN420_IRQ_E;
struct hggen420 {
struct gen420_device dev;
uint32 hw;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hggen420_attach(uint32 dev_id, struct hggen420 *gen420);
#endif

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#ifndef HG_GEN422_H
#define HG_GEN422_H
#include "hal/gen422.h"
typedef enum {
GEN422_GDONE_ISR = 0,
GEN422_RDONE_ISR,
GEN422_RD_SLOW_ISR,
GEN422_WR_SLOW_ISR,
GEN422_GEN_OV_ISR,
GEN422_IRQ_NUM,
}GEN422_IRQ_E;
struct hggen422 {
struct gen422_device dev;
uint32 hw;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hggen422_attach(uint32 dev_id, struct hggen422 *gen422);
#endif

101
sdk/include/dev/gpio/hggpio_v4.h Normal file
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#ifndef _HUGEIC_GPIO_V4_H_
#define _HUGEIC_GPIO_V4_H_
#include "hal/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGGPIO_V4_MAX_PINS (16)
#ifdef HG_GPIOA_BASE
#ifndef GPIOA_BASE
#define GPIOA_BASE HG_GPIOA_BASE
#endif
#endif
#ifdef HG_GPIOB_BASE
#ifndef GPIOB_BASE
#define GPIOB_BASE HG_GPIOB_BASE
#endif
#endif
#ifdef HG_GPIOC_BASE
#ifndef GPIOC_BASE
#define GPIOC_BASE HG_GPIOC_BASE
#endif
#endif
#ifdef HG_GPIOD_BASE
#ifndef GPIOD_BASE
#define GPIOD_BASE HG_GPIOD_BASE
#endif
#endif
#ifdef HG_GPIOE_BASE
#ifndef GPIOE_BASE
#define GPIOE_BASE HG_GPIOE_BASE
#endif
#endif
#ifdef TXW80X
#define INMAP_CONST_1 0x28
#define INMAP_CONST_0 0x29
#elif defined(TXW81X)
#define INMAP_CONST_1 0x2e
#define INMAP_CONST_0 0x2f
#elif defined(TXW82X)
#define INMAP_CONST_1 0x44
#define INMAP_CONST_0 0x45
#endif
struct gpio_bk{
__IO uint32_t MODE;
__IO uint32_t OTYPE;
__IO uint32_t OSPEEDL;
__IO uint32_t OSPEEDH;
__IO uint32_t PUPL;
__IO uint32_t PUPH;
__IO uint32_t PUDL;
__IO uint32_t PUDH;
__IO uint32_t ODAT;
__IO uint32_t AFRL;
__IO uint32_t AFRH;
__IO uint32_t IMK;
__IO uint32_t DEBEN;
__IO uint32_t AIOEN;
__IO uint32_t TRG0;
__IO uint32_t IEEN;
__IO uint32_t IOFUNCOUTCON0;
__IO uint32_t IOFUNCOUTCON1;
__IO uint32_t IOFUNCOUTCON2;
__IO uint32_t IOFUNCOUTCON3;
};
struct hggpio_v4 {
struct gpio_device dev;
uint32 hw;
uint32 comm_irq_num;
int32 pin_id[HGGPIO_V4_MAX_PINS];
gpio_irq_hdl irq_hdl[HGGPIO_V4_MAX_PINS];
uint32 pin_num[2];
uint8 irq_num;
uint32_t flag;
#ifdef CONFIG_SLEEP
struct gpio_bk bk;
#endif
};
struct hggpio_v4_hw;
int32 hggpio_v4_attach(uint32 dev_id, struct hggpio_v4 *gpio);
uint32_t hggpio_v4_mask_opa(struct hggpio_v4_hw *reg, uint32_t pin_num, enum gpio_iomap_out_func func_sel, uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif

29
sdk/include/dev/gpio/hggpio_v5.h Normal file
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#ifndef _HUGEIC_GPIO_V5_H_
#define _HUGEIC_GPIO_V5_H_
#include "hal/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGGPIO_V5_MAX_PINS (16)
struct hggpio_v5 {
struct gpio_device dev;
uint32 hw;
int32 pin_id[HGGPIO_V5_MAX_PINS];
gpio_irq_hdl irq_hdl[HGGPIO_V5_MAX_PINS];
uint32 pin_num[2];
uint8 irq_num;
};
int32 hggpio_v5_attach(uint32 dev_id, struct hggpio_v5 *gpio);
#ifdef __cplusplus
}
#endif
#endif

39
sdk/include/dev/h264/hg264.h Normal file
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#ifndef HG_H264_H
#define HG_H264_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/h264.h"
typedef enum {
H264_FRAME_DONE,
H264_BUF0_FULL,
H264_BUF1_FULL,
H264_SOFT_SLOW,
H264_FRAME_FAST,
H264_PIXEL_FAST,
H264_PIXEL_DONE,
H264_ENC_TIME_OUT,
H264_DEC_FRAME_ERR,
H264_BS_LEN_ERR,
H264_CFG_W_ERR,
H264_IRQ_NUM
}H264_IRQ_E;
struct hg264 {
struct h264_device dev;
uint32 hw;
h264_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
volatile uint32 opened:1, use_dma:1,err:1, dsleep:1,h264_clt:1,h264_close_status:1,h264_oe_enable:1,h264_oe_used:1;
uint32 *cfg_backup;
};
int32 hg264_attach(uint32 dev_id, struct hg264 *lcdc);
#endif

66
sdk/include/dev/i2c/hgi2c_v1.h Normal file
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/**
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HGI2C_V1_H
#define __HGI2C_V1_H
#ifdef __cplusplus
extern "C" {
#endif
struct hgi2c_v1 {
struct i2c_device dev;
uint32 hw;
i2c_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
struct os_mutex i2c_lock;
struct os_semaphore i2c_done;
uint32 irq_tx_done_en : 1,
irq_rx_done_en : 1,
flag_tx_done : 1,
flag_rx_done : 1,
flag_table_done : 1,
flag_table_config_en : 1,
opened : 1,
dsleep : 1;
#ifdef CONFIG_SLEEP
struct {
__IO uint32_t con0;
__IO uint32_t con1;
__IO uint32_t timecon;
__IO uint32_t tdmalen;
__IO uint32_t rdmalen;
__IO uint32_t tstadr;
__IO uint32_t rstadr;
__IO uint32_t slavesta;
__IO uint32_t ownadrcon;
__IO uint32_t timeoutcon;
__IO uint32_t rxtimeoutcon;
__IO uint32_t rstadr1;
__IO uint32_t vsync_tcon;
__IO uint32_t hsync_tcon;
}bp_regs;
uint32 bp_irq_flags;
i2c_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
struct os_mutex bp_suspend_lock;
struct os_mutex bp_resume_lock;
#endif
};
int32 hgi2c_v1_attach(uint32 dev_id, struct hgi2c_v1 *hgi2c_s);
#ifdef __cplusplus
}
#endif
#endif //__HGI2C_V1_H
/*************************** (C) COPYRIGHT 2018 HUGE-IC ***** END OF FILE *****/

49
sdk/include/dev/i2s/hgi2s_v0.h Normal file
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#ifndef _HGI2S_V0_H_
#define _HGI2S_V0_H_
#include "hal/i2s.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief I2S operating handle structure
* @{
*/
struct hgi2s_v0 {
struct i2s_device dev ;
uint32 hw ;
i2s_irq_hdl irq_hdl ;
uint32 irq_data ;
uint16 irq_num ;
uint16 opened :1,
dsleep :1,
duplex_en:1;
#ifdef CONFIG_SLEEP
struct {
uint32 con;
uint32 bit_set;
uint32 baud;
uint32 ws_con;
uint32 dma_stadr;
uint32 dma_len;
}bp_regs;
uint32 bp_irq_flags;
i2s_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgi2s_v0_attach(uint32 dev_id, struct hgi2s_v0 *i2s);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

81
sdk/include/dev/isp/hgisp_v0.h Normal file
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#ifndef _HGISP_V0_H_
#define _HGISP_V0_H_
#include "hal/isp.h"
#include "lib/video/dvp/cmos_sensor/csi.h"
#ifdef __cplusplus
extern "C" {
#endif
enum isp_data_type {
ISP_DAT_GAMMA_R = 0,
ISP_DAT_GAMMA_G,
ISP_DAT_GAMMA_B,
ISP_DAT_GAMMA_Y,
ISP_DAT_HIST_R = BIT(2),
ISP_DAT_HIST_G,
ISP_DAT_HIST_B,
ISP_DAT_HIST_Y,
ISP_DAT_LSC = BIT(3),
ISP_DAT_GTMO = BIT(4),
ISP_DAT_HDR_HIST0 = BIT(5),
ISP_DAT_HDR_HIST1 = BIT(6),
ISP_DAT_INFRA = BIT(7),
};
enum isp_data_size{
ISP_DAT_SINGLE_GAMMA_SIZE = 0x100,
ISP_DAT_HIST_SIZE = 0x400,
ISP_DAT_GAMMA_SIZE = 0x400,
ISP_DAT_LSC_SIZE = 0x990,
// ISP_DAT_GTMO_SIZE = 0x304,
// ISP_DAT_HDR_HIST0_SIZE = 0x2E0,
// ISP_DAT_HDR_HIST1_SIZE = 0x2E0,
ISP_DAT_GTMO_SIZE = 0x000,
ISP_DAT_HDR_HIST0_SIZE = 0x000,
ISP_DAT_HDR_HIST1_SIZE = 0x000,
};
enum{
LL_ISP_ENABLE_FUNC_GAMMA = BIT(0),
LL_ISP_ENABLE_FUNC_HIST = BIT(1),
LL_ISP_ENABLE_FUNC_LSC = BIT(2),
LL_ISP_ENABLE_FUNC_GTMO = BIT(3),
LL_ISP_ENABLE_FUNC_HDR_HIST0 = BIT(4),
LL_ISP_ENABLE_FUNC_HDR_HIST1 = BIT(5),
};
enum {
ISP_LUMA_CA_MODE_0,
ISP_LUMA_CA_MODE_IRON,
ISP_LUMA_CA_MODE_GLOWBOW,
ISP_LUMA_CA_MODE_RAINBOW,
};
/** @brief ISP operating handle structure
* @{
*/
struct hgisp_v0 {
struct isp_device dev ;
uint32 hw ;
uint32 data_hw ;
isp_irq_hdl irq_hdl ;
uint32 irq_data ;
uint32 slave_index : 16,
curr_index : 16 ;
uint32 irq_num : 16,
opened : 1,
dsleep : 1,
dma_en : 1,
reserved : 12;
uint16 i2c_devid[4];
uint16 i2c_opt[4];
uint32 module;
};
int32 hgisp_v0_attach(uint32 dev_id, struct hgisp_v0 *isp);
void image_isp_status();
#ifdef __cplusplus
}
#endif
#endif /* _HGISP_V0_H_ */

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#ifndef HG_JPG_H
#define HG_JPG_H
#include "hal/jpeg.h"
//typedef int (*jgp_isr_func)(uint32);
//typedef int32 (*jpg_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param);
#ifdef TXW80X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
// JPG_READ_EMPTY,
// JPG_WRITE_FULL,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
#ifdef TXW81X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
JPG_PIXEL_DONE,
JPG_TIME_OUT,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
#if TXW82X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
JPG_PIXEL_DONE,
JPG_TIME_OUT,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
struct hgjpg {
struct jpg_device dev;
uint32 hw;
uint32 thw;
uint32 huf_hw;
//jpg_irq_hdl irq_hdl;
uint32 irq_num;
uint8 opened : 1,
jpg_run : 1,
decode : 1,
set_buf_len : 1;
uint8 addr_count;
uint8 deal_time;
uint32 *cfg_backup;
};
//int32 jpg_open(struct jpg_device *p_jpg);
//int32 jpg_close(struct jpg_device *p_jpg);
//int32 jpg_init(struct jpg_device *p_jpg,uint32 table_index,uint32 qt,uint32 buflen,uint32 head_reserver);
//int32 jpg_set_size(struct jpg_device *p_jpg,uint32 h,uint32 w);
//int32 jpg_set_len(struct jpg_device *p_jpg,uint32 buflen,uint32 head_reserver);
//int32 jpg_updata_dqt(struct jpg_device *p_jpg,uint32* dqtbuf);
//int32 jpg_set_addr(struct jpg_device *p_jpg,uint32 addr);
//int32 jpg_set_qt(struct jpg_device *p_jpg,uint32 qt);
//int32 jpg_get_len(struct jpg_device *p_jpg);
//int32 jpg_get_outbuf_num(struct jpg_device *p_jpg);
//int32 jpg_request_irq(struct jpg_device *p_jpg,uint32 irq, jgp_isr_func isr, void *dev_id);
//int32 jpg_release_irq(struct jpg_device *p_jpg,uint32 irq);
void hgjpg_attach(uint32 dev_id, struct hgjpg *jpg);
#endif

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sdk/include/dev/lcdc/hgdsi.h Normal file
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#ifndef HG_DSI_H
#define HG_DSI_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dsi.h"
struct hgdsi {
struct dsi_device dev;
uint32 hw;
dsi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgdsi_attach(uint32 dev_id, struct hgdsi *dsi);
#endif

30
sdk/include/dev/lcdc/hglcdc.h Normal file
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#ifndef HG_LCDC_H
#define HG_LCDC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/lcdc.h"
typedef enum {
LCD_DONE_IRQ,
LCD_TE_IRQ,
OSD_EN_IRQ,
SCREEN_DONE_IRQ = OSD_EN_IRQ,
TIMEOUT_IRQ,
LCD_IRQ_NUM
}LCD_IRQ_E;
struct hglcdc {
struct lcdc_device dev;
uint32 hw;
lcdc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hglcdc_attach(uint32 dev_id, struct hglcdc *lcdc);
#endif

28
sdk/include/dev/led/hgled_v0.h Normal file
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#ifndef _HGLED_V0_H
#define _HGLED_V0_H
#include "hal/led.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgled_v0 {
struct led_device dev;
uint32 hw;
led_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 seg_cnt;
uint16 com_cnt;
uint32 tube_type;
uint32 opened;
};
int32 hgled_v0_attach(uint32 dev_id, struct hgled_v0 *led);
#ifdef __cplusplus
}
#endif
#endif

30
sdk/include/dev/mipi_csi/hgmipi_csi.h Normal file
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#ifndef HG_MIPI_CSI_H
#define HG_MIPI_CSI_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dvp.h"
#include "hal/csi2.h"
typedef enum {
CSI2_FOVIE_ISR = 0,
CSI2_VSIP_ISR,
CSI2_HSIP_ISR,
MIPI_CSI_IRQ_NUM
}MIPI_CSI_IRQ_E;
struct hgmipi_csi {
struct mipi_csi_device dev;
uint32 hw;
mipi_csi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgmipi_csi_attach(uint32 dev_id, struct hgmipi_csi *mipi_csi);
#endif

18
sdk/include/dev/of/hgof.h Normal file
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#ifndef HG_OF_H
#define HG_OF_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/of.h"
struct hgof {
struct of_device dev;
uint32 hw;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
void hgof_attach(uint32 dev_id, struct hgof *of);
#endif

27
sdk/include/dev/osd_enc/hgosd_enc.h Normal file
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#ifndef HG_OSD_ENC_H
#define HG_OSD_ENC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/osd_enc.h"
typedef enum {
ENC_DONE_IRQ,
ENC_IRQ_NUM
}OSD_ENC_IRQ_E;
struct hgosd {
struct osdenc_device dev;
uint32 hw;
osdenc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hgosdenc_attach(uint32 dev_id, struct hgosd *lcdc);
#endif

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sdk/include/dev/para_in/hgpara_in.h Normal file
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#ifndef _HGPARA_IN_H
#define _HGPARA_IN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "devid.h"
#include "osal/semaphore.h"
#include "osal/mutex.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "hal/para_in.h"
struct hgpara_in_hw {
__IO uint32_t PARA_IN_CON;
__IO uint32_t PARA_IN_STA;
__IO uint32_t PARA_IN_ACT_SIZE;
__IO uint32_t PARA_IN_BLK_SIZE;
__IO uint32_t PARA_IN_TO_CON;
};
enum hgpara_in_flags {
HGPARA_IN_FLAGS_OPENED = BIT(0),
HGPARA_IN_FLAGS_READY = BIT(1),
HGPARA_IN_FLAGS_SUSPEND = BIT(2),
};
struct hgpara_in {
struct para_in_device dev;
struct hgpara_in_hw *hw;
para_in_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
//状态位
uint32 flags;
};
int32 hgpara_in_attach(uint32 dev_id, struct hgpara_in *p_para_in);
#ifdef __cplusplus
}
#endif
#endif

41
sdk/include/dev/pdm/hgpdm_v0.h Normal file
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#ifndef _HGPDM_V0_H_
#define _HGPDM_V0_H_
#include "hal/pdm.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgpdm_v0 {
struct pdm_device dev;
uint32 hw;
pdm_irq_hdl irq_hdl;
uint32 irq_data;
uint16 irq_num;
uint16 opened:1,
dsleep:1;
#ifdef CONFIG_SLEEP
struct {
uint32 con;
uint32 dmacon;
uint32 dmastadr;
uint32 dmalen;
}bp_regs;
uint32 bp_irq_flags;
pdm_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgpdm_v0_attach(uint32 dev_id, struct hgpdm_v0 *pdm);
#ifdef __cplusplus
}
#endif
#endif

29
sdk/include/dev/prc/hgprc.h Normal file
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#ifndef HG_PRC_H
#define HG_PRC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/prc.h"
typedef enum {
PRC_ISR = 0,
PRC_IRQ_NUM,
}PRC_IRQ_E;
struct hgprc {
struct prc_device dev;
//struct hgdvp_hw *hw;
uint32 hw;
prc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hgprc_attach(uint32 dev_id, struct hgprc *prc);
#endif

58
sdk/include/dev/pwm/hgpwm_v0.h Normal file
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#ifndef _HGPWM_V0_H
#define _HGPWM_V0_H
#include "hal/pwm.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGPWM_MAX_PWM_CHANNEL 6
enum hgpwm_v0_func_cmd {
HGPWM_V0_FUNC_CMD_MASK = BIT(6),
HGPWM_V0_FUNC_CMD_INIT = HGPWM_V0_FUNC_CMD_MASK | 1,
HGPWM_V0_FUNC_CMD_DEINIT = HGPWM_V0_FUNC_CMD_MASK | 2,
HGPWM_V0_FUNC_CMD_START = HGPWM_V0_FUNC_CMD_MASK | 3,
HGPWM_V0_FUNC_CMD_STOP = HGPWM_V0_FUNC_CMD_MASK | 4,
/* IOCTL CMD */
HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY = HGPWM_V0_FUNC_CMD_MASK | 5,
HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY = HGPWM_V0_FUNC_CMD_MASK | 6,
HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM = HGPWM_V0_FUNC_CMD_MASK | 7,
HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE = HGPWM_V0_FUNC_CMD_MASK | 8,
HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER = HGPWM_V0_FUNC_CMD_MASK | 14,
HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY = HGPWM_V0_FUNC_CMD_MASK | 15,
/* IRQ_FLAG */
HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE = HGPWM_V0_FUNC_CMD_MASK | 9,
HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD = HGPWM_V0_FUNC_CMD_MASK | 10,
HGPWM_V0_FUNC_CMD_RELEASE_IRQ = HGPWM_V0_FUNC_CMD_MASK | 11,
HGPWM_V0_FUNC_CMD_SUSPEND = HGPWM_V0_FUNC_CMD_MASK | 12,
HGPWM_V0_FUNC_CMD_RESUME = HGPWM_V0_FUNC_CMD_MASK | 13,
};
struct hgpwm_v0_config {
uint32 period;
uint32 duty;
pwm_irq_hdl irq_hdl;
uint32 irq_data;
uint32 func_cmd;
uint32 param1;
uint32 param2;
};
struct hgpwm_v0 {
struct pwm_device dev;
void *channel[HGPWM_MAX_PWM_CHANNEL];
uint8 opened[HGPWM_MAX_PWM_CHANNEL];
};
int32 hgpwm_v0_attach(uint32 dev_id, struct hgpwm_v0 *pwm);
#ifdef __cplusplus
}
#endif
#endif

17
sdk/include/dev/rotate/hgrotate.h Normal file
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#ifndef HG_ROTATE_H
#define HG_ROTATE_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/rotate.h"
struct hgrotate {
struct rotate_device dev;
uint32 hw;
uint32 opened:1, use_dma:1;
};
int32 hgrotate_attach(uint32 dev_id, struct hgrotate *rotate);
#endif

38
sdk/include/dev/rtc/hgrtc_v0.h Normal file
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#ifndef _HGRTC_V1_H
#define _HGRTC_V1_H
#include "hal/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgrtc_v0 {
struct rtc_device dev;
uint32 hw;
rtc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t os_lock_set_time;
os_mutex_t os_lock_get_time;
struct rtc_time_type time;
struct {
//1：闰年；0：平年
uint8 leap_year;
}time_ctrl;
uint8 irq_second:1,
opened :1;
};
int32 hgrtc_v0_attach(uint32 dev_id, struct hgrtc_v0 *rtc);
#ifdef __cplusplus
}
#endif
#endif

33
sdk/include/dev/scale/hgscale.h Normal file
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#ifndef HG_SCALE_H
#define HG_SCALE_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/scale.h"
typedef enum {
FRAME_END,
INBUF_OV,
ERROR_PEND,
SCALE_IRQ_NUM
}SCALE_IRQ_E;
struct hgscale {
struct scale_device dev;
uint32 hw;
scale_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
volatile uint32_t opened:1, use_dma:1, clk_en:1, dsleep:1,need_close:1;
uint32 *cfg_backup;
};
int32 hgscale1_attach(uint32 dev_id, struct hgscale *scale);
int32 hgscale2_attach(uint32 dev_id, struct hgscale *scale);
int32 hgscale3_attach(uint32 dev_id, struct hgscale *scale);
void scale_ov_isr(uint32 irq_flag,uint32 irq_data,uint32 param1);
#endif

37
sdk/include/dev/sdio/hgsdio20_slave.h Normal file
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#ifndef _HGSDIO20_SLAVE_H_
#define _HGSDIO20_SLAVE_H_
#include "hal/sdio_slave.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsdio20_slave {
struct sdio_slave dev;
void *hw;
sdio_slave_irq_hdl irq_hdl;
uint32 irq_data;
os_mutex_t tx_lock;
os_semaphore_t tx_done;
uint8 *rx_buff;
uint8 irq_num;
uint8 rst_irq_num;
uint8 flags;
uint8 opened: 1, rev: 7;
uint16 rx_len;
uint8 speed, rev2;
uint8 func0_cis[17];
uint8 func1_cis[53];
uint64 mntr_tick;
};
int32 hgsdio20_slave_attach(uint32 dev_id, struct hgsdio20_slave *slave);
#ifdef __cplusplus
}
#endif
#endif /* _HGSDIO20_SLAVE_H_ */

33
sdk/include/dev/sha/hgsha_v0.h Normal file
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#ifndef _HGSHA_V0_H_
#define _HGSHA_V0_H_
#include "hal/sha.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsha_v0 {
struct sha_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
os_semaphore_t using256;
uint32 irq_num;
uint32 alg_type;
volatile uint32 flags_busy_or_idle :1,
flags_in_the_interupt:1,
flags_got_result :1,
flags_first_pack :1,
flags_media_pack :1,
flags_in_multi_mode:1,
flags_last_mode :1,
flags_cur_mode :1;
void (*sha_irq_func)(void *args);
void *irq_func_data;
};
int32 hgsha_v0_attach(uint32 dev_id, struct hgsha_v0 *sha);
#endif /* _hgsha256_H_ */

26
sdk/include/dev/sha/hgsha_v1.h Normal file
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#ifndef _HGSHA_V0_H_
#define _HGSHA_V0_H_
#include "hal/sha.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsha_v1 {
struct sha_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
void (*irq_func)(void *args);
void *irq_data;
struct sha_ctx ctx;
struct sha_ctx *pctx;
};
int32 hgsha_v1_attach(uint32 dev_id, struct hgsha_v1 *sha);
#endif /* _hgsha256_H_ */

15
sdk/include/dev/spi/hgic_sdspi.h Normal file
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#ifndef _HGIC_SDSPI_H_
#define _HGIC_SDSPI_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hgic_sdspi_attach(uint32 dev_id, uint32 spi_dev);
#ifdef __cplusplus
}
#endif
#endif

57
sdk/include/dev/spi/hgspi_v1.h Normal file
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#ifndef _HGSPI_V1_H_
#define _HGSPI_V1_H_
#include "hal/spi.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v1 {
struct spi_device dev;
uint32 hw;
uint32 irq_num;
spi_irq_hdl irq_hdl;
uint32 irq_data;
//os_mutex_t os_spi_tx_lock;
//os_mutex_t os_spi_rx_lock;
os_mutex_t os_spi_lock;
os_semaphore_t os_spi_tx_done;
os_semaphore_t os_spi_rx_done;
uint32 timeout;
uint16 len_threshold;
uint16 spi_tx_done :1,
spi_rx_done :1,
spi_irq_flag_tx_done :1,
spi_irq_flag_rx_done :1,
spi_tx_async :1,
spi_rx_async :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 con0;
uint32 con1;
uint32 baud;
uint32 tdmalen;
uint32 rdmalen;
uint32 tstadr;
uint32 rstadr;
uint32 slavesta;
uint32 ssp_dly;
}bp_regs;
uint32 bp_irq_flags;
spi_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgspi_v1_attach(uint32 dev_id, struct hgspi_v1 *p_spi);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V1_H_ */

28
sdk/include/dev/spi/hgspi_v2.h Normal file
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#ifndef _HGSPI_V2_H
#define _HGSPI_V2_H
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v2 {
struct spi_device dev;
uint32 hw ;
spi_irq_hdl irq_hdl ;
uint32 irq_data;
uint32 irq_num ;
uint16 opened ;
uint16 spi_irq_flag_tx_done: 1,
spi_irq_flag_rx_done: 1;
};
int32 hgspi_v2_attach(uint32 dev_id, struct hgspi_v2 *spi);
#ifdef __cplusplus
}
#endif
#endif

69
sdk/include/dev/spi/hgspi_v3.h Normal file
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#ifndef _HGSPI_V3_H_
#define _HGSPI_V3_H_
#include "hal/spi.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v3 {
struct spi_device dev;
uint32 hw;
uint32 irq_num;
spi_irq_hdl irq_hdl;
uint32 irq_data;
//os_mutex_t os_spi_tx_lock;
//os_mutex_t os_spi_rx_lock;
os_mutex_t os_spi_lock;
os_semaphore_t os_spi_tx_done;
os_semaphore_t os_spi_rx_done;
uint32 timeout;
uint16 len_threshold;
uint16 spi_tx_done :1,
spi_rx_done :1,
spi_irq_flag_tx_done :1,
spi_irq_flag_rx_done :1,
spi_tx_async :1,
spi_rx_async :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 con0;
uint32 con1;
uint32 cmd_data;
uint32 timecon;
uint32 tdmalen;
uint32 rdmalen;
uint32 tdmacnt;
uint32 rdmacnt;
uint32 tstadr;
uint32 rstadr;
uint32 sta1;
uint32 sta2;
uint32 slavesta;
uint32 ownadrcon;
uint32 rbuf;
uint32 timeoutcon;
uint32 rxtimeoutcon;
uint32 rstadr1;
uint32 vsync_tcon;
uint32 hsync_tcon;
}bp_regs;
uint32 bp_irq_flags;
spi_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgspi_v3_attach(uint32 dev_id, struct hgspi_v3 *p_spi);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V3_H_ */

147
sdk/include/dev/spi/hgspi_xip.h Normal file
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#ifndef _HGSPI_XIP_H_
#define _HGSPI_XIP_H_
#include "hal/spi.h"
#include "osal/task.h"
#include "list.h"
#ifdef __cplusplus
extern "C" {
#endif
enum hgspi_xip_flags {
hgspi_xip_flags_ready,
hgspi_xip_flags_suspend,
hgspi_xip_flags_suspend_pasr,
hgspi_xip_flags_suspend_ulp,
hgspi_xip_flags_suspend_pd,
hgspi_xip_flags_wip,
hgspi_xip_flags_xip,
};
struct xip_wip {
uint32 addrl;
uint32 addru;
uint32 addr;
uint32 tsr :16,
trs :16;
uint32 tsus :16,
trus :16;
struct os_semaphore rc;
struct os_task task;
};
struct rdcfg_bk {
uint32_t rdinstr;
uint32_t rd_capt;
};
struct hgspi_xip {
struct spi_device dev;
uint32_t hw;
uint32_t ddr : 1,
nbp : 1,
xip : 1,
flags : 29;
uint32_t tms; //io timeout ms
uint16_t tdp : 8,
trst : 8;
struct xip_wip wip;
struct rdcfg_bk def_cfg;
struct rdcfg_bk dtr_cfg;
#ifdef CONFIG_SLEEP
uint32 regs[30];
#endif
};
struct hgcqspi {
//struct qspi_device dev;
void *hw;
uint32 irq_num;
//qspi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 opened;
uint32 flags;
};
struct hgxip_flash_custom_opa {
uint8_t dummys; //最大31,内部默认有24个dummys
uint8_t cmd;
uint16_t size;
uint32_t addr;
uint8_t *buf;
};
struct hgxip_flash_custom_read {
uint8_t dummys; //最大31,内部默认有24个dummys
uint8_t cmd;
uint16_t size;
uint32_t addr;
uint8_t *buf;
};
struct hgxip_flash_custom_write {
struct hgxip_flash_custom_opa opa;
};
struct hgxip_flash_reg_opt_param
{
uint8_t cmd;
/* write opt when pre_cmd is valid(0xFF != pre_cmd); e.g.: 0x06/0x50 */
uint8_t pre_cmd;
uint8_t len;
uint8_t *buf;
};
enum MSROM_FUNC
{
#ifdef TXW82X
MSROM_MEMSET,
MSROM_MEMCPY,
MSROM_MEMCMP,
MSROM_QSPI_CMD_BUSY_WAIT,
MSROM_HIGHPASS_FILTER_100HZ_ASM,
MSROM_QSPI_XIP_ERASE,
MSROM_QSPI_XIP_READ,
MSROM_QSPI_XIP_WRITE,
MSROM_QSPI_XIP_OPT_ENTER,
MSROM_QSPI_XIP_OPT_EXIT,
MSROM_QSPI_ENTER_XIP_MODE,
MSROM_QSPI_EXIT_XIP_MODE, // NULL?
MSROM_QSPI_STIG,
MSROM_QSPI_ENTER_4B,
MSROM_QSPI_EXIT_4B,
MSROM_OSPI_SEND_SEQ,
MSROM_SYSCLK_SET_BUT_QSPI_CHAOS_DO,
#else
MSROM_MEMSET,
MSROM_MEMCPY,
MSROM_MEMCMP,
MSROM_STRCASECMP,
MSROM_QSPI_CMD_BUSY_WAIT = MSROM_STRCASECMP,
MSROM_STRNCASECMP,
MSROM_HIGHPASS_FILTER_100HZ_ASM = MSROM_STRNCASECMP,
MSROM_QSPI_XIP_ERASE,
MSROM_QSPI_XIP_READ,
MSROM_QSPI_XIP_WRITE,
MSROM_QSPI_XIP_OPT_ENTER,
MSROM_QSPI_XIP_OPT_EXIT,
MSROM_QSPI_ENTER_XIP_MODE,
MSROM_QSPI_EXIT_XIP_MODE,
MSROM_QSPI_STIG,
MSROM_OSPI_PSRAM_MRR,
MSROM_OSPI_PSRAM_MRW,
MSROM_OSPI_STIG,
#endif
};
int32 hgspi_xip_attach(uint32 dev_id, struct hgspi_xip *p_spi);
uint32_t get_msrom_func(uint32_t func_code);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V1_H_ */

23
sdk/include/dev/sysaes/hg_sysaes_v2.h Normal file
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#ifndef _HG_SYSAES_V2_H_
#define _HG_SYSAES_V2_H_
#include "hal/sysaes.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_sysaes_v2 {
struct sysaes_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
#ifdef CONFIG_SLEEP
uint32 *regs;
#endif
};
int32 hg_sysaes_v2_attach(uint32 dev_id, struct hg_sysaes_v2 *sysaes);
#endif /* _HG_SYSAES_V2_H_ */

20
sdk/include/dev/sysaes/hg_sysaes_v3.h Normal file
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#ifndef _HG_SYSAES_V3_H_
#define _HG_SYSAES_V3_H_
#include "hal/sysaes.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_sysaes_v3 {
struct sysaes_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
};
int32 hg_sysaes_v3_attach(uint32 dev_id, struct hg_sysaes_v3 *sysaes);
#endif /* _HG_SYSAES_V3_H_ */

107
sdk/include/dev/timer/hgtimer_v4.h Normal file
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#ifndef _HGTIMER_V4_H
#define _HGTIMER_V4_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V4_TYPE_ONCE BIT(0)
#define HGTIMER_V4_TYPE_PERIODIC BIT(1)
#define HGTIMER_V4_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V4_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V4_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V4_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V4_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V4_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V4_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V4_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
#define HGTIMER_V4_CAPTURE_FUNC_CMD_INIT HGCAPTURE_V0_FUNC_CMD_INIT
#define HGTIMER_V4_CAPTURE_FUNC_CMD_DEINIT HGCAPTURE_V0_FUNC_CMD_DEINIT
#define HGTIMER_V4_CAPTURE_FUNC_CMD_START HGCAPTURE_V0_FUNC_CMD_START
#define HGTIMER_V4_CAPTURE_FUNC_CMD_STOP HGCAPTURE_V0_FUNC_CMD_STOP
/* IOCTL CMD */
/* IRQ_FLAG */
#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
#define HGTIMER_V4_CAPTURE_FUNC_CMD_RELEASE_IRQ HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V4_CAPTURE_FUNC_CMD_SUSPEND HGCAPTURE_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V4_CAPTURE_FUNC_CMD_RESUME HGCAPTURE_V0_FUNC_CMD_RESUME
struct hgtimer_v4 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 tmr_con;
uint32 tmr_en;
uint32 tmr_ie;
uint32 tmr_cnt;
uint32 tmr_cap1;
uint32 tmr_cap2;
uint32 tmr_cap3;
uint32 tmr_cap4;
/* The following registers only for timer1 & timer2 */
uint32 tmr_dctl;
uint32 tmr_dadr;
uint32 tmr_dlen;
uint32 tmr_dcnt;
uint32 tmr_ir_bcnt;
}bp_regs;
uint32 bp_irq_flags;
#endif
};
int32 hgtimer_v4_attach(uint32 dev_id, struct hgtimer_v4 *timer);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/timer/hgtimer_v5.h Normal file
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#ifndef _HGTIMER_V5_H
#define _HGTIMER_V5_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V5_TYPE_ONCE BIT(0)
#define HGTIMER_V5_TYPE_PERIODIC BIT(1)
#define HGTIMER_V5_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V5_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V5_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V5_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V5_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V5_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V5_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_INIT BIT(30) | 1
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_DEINIT BIT(30) | 2
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_START BIT(30) | 3
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_STOP BIT(30) | 4
///* IOCTL CMD */
//
///* IRQ_FLAG */
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE BIT(30) | 7
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW BIT(30) | 8
//
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_RELEASE_IRQ BIT(30) | 9
struct hgtimer_v5 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
//capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1;
};
int32 hgtimer_v5_attach(uint32 dev_id, struct hgtimer_v5 *timer);
#ifdef __cplusplus
}
#endif
#endif

106
sdk/include/dev/timer/hgtimer_v7.h Normal file
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#ifndef _HGTIMER_V7_H
#define _HGTIMER_V7_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V7_TYPE_ONCE BIT(0)
#define HGTIMER_V7_TYPE_PERIODIC BIT(1)
#define HGTIMER_V7_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V7_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V7_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V7_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V7_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V7_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V7_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V7_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
#define HGTIMER_V7_CAPTURE_FUNC_CMD_INIT HGCAPTURE_V0_FUNC_CMD_INIT
#define HGTIMER_V7_CAPTURE_FUNC_CMD_DEINIT HGCAPTURE_V0_FUNC_CMD_DEINIT
#define HGTIMER_V7_CAPTURE_FUNC_CMD_START HGCAPTURE_V0_FUNC_CMD_START
#define HGTIMER_V7_CAPTURE_FUNC_CMD_STOP HGCAPTURE_V0_FUNC_CMD_STOP
/* IOCTL CMD */
/* IRQ_FLAG */
#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
#define HGTIMER_V7_CAPTURE_FUNC_CMD_RELEASE_IRQ HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V7_CAPTURE_FUNC_CMD_SUSPEND HGCAPTURE_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V7_CAPTURE_FUNC_CMD_RESUME HGCAPTURE_V0_FUNC_CMD_RESUME
struct hgtimer_v7 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 tmr_ctl;
uint32 tmr_cnt;
uint32 tmr_pr;
uint32 tmr_pwm;
}bp_regs;
uint32 bp_irq_flags;
timer_irq_hdl bp_irq_hdl_timer;
pwm_irq_hdl bp_irq_hdl_pwm;
capture_irq_hdl bp_irq_hdl_capture;
uint32 bp_irq_data_timer;
uint32 bp_irq_data_pwm;
uint32 bp_irq_data_capture;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgtimer_v7_attach(uint32 dev_id, struct hgtimer_v7 *timer);
#ifdef __cplusplus
}
#endif
#endif

99
sdk/include/dev/tk/hg_touchKey.h Normal file
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#ifndef __HG_TOUCHKEY_H
#define __HG_TOUCHKEY_H
enum tk_ioctl_cmd
{
//硬件寄存器配置
TK_IOCTL_CSRST_SET,
TK_IOCTL_CMPEN_SET,
TK_IOCTL_CMPRB_SET,
TK_IOCTL_RES_SET,
TK_IOCTL_CURR_SET,
TK_IOCTL_ANA_TEN_SET,
TK_IOCTL_VOLT_REF_SET,
TK_IOCTL_PSR_CNT_SET,
TK_IOCTL_PRE_CHARGE_TIME,
TK_IOCTL_PRE_DISCHARGE_TIME,
TK_IOCTL_CONV_TIME,
TK_IOCTL_CHANNLE_MODE,
TK_IOCTL_CHARGE_FRE_DIV,
TK_IOCTL_CHARGE_FRE0_DIV,
TK_IOCTL_CHARGE_FRE1_DIV,
TK_IOCTL_CHARGE_FRE2_DIV,
TK_IOCTL_CHARGE_FRE3_DIV,
TK_IOCTL_SHIELD_SET,
TK_IOCTL_SSC_BW,
TK_IOCTL_SSC_TYPE_SEL,
TK_IOCTL_AUTO_SCAN_EN,
TK_IOCTL_ADDR_SET,
TK_IOCTL_KICK,
//算法参数配置
TK_IOCTL_ADJUST_TIME,
TK_IOCTL_LONG_KEY_TIME,
TK_IOCTL_ADJUST_LINE,
TK_IOCTL_ADJUST_DIFF_VALU,
TK_IOCTL_USE_NUM,
TK_IOCTL_WATER_MODE,
TK_IOCTL_NM_NUM,
TK_IOCTL_NM_LEAVE_CNT,
TK_IOCTL_TP_EN,
TK_IOCTL_NOISE_VALUE,
TK_IOCTL_NM_CM_CNT,
TK_IOCTL_NM_CM_VALUE,
//系统级别的配置(类似信号量,timer等等)
TK_SCAN_SEM_HANDL,
TK_TIMER_HANDL,
};
enum tk_irq_flag
{
TK_SG_CONV_FLAG = BIT(0),
TK_CH_DONE_FLAG = BIT(1),
TK_SCAN_DONE_FLAG = BIT(2),
TK_DMA_FLAG = BIT(3),
TK_DMA_ERR_FLAG = BIT(4),
};
typedef int32 (*tk_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
struct tk_device {
struct dev_obj dev;
int32(*open)(struct tk_device *tk);
int32(*close)(struct tk_device *tk);
int32(*ioctl)(struct tk_device *tk, uint32 cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag, tk_irq_hdl irq_hdl, uint32 data);
int32(*release_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag);
};
//tk算法私有结构体
struct hgtk_algorithm
{
uint16 __tk_adjust_time;
uint16 __tk_valid_time;
uint16 __tk_adjust_line;
uint16 __tk_adjust_diff_valu;
uint16 __tk_use_num;
uint16 __tk_water_mode;
uint16 __tk_nm_num;
uint16 __tk_nm_leave_cnt;
uint16 __tk_tp_en;
uint16 __tk_noise_value;
uint16 __tk_nm_cm_cnt;
uint16 __tk_nm_cm_value;
};
struct hgtk_device {
struct tk_device dev ;
uint32 hw ;
tk_irq_hdl irq_hdl ;
uint32 irq_data;
uint32 irq_num ;
uint32 opened ;
void* timer;
void* sem;
struct hgtk_algorithm tk_pri;
};
#endif

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