504 lines
19 KiB
C
504 lines
19 KiB
C
#ifndef _TXW82X_DEF_H_
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#define _TXW82X_DEF_H_
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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#define RETURN_ADDR() __builtin_return_address(0)
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#define cpu_dcache_disable() csi_dcache_clean_invalid(); csi_dcache_disable();
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#define cpu_dcache_enable() csi_dcache_enable()
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typedef signed char int8;
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typedef signed short int16;
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typedef signed int int32;
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typedef signed long long int64;
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typedef unsigned char uint8;
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typedef unsigned short uint16;
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typedef unsigned int uint32;
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typedef unsigned long long uint64;
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typedef unsigned long ulong;
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#ifndef _SIZE_T_DECLARED
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typedef unsigned int size_t;
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#define _SIZE_T_DECLARED
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#endif
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#ifndef _SSIZE_T_DECLARED
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#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
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typedef int ssize_t;
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#else
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typedef long ssize_t;
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#endif
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#define _SSIZE_T_DECLARED
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#endif
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/////////////////////////////////////////////////////////////////////////////////
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/* ------------------------- Interrupt Number Definition ------------------------ */
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enum IRQn {
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/****** Peripheral Interrupt Numbers *********************************************************/
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USB20DMA_IRQn = 0,
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USB20MC_IRQn = 1,
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UART0_IRQn = 2,
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UART1_IRQn = 3,
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LCD_IRQn = 4,
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QSPI_IRQn = 5,
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SPI0_IRQn = 6,
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SPI1_IRQn = 7,
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SPI2_IRQn = 8,
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OSPI_IRQn = 9,
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TIM0_IRQn = 10,
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TIM1_IRQn = 11,
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TIM2_IRQn = 12,
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TIM3_IRQn = 13,
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SCALE1_IRQn = 14,
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AUDIO_SUBSYS2_IRQn = 15,//Swap the position of number 2 with number 0 ,
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AUDIO_SUBSYS1_IRQn = 16,//To keep consist with rtl design
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AUDIO_SUBSYS0_IRQn = 17,//
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SDIO_IRQn = 18,
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SDHOST1_IRQn = 19,
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SDHOST_IRQn = 20,
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LMAC_IRQn = 21,
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GMAC_IRQn = 22,
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DUAL_ORG_IRQn = 23,
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GEN422_IRQn = 24,
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CORET_IRQn = 25, //CPU TIMER
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SHA_IRQn = 26, //SHA/SYS_AES
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CRC_IRQn = 27,
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ADKEY0_IRQn = 28,
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PD_TMR_IRQn = 29,
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WKPND_IRQn = 30,
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PDWKPND_IRQn = 31,
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LVD_IRQn = 32,
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WDT_IRQn = 33,
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SYS_ERR_IRQn = 34,
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IIS0_IRQn = 35,
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IIS1_IRQn = 36,
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GPIOA_IRQn = 37,
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LO_MNT_IRQn = 38,
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DVP_IRQn = 39,
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MJPEG01_IRQn = 40,
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H264ENC_IRQn = 41,
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VPP_IRQn = 42,
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PRC_IRQn = 43,
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STMR5_IRQn = 44,
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PDM_IRQn = 45,
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LED_TMR_IRQn = 46,
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SCALE2_IRQn = 47,
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GFSK_IRQn = 48,
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CMPOUT0_IRQn = 49,
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UART6_IRQn = 50,
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SCALE3_IRQn = 51,
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IMG_ISP_IRQn = 52,
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MIPI_CSI2_IRQn = 53,
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RF_IRQn = 54,
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USB11_MC_IRQn = 55,
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USB11_DMA_IRQn = 56,
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RTC_VCCHVD_IRQn = 57,
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RTC_IRQn = 58,
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MIPI_DSI_IRQn = 59,
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PARA_OUT_IRQn = 60,
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M2M_DMA0_IRQn = 61,
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CAN_IRQn = 62,
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EXT_DCACHE_IRQn = 63,
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CPU_SPINLOCK_IRQn = 64,
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CPU_RECV_MAIL_IRQn = 65,
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CPU_SEND_MAIL_IRQn = 66,
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CPU_DBG_ON_IRQn = 67,
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OSPI_FIFO_IRQn = 68,
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OSPI_EFF_IRQn = 69,
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GEN420_IRQn = 70,
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SYS_AES_IRQn = 71,
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PKA_IRQn = 72,
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WDT1_IRQn = 73,
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GPIOB_IRQn = 74,
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GPIOC_IRQn = 75,
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GPIOD_IRQn = 76,
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GPIOE_IRQn = 77,
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GPIOF_IRQn = 78,
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DVP1_IRQn = 79,
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PNG_IRQn = 80,
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STMR4_IRQn = 81,
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STMR3_IRQn = 82,
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STMR2_IRQn = 83,
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STMR1_IRQn = 84,
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STMR0_IRQn = 85,
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CMPOUT1_IRQn = 86,
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UART5_IRQn = 87,
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UART4_IRQn = 88,
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MIPI1_CSI2_IRQn = 89,
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DMA2D_IRQn = 90,
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CSC_IRQn = 91,
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OSD_ENC_IRQn = 92,
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USB20PHY_IRQn = 93,
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PARA_IN_IRQn = 94,
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M2M_DMA1_IRQn = 95,
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WKUP_IRQn = 96,
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SAM_IRQn = 97,
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LIN_IRQn = 98,
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LIN1_IRQn = 99,
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CPU_SOFT_INT_IRQn = 100,
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M2M_DMA2_IRQn = 105,
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IRQ_NUM,
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};
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the CK804 Processor and Core Peripherals ------- */
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#define __CK803_REV 0x0000U /* Core revision r0p0 */
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#define __CK804_REV 0x0000U /* Core revision r0p0 */
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#define __MPU_PRESENT 0 /* MGU present or not */
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#define __VIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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#include "csi_core.h" /* Processor and core peripherals */
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#include "stdint.h"
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/** @addtogroup Peripheral_registers_structures
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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#define PSRAM_BASE_I ((uint32_t)0x08000000) /*!< SRAM base address in the alias region */
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#define PSRAM_END_ADDR_I ((uint32_t)0x10000000) /*!< SRAM end address in the alias region */
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#define FLASH_BASE ((uint32_t)0x10000000) /*!< FLASH base address in the alias region */
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#define FLASH_END_BASE ((uint32_t)0x20000000) /*!< FLASH base address in the alias region */
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#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define DCACHE_CTRL_BASE ((uint32_t)0x50000000)
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#define PSRAM_BASE ((uint32_t)0x28000000) /*!< SRAM base address in the alias region */
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#define PSRAM_END_ADDR ((uint32_t)0x30000000) /*!< SRAM end address in the alias region */
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/*!< Peripheral memory map */
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#define APB0_BASE PERIPH_BASE
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#define APB1_BASE (PERIPH_BASE + 0x10000)
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#define APB2_BASE (PERIPH_BASE + 0xc0000)
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#define AHB_BASE (PERIPH_BASE + 0x20000)
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#define GPIO_BASE (PERIPH_BASE + 0xe0000)
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#define SYSCTRL_BASE (AHB_BASE + 0x0000)
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#define CPUDBG_BASE (AHB_BASE + 0x0280)
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#define GPIOA_BASE (GPIO_BASE + 0x0000)
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#define GPIOB_BASE (GPIO_BASE + 0x0100)
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#define GPIOC_BASE (GPIO_BASE + 0x0200)
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#define GPIOD_BASE (GPIO_BASE + 0x0300)
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#define GPIOE_BASE (GPIO_BASE + 0x0400)
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#define GPIOF_BASE (GPIO_BASE + 0x0500)
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#define SYS_MNT_BASE (AHB_BASE + 0x023c)
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#define SDHOST_BASE (0x40040048)
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#define SDHOST1_BASE (0x40040068)
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#define SDIO_HOST_BASE (AHB_BASE + 0x3000) //not used
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#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
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#define LMAC_BASE (AHB_BASE + 0x42000)
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#define USB11S_BASE (PERIPH_BASE + 0x70000)
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#define GMAC_BASE (PERIPH_BASE + 0x71000)
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#define MODEM_BASE (PERIPH_BASE + 0xd0000)
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#define USB20_BASE (PERIPH_BASE + 0xf0000)
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//#define DMAC_BASE (AHB_BASE + 0x0000)
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//#define GPIOA_BASE (AHB_BASE + 0x2000)
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//#define GPIOB_BASE (AHB_BASE + 0x5000)
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//#define SYS_MNT_BASE (AHB_BASE + 0x9000)
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//-------------------------------------------------------
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// APB0 SYNC CLK DOMAIN PERIS
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//-------------------------------------------------------
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#define QSPI_BASE (APB0_BASE + 0x0000)
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#define OSPI_BASE (APB0_BASE + 0x1000)
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#define SCHED_BASE (APB0_BASE + 0x2000)
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#define UART0_BASE (APB2_BASE + 0x0000)
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#define UART1_BASE (APB2_BASE + 0x0100)
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#define UART2_BASE (APB2_BASE + 0x0200)
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#define UART3_BASE (APB2_BASE + 0x0300)
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#define UART4_BASE (APB2_BASE + 0x0b70)
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#define UART5_BASE (APB2_BASE + 0x0b90)
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#define UART6_BASE (APB2_BASE + 0x0bb0)
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#define SPI0_BASE (APB0_BASE + 0x7400)
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#define SPI1_BASE (APB0_BASE + 0x7500)
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#define SPI2_BASE (APB2_BASE + 0x0600)
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#define SPI3_BASE (APB2_BASE + 0x0700)
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#define SPI4_BASE (APB2_BASE + 0x0800)
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#define SPI5_BASE (APB2_BASE + 0x0b20)
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#define SPI6_BASE (APB2_BASE + 0x0b38)
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#define LED_BASE (APB0_BASE + 0x4b50)
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#define IIC0_BASE (APB0_BASE + 0x7400)
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#define IIC1_BASE (APB0_BASE + 0x7500)
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#define IIC2_BASE (APB2_BASE + 0x0600)
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#define IIC3_BASE (APB2_BASE + 0x0700)
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#define IIC4_BASE (APB2_BASE + 0x0800)
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#define IIS0_BASE (APB2_BASE + 0x3400)
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#define IIS1_BASE (APB2_BASE + 0x3440)
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#define PDM_BASE (APB2_BASE + 0x3480)
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#define PRC_BASE (APB0_BASE + 0x5000)
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#define OF_BASE (APB0_BASE + 0x5020)
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#define FT_BASE (APB0_BASE + 0x5040)
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#define PALE_BASE (APB0_BASE + 0x5060)
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#define VPP_BASE (APB0_BASE + 0x5100)
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#define MJPEG0_BASE (APB0_BASE + 0x5200)
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#define MJPEG0_DQT_BASE (APB0_BASE + 0x5280)
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#define MJPEG1_BASE (APB0_BASE + 0x5300)
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#define CSI2_HOST_BASE (APB0_BASE + 0x5700)
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#define MJPEG0_TAB_BASE (APB0_BASE + 0x5280)
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#define MJPEG1_TAB_BASE (APB0_BASE + 0x5380)
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#define MJPEG_HUFF_BASE (APB0_BASE + 0x5400)
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#define PARA_OUT_BASE (APB0_BASE + 0x6000)
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#define PARA_IN_BASE (APB0_BASE + 0x6040)
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#define DVP_BASE (APB0_BASE + 0x6070)
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#define DVP1_BASE (APB0_BASE + 0x6088)
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#define GEN422_BASE (APB0_BASE + 0x60a0)
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#define GEN420_BASE (APB0_BASE + 0x60e0)
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#define DUAL_ORG_BASE (APB0_BASE + 0x6110)
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#define MIPI_DSI_BASE (APB0_BASE + 0x6200)
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#define MIPI_CSI0_BASE (APB0_BASE + 0x6400)
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#define MIPI_CSI1_BASE (APB0_BASE + 0x6600)
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#define SCALE1_BASE (APB0_BASE + 0x7100)
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#define LCDC_BASE (APB0_BASE + 0x7000)
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#define ROT_BASE (APB1_BASE + 0xc140)
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#define FILL_BASE (APB1_BASE + 0xc180)
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#define CSC_BASE (APB1_BASE + 0xc200)
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#define OSD_ENC_BASE (APB1_BASE + 0xc240)
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#define SHADOW_BASE (APB1_BASE + 0xc280)
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#define TRANSFORM_BASE (APB1_BASE + 0xc300)
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#define SCALE2_BASE (APB0_BASE + 0x71A0)
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#define SCALE3_BASE (APB0_BASE + 0x7200)
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#define AUDIO_BASE (APB2_BASE + 0x3000)
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#define COMP_BASE (APB0_BASE + 0x9000)
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#define EFUSE_BASE (APB0_BASE + 0xa000)
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#define LO_MNT_BASE (APB2_BASE + 0x3740)
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#define AUDIO_DSP (APB2_BASE + 0x3600)
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#define CAN_RBUF_BASE (APB2_BASE + 0x4000)
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#define CAN_TBUF_BASE (APB2_BASE + 0x4050)
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#define CAN_CTRL_BASE (APB2_BASE + 0x4098)
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#define CAN_ACF_BASE (APB2_BASE + 0x40b8)
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#define FPGA_DDR_BASE (APB0_BASE + 0xf000)
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#define H264_REG_BASE (APB1_BASE + 0x1000)
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#define RFADCDIG_BASE (APB1_BASE + 0x4000)
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#define WDT_BASE (APB2_BASE + 0x1000)
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#define WDT1_BASE (APB2_BASE + 0x1010)
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#define TIMER_ALL_BASE (APB2_BASE + 0x1128)
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#define TIMER0_BASE (APB2_BASE + 0x1100)
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#define TIMER1_BASE (APB2_BASE + 0x1200)
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#define TIMER2_BASE (APB2_BASE + 0x1300)
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#define TIMER3_BASE (APB2_BASE + 0x1400)
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#define TIMER4_BASE (APB2_BASE + 0x1500)
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#define SUPTMR_BASE (APB2_BASE + 0x1600)
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#define SIMPLE_TIMER0_BASE (APB2_BASE + 0x1b00)
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#define SIMPLE_TIMER1_BASE (APB2_BASE + 0x1b10)
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#define SIMPLE_TIMER2_BASE (APB2_BASE + 0x1b20)
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#define SIMPLE_TIMER3_BASE (APB2_BASE + 0x1b30)
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#define SIMPLE_TIMER4_BASE (APB2_BASE + 0x1b40)
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#define SIMPLE_TIMER5_BASE (APB2_BASE + 0x1b50)
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#define CRC_BASE (APB1_BASE + 0x2000)
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#define SYS_AES_BASE (APB1_BASE + 0x2100)
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#define SHA_BASE (APB1_BASE + 0X2200)
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#define IMAGE_ISP_BASE (APB1_BASE + 0x6000)
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#define ISP_LSC_BASE (APB1_BASE + 0x6300)
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#define ISP_R_GAMMA_BASE (APB1_BASE + 0x6400)
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#define ISP_G_GAMMA_BASE (APB1_BASE + 0x6500)
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#define ISP_B_GAMMA_BASE (APB1_BASE + 0x6600)
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#define ISP_Y_GAMMA_BASE (APB1_BASE + 0x6700)
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#define ISP_R_HIST_BASE (APB1_BASE + 0x6800)
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#define ISP_G_HIST_BASE (APB1_BASE + 0x6900)
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#define ISP_B_HIST_BASE (APB1_BASE + 0x6a00)
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#define ISP_Y_HIST_BASE (APB1_BASE + 0x6b00)
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#define PMU_BASE (APB1_BASE + 0x8000)
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#define LVD_BASE (APB1_BASE + 0x8000)
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#define RTC_BASE (APB1_BASE + 0x8000)
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#define RFDIG_BASE (APB1_BASE + 0x9000)
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#define ADKEY_BASE (APB2_BASE + 0x2000)
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#define CMP_BASE (APB1_BASE + 0xa020)
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#define ADKEY1_BASE (APB1_BASE + 0xa024)
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#define USB11_BASE (APB1_BASE + 0xb000)
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#define DMA2D_BASE (APB1_BASE + 0xc000)
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#define DMA2D_FGCLUT_BASE (APB1_BASE + 0xc800)
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#define DMA2D_BGCLUT_BASE (APB1_BASE + 0xcc00)
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#define RFDIGCAL_BASE (APB1_BASE + 0xd000)
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#define NPU_BASE (APB1_BASE + 0xe000)
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#define SYSCTRL_BASE (AHB_BASE + 0x0000)
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#define GPIOA_BASE (GPIO_BASE + 0x0000)
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#define GPIOB_BASE (GPIO_BASE + 0x0100)
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#define GPIOC_BASE (GPIO_BASE + 0x0200)
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#define GPIOD_BASE (GPIO_BASE + 0x0300)
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#define GPIOE_BASE (GPIO_BASE + 0x0400)
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#define GPIOF_BASE (GPIO_BASE + 0x0500)
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#define AUDIO_CORDIC_BASE (AUDIO_BASE+ 0x500)
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#define AUDIO_DSP_FLT_BASE (AUDIO_BASE+ 0x600)
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#define AUDIO_EQ_BASE (AUDIO_BASE+ 0x700)
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#define AUDIO_ASRC_BASE (AUDIO_BASE+ 0x710)
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#define AUDIO_DRC_BASE (AUDIO_BASE+ 0x720)
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#define M2M_DMA_BASE (0x40040000)
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#define M2M_DMA0_BASE (M2M_DMA_BASE + 0x00)
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#define M2M_DMA1_BASE (M2M_DMA_BASE + 0x18)
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#define M2M_DMA2_BASE (M2M_DMA_BASE + 0x30)
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#define SYS_MNT_BASE (AHB_BASE + 0x023c)
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#define SDHOST_BASE (0x40040048)
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#define SDHOST1_BASE (0x40040068)
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#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
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#define MODEM_BASE (PERIPH_BASE + 0xd0000)
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#define LMAC_BASE (AHB_BASE + 0x42000)
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#define GMAC_BASE (PERIPH_BASE + 0x71000)
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#define USB20_BASE (PERIPH_BASE + 0xf0000)
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#define FT_USB3_BASE (APB0_BASE + 0x5040)
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#define LED_TIMER0_BASE (PMU_BASE + 0x000d0)
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#define LED_TIMER1_BASE (PMU_BASE + 0x000d4)
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#define LED_TIMER2_BASE (PMU_BASE + 0x000d8)
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#define LED_TIMER3_BASE (PMU_BASE + 0x000dc)
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#define CPU0_MSGBOX_BASE (0x80001000)
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#define CPU0_SPLCK_BASE (0x80001060)
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#define CPU1_MSGBOX_BASE (0x80000000)
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#define CPU1_SPLCK_BASE (0x80000060)
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#define CORESETTING_BASE (0x2006bf00)
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typedef enum {
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HG_AHB_PT_ALL,
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HG_AHB_PT_GPIOA_DEBUNCE,
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HG_AHB_PT_GPIOB_DEBUNCE,
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HG_AHB_PT_GPIOC_DEBUNCE,
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HG_AHB_PT_M2M_DMA,
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HG_AHB_PT_SYS_MNT,
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HG_AHB_PT_SDMMC,
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HG_AHB_PT_SDIO,
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HG_AHB_PT_MODEM,
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HG_AHB_PT_LMAC,
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HG_AHB_PT_GMAC,
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HG_AHB0_PT_DISPLAY, //scale0/2/3,rotate,screenshot,osd0,gama,dither,lcd_if,ccm_constrast_saturation,alpha_blend,video
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|
HG_AHB0_PT_VEDIO_IF, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
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|
|
|
HG_APB0_PT_ALL,
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|
HG_AHB0_PT_H264, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
|
|
HG_APB0_PT_QSPI,
|
|
HG_APB0_PT_OSPI,
|
|
HG_APB0_PT_UART0,
|
|
HG_APB0_PT_UART1,
|
|
HG_APB0_PT_UART4,
|
|
HG_APB0_PT_UART5,
|
|
HG_APB0_PT_UART6,
|
|
HG_APB0_PT_SPI0,
|
|
HG_APB0_PT_SPI1,
|
|
HG_APB0_PT_SPI2,
|
|
HG_APB0_PT_SPI3,
|
|
HG_APB0_PT_SPI5,
|
|
HG_APB0_PT_SPI6,
|
|
HG_APB0_PT_LED,
|
|
HG_APB0_PT_IIC0,
|
|
HG_APB0_PT_IIC1,
|
|
HG_APB0_PT_IIC2,
|
|
HG_APB0_PT_IIC3,
|
|
HG_APB0_PT_IIS0,
|
|
HG_APB0_PT_IIS1,
|
|
HG_APB0_PT_PDM,
|
|
HG_APB0_PT_JPEG,
|
|
HG_APB0_PT_DVP,
|
|
HG_APB0_PT_CMP,
|
|
HG_APB0_PT_EFUSE,
|
|
|
|
HG_APB1_PT_ALL,
|
|
HG_APB1_PT_AES,
|
|
HG_APB1_PT_ISP,
|
|
HG_APB1_PT_TMR0,
|
|
HG_APB1_PT_TMR1,
|
|
HG_APB1_PT_TMR2,
|
|
HG_APB1_PT_TMR3,
|
|
HG_APB1_PT_STMR,
|
|
HG_APB1_PT_SUPTMR,
|
|
HG_APB1_PT_CRC,
|
|
HG_APB1_PT_PMU,
|
|
HG_APB1_PT_LVD,
|
|
HG_APB1_PT_ADKEY,
|
|
HG_ASYNC_APB1_PT_AUDIO_SUB, //adc,dac,iis0/1,pdm,cordic,hs,sync,vad
|
|
} HG_Peripheral_Type;
|
|
|
|
typedef enum {
|
|
CPU_SPLOCK_ID_0,
|
|
CPU_SPLOCK_ID_1,
|
|
CPU_SPLOCK_ID_2,
|
|
CPU_SPLOCK_ID_3,
|
|
CPU_SPLOCK_ID_4,
|
|
CPU_SPLOCK_ID_5,
|
|
CPU_SPLOCK_ID_6,
|
|
CPU_SPLOCK_ID_7,
|
|
CPU_SPLOCK_ID_8,
|
|
CPU_SPLOCK_ID_9,
|
|
CPU_SPLOCK_ID_10,
|
|
CPU_SPLOCK_ID_11,
|
|
CPU_SPLOCK_ID_12,
|
|
CPU_SPLOCK_ID_13_DMA2D,
|
|
CPU_SPLOCK_ID_14_EFUSE,
|
|
CPU_SPLOCK_ID_15_DCACHE,
|
|
CPU_SPLOCK_ID_MAX,
|
|
} CPU_SPLOCK_ID;
|
|
|
|
#define EFUSE_OFFSET 3
|
|
#define JPG_NUM 2
|
|
#define OSC_CLK 32000000UL
|
|
|
|
#define JPG_NUM 2
|
|
|
|
#define CPU_CYCLE_VALUE() csi_coret_get_value()
|
|
#define IS_DCACHE_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
|
|
#define IS_PSRAM_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
|
|
#define IS_FLASH_ADDR(addr) ((uint32_t)(addr) >= FLASH_BASE && (uint32_t)(addr) < FLASH_END_BASE)
|
|
#define IS_SRAM_ADDR(addr) ((uint32_t)(addr) >= SRAM_BASE && (uint32_t)(addr) < PSRAM_BASE)
|
|
|
|
typedef struct {
|
|
uint32_t crc32;
|
|
volatile uint8 cpu1_ready;
|
|
volatile uint8 soft_int_pending;
|
|
uint8_t print_level;
|
|
uint8_t disable_print:1, dcache_maint_en:1, afh_en:1, rev:5;
|
|
uint8_t vif_maxcnt;
|
|
uint8_t bss_maxcnt;
|
|
uint16_t dbg_flags;
|
|
uint16_t sta_maxcnt;
|
|
uint16_t bss_lifetime;
|
|
uint32_t dbg_uart_dev;
|
|
uint32_t m2m_dma_dev;
|
|
uint32_t wdt1_to;
|
|
void * wdt1_irq_hdl;
|
|
uint32_t adc_dev;
|
|
uint32_t cpu_clk;
|
|
uint32_t rxbuf_addr;
|
|
uint32_t rxbuf_size;
|
|
uint32_t heap_addr;
|
|
uint32_t heap_size;
|
|
uint32_t skbpool_addr;
|
|
uint32_t skbpool_size;
|
|
uint32_t skbpool_flag;
|
|
uint32_t heap_flag;
|
|
uint32_t afh_chan_mask;
|
|
uint32_t psram_rsv_addr_core0;
|
|
|
|
} txw82x_CoreSetting;
|
|
#define CoreSetting ((txw82x_CoreSetting *) CORESETTING_BASE)
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|