83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
#ifndef _HG_M2M_DMA_H_
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#define _HG_M2M_DMA_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef TXW82X
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#define HG_M2M_DMA_NUM (CONFI_CORE_M2M_DMA ? 2 : 3)
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#define HG_M2M_DMA_MAX_LEN (1<<20)
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#else
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#define HG_M2M_DMA_NUM 2
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#define HG_M2M_DMA_MAX_LEN (64<<10)
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#endif
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/**
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* @brief M2M_DMA
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*/
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struct mem_dma_ch {
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__IO uint32 DMA_CON;
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__IO uint32 DMA_SAIE;
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__IO uint32 DMA_DATA;
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__IO uint32 DMA_SADR;
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__IO uint32 DMA_TADR;
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__IO uint32 DMA_DLEN;
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#ifdef TXW81X
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__IO uint32 DMA_ISIZE;
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#endif
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};
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struct mem_dma_hw {
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struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
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};
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struct mem_dma_dev {
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struct dma_device dev;
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struct mem_dma_hw *hw;
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uint32 irq_num[HG_M2M_DMA_NUM];
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uint32 busy_flag : 8,
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dma1_status : 1,
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dma1_mutex : 1,
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suspend : 1,
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reserved : 21;
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struct os_semaphore done[HG_M2M_DMA_NUM];
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};
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/** @brief M2M DMA register constant table definition
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* @{
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*/
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/***** DMA_CON *****/
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#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
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#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
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#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
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#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
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#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
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#define HG_M2M_DMA_CON_DTE (1UL << 0)
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/***** DMA_SAIE *****/
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#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
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#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
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/***** DMA_ISIZE *****/
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#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
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#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
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/***** DMA_DLEN *****/
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#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
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#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
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/**
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* @}
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*/
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int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
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#ifdef __cplusplus
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}
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#endif
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#endif
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