Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
201
sdk/include/hal/adc.h
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201
sdk/include/hal/adc.h
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@@ -0,0 +1,201 @@
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#ifndef _HAL_ADC_H_
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#define _HAL_ADC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC ioctl_cmd type
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*/
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enum adc_ioctl_cmd {
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ADC_IOCTL_SET_REF_TMP,
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ADC_IOCTL_GET_VREF,
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};
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/**
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* @brief ADC irq_flag type
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*/
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enum adc_irq_flag {
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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ADC_IRQ_FLAG_SAMPLE_DONE = BIT(0),
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};
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/* User interrupt handle */
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typedef void (*adc_irq_hdl)(uint32 irq, uint32 channel, uint32 irq_data);
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/* ADC api for user */
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struct adc_device {
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struct dev_obj dev;
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};
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struct adc_hal_ops{
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struct devobj_ops ops;
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int32(*open)(struct adc_device *adc);
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int32(*close)(struct adc_device *adc);
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int32(*add_channel)(struct adc_device *adc, uint32 channel);
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int32(*delete_channel)(struct adc_device *adc, uint32 channel);
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int32(*get_value)(struct adc_device *adc, uint32 channel, uint32 *raw_data);
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int32(*ioctl)(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
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int32(*request_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
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int32(*release_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag);
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};
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/* ADC API functions */
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/**
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* @brief adc_open
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_open(struct adc_device *adc);
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/**
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* @brief adc_close
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_close(struct adc_device *adc);
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/**
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* @brief adc_add_channel
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_add_channel(struct adc_device *adc, uint32 channel);
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/**
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* @brief adc_delete_channel
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_delete_channel(struct adc_device *adc, uint32 channel);
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/**
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* @brief adc_get_value
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_get_value(struct adc_device *adc, uint32 channel, uint32 *raw_data);
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/**
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* @brief adc_ioctl
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_ioctl(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
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/**
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* @brief adc_request_irq
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_request_irq(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
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/**
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* @brief adc_release_irq
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param adc The address of adc device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 adc_release_irq(struct adc_device *adc, enum adc_irq_flag irq_flag);
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int32 adc_get_vref(struct adc_device *adc, float *vref);
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#ifdef __cplusplus
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}
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#endif
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#endif
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272
sdk/include/hal/capture.h
Normal file
272
sdk/include/hal/capture.h
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@@ -0,0 +1,272 @@
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#ifndef _HAL_CAPTURE_H_
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#define _HAL_CAPTURE_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief CAPTURE channel type
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*/
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enum capture_channel {
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_CHANNEL_0,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_CHANNEL_1,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_CHANNEL_2,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_CHANNEL_3,
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};
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/**
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* @brief CAPTURE mode type
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*/
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enum capture_mode {
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_MODE_RISE,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_MODE_FALL,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_MODE_ALL,
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};
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/**
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* @brief CAPTURE irq_flag type
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*/
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enum capture_irq_flag {
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_IRQ_FLAG_CAPTURE,
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/*! Compatible version: V0;
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*@ Describe:
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*
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*/
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CAPTURE_IRQ_FLAG_OVERFLOW,
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};
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/**
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* @brief CAPTURE ioctl_cmd type
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*/
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enum capture_ioctl_cmd {
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NONE,
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};
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/* User interrupt handle */
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typedef void (*capture_irq_hdl)(uint32 irq, uint32 irq_data);
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/* CAPTURE api for user */
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struct capture_device {
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struct dev_obj dev;
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};
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struct capture_hal_ops{
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struct devobj_ops ops;
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int32(*init)(struct capture_device *cap, enum capture_channel channel, enum capture_mode mode);
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int32(*deinit)(struct capture_device *cap, enum capture_channel channel);
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int32(*start)(struct capture_device *cap, enum capture_channel channel);
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int32(*stop)(struct capture_device *cap, enum capture_channel channel);
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int32(*suspend)(struct capture_device *cap, enum capture_channel channel);
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int32(*resume)(struct capture_device *cap, enum capture_channel channel);
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int32(*ioctl)(struct capture_device *cap, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
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int32(*request_irq)(struct capture_device *cap, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
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int32(*release_irq)(struct capture_device *cap, enum capture_channel channel);
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};
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/* CAPTURE API functions */
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/**
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* @brief capture_init
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param capture The address of capture device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 capture_init(struct capture_device *capture, enum capture_channel channel, enum capture_mode mode);
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/**
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* @brief capture_deinit
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*
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* @Compatible version: V0;
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*
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* @note .
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*
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* @param capture The address of capture device in the RTOS.
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* @param .
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* @param .
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*
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* @return
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* - RET_OK Success
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* - RET_ERR Fail
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*/
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int32 capture_deinit(struct capture_device *capture, enum capture_channel channel);
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/**
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* @brief capture_start
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*
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* @Compatible version: V0;
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||||
*
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||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
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||||
* @return
|
||||
* - RET_OK Success
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||||
* - RET_ERR Fail
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||||
*/
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int32 capture_start(struct capture_device *capture, enum capture_channel channel);
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/**
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* @brief capture_stop
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*
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||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
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||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
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int32 capture_stop(struct capture_device *capture, enum capture_channel channel);
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/**
|
||||
* @brief capture_suspend channel
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||||
*
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||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
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||||
int32 capture_suspend(struct capture_device *capture, enum capture_channel channel);
|
||||
|
||||
/**
|
||||
* @brief capture_resume channel
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 capture_resume(struct capture_device *capture, enum capture_channel channel);
|
||||
|
||||
/**
|
||||
* @brief capture_ioctl
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 capture_ioctl(struct capture_device *capture, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
|
||||
|
||||
/**
|
||||
* @brief capture_request_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 capture_request_irq(struct capture_device *capture, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
|
||||
|
||||
/**
|
||||
* @brief capture_release_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param capture The address of capture device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 capture_release_irq(struct capture_device *capture, enum capture_channel channel);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
72
sdk/include/hal/crc.h
Normal file
72
sdk/include/hal/crc.h
Normal file
@@ -0,0 +1,72 @@
|
||||
#ifndef _HAL_CRC_H_
|
||||
#define _HAL_CRC_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum CRC_DEV_FLAGS {
|
||||
CRC_DEV_FLAGS_CONTINUE_CALC = BIT(0),
|
||||
};
|
||||
|
||||
enum CRC_DEV_TYPE {
|
||||
CRC_TYPE_CRC5_USB = 0,
|
||||
CRC_TYPE_CRC7_MMC,
|
||||
CRC_TYPE_CRC8_MAXIM,
|
||||
CRC_TYPE_CRC8,
|
||||
CRC_TYPE_CRC16,
|
||||
CRC_TYPE_CRC16_CCITT,
|
||||
CRC_TYPE_CRC16_MODBUS,
|
||||
CRC_TYPE_CRC32_WINRAR,
|
||||
CRC_TYPE_TCPIP_CHKSUM,
|
||||
|
||||
CRC_TYPE_MAX,
|
||||
};
|
||||
|
||||
/**
|
||||
* CRC len 512KB for TXW81x； 64KB for TXW80x
|
||||
*/
|
||||
struct crc_dev_req {
|
||||
uint16 type : 8,
|
||||
flag : 8;
|
||||
uint16 cookie;
|
||||
uint8 *data;
|
||||
uint32 len;
|
||||
uint32 crc_last; //use when CRC_DEV_FLAGS_CONTINUE_CALC
|
||||
};
|
||||
|
||||
struct crc_dev {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct crc_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*calc)(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags);
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Hold CRC .
|
||||
* @param dev : crc_dev use @ref dev_get() function to get the handle.
|
||||
* @param req : req(type\addr\len) for crc dev.
|
||||
* 1、req crc_last must set when flags:CRC_DEV_FLAGS_CONTINUE_CALC
|
||||
* @param crc_val : crc result.
|
||||
* @param flags : CRC_DEV_FLAGS .
|
||||
* @return
|
||||
* - RET_OK : Successfully.
|
||||
* - RET_ERR : Failed.
|
||||
* @note
|
||||
*/
|
||||
static inline int32 crc_dev_calc(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags)
|
||||
{
|
||||
const struct crc_hal_ops *ops = (const struct crc_hal_ops *)dev->dev.ops;
|
||||
return (dev && ops->calc) ? ops->calc(dev, req, crc_val, flags) : RET_ERR;
|
||||
}
|
||||
|
||||
extern uint32 hw_crc(enum CRC_DEV_TYPE type, uint8 *data, uint32 len);
|
||||
extern uint32 hw_crc_no_cache(enum CRC_DEV_TYPE type, uint8 *data, uint32 len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
80
sdk/include/hal/csc.h
Normal file
80
sdk/include/hal/csc.h
Normal file
@@ -0,0 +1,80 @@
|
||||
#ifndef HAL_CSC_H
|
||||
#define HAL_CSC_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*csc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
enum csc_ioctl_cmd {
|
||||
CSC_IOCTL_FORMAT_TRAN,
|
||||
|
||||
CSC_IOCTL_PHOTO_SIZE,
|
||||
|
||||
CSC_IOCTL_COEF_TYPE,
|
||||
|
||||
CSC_IOCTL_INPUT_ADDR,
|
||||
|
||||
CSC_IOCTL_OUTPUT_ADDR,
|
||||
|
||||
CSC_IOCTL_KICK_RUN,
|
||||
};
|
||||
|
||||
|
||||
enum csc_format {
|
||||
CSC_BGR565,
|
||||
CSC_RGB565,
|
||||
CSC_BGR888,
|
||||
CSC_RGB888,
|
||||
CSC_RGB888P,
|
||||
CSC_YUYV422,
|
||||
CSC_YVYU422,
|
||||
CSC_UYVY422,
|
||||
CSC_VYUY422,
|
||||
CSC_YUV422P,
|
||||
CSC_YUV422SP,
|
||||
CSC_YVU422SP,
|
||||
CSC_YUV420P,
|
||||
CSC_YUV444,
|
||||
CSC_YVU444,
|
||||
CSC_UVY444,
|
||||
CSC_VUY444,
|
||||
CSC_YUV444P,
|
||||
CSC_YUV444SP,
|
||||
CSC_YVU444SP,
|
||||
} ;
|
||||
|
||||
|
||||
|
||||
struct csc_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct csc_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct csc_device *csc_dev);
|
||||
int32(*suspend)(struct csc_device *csc_dev);
|
||||
int32(*resume)(struct csc_device *csc_dev);
|
||||
int32(*ioctl)(struct csc_device *csc_dev, enum csc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct csc_device *csc_dev, uint32 irq_flag, csc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct csc_device *csc_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 csc_suspend(struct csc_device *p_csc);
|
||||
int32 csc_resume(struct csc_device *p_csc);
|
||||
int32 csc_init(struct csc_device *p_csc);
|
||||
int32 csc_request_irq(struct csc_device *p_csc, uint32 irq_flags, csc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 csc_release_irq(struct csc_device *p_csc, uint32 irq_flags);
|
||||
int32 csc_set_format(struct csc_device *p_csc, uint8_t input_format,uint8_t output_format);
|
||||
int32 csc_set_photo_size(struct csc_device *p_csc, uint32_t w,uint32_t h);
|
||||
int32 csc_set_type(struct csc_device *p_csc, uint8_t type);
|
||||
int32 csc_set_input_addr(struct csc_device *p_csc, uint32_t in0,uint32_t in1,uint32_t in2);
|
||||
int32 csc_set_output_addr(struct csc_device *p_csc, uint32_t out0,uint32_t out1,uint32_t out2);
|
||||
int32 csc_start_run(struct csc_device *p_csc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
186
sdk/include/hal/csi2.h
Normal file
186
sdk/include/hal/csi2.h
Normal file
@@ -0,0 +1,186 @@
|
||||
#ifndef HAL_MIPI_CSI_H
|
||||
#define HAL_MIPI_CSI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*mipi_csi_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum mipi_csi_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_LANE_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_IMG_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_IMG_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_HSYNC_REC_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_HSYNC_REC_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_HSYNC_REC_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_HSYNC_REC_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_CROP_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_CROP_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_CROP_COORD_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_CROP_COORD_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_CROP_COORD_END,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_CROP_COORD_END,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_FORMAT_INPUT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI1_FORMAT_INPUT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_DPHY_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_DPHY_DBG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
MIPI_CSI_OPEN_VIRTUAL_CHANNEL,
|
||||
|
||||
MIPI_CSI_FTUSB3_OPEN,
|
||||
|
||||
MIPI_CSI_HS_RX_ZERO_CNT,
|
||||
|
||||
MIPI_CSI_GET_MATCH_VALUE,
|
||||
|
||||
MIPI_CSI_STOP_STATE,
|
||||
};
|
||||
|
||||
struct mipi_csi_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct mipi_csi_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct mipi_csi_device *mipi_csi_dev,uint8_t lane_num);
|
||||
int32(*deinit)(struct mipi_csi_device *mipi_csi_dev);
|
||||
int32(*open)(struct mipi_csi_device *mipi_csi_dev);
|
||||
int32(*baudrate)(struct mipi_csi_device *mipi_csi_dev, uint32 baudrate);
|
||||
int32(*close)(struct mipi_csi_device *mipi_csi_dev);
|
||||
int32(*ioctl)(struct mipi_csi_device *mipi_csi_dev, enum mipi_csi_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct mipi_csi_device *mipi_csi_dev, uint32 irq_flag, mipi_csi_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct mipi_csi_device *mipi_csi_dev, uint32 irq_flag);
|
||||
int32(*request_irq1)(struct mipi_csi_device *mipi_csi_dev, uint32 irq_flag, mipi_csi_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq1)(struct mipi_csi_device *mipi_csi_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 mipi_csi_open(struct mipi_csi_device *p_mipi_csi);
|
||||
int32 mipi_csi_close(struct mipi_csi_device *p_mipi_csi);
|
||||
int32 mipi_csi_init(struct mipi_csi_device *p_mipi_csi,uint8_t lane_num);
|
||||
int32 mipi_csi_deinit(struct mipi_csi_device *p_mipi_csi);
|
||||
int32 mipi_csi_set_baudrate(struct mipi_csi_device *p_mipi_csi, uint32 mclk);
|
||||
int32 mipi_csi_request_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags, mipi_csi_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 mipi_csi_release_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags);
|
||||
int32 mipi_csi1_request_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags, mipi_csi_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 mipi_csi1_release_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags);
|
||||
int32 mipi_csi_set_lane_num(struct mipi_csi_device *p_mipi_csi,uint32 lane_num);
|
||||
int32 mipi_csi_open_virtual_channel(struct mipi_csi_device *p_mipi_csi,uint8 open);
|
||||
int32 mipi_csi_img_size(struct mipi_csi_device *p_mipi_csi,uint32 w,uint32 h);
|
||||
int32 mipi_csi_hsync_rec_time(struct mipi_csi_device *p_mipi_csi,uint8 time);
|
||||
int32 mipi_csi_hsync_rec_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable);
|
||||
int32 mipi_csi_crop_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable);
|
||||
int32 mipi_csi_crop_img_start(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y);
|
||||
int32 mipi_csi_crop_img_end(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y);
|
||||
int32 mipi_csi_input_format(struct mipi_csi_device *p_mipi_csi,uint8 format);
|
||||
int32 mipi_csi_dphy_cfg(struct mipi_csi_device *p_mipi_csi,uint32 c0,uint32 c1,uint32 c2,uint32 c3,uint32 c4,uint32 c5,uint32 c6,uint32 c7);
|
||||
int32 mipi_csi_dphy_dbg(struct mipi_csi_device *p_mipi_csi,uint32 d0,uint32 d1,uint32 d2,uint32 d3);
|
||||
int32 mipi_csi_ftusb3_open(struct mipi_csi_device *p_mipi_csi, uint8 enable);
|
||||
int32 mipi_csi1_img_size(struct mipi_csi_device *p_mipi_csi,uint32 w,uint32 h);
|
||||
int32 mipi_csi1_hsync_rec_time(struct mipi_csi_device *p_mipi_csi,uint8 time);
|
||||
int32 mipi_csi1_hsync_rec_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable);
|
||||
int32 mipi_csi1_crop_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable);
|
||||
int32 mipi_csi1_crop_img_start(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y);
|
||||
int32 mipi_csi1_crop_img_end(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y);
|
||||
int32 mipi_csi1_input_format(struct mipi_csi_device *p_mipi_csi,uint8 format);
|
||||
int32 mipi_csi_hs_rx_zero_cnt_set(struct mipi_csi_device *p_mipi_csi, uint32 value);
|
||||
int32 mipi_csi_get_match_value(struct mipi_csi_device *p_mipi_csi, uint32 *value);
|
||||
int32 mipi_csi_get_stop_state(struct mipi_csi_device *p_mipi_csi, uint32 *value);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
151
sdk/include/hal/dma.h
Normal file
151
sdk/include/hal/dma.h
Normal file
@@ -0,0 +1,151 @@
|
||||
#ifndef _HAL_DMA_H_
|
||||
#define _HAL_DMA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* enum dma_status - DMA transaction status
|
||||
* @DMA_SUCCESS: transaction completed successfully
|
||||
* @DMA_IN_PROGRESS: transaction not yet processed
|
||||
* @DMA_PAUSED: transaction is paused
|
||||
* @DMA_ERROR: transaction failed
|
||||
*/
|
||||
enum dma_status {
|
||||
DMA_SUCCESS,
|
||||
DMA_IN_PROGRESS,
|
||||
DMA_PAUSED,
|
||||
DMA_ERROR,
|
||||
};
|
||||
|
||||
enum dma_xfer_direct {
|
||||
/*! xfer directiont: NONE
|
||||
*/
|
||||
DMA_XFER_DIR_NONE,
|
||||
|
||||
/*! xfer directiont: memory to memory
|
||||
*/
|
||||
DMA_XFER_DIR_M2M,
|
||||
|
||||
/*! xfer directiont: memory to device
|
||||
*/
|
||||
DMA_XFER_DIR_M2D,
|
||||
|
||||
/*! xfer directiont: device to memory
|
||||
*/
|
||||
DMA_XFER_DIR_D2M,
|
||||
|
||||
/*! xfer directiont: device to device
|
||||
*/
|
||||
DMA_XFER_DIR_D2D,
|
||||
};
|
||||
|
||||
enum dma_xfer_mode {
|
||||
/*! xfer mode: source address increase
|
||||
*/
|
||||
DMA_XFER_MODE_INCREASE,
|
||||
|
||||
/*! xfer mode: source address recycling
|
||||
*/
|
||||
DMA_XFER_MODE_RECYCLE,
|
||||
|
||||
/*! xfer mode: source address block copy
|
||||
*/
|
||||
DMA_XFER_MODE_BLKCPY,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* enum dma_slave_buswidth - defines bus with of the DMA slave
|
||||
* device, source or target buses
|
||||
*/
|
||||
enum dma_slave_buswidth {
|
||||
DMA_SLAVE_BUSWIDTH_1_BYTE = 0,
|
||||
DMA_SLAVE_BUSWIDTH_2_BYTES = 1,
|
||||
DMA_SLAVE_BUSWIDTH_4_BYTES = 2,
|
||||
DMA_SLAVE_BUSWIDTH_8_BYTES = 3,
|
||||
DMA_SLAVE_BUSWIDTH_UNDEFINED = 4,
|
||||
};
|
||||
|
||||
enum dma_irq_type {
|
||||
DMA_IRQ_TYPE_DONE,
|
||||
DMA_IRQ_TYPE_ERROR,
|
||||
};
|
||||
|
||||
enum dma_endian_type{
|
||||
DMA_ENDIAN_TYPE_NO_OVERTURN,
|
||||
DMA_ENDIAN_TYPE_16BIT_OVERTURN,
|
||||
DMA_ENDIAN_TYPE_32BIT_OVERTURN,
|
||||
};
|
||||
|
||||
enum dma_ioctl_cmd{
|
||||
DMA_IOCTL_CMD_ENDIAN,
|
||||
DMA_IOCTL_CMD_CHECK_DMA1_STATUS,
|
||||
DMA_IOCTL_CMD_DMA1_LOCK,
|
||||
DMA_IOCTL_CMD_DMA1_UNLOCK,
|
||||
};
|
||||
|
||||
struct dma_device;
|
||||
|
||||
typedef void (*dma_irq_hdl)(struct dma_device *p_dma, uint32 ch, enum dma_irq_type irq, uint32 data);
|
||||
|
||||
struct dma_xfer_data {
|
||||
uint32 dest;
|
||||
uint32 src;
|
||||
uint32 dir : 3, //enum dma_xfer_direct
|
||||
endian : 2,
|
||||
dst_id : 8,
|
||||
src_id : 8,
|
||||
src_addr_mode : 2,
|
||||
dst_addr_mode : 2,
|
||||
reserved : 7;
|
||||
uint32 element_per_width;
|
||||
uint32 element_num;
|
||||
uint32 irq_data;
|
||||
dma_irq_hdl irq_hdl;
|
||||
};
|
||||
|
||||
struct dma_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct dma_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*pause)(struct dma_device *dma, uint32 ch);
|
||||
int32(*resume)(struct dma_device *dma, uint32 ch);
|
||||
int32(*xfer)(struct dma_device *dma, struct dma_xfer_data *data);
|
||||
int32(*only_hw_xfer)(struct dma_device *dma, struct dma_xfer_data *data);
|
||||
int32(*get_status)(struct dma_device *dma, uint32 ch);
|
||||
int32(*stop)(struct dma_device *dma, uint32 ch);
|
||||
int32(*ioctl)(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
|
||||
};
|
||||
|
||||
int32 dma_pause(struct dma_device *dma, uint32 ch);
|
||||
|
||||
int32 dma_resume(struct dma_device *dma, uint32 ch);
|
||||
|
||||
void dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n);
|
||||
|
||||
void dma_memcpy_no_cache(struct dma_device *dma, void *dst, const void *src, uint32 n);
|
||||
|
||||
void dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n);
|
||||
|
||||
void dma_memset_word(struct dma_device *dma, void *dst, uint32 c, uint32 n);
|
||||
|
||||
void dma_memcpy_endian(struct dma_device *dma, void *dst, const void *src, uint32 n, enum dma_endian_type type);
|
||||
|
||||
int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
|
||||
|
||||
int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data);
|
||||
|
||||
int32 dma_status(struct dma_device *dma, uint32 ch);
|
||||
|
||||
int32 dma_stop(struct dma_device *dma, uint32 ch);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
183
sdk/include/hal/dma2d.h
Normal file
183
sdk/include/hal/dma2d.h
Normal file
@@ -0,0 +1,183 @@
|
||||
#ifndef _HAL_DMA2D_H_
|
||||
#define _HAL_DMA2D_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum dma2d_color_type {
|
||||
DMA2D_COLOR_TYPE_ARGB8888,
|
||||
DMA2D_COLOR_TYPE_RGB888 ,
|
||||
DMA2D_COLOR_TYPE_RGB565 ,
|
||||
DMA2D_COLOR_TYPE_ARGB1555,
|
||||
DMA2D_COLOR_TYPE_ARGB4444,
|
||||
DMA2D_COLOR_TYPE_L8 ,
|
||||
DMA2D_COLOR_TYPE_AL44 ,
|
||||
DMA2D_COLOR_TYPE_AL88 ,
|
||||
DMA2D_COLOR_TYPE_L4 ,
|
||||
DMA2D_COLOR_TYPE_A8 ,
|
||||
DMA2D_COLOR_TYPE_A4 ,
|
||||
DMA2D_COLOR_TYPE_RESERVED,
|
||||
};
|
||||
|
||||
enum dma2d_ioctl_type {
|
||||
DMA2D_IOCTL_CHECK_DONE,
|
||||
DMA2D_IOCTL_CHECK_RESULT,
|
||||
DMA2D_IOCTL_SUSPEND,
|
||||
DMA2D_IOCTL_SUSPEND_CHECK,
|
||||
DMA2D_IOCTL_RESUME,
|
||||
DMA2D_IOCTL_RESUME_CHECK,
|
||||
DMA2D_IOCTL_ABORT,
|
||||
DMA2D_IOCTL_WATERMARK,
|
||||
DMA2D_IOCTL_CONFIG_FG,
|
||||
DMA2D_IOCTL_CONFIG_BG,
|
||||
};
|
||||
|
||||
enum dma2d_irq_type {
|
||||
DMA2D_IRQ_TYPE_TRANS_ERR,
|
||||
DMA2D_IRQ_TYPE_TRANS_DONE,
|
||||
DMA2D_IRQ_TYPE_TRANS_WM,
|
||||
DMA2D_IRQ_TYPE_CLUT_ERR,
|
||||
DMA2D_IRQ_TYPE_CLUT_DONE,
|
||||
DMA2D_IRQ_TYPE_CONFIG_ERR,
|
||||
};
|
||||
|
||||
enum dma2d_clut_mode_type {
|
||||
DMA2D_CLUT_MODE_ARGB8888 = 0,
|
||||
DMA2D_CLUT_MODE_RGB888,
|
||||
};
|
||||
|
||||
enum dma2d_work_status {
|
||||
DMA2D_STATUS_DONE = 0,
|
||||
DMA2D_STATUS_WORKING,
|
||||
DMA2D_STATUS_SUSPEND,
|
||||
DMA2D_STATUS_CLUT_ERR,
|
||||
DMA2D_STATUS_CONFIG_ERR,
|
||||
DMA2D_STATUS_TRANS_ERR,
|
||||
DMA2D_STATUS_TIMEOUT,
|
||||
};
|
||||
|
||||
enum dma2d_alpha_type {
|
||||
DMA2D_ALPHA_MODE_SAVE = 0,
|
||||
DMA2D_ALPHA_MODE_FIXED_VAL,
|
||||
DMA2D_ALPHA_MODE_PRESENTAGE,
|
||||
DMA2D_ALPHA_MODE_RESERVED,
|
||||
};
|
||||
|
||||
struct dma2d_src_param {
|
||||
uint32 alpha_val : 8, alpha_mode : 8, alpha_reverse : 1, r_b_swap : 1, clut_mode : 4, reserved : 10;
|
||||
};
|
||||
|
||||
struct dma2d_dst_param {
|
||||
uint32 r_b_swap : 1, alpha_reverse : 1, byte_swap : 1, reserved : 29;
|
||||
};
|
||||
|
||||
struct dma2d_blkcpy_param {
|
||||
uint32 color_mode;
|
||||
uint32 src_addr;
|
||||
uint32 dst_addr;
|
||||
uint32 src_pixel_width : 16,
|
||||
dst_pixel_width : 16;
|
||||
uint32 blk_pixel_width : 16,
|
||||
blk_pixel_height : 16;
|
||||
uint32 src_pixel_start_width : 16,
|
||||
src_pixel_start_height : 16;
|
||||
uint32 dst_pixel_start_width : 16,
|
||||
dst_pixel_start_height : 16;
|
||||
};
|
||||
|
||||
struct dma2d_memcpy_param {
|
||||
uint32 color_mode;
|
||||
uint32 src_addr;
|
||||
uint32 dst_addr;
|
||||
uint32 src_pixel_width : 16,
|
||||
src_pixel_height : 16;
|
||||
};
|
||||
|
||||
struct dma2d_memset_param {
|
||||
uint32 color_mode;
|
||||
uint32 color_set;
|
||||
uint32 dst_addr;
|
||||
uint32 dst_pixel_width : 16,
|
||||
dst_pixel_height : 16;
|
||||
uint32 pixel_start_width : 16,
|
||||
pixel_start_height : 16;
|
||||
uint32 set_pixel_width : 16,
|
||||
set_pixel_height : 16;
|
||||
};
|
||||
|
||||
struct dma2d_convert_param {
|
||||
uint32 src_addr;
|
||||
uint32 dst_addr;
|
||||
uint32 photo_pixel_width : 16,
|
||||
photo_pixel_height : 16;
|
||||
uint32 src_color_mode : 16,
|
||||
dst_color_mode : 16;
|
||||
struct dma2d_src_param src_param;
|
||||
struct dma2d_dst_param dst_param;
|
||||
};
|
||||
|
||||
struct dma2d_mixture_param {
|
||||
uint32 photo0_addr;
|
||||
uint32 photo1_addr;
|
||||
uint32 output_addr;
|
||||
uint32 photo0_color_val;
|
||||
uint32 photo1_color_val;
|
||||
uint32 photo_pixel_width : 16,
|
||||
photo_pixel_height : 16;
|
||||
uint32 photo0_color_mode : 10,
|
||||
photo1_color_mode : 10,
|
||||
output_color_mode : 10,
|
||||
reserved : 2;
|
||||
struct dma2d_src_param src_param[2];
|
||||
struct dma2d_dst_param dst_param;
|
||||
};
|
||||
|
||||
|
||||
struct dma2d_clut_param {
|
||||
uint32 clut_addr;
|
||||
uint32 clut_size;
|
||||
enum dma2d_clut_mode_type clut_mode;
|
||||
};
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*dma2d_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* DMA2D api for user */
|
||||
struct dma2d_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct dma2d_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*blkcpy) (struct dma2d_device *dma2d, struct dma2d_blkcpy_param *p_blkcpy);
|
||||
int32(*memcpy) (struct dma2d_device *dma2d, struct dma2d_memcpy_param *p_memcpy);
|
||||
int32(*memset) (struct dma2d_device *dma2d, struct dma2d_memset_param *p_memset);
|
||||
int32(*convert)(struct dma2d_device *dma2d, struct dma2d_convert_param *p_convert);
|
||||
int32(*mixture)(struct dma2d_device *dma2d, struct dma2d_mixture_param *p_mixture);
|
||||
int32(*ioctl)(struct dma2d_device *dma2d, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct dma2d_device *dma2d, uint32 irq_flag, dma2d_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct dma2d_device *dma2d, uint32 irq_flag);
|
||||
};
|
||||
|
||||
/* DMA2d API functions */
|
||||
int32 dma2d_blkcpy (struct dma2d_device *dma2d, struct dma2d_blkcpy_param *p_blkcpy);
|
||||
int32 dma2d_memcpy (struct dma2d_device *dma2d, struct dma2d_memcpy_param *p_memcpy);
|
||||
int32 dma2d_memset (struct dma2d_device *dma2d, struct dma2d_memset_param *p_memset);
|
||||
int32 dma2d_convert(struct dma2d_device *dam2d, struct dma2d_convert_param *p_convert);
|
||||
int32 dma2d_mixture(struct dma2d_device *dma2d, struct dma2d_mixture_param *p_mixture);
|
||||
int32 dma2d_clut_init(struct dma2d_device *dam2d);
|
||||
int32 dma2d_ioctl(struct dma2d_device *dam2d);
|
||||
int32 dma2d_request_irq(struct dma2d_device *dam2d);
|
||||
int32 dma2d_release_irq(struct dma2d_device *dam2d);
|
||||
int32 dma2d_check_status(struct dma2d_device *dma2d);
|
||||
int32 dma2d_abort_trans(struct dma2d_device *dma2d);
|
||||
int32 dma2d_suspend_trans(struct dma2d_device *dma2d);
|
||||
int32 dma2d_suspend_status(struct dma2d_device *dma2d);
|
||||
int32 dma2d_resume_trans(struct dma2d_device *dma2d);
|
||||
int32 dma2d_resume_status(struct dma2d_device *dma2d);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
374
sdk/include/hal/dsi.h
Normal file
374
sdk/include/hal/dsi.h
Normal file
@@ -0,0 +1,374 @@
|
||||
#ifndef HAL_DSI_H
|
||||
#define HAL_DSI_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*dsi_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
// Data Types for Processor-Sourced Packets
|
||||
#define DSI_SP_VSS 0x01
|
||||
#define DSI_SP_VSE 0x11
|
||||
#define DSI_SP_HSS 0x21
|
||||
#define DSI_SP_HSE 0x31
|
||||
#define DSI_SP_EOTP 0x08
|
||||
#define DSI_SP_CMOFF 0x02
|
||||
#define DSI_SP_CMON 0x12
|
||||
#define DSI_SP_SDON 0x22
|
||||
#define DSI_SP_SDOFF 0x32
|
||||
#define DSI_SP_GENW0P 0x03
|
||||
#define DSI_SP_GENW1P 0x13
|
||||
#define DSI_SP_GENW2P 0x23
|
||||
#define DSI_SP_GENR0P 0x04
|
||||
#define DSI_SP_GENR1P 0x14
|
||||
#define DSI_SP_GENR2P 0x24
|
||||
#define DSI_SP_DCSW0P 0x05
|
||||
#define DSI_SP_DCSW1P 0x15
|
||||
#define DSI_SP_DCSR0P 0x06
|
||||
#define DSI_SP_MAXRPACK 0x37
|
||||
#define DSI_LP_NULL 0x09
|
||||
#define DSI_LP_BLANK 0x19
|
||||
#define DSI_LP_GENW 0x29
|
||||
#define DSI_LP_DCSW 0x39
|
||||
#define DSI_LP_PPS16B 0x0E
|
||||
#define DSI_LP_PPS18B 0x1E
|
||||
#define DSI_LP_LPPS18B 0x2E
|
||||
#define DSI_LP_PPS24B 0x3E
|
||||
|
||||
//display command set
|
||||
#define DSI_ENTER_IDLE_MODE 0x39
|
||||
#define DSI_ENTER_INVERT_MODE 0x21
|
||||
#define DSI_ENTER_NORMAL_MODE 0x13
|
||||
#define DSI_ENTER_PARTIAL_MODE 0x12
|
||||
#define DSI_ENTER_SLEEP_MODE 0x10
|
||||
#define DSI_EXIT_IDLE_MODE 0x38
|
||||
#define DSI_EXIT_INVERT_MODE 0x20
|
||||
#define DSI_EXIT_SLEEP_MODE 0x11
|
||||
#define DSI_NOP 0x00
|
||||
#define DSI_SET_DISPLAY_OFF 0x28
|
||||
#define DSI_SET_DISPLAY_ON 0x29
|
||||
#define DSI_SET_ALLP_ON 0x23
|
||||
#define DSI_SET_ALLP_OFF 0x22
|
||||
#define DSI_SET_TEAR_OFF 0x34
|
||||
#define DSI_SOFT_RESET 0x01
|
||||
#define DSI_SET_ADDRESS_MODE 0x36
|
||||
#define DSI_SET_GAMMA_CURVE 0x26
|
||||
#define DSI_SET_PIXEL_FORMAT 0x3A
|
||||
#define DSI_SET_TEAR_ON 0x35
|
||||
#define DSI_SET_SCROLL_START 0x37
|
||||
#define DSI_SET_TEAR_SCAN_LINE 0x44
|
||||
#define DSI_SET_COLUMN_ADDRESS 0x2A
|
||||
#define DSI_SET_PAGE_ADDRESS 0x2B
|
||||
#define DSI_SET_PARTIAL_COLUMNS 0x31
|
||||
#define DSI_SET_PARTIAL_ROWS 0x30
|
||||
#define DSI_SET_SCROLL_AREA 0x33
|
||||
#define DSI_WRITE_LUT 0x2D
|
||||
#define DSI_WRITE_MEMORY_CONTINUE 0x3C
|
||||
#define DSI_WRITE_MEMORY_START 0x2C
|
||||
#define DSI_GET_ADDRESS_MODE 0x0B
|
||||
#define DSI_GET_BLUE_CHANNEL 0x08
|
||||
#define DSI_GET_COMPRESSION_MODE 0x03
|
||||
#define DSI_GET_DIAGNOSTIC_RESULT 0x0F
|
||||
#define DSI_GET_DISPLAY_MODE 0x0D
|
||||
#define DSI_GET_GREEN_CHANNEL 0x07
|
||||
#define DSI_GET_PIXEL_FORMAT 0x0C
|
||||
#define DSI_GET_POWER_MODE 0x0A
|
||||
#define DSI_GET_RED_CHANNEL 0x06
|
||||
#define DSI_GET_SCAN_LINE 0x45
|
||||
#define DSI_GET_SIGNAL_MODE 0x0E
|
||||
#define DSI_READ_DDB_CONTINUE 0xA8
|
||||
#define DSI_READ_DDB_START 0xA1
|
||||
#define DSI_READ_MEMORY_CONTINUE 0x3E
|
||||
#define DSI_READ_MEMORY_START 0x2E
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum dsi_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_LANE_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_MAX_CLK_TIM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_REMAIN_STOP_STATE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CFG_ENABLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_ULPS_CTRL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_ULPS_MIN_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_ULPS_ENTRY_DELAY_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_ULPS_WAKEUP_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_ULPS_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CMD_VIDEO_SELECT_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GEN_VCID_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CMD_MODE_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_DPI_VCID,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_COLOR_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CFG_POL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_VID_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_VID_PKT_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_VID_CHUNK_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_VID_NULL_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_VID_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_LPCMD_TMR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_EDPI_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_DPHY_RST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_PIXEL_GENERIC_SRAM_FIFO,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_FIFO_DEPTH,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CMD_PKT_FIFO_EMPTY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_WAIT_PKT_FIFO_FULL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GEN_PLD_WRITE_FULL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GEN_PLD_READ_EMPTY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_CMD_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_SET_GEN_PLD_DATA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GET_GEN_PLD_DATA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GET_STA0,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_GET_STA1,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_SET_IO_REMAP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DSI_IOCTL_RESET_MODULE,
|
||||
|
||||
};
|
||||
|
||||
struct dsi_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct dsi_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct dsi_device *dsi_dev,uint8 clk_div,uint8_t tx_esc_clk_div,uint8_t auto_clklane,uint8_t lane_num,uint8_t clkselect,uint8_t div_strong);
|
||||
int32(*deinit)(struct dsi_device *dsi_dev);
|
||||
int32(*open)(struct dsi_device *dsi_dev);
|
||||
int32(*close)(struct dsi_device *dsi_dev);
|
||||
int32(*ioctl)(struct dsi_device *dsi_dev, enum dsi_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct dsi_device *dsi_dev, uint32 irq_flag, dsi_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct dsi_device *dsi_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
enum dsi_module_clk {
|
||||
DSI_MODULE_CLK_480M = 0,
|
||||
DSI_MODULE_CLK_960M,
|
||||
|
||||
DSI_MODULE_CLK_240M,
|
||||
};
|
||||
|
||||
int32 dsi_init(struct dsi_device *p_dsi,uint8 clk_div,uint8_t tx_esc_clk_div,uint8_t auto_clklane,uint8_t lane_num,uint8_t clkselect,uint8_t div_strong);
|
||||
int32 dsi_deinit(struct dsi_device *p_dsi);
|
||||
int32 dsi_open(struct dsi_device *p_dsi);
|
||||
int32 dsi_close(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_set_lane_num(struct dsi_device *p_dsi,uint8 lane_num);
|
||||
int32 mipi_dsi_max_clk_time(struct dsi_device *p_dsi,uint32 max_clk);
|
||||
int32 mipi_dsi_remain_stop_state(struct dsi_device *p_dsi,uint8 state);
|
||||
int32 mipi_dsi_cfg_enable(struct dsi_device *p_dsi,uint8_t htxeotp_en,uint8_t rxeotp_en,uint8_t bta_en,uint8_t ecc_en,uint8_t crc_en,uint8_t ltxeotp_en);
|
||||
int32 mipi_dsi_ulps_ctrl(struct dsi_device *p_dsi,uint8_t indatulps,uint8_t outdatulps,uint8_t inclkulps,uint8_t outclkulps);
|
||||
int32 mipi_dsi_ulps_min_time(struct dsi_device *p_dsi,uint8 time);
|
||||
int32 mipi_dsi_ulps_entry_delay_time(struct dsi_device *p_dsi,uint32 time);
|
||||
int32 mipi_dsi_ulps_wakeup_time(struct dsi_device *p_dsi,uint16 twakeup_clk,uint16 twakeup_cnt);
|
||||
int32 mipi_dsi_ulps_mode(struct dsi_device *p_dsi,uint8_t pll_off,uint8_t auto_ulps,uint8_t pre_pll_off_req);
|
||||
int32 mipi_dsi_select_mode(struct dsi_device *p_dsi,uint8 cmd);
|
||||
int32 mipi_dsi_gen_vcid_cfg(struct dsi_device *p_dsi,uint8_t vcid,uint8_t vcid_tear_auto,uint8_t vcid_tx_auto);
|
||||
int32 mipi_dsi_cmd_mode_cfg(struct dsi_device *p_dsi,uint8_t te_ack,uint8_t ack,uint8_t sw0p_tx,uint8_t sw1p_tx,uint8_t sw2p_tx,uint8_t sr0p_tx,uint8_t sr1p_tx,uint8_t sr2p_tx, uint8_t gen_lw_tx,uint8_t dcs_sw0p_tx,uint8_t dcs_sw1p_tx,uint8_t dcs_sr0p_tx,uint8_t dcs_lw_tx,uint8_t max_rd_pkt_size);
|
||||
int32 mipi_dsi_dpi_vcid(struct dsi_device *p_dsi,uint8 vcid);
|
||||
int32 mipi_dsi_color_cfg(struct dsi_device *p_dsi,uint8_t color_mode,uint8_t loosely18_en);
|
||||
int32 mipi_dsi_cfg_pol(struct dsi_device *p_dsi,uint8_t dataen_active,uint8_t vsync_active,uint8_t hsync_active,uint8_t shutd_active,uint8_t colorm_active);
|
||||
int32 mipi_dsi_vid_mode(struct dsi_device *p_dsi,uint8_t vsa_en,uint8_t vbp_en,uint8_t vfp_en,uint8_t vact_en,uint8_t hbp_en,uint8_t hfp_en,uint8_t frame_bta_ack_en,uint8_t cmd_en,uint8_t vid_mode_type);
|
||||
int32 mipi_dsi_vid_pkt_size(struct dsi_device *p_dsi,uint32 size);
|
||||
int32 mipi_dsi_vid_chunk_num(struct dsi_device *p_dsi,uint32 chunk_num);
|
||||
int32 mipi_dsi_vid_null_size(struct dsi_device *p_dsi,uint32 null_num);
|
||||
int32 mipi_dsi_vid_cfg(struct dsi_device *p_dsi,uint32 dpi2laneclkratio,uint32_t vid_vsa,uint32_t vid_vbp,uint32_t vid_vactive,uint32_t w,uint32_t vid_vfp,uint8_t hsa,uint8_t hbp,uint8_t hfp);
|
||||
int32 mipi_dsi_lpcmd_tmr(struct dsi_device *p_dsi,uint16_t invact_lptime,uint16_t outvact_lptime);
|
||||
int32 mipi_dsi_edpi_cfg(struct dsi_device *p_dsi,uint16_t edpi_maxpkt,uint8_t hw_te_on,uint8_t hw_te_gen,uint8_t hw_scan_line,uint16_t line_parameter);
|
||||
int32 mipi_dsi_phy_rst(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_set_pixel_sram_fifo(struct dsi_device *p_dsi,uint32 gen_addr);
|
||||
int32 mipi_dsi_set_fifo_depth(struct dsi_device *p_dsi,uint32 depth);
|
||||
int32 mipi_dsi_cmd_pkt_fifo_empty(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_wait_pkt_fifo_full(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_gen_pld_write_full(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_gen_pld_read_empty(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_cmd_cfg(struct dsi_device *p_dsi,uint8_t cmdid,uint8_t cmd,uint8_t vcid,uint8_t dat);
|
||||
int32 mipi_dsi_set_gen_pld_data(struct dsi_device *p_dsi,uint8_t param0,uint8_t param1,uint8_t param2,uint8_t param3);
|
||||
int32 mipi_dsi_get_gen_pld_data(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_set_lane_remap(struct dsi_device *p_dsi,uint8_t clklane,uint8_t lane0,uint8_t lane1,uint8_t lane2,uint8_t lane3,uint8_t clk_pol,uint8_t lane0_pol,uint8_t lane1_pol,uint8_t lane2_pol,uint8_t lane3_pol);
|
||||
int32 mipi_dsi_get_sta0(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_get_sta1(struct dsi_device *p_dsi);
|
||||
int32 mipi_dsi_reset_module(struct dsi_device *p_dsi);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
139
sdk/include/hal/dual_org.h
Normal file
139
sdk/include/hal/dual_org.h
Normal file
@@ -0,0 +1,139 @@
|
||||
#ifndef HAL_DUAL_H
|
||||
#define HAL_DUAL_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*dual_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
enum dual_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_INPUT_TYPE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_WORK_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_INPUT_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_OPEN_HDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_TIMER_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_SIZE_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_FS_TRIG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_RD_TRIG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_WR_CNT_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SET_PSRAM_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SAVE_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_RECOVER_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_SAVE_STA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DUAL_IOCTL_KICK_READ,
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
struct dual_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct dual_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct dual_device *dual_dev);
|
||||
int32(*deinit)(struct dual_device *dual_dev);
|
||||
int32(*open)(struct dual_device *dual_dev);
|
||||
int32(*close)(struct dual_device *dual_dev);
|
||||
int32(*ioctl)(struct dual_device *dual_dev, enum dual_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct dual_device *dual_dev, uint32 irq_flag, dual_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct dual_device *dual_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 dual_init(struct dual_device *p_dual);
|
||||
int32 dual_deinit(struct dual_device *p_dual);
|
||||
int32 dual_open(struct dual_device *p_dual);
|
||||
int32 dual_close(struct dual_device *p_dual);
|
||||
int32 dual_request_irq(struct dual_device *p_dual, uint32 irq_flags, dual_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 dual_release_irq(struct dual_device *p_dual, uint32 irq_flags);
|
||||
int32 dual_input_type(struct dual_device *p_dual,uint8 src,uint8 type);
|
||||
int32 dual_work_mode(struct dual_device *p_dual,uint8 mode);
|
||||
int32 dual_input_src_num(struct dual_device *p_dual,uint8 num);
|
||||
int32 dual_open_hdr(struct dual_device *p_dual,uint8 en);
|
||||
int32 dual_timer_cfg(struct dual_device *p_dual,uint32_t fs_clk_num,uint32_t hs_timer,uint32_t vs_timer);
|
||||
int32 dual_size_cfg(struct dual_device *p_dual,uint32_t src0_w,uint32_t src1_w,uint32_t src0_raw_num,uint32_t src1_raw_num);
|
||||
int32 dual_fs_trig(struct dual_device *p_dual,uint32 fs_trig_num);
|
||||
int32 dual_rd_trig(struct dual_device *p_dual,uint32 rd0_trig,uint32 rd1_trig);
|
||||
int32 dual_wr_cnt_cfg(struct dual_device *p_dual,uint32 src0_w,uint32 src0_h,uint32 src1_w,uint32 src1_h,uint32 src0_raw_num,uint32 src1_raw_num);
|
||||
int32 dual_set_addr(struct dual_device *p_dual,uint32 psram_Src0, uint32 psram_Src1);
|
||||
int32 dual_save_cfg(struct dual_device *p_dual, uint32 channel, uint32 img_size);
|
||||
int32 dual_recover_cfg(struct dual_device *p_dual);
|
||||
int32 dual_save_addr_cfg(struct dual_device *p_dual);
|
||||
int32 dual_save_status(struct dual_device *p_dual);
|
||||
int32 dual_kick_read(struct dual_device *p_dual);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
200
sdk/include/hal/dvp.h
Normal file
200
sdk/include/hal/dvp.h
Normal file
@@ -0,0 +1,200 @@
|
||||
#ifndef HAL_DVP_H
|
||||
#define HAL_DVP_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*dvp_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum dvp_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_FORMAT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_RGB_2_YUV,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_ADR_1,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_ADR_2,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_SCEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_HSYNC_VAILD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_VSYNC_VAILD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_ONE_SAMPLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_DEBOUNCE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_YCBCR_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_DIS_UV_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_FRAME_RATE,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_SET_THRESHOLD,
|
||||
|
||||
DVP_IOCTL_CMD_EX_D5_D6,
|
||||
|
||||
DVP_IOCTL_CMD_SET_JPEG_LEN,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_VSYNC_RST_TM,
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_10BITS_MAP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_8BITS_MAP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_PCLK_EDGE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_CROP_ENABLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_CROP_COORD_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_CROP_COORD_END,
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
DVP_IOCTL_CMD_GET_STA,
|
||||
|
||||
};
|
||||
|
||||
struct dvp_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct dvp_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct dvp_device *dvp_dev);
|
||||
int32(*deinit)(struct dvp_device *dvp_dev);
|
||||
int32(*baudrate)(struct dvp_device *dvp_dev, uint32 baudrate);
|
||||
int32(*open)(struct dvp_device *dvp_dev);
|
||||
int32(*close)(struct dvp_device *dvp_dev);
|
||||
int32(*ioctl)(struct dvp_device *dvp_dev, enum dvp_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct dvp_device *dvp_dev, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct dvp_device *dvp_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 dvp_open(struct dvp_device *p_dvp);
|
||||
int32 dvp_close(struct dvp_device *p_dvp);
|
||||
int32 dvp_init(struct dvp_device *p_dvp);
|
||||
int32 dvp_deinit(struct dvp_device *p_dvp);
|
||||
int32 dvp_set_baudrate(struct dvp_device *p_dvp, uint32 mclk);
|
||||
int32 dvp_set_size(struct dvp_device *p_dvp, uint32 x_s, uint32 y_s, uint32 x_e, uint32 y_e);
|
||||
int32 dvp_set_addr1(struct dvp_device *p_dvp, uint32 yuv_addr);
|
||||
int32 dvp_set_addr2(struct dvp_device *p_dvp, uint32 yuv_addr);
|
||||
int32 dvp_set_rgb2yuv(struct dvp_device *p_dvp, uint8 en);
|
||||
int32 dvp_set_format(struct dvp_device *p_dvp, uint8 format);
|
||||
int32 dvp_set_half_size(struct dvp_device *p_dvp, uint8 en);
|
||||
int32 dvp_set_vsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
|
||||
int32 dvp_set_hsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
|
||||
int32 dvp_set_once_sampling(struct dvp_device *p_dvp, uint8 en);
|
||||
int32 dvp_debounce_enable(struct dvp_device *p_dvp, uint8 en, uint8 pixel);
|
||||
int32 dvp_set_ycbcr(struct dvp_device *p_dvp, uint8 mode);
|
||||
int32 dvp_unload_uv(struct dvp_device *p_dvp, uint8 en);
|
||||
int32 dvp_frame_load_precent(struct dvp_device *p_dvp, uint8 precent);
|
||||
int32 dvp_low_high_threshold(struct dvp_device *p_dvp, bool low_high);
|
||||
int32 dvp_jpeg_mode_set_len(struct dvp_device *p_dvp, uint32 len);
|
||||
int32 dvp_request_irq(struct dvp_device *p_dvp, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 dvp_release_irq(struct dvp_device *p_dvp, uint32 irq_flag);
|
||||
int32 dvp_set_exchange_d5_d6(struct dvp_device *p_dvp, uint8 en);
|
||||
int32 dvp_10BITS_map(struct dvp_device *p_dvp, uint8 mode);
|
||||
int32 dvp_8BITS_map(struct dvp_device *p_dvp, uint8 mode);
|
||||
int32 dvp_set_vsync_rst_offline(struct dvp_device *p_dvp,uint8 enable,uint32 timeout);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
54
sdk/include/hal/gen420.h
Normal file
54
sdk/include/hal/gen420.h
Normal file
@@ -0,0 +1,54 @@
|
||||
#ifndef _HAL_GEN420_H_
|
||||
#define _HAL_GEN420_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum gen420_ioctl_cmd {
|
||||
GEN420_IOCTL_CMD_SET_SRAM_ADR,
|
||||
|
||||
GEN420_IOCTL_CMD_SET_PSRAM_ADR,
|
||||
|
||||
GEN420_IOCTL_CMD_SET_FRAME_SIZE,
|
||||
|
||||
GEN420_IOCTL_CMD_DST_MODE,
|
||||
|
||||
GEN420_IOCTL_CMD_DMA_RUN,
|
||||
};
|
||||
|
||||
|
||||
typedef int32(*gen420_irq_hdl)(uint32 irq_flag, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
struct gen420_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct gen420_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct gen420_device *gen420);
|
||||
int32(*suspend)(struct gen420_device *gen420);
|
||||
int32(*resume)(struct gen420_device *gen420);
|
||||
int32(*close)(struct gen420_device *gen420);
|
||||
int32(*ioctl)(struct gen420_device *gen420, enum gen420_ioctl_cmd cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct gen420_device *gen420,uint32 irq_flag,gen420_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct gen420_device *gen420, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
int32 gen420_suspend(struct gen420_device *p_gen);
|
||||
int32 gen420_resume(struct gen420_device *p_gen);
|
||||
int32 gen420_open(struct gen420_device *p_gen);
|
||||
int32 gen420_close(struct gen420_device *p_gen);
|
||||
int32 gen420_request_irq(struct gen420_device *p_gen, uint32 irq_flags, gen420_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 gen420_release_irq(struct gen420_device *p_gen, uint32 irq_flags);
|
||||
int32 gen420_sram_linebuf_adr(struct gen420_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr);
|
||||
int32 gen420_psram_adr(struct gen420_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr);
|
||||
int32 gen420_frame_size(struct gen420_device *p_gen,uint16 w,uint16 h);
|
||||
int32 gen420_dst_h264_and_jpg(struct gen420_device *p_gen,uint8 both);
|
||||
int32 gen420_dma_run(struct gen420_device *p_gen);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
72
sdk/include/hal/gen422.h
Normal file
72
sdk/include/hal/gen422.h
Normal file
@@ -0,0 +1,72 @@
|
||||
#ifndef _HAL_GEN422_H_
|
||||
#define _HAL_GEN422_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum gen422_ioctl_cmd {
|
||||
GEN422_IOCTL_CMD_SW_ENABLE,
|
||||
|
||||
GEN422_IOCTL_CMD_OUTPUT_SELECT,
|
||||
|
||||
GEN422_IOCTL_CMD_YUV_MODE,
|
||||
|
||||
GEN422_IOCTL_CMD_INPUT_SRC,
|
||||
|
||||
GEN422_IOCTL_CMD_SINGLE_MODE,
|
||||
|
||||
GEN422_IOCTL_CMD_SET_FRAME_SIZE,
|
||||
|
||||
GEN422_IOCTL_CMD_SET_FRAME_TIMING,
|
||||
|
||||
GEN422_IOCTL_CMD_SET_SRAM_ADDR,
|
||||
|
||||
GEN422_IOCTL_CMD_SET_PSRAM_ADDR,
|
||||
|
||||
GEN422_IOCTL_CMD_DMA_RUN,
|
||||
};
|
||||
|
||||
|
||||
typedef int32(*gen422_irq_hdl)(uint32 irq_flag, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
struct gen422_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct gen422_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct gen422_device *gen422);
|
||||
int32(*suspend)(struct gen422_device *gen422);
|
||||
int32(*resume)(struct gen422_device *gen422);
|
||||
int32(*close)(struct gen422_device *gen422);
|
||||
int32(*ioctl)(struct gen422_device *gen422, enum gen422_ioctl_cmd cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct gen422_device *gen422, uint32 irq_flag, gen422_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct gen422_device *gen422, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
int32 gen422_suspend(struct gen422_device *p_gen);
|
||||
int32 gen422_resume(struct gen422_device *p_gen);
|
||||
int32 gen422_open(struct gen422_device *p_gen);
|
||||
int32 gen422_close(struct gen422_device *p_gen);
|
||||
int32 gen422_request_irq(struct gen422_device *p_gen, uint32 irq_flags, gen422_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 gen422_release_irq(struct gen422_device *p_gen, uint32 irq_flags);
|
||||
int32 gen422_sw_enable(struct gen422_device *p_gen,uint8 enable);
|
||||
int32 gen422_output_enable(struct gen422_device *p_gen,uint8 vpp_en,uint8 bt_en);
|
||||
int32 gen422_yuv_mode(struct gen422_device *p_gen,uint8 yuv_mode);
|
||||
int32 gen422_input_from_sram_or_psram(struct gen422_device *p_gen,uint8 is_sram);
|
||||
int32 gen422_output_single_mode(struct gen422_device *p_gen,uint8 single);
|
||||
int32 gen422_frame_size(struct gen422_device *p_gen,uint16 w,uint16 h);
|
||||
int32 gen422_frame_time(struct gen422_device *p_gen,uint32 vsync,uint32 hsync,uint32 pclk);
|
||||
int32 gen422_sram_linebuf_adr(struct gen422_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr);
|
||||
int32 gen422_psram_adr(struct gen422_device *p_gen,uint32 frame0,uint32 frame1,uint32 w,uint32 h);
|
||||
int32 gen422_dma_run(struct gen422_device *p_gen);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
173
sdk/include/hal/gpio.h
Normal file
173
sdk/include/hal/gpio.h
Normal file
@@ -0,0 +1,173 @@
|
||||
/**
|
||||
* @file gpio.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @brief GPIO HAL driver
|
||||
* @version 1.0.0
|
||||
* @date 2021-9-8
|
||||
*
|
||||
* @copyright Copyright (c) 2021 HUGE-IC
|
||||
*/
|
||||
#ifndef _HAL_GPIO_H_
|
||||
#define _HAL_GPIO_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* @brief Enumeration constant for GPIO pin direction select
|
||||
* @note : this enum must mapping to OS @PinDirection
|
||||
*/
|
||||
enum gpio_pin_direction {
|
||||
/*! Set GPIO to input mode.
|
||||
*/
|
||||
GPIO_DIR_INPUT,
|
||||
|
||||
/*! Set GPIO to output mode.
|
||||
*/
|
||||
GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
/**
|
||||
* @breif : enum of GPIO pin mode
|
||||
* @note : this enum must mapping to OS @PinMode
|
||||
*/
|
||||
enum gpio_pin_mode {
|
||||
/*! gpio mode : push-pull & pull none
|
||||
*/
|
||||
GPIO_PULL_NONE,
|
||||
|
||||
/*! gpio mode : push-pull & pull up
|
||||
*/
|
||||
GPIO_PULL_UP,
|
||||
|
||||
/*! gpio mode : push-pull & pull down
|
||||
*/
|
||||
GPIO_PULL_DOWN,
|
||||
|
||||
/*! gpio mode : open-drain & pull none
|
||||
*/
|
||||
GPIO_OPENDRAIN_PULL_NONE,
|
||||
|
||||
/*! gpio mode : open-drain & pull up
|
||||
*/
|
||||
GPIO_OPENDRAIN_PULL_UP,
|
||||
|
||||
/*! Set the GPIO drop open-drain mode to NO.
|
||||
*/
|
||||
GPIO_OPENDRAIN_DROP_NONE,
|
||||
|
||||
/*! Set the GPIO drop open-drain mode to down mode.
|
||||
*/
|
||||
GPIO_OPENDRAIN_DROP_DOWN,
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* @breif : Enumeration constant for GPIO pin interrupt event.
|
||||
*/
|
||||
enum gpio_irq_event {
|
||||
/*! None interrupt event.
|
||||
*/
|
||||
GPIO_IRQ_EVENT_NONE,
|
||||
|
||||
/*! Rising interrupt event.
|
||||
*/
|
||||
GPIO_IRQ_EVENT_RISE,
|
||||
|
||||
/*! Falling interrupt event.
|
||||
*/
|
||||
GPIO_IRQ_EVENT_FALL,
|
||||
|
||||
/*! Rising and falling interrupt event.
|
||||
*/
|
||||
GPIO_IRQ_EVENT_ALL,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @breif : enum of io control cmd
|
||||
*/
|
||||
enum gpio_ioctl_cmd {
|
||||
/*! switch GPIO input delay on or off
|
||||
*/
|
||||
GPIO_INPUT_DELAY_ON_OFF,
|
||||
|
||||
/*! Atomic operation in GPIO direction.
|
||||
*/
|
||||
GPIO_DIR_ATOMIC,
|
||||
|
||||
/*! Atomic operation in GPIO vaule.
|
||||
*/
|
||||
GPIO_VALUE_ATOMIC,
|
||||
|
||||
/*! LOCK GPIO config exclude I/O DAT register until MCU reset or peripheral reset.
|
||||
*/
|
||||
GPIO_LOCK,
|
||||
|
||||
/*! GPIO debunce
|
||||
*/
|
||||
GPIO_DEBUNCE,
|
||||
|
||||
/*! GPIO toggle, use for output data toggle
|
||||
*/
|
||||
GPIO_OUTPUT_TOGGLE,
|
||||
|
||||
/*! Set GPIO pin to general analog function
|
||||
*/
|
||||
GPIO_GENERAL_ANALOG,
|
||||
|
||||
/*! Set GPIO pin to analog function with disable AIOEN
|
||||
*/
|
||||
GPIO_AIODIS_ANALOG,
|
||||
|
||||
GPIO_CMD_SET_IEEN,
|
||||
/*! Get IOMAP O_FUNC according to pin
|
||||
*/
|
||||
GPIO_GET_OUTMAP,
|
||||
|
||||
/*! Get IOMAP I_FUNC according to pin
|
||||
*/
|
||||
GPIO_GET_INMAP,
|
||||
|
||||
/* PARA1: enum smap_node
|
||||
* PARA2: enum smap_output/smap_input
|
||||
*/
|
||||
GPIO_SET_SMAP,
|
||||
/*! Get pin according to IOMAP O_FUNC
|
||||
*/
|
||||
GPIO_GET_OUTMAP_PIN,
|
||||
};
|
||||
|
||||
|
||||
typedef void (*gpio_irq_hdl)(int32 id, enum gpio_irq_event event, uint32 param1, uint32 param2);
|
||||
|
||||
struct gpio_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct gpio_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*mode)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
|
||||
int32(*dir)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_direction direction);
|
||||
int32(*set)(struct gpio_device *gpio, uint32 pin, uint32 val);
|
||||
int32(*get)(struct gpio_device *gpio, uint32 pin);
|
||||
int32(*request_pin_irq)(struct gpio_device *gpio, uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
|
||||
int32(*release_pin_irq)(struct gpio_device *gpio, uint32 pin, enum gpio_irq_event evt);
|
||||
int32(*ioctl)(struct gpio_device *gpio, uint32 pin, uint32 cmd, uint32 param1, uint32 param2);
|
||||
};
|
||||
|
||||
int32 gpio_set_mode(uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
|
||||
int32 gpio_set_dir(uint32 pin, enum gpio_pin_direction direction);
|
||||
int32 gpio_set_val(uint32 pin, uint32 value);
|
||||
int32 gpio_get_val(uint32 pin);
|
||||
int32 gpio_request_pin_irq(uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
|
||||
int32 gpio_release_pin_irq(uint32 pin, enum gpio_irq_event evt);
|
||||
int32 gpio_ioctl(uint32 pin, uint32 cmd, uint32 param1, uint32 param2);
|
||||
|
||||
extern struct gpio_device *gpio_get(uint32 pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
418
sdk/include/hal/h264.h
Normal file
418
sdk/include/hal/h264.h
Normal file
@@ -0,0 +1,418 @@
|
||||
#ifndef HAL_H264_H
|
||||
#define HAL_H264_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*h264_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum h264_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SRC_FROM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_HW_OPEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_IS_RUNNING,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SW_BUF_READY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SW_FRAME_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SW_READY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_VPP_VSYNC_DEALY_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_WRAP_IMG_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_PHY_IMG_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FRAME_BASE_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FRAME_QP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_TIMEOUT_LIMIT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_LEN_LIMIT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_REF_LU_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_REF_CHRO_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_FRM_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_ENC_CNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_ENC_FRAME_ID,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_DMA_BS_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FRAME_MB_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_REF_WB_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_REF_RB_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_RATE_CTL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_RATE_CTL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_RATE_CTL_BYTE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_RATE_CTL_RDCOST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_FLT_3DNR,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_FLT_3DNR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_Y_CROP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_MB_PIPE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_3DNR_LUT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_MIN_LUT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_MAX_LUT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_3DNR_SF,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_3DNR_CON,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_FLT_3DNR_CON1,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_BANDWIDTH_WR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_BANDWIDTH_RD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_DBG_CYC_DONE_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_FRM_LEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_DEC_DEL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_STA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_STA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_ENC_FRM_RDCOST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_DEC_CLR_ENC_FUNCS,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_DEC_HEADB_NUM,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_OE_SELECT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_FRAME_IMB,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_MBL_CALC,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_GET_MBL_CALC_MAX,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_IS_ERR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
H264_IOCTL_SET_ERR,
|
||||
|
||||
};
|
||||
|
||||
enum h264_module_clk {
|
||||
H264_MODULE_CLK_240M,
|
||||
H264_MODULE_CLK_480M,
|
||||
};
|
||||
|
||||
struct h264_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct h264_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct h264_device *h264_dev,enum h264_module_clk clk_type);
|
||||
int32(*suspend)(struct h264_device *h264_dev);
|
||||
int32(*resume)(struct h264_device *h264_dev);
|
||||
int32(*deinit)(struct h264_device *h264_dev);
|
||||
int32(*open)(struct h264_device *h264_dev);
|
||||
int32(*close)(struct h264_device *h264_dev);
|
||||
int32(*decode)(struct h264_device *h264_dev);
|
||||
int32(*ioctl)(struct h264_device *h264_dev, enum h264_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct h264_device *h264_dev, uint32 irq_flag, h264_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct h264_device *h264_dev, uint32 irq_flag);
|
||||
};
|
||||
int32 h264_suspend(struct h264_device *p_h264);
|
||||
int32 h264_resume(struct h264_device *p_h264);
|
||||
int32 h264_init(struct h264_device *p_h264,enum h264_module_clk clk_type);
|
||||
int32 h264_deinit(struct h264_device *p_h264);
|
||||
int32 h264_open(struct h264_device *p_h264);
|
||||
int32 h264_close(struct h264_device *p_h264);
|
||||
int32 h264_decode_start(struct h264_device *p_h264);
|
||||
int32 h264_request_irq(struct h264_device *p_h264, uint32 irq_flags, h264_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 h264_release_irq(struct h264_device *p_h264, uint32 irq_flags);
|
||||
int32 h264_set_src_from(struct h264_device *p_h264, uint8_t src_from);
|
||||
int32 h264_set_hw_open(struct h264_device *p_h264, uint8_t enable);
|
||||
int32 h264_set_sw_buf_ready(struct h264_device *p_h264);
|
||||
int32 h264_set_sw_frame_ready(struct h264_device *p_h264);
|
||||
int32 h264_set_sw_ready(struct h264_device *p_h264);
|
||||
int32 h264_set_vpp_vsync_delay(struct h264_device *p_h264, uint8_t enable);
|
||||
int32 h264_set_wrap_img_size(struct h264_device *p_h264, uint16_t w,uint16_t h);
|
||||
int32 h264_set_phy_img_size(struct h264_device *p_h264, uint16_t w,uint16_t h);
|
||||
int32 h264_set_frame_base_cfg(struct h264_device *p_h264, uint8_t frm_type,uint16_t enc_mode,uint32_t enc_bs_buf_size,uint32_t timeout_en);
|
||||
int32 h264_set_frame_qp(struct h264_device *p_h264, uint32_t frame_qp);
|
||||
int32 h264_set_timeout_limit(struct h264_device *p_h264, uint32_t time);
|
||||
int32 h264_set_len_limit(struct h264_device *p_h264, uint32_t len);
|
||||
int32 h264_set_ref_lu_addr(struct h264_device *p_h264, uint32_t saddr, uint32_t eaddr);
|
||||
int32 h264_set_ref_chro_addr(struct h264_device *p_h264, uint32_t saddr, uint32_t eaddr);
|
||||
int32 h264_set_frame_num(struct h264_device *p_h264, uint32_t num);
|
||||
int32 h264_set_enc_cnt(struct h264_device *p_h264, uint32_t cnt);
|
||||
int32 h264_set_enc_frame_id(struct h264_device *p_h264, uint32_t id);
|
||||
int32 h264_set_buf_addr(struct h264_device *p_h264, uint32_t addr);
|
||||
int32 h264_set_frame_mb_num(struct h264_device *p_h264, uint32_t num);
|
||||
int32 h264_set_ref_wb_addr(struct h264_device *p_h264, uint32_t lpf_lu_base, uint32_t lpf_ch_base);
|
||||
int32 h264_set_ref_rb_addr(struct h264_device *p_h264, uint32_t last_lpf_lu_base, uint32_t last_lpf_ch_base);
|
||||
int32 h264_set_frame_rate_ctl(struct h264_device *p_h264, uint32_t rc_grp,uint32_t rc_effort,uint32_t rc_en);
|
||||
int32 h264_get_rate_ctl(struct h264_device *p_h264);
|
||||
int32 h264_set_rate_ctl_byte(struct h264_device *p_h264,uint32_t byte);
|
||||
int32 h264_set_rate_ctl_rdcost(struct h264_device *p_h264,uint32_t rdcost);
|
||||
int32 h264_set_flt_3dnr(struct h264_device *p_h264,uint32_t dnr);
|
||||
int32 h264_get_flt_3dnr(struct h264_device *p_h264);
|
||||
int32 h264_set_y_crop(struct h264_device *p_h264,uint32_t enable,uint32_t linenum);
|
||||
int32 h264_set_mb_pipe(struct h264_device *p_h264,uint32_t pipe);
|
||||
int32 h264_set_flt_3dnr_lut(struct h264_device *p_h264,uint32_t num,uint32_t param);
|
||||
int32 h264_set_flt_min_lut(struct h264_device *p_h264,uint32_t num,uint32_t param);
|
||||
int32 h264_set_flt_max_lut(struct h264_device *p_h264,uint32_t num,uint32_t param);
|
||||
int32 h264_set_flt_3dnr_sf(struct h264_device *p_h264,uint32_t param);
|
||||
int32 h264_set_flt_3dnr_con(struct h264_device *p_h264,uint32_t param);
|
||||
int32 h264_set_flt_3dnr_con1(struct h264_device *p_h264,uint32_t param);
|
||||
int32 h264_get_bandwidth_wr(struct h264_device *p_h264);
|
||||
int32 h264_get_bandwidth_rd(struct h264_device *p_h264);
|
||||
int32 h264_get_cyc_done_num(struct h264_device *p_h264);
|
||||
int32 h264_get_frame_len(struct h264_device *p_h264);
|
||||
int32 h264_get_dec_del(struct h264_device *p_h264);
|
||||
int32 h264_set_sta(struct h264_device *p_h264,uint32_t sta);
|
||||
int32 h264_get_sta(struct h264_device *p_h264);
|
||||
int32 h264_get_enc_frame_rdcost(struct h264_device *p_h264);
|
||||
int32 h264_set_enc_frame_rdcost(struct h264_device *p_h264);
|
||||
int32 h264_set_dec_headb_num(struct h264_device *p_h264,uint32_t dec_num);
|
||||
int32 h264_set_oe_select(struct h264_device *p_h264,uint8_t enable,uint8_t oe);
|
||||
int32 h264_is_running(struct h264_device *p_h264);
|
||||
|
||||
int32 h264_get_mbl_calc(struct h264_device *p_h264);
|
||||
int32 h264_get_mbl_calc_max(struct h264_device *p_h264);
|
||||
int32 h264_is_err(struct h264_device *p_h264);
|
||||
int32 h264_set_err(struct h264_device *p_h264,uint32_t err);
|
||||
int32 h264_get_imb_num(struct h264_device *p_h264);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
174
sdk/include/hal/i2c.h
Normal file
174
sdk/include/hal/i2c.h
Normal file
@@ -0,0 +1,174 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file sdk/include/hal/i2c.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @version V1.0.0
|
||||
* @date 01-08-2018
|
||||
* @brief Main program body header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2018 HUGE-IC</center></h2>
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef _HAL_I2C_H_
|
||||
#define _HAL_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup Template_Project
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for IIC ioctrl cmd
|
||||
*/
|
||||
enum i2c_ioctl_cmd {
|
||||
/*! IIC SDA output delay
|
||||
*/
|
||||
IIC_SDA_OUTPUT_DELAY,
|
||||
|
||||
/*! IIC SCL strong output
|
||||
*@note: I/O cannot be configured when the strong output is on
|
||||
*/
|
||||
IIC_STRONG_OUTPUT,
|
||||
|
||||
IIC_FILTERING,
|
||||
|
||||
IIC_SET_DEVICE_ADDR,
|
||||
|
||||
IIC_SET_WRITE_TABLE_MODE,
|
||||
|
||||
IIC_GET_TX_STATUS,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for IIC mode selection
|
||||
*/
|
||||
enum i2c_mode {
|
||||
/*! IIC selects the master mode.
|
||||
*/
|
||||
IIC_MODE_MASTER,
|
||||
|
||||
/*! IIC selects the slave mode.
|
||||
*/
|
||||
IIC_MODE_SLAVE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for IIC address bit selection
|
||||
*/
|
||||
enum i2c_addr_mode {
|
||||
/*! The IIC communication address selects the 7-bit mode.
|
||||
*/
|
||||
|
||||
IIC_ADDR_7BIT,
|
||||
/*! The IIC communication address selects the 10-bit mode.
|
||||
*/
|
||||
IIC_ADDR_10BIT,
|
||||
};
|
||||
|
||||
enum i2c_irq_flag {
|
||||
/*!
|
||||
* @brief Interrupt: IIC send data completed.
|
||||
* @Note
|
||||
* This interrupt is only used for IIC transmit.
|
||||
*/
|
||||
I2C_IRQ_FLAG_TX_DONE = BIT(0),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: IIC receive data completed.
|
||||
* @Note:
|
||||
* This interrupt is only used for IIC receive.
|
||||
*/
|
||||
I2C_IRQ_FLAG_RX_DONE = BIT(1),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: IIC slave nack to IIC master
|
||||
*/
|
||||
I2C_IRQ_FLAG_RX_NACK = BIT(2),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: IIC rececive error
|
||||
* @Note:
|
||||
* IIC buf overflow means rx error
|
||||
*/
|
||||
I2C_IRQ_FLAG_RX_ERROR = BIT(3),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: IIC detect stop
|
||||
* @Note:
|
||||
* IIC has detected the stop signal on the bus
|
||||
*/
|
||||
I2C_IRQ_FLAG_DETECT_STOP = BIT(4),
|
||||
|
||||
/*
|
||||
* @brief Interrupt: IIC slave addressed
|
||||
* @Note :
|
||||
* The interrupt triggered when the II slave is addressed
|
||||
*/
|
||||
|
||||
I2C_IRQ_FLAG_SLAVE_ADDRESSED = BIT(5)
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
typedef void (*i2c_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
struct i2c_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct i2c_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
|
||||
int32(*close)(struct i2c_device *i2c);
|
||||
int32(*ioctl)(struct i2c_device *i2c, int32 cmd, uint32 param);
|
||||
int32(*baudrate)(struct i2c_device *i2c, uint32 baudrate);
|
||||
int32(*read)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
|
||||
int32(*write)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
|
||||
int32(*write_scatter)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
|
||||
int32(*write_table)(struct i2c_device *i2c, uint8 cmd_len, uint8 slave_id, scatter_data *data);
|
||||
int32(*request_irq)(struct i2c_device *i2c, i2c_irq_hdl irqhdl, uint32 irq_data, uint32 irq_flag);
|
||||
int32(*release_irq)(struct i2c_device *i2c, uint32 irq_flag);
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HGI2C_DW_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32 i2c_open(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
|
||||
int32 i2c_close(struct i2c_device *i2c);
|
||||
int32 i2c_set_baudrate(struct i2c_device *i2c, uint32 baudrate);
|
||||
int32 i2c_ioctl(struct i2c_device *i2c, uint32 cmd, uint32 param);
|
||||
int32 i2c_read(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
|
||||
int32 i2c_write(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
|
||||
int32 i2c_write_scatter(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
|
||||
int32 i2c_master_write_table(struct i2c_device *i2c, uint8 cmd_len, uint8 slave_id, scatter_data *data);
|
||||
int32 i2c_request_irq(struct i2c_device *i2c, i2c_irq_hdl handle, uint32 irq_data, uint32 irq_flag);
|
||||
int32 i2c_release_irq(struct i2c_device *i2c, uint32 irq_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
325
sdk/include/hal/i2s.h
Normal file
325
sdk/include/hal/i2s.h
Normal file
@@ -0,0 +1,325 @@
|
||||
#ifndef _HAL_I2S_H_
|
||||
#define _HAL_I2S_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief i2s bit width per sample type
|
||||
*/
|
||||
enum i2s_sample_bits {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s bit width per sample: 8bits
|
||||
*/
|
||||
I2S_SAMPLE_BITS_8BITS,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s bit width per sample: 16bits
|
||||
*/
|
||||
I2S_SAMPLE_BITS_16BITS,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s bit width per sample: 24bits
|
||||
*/
|
||||
I2S_SAMPLE_BITS_24BITS,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2s sample frequency type
|
||||
*/
|
||||
enum i2s_sample_freq {
|
||||
|
||||
I2S_SAMPLE_FREQ_8K,
|
||||
|
||||
|
||||
I2S_SAMPLE_FREQ_16K,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s sample frequency: 44.1K(WS frequency)
|
||||
*/
|
||||
I2S_SAMPLE_FREQ_44_1K,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s sample frequency: 48K(WS frequency)
|
||||
*/
|
||||
I2S_SAMPLE_FREQ_48K,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief i2s channel type
|
||||
*/
|
||||
enum i2s_channel {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s mono channel
|
||||
*/
|
||||
I2S_CHANNEL_MONO,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s stereo channel
|
||||
*/
|
||||
I2S_CHANNEL_STEREO,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2s data format type
|
||||
*/
|
||||
enum i2s_data_fmt {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S communication format I2S
|
||||
*/
|
||||
I2S_DATA_FMT_I2S,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S communication format MSB(right justified)
|
||||
*/
|
||||
I2S_DATA_FMT_MSB,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S communication format LSB(left justified)
|
||||
*/
|
||||
I2S_DATA_FMT_LSB,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S communication format PCM
|
||||
*/
|
||||
I2S_DATA_FMT_PCM,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2s mode type
|
||||
*/
|
||||
enum i2s_mode {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S master mode setting
|
||||
*/
|
||||
I2S_MODE_MASTER,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S slave mode setting
|
||||
*/
|
||||
I2S_MODE_SLAVE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi ioctl cmd
|
||||
*
|
||||
*/
|
||||
enum i2s_ioctl_cmd {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* Set the polarity of WSCLK
|
||||
*@The specific Settings:
|
||||
* (1)left channel WSCLK level is low , right channel WSCLK level is high
|
||||
* (2)left channel WSCLK level is high, right channel WSCLK level is low
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_WSCLK_POL,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s bit width per sample
|
||||
*@The specific Settings:
|
||||
* (1)I2S_SAMPLE_BITS_8BITS
|
||||
* (2)I2S_SAMPLE_BITS_16BITS
|
||||
* (3)I2S_SAMPLE_BITS_24BITS
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_SAMPLE_BITS,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s bit width per sample
|
||||
*@The specific Settings:
|
||||
* (1)I2S_CHANNEL_MONO
|
||||
* (2)I2S_CHANNEL_STEREO
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_CHANNEL,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s communication format
|
||||
*@The specific Settings:
|
||||
* (1)I2S_DATA_FMT_I2S
|
||||
* (2)I2S_DATA_FMT_MSB
|
||||
* (3)I2S_DATA_FMT_LSB
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_DATA_FMT,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s open WSCLK & BCLK & DATA debounce
|
||||
* (Only for i2s slave)
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_DEBOUNCE,
|
||||
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* i2s open duplex using iis0 & iis1
|
||||
*/
|
||||
I2S_IOCTL_CMD_SET_DUPLEX,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi request interrupt flag
|
||||
*
|
||||
*/
|
||||
enum i2s_irq_flag {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S interrupt signal that transmits half of the data
|
||||
*/
|
||||
I2S_IRQ_FLAG_HALF = BIT(0),
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* I2S interrupt signal that transmits all data
|
||||
*/
|
||||
I2S_IRQ_FLAG_FULL = BIT(1),
|
||||
|
||||
I2S_IRQ_FLAG_RESET = BIT(2),
|
||||
};
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*i2s_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* I2S api for user */
|
||||
struct i2s_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct i2s_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
|
||||
int32(*close)(struct i2s_device *i2s);
|
||||
int32(*ioctl)(struct i2s_device *i2s, uint32 cmd, uint32 param);
|
||||
int32(*read)(struct i2s_device *i2s, void *buf, uint32 len);
|
||||
int32(*write)(struct i2s_device *i2s, const void *buf, uint32 len);
|
||||
int32(*write_scatter)(struct i2s_device *i2s, const scatter_data *data, uint32 count);
|
||||
int32(*request_irq)(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct i2s_device *i2s, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
/* I2S API functions */
|
||||
|
||||
/**
|
||||
* @brief i2s_open.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @note This function must be called before any I2S driver operations.
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param mode I2S work mode setting - see "enum i2s_mode".
|
||||
* @param frequency I2S sample frequency setting - see "enum i2s_sample_freq".
|
||||
* @param bits I2S sample bits setting - see "enum i2s_sample_bits".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_open(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
|
||||
|
||||
/**
|
||||
* @brief i2s_close.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_close(struct i2s_device *i2s);
|
||||
|
||||
/**
|
||||
* @brief i2s_write.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param buf Write the start address of buf.
|
||||
* @param len Write length, uint: byte.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_write(struct i2s_device *i2s, const void *buf, uint32 len);
|
||||
|
||||
int32 i2s_write_scatter(struct i2s_device *i2s, const scatter_data *data, uint32 count);
|
||||
|
||||
/**
|
||||
* @brief i2s_read.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param buf Read the start address of buf.
|
||||
* @param len Read length, uint: byte.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_read(struct i2s_device *i2s, void *buf, uint32 len);
|
||||
|
||||
/**
|
||||
* @brief i2s_ioctl.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param cmd Control command - see"enum i2s_ioctl_cmd".
|
||||
* @param param Parameters required to execute the current Control command.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_ioctl(struct i2s_device *i2s, uint32 cmd, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief i2s_request_irq.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param irq_flag The type of interrupt - see"enum i2s_irq_flag".
|
||||
* @param irqhdl The interrupt function.
|
||||
* @param irq_data The parameters of the interrupt function
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_request_irq(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
|
||||
|
||||
/**
|
||||
* @brief i2s_release_irq.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param i2s The address of I2S device in the RTOS.
|
||||
* @param irq_flag The type of interrupt - see"enum i2s_irq_flag".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 i2s_release_irq(struct i2s_device *i2s, uint32 irq_flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
493
sdk/include/hal/isp.h
Normal file
493
sdk/include/hal/isp.h
Normal file
@@ -0,0 +1,493 @@
|
||||
#ifndef _HAL_ISP_H_
|
||||
#define _HAL_ISP_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "hal/isp_param.h"
|
||||
#include "lib/video/isp/isp_ircut.h"
|
||||
|
||||
#define EVENT_ISP_CALC (BIT(0))
|
||||
#define EVENT_ISP_IMG_OPT (BIT(1))
|
||||
#define EVENT_ISP_FPS_OPT (BIT(2))
|
||||
|
||||
enum sensor_type {
|
||||
SENSOR_TYPE_MASTER = 0,
|
||||
SENSOR_TYPE_SLAVE0,
|
||||
SENSOR_TYPE_SLAVE1,
|
||||
};
|
||||
|
||||
enum isp_input_dat_src{
|
||||
ISP_INPUT_DAT_SRC_DVP = 0,
|
||||
ISP_INPUT_DAT_SRC_DVP1,
|
||||
ISP_INPUT_DAT_SRC_MIPI0,
|
||||
ISP_INPUT_DAT_SRC_MIPI1,
|
||||
ISP_INPUT_DAT_SRC_ORG_DMA,
|
||||
ISP_INPUT_DAT_SRC_GEN422,
|
||||
ISP_INPUT_DAT_SRC_PARA,
|
||||
ISP_INPUT_DAT_SRC_RESERVED,
|
||||
};
|
||||
|
||||
enum isp_yuv_range {
|
||||
ISP_YUV_RANGE_NARROW = 0,
|
||||
ISP_YUV_RANGE_FULL,
|
||||
};
|
||||
|
||||
enum isp_yuv_gamut {
|
||||
ISP_YUV_GAMUT_BT601,
|
||||
ISP_YUV_GAMUT_BT709,
|
||||
};
|
||||
|
||||
enum isp_input_dat_format{
|
||||
ISP_INPUT_DAT_FORMAT_RAW08,
|
||||
ISP_INPUT_DAT_FORMAT_RAW10,
|
||||
ISP_INPUT_DAT_FORMAT_RAW12,
|
||||
ISP_INPUT_DAT_FORMAT_YUV422,
|
||||
};
|
||||
|
||||
enum isp_bayer_format{
|
||||
ISP_BAYER_FORMAT_RGGB,
|
||||
ISP_BAYER_FORMAT_GRBG,
|
||||
ISP_BAYER_FORMAT_GBRG,
|
||||
ISP_BAYER_FORMAT_BGGR,
|
||||
};
|
||||
|
||||
enum isp_ycrcb_gamut_type{
|
||||
ISP_YCRCB_GAMUT_TYPE_BT601,
|
||||
ISP_YCRCB_GAMUT_TYPE_BT709,
|
||||
};
|
||||
|
||||
enum isp_ycrcb_range{
|
||||
ISP_YCRCB_RANGE_NARROW,
|
||||
ISP_YCRCB_RANGE_FULL,
|
||||
};
|
||||
|
||||
enum isp_detect_frame_interval{
|
||||
ISP_DETECT_FRAME_INR_00,
|
||||
ISP_DETECT_FRAME_INR_01,
|
||||
ISP_DETECT_FRAME_INR_02,
|
||||
ISP_DETECT_FRAME_INR_03,
|
||||
ISP_DETECT_FRAME_INR_04,
|
||||
ISP_DETECT_FRAME_INR_05,
|
||||
ISP_DETECT_FRAME_INR_06,
|
||||
ISP_DETECT_FRAME_INR_07,
|
||||
ISP_DETECT_FRAME_INR_08,
|
||||
ISP_DETECT_FRAME_INR_09,
|
||||
ISP_DETECT_FRAME_INR_10,
|
||||
ISP_DETECT_FRAME_INR_11,
|
||||
ISP_DETECT_FRAME_INR_12,
|
||||
ISP_DETECT_FRAME_INR_13,
|
||||
ISP_DETECT_FRAME_INR_14,
|
||||
ISP_DETECT_FRAME_INR_15,
|
||||
ISP_DETECT_FRAME_INR_16,
|
||||
ISP_DETECT_FRAME_INR_17,
|
||||
ISP_DETECT_FRAME_INR_18,
|
||||
ISP_DETECT_FRAME_INR_19,
|
||||
ISP_DETECT_FRAME_INR_20,
|
||||
ISP_DETECT_FRAME_INR_21,
|
||||
ISP_DETECT_FRAME_INR_22,
|
||||
ISP_DETECT_FRAME_INR_23,
|
||||
ISP_DETECT_FRAME_INR_24,
|
||||
ISP_DETECT_FRAME_INR_25,
|
||||
ISP_DETECT_FRAME_INR_26,
|
||||
ISP_DETECT_FRAME_INR_27,
|
||||
ISP_DETECT_FRAME_INR_28,
|
||||
ISP_DETECT_FRAME_INR_29,
|
||||
ISP_DETECT_FRAME_INR_30,
|
||||
ISP_DETECT_FRAME_INR_31,
|
||||
};
|
||||
|
||||
enum isp_irq_flag {
|
||||
ISP_IRQ_FLAG_INTF_SLOW = 0,
|
||||
ISP_IRQ_FLAG_FRM_FAST,
|
||||
ISP_IRQ_FLAG_DAT_OF,
|
||||
ISP_IRQ_FLAG_FRM_END,
|
||||
ISP_IRQ_FLAG_AWB_DONE,
|
||||
ISP_IRQ_FLAG_AE_DONE,
|
||||
ISP_IRQ_FLAG_MD_DONE,
|
||||
ISP_IRQ_FLAG_DMA_DONE,
|
||||
ISP_IRQ_FLAG_AF_DONE,
|
||||
ISP_IRQ_FLAG_DPC_ERR,
|
||||
ISP_IRQ_FLAG_IIC_CFG,
|
||||
ISP_IRQ_FLAG_TOTAL_NUM,
|
||||
};
|
||||
|
||||
enum isp_clk_divide{
|
||||
ISP_CLK_DIVIDE_1 = 0,
|
||||
ISP_CLK_DIVIDE_2,
|
||||
ISP_CLK_DIVIDE_3,
|
||||
ISP_CLK_DIVIDE_4,
|
||||
ISP_CLK_DIVIDE_5,
|
||||
ISP_CLK_DIVIDE_6,
|
||||
ISP_CLK_DIVIDE_7,
|
||||
};
|
||||
|
||||
enum isp_input_fifo{
|
||||
ISP_INPUT_FIFO_FULL,
|
||||
ISP_INPUT_FIFO_HALF,
|
||||
ISP_INPUT_FIFO_QUARTER,
|
||||
ISP_INPUT_FIFO_EIGHTHS,
|
||||
};
|
||||
|
||||
enum isp_filter_mode {
|
||||
ISP_FILTER_MODE_NORMAL,
|
||||
ISP_FILTER_MODE_BLACK_WHITE,
|
||||
ISP_FILTER_MODE_BINARYZATION,
|
||||
ISP_FILTER_MODE_RETRO,
|
||||
};
|
||||
|
||||
enum isp_ioctl_cmd {
|
||||
ISP_IOCTL_CMD_GET_STA,
|
||||
ISP_IOCTL_CMD_GET_VERSION,
|
||||
ISP_IOCTL_CMD_DUMP_PARAM,
|
||||
ISP_IOCTL_CMD_PROGRAM_PARAM,
|
||||
ISP_IOCTL_CMD_INIT_SENSOR_PARAM,
|
||||
ISP_IOCTL_CMD_SENSOR_INIT,
|
||||
ISP_IOCTL_CMD_CLK_DIVIDE,
|
||||
ISP_IOCTL_CMD_FIFO_TYPE,
|
||||
ISP_IOCTL_CMD_CROP_INPUT,
|
||||
ISP_IOCTL_CMD_CROP_OUTPUT,
|
||||
ISP_IOCTL_CMD_Y_GAMMA_ADDR,
|
||||
ISP_IOCTL_CMD_RGB_GAMMA_ADDR,
|
||||
ISP_IOCTL_CMD_SENSOR_IIC_DEVID,
|
||||
ISP_IOCTL_CMD_SENSOR_IIC_OPTCMD,
|
||||
ISP_IOCTL_CMD_SLAVE_INDEX,
|
||||
ISP_IOCTL_CMD_BLACK_WHITE_MODE,
|
||||
ISP_IOCTL_CMD_IMG_MIRROR,
|
||||
ISP_IOCTL_CMD_IMG_REVERSE,
|
||||
ISP_IOCTL_CMD_GET_IMG,
|
||||
ISP_IOCTL_CMD_FILTER_MODE,
|
||||
ISP_IOCTL_CMD_AWB_MANNUL_MODE_MAP,
|
||||
ISP_IOCTL_CMD_AWB_MANNUL_MODE_TYPE,
|
||||
ISP_IOCTL_CMD_AWB_CONTROL_STEP,
|
||||
ISP_IOCTL_CMD_AWB_CONTROL_THR,
|
||||
ISP_IOCTL_CMD_AWB_AUTO_CTRL,
|
||||
ISP_IOCTL_CMD_AWB_FINE_CONSTRAINT_CTRL,
|
||||
ISP_IOCTL_CMD_AWB_COARSE_CONSTRAINT_CTRL,
|
||||
ISP_IOCTL_CMD_AWB_MEAS_MODE,
|
||||
ISP_IOCTL_CMD_AWB_WP_EXPECT,
|
||||
ISP_IOCTL_CMD_AWB_WP_RANGE_CONSTRAINT,
|
||||
ISP_IOCTL_CMD_AWB_WP_RANGE_CONSTRAINTF,
|
||||
ISP_IOCTL_CMD_AWB_WP_RANGE_CONSTRAINT_RESTRAIN,
|
||||
ISP_IOCTL_CMD_AWB_RGB_CONSTRAINT,
|
||||
ISP_IOCTL_CMD_AWB_WP_NUM_RESTRAIN,
|
||||
ISP_IOCTL_CMD_AWB_GAIN_TYPE,
|
||||
ISP_IOCTL_CMD_AWB_GAIN_CONSTRAINT,
|
||||
ISP_IOCTL_CMD_AWB_GAIN_COARSE_CONSTRAINT,
|
||||
ISP_IOCTL_CMD_AWB_GAIN_FINE_CONSTRAINT,
|
||||
ISP_IOCTL_CMD_AWB_CROP_RANGE,
|
||||
ISP_IOCTL_CMD_AE_BV,
|
||||
ISP_IOCTL_CMD_AE_MANUAL_PARAM,
|
||||
ISP_IOCTL_CMD_AE_ROW_TIME_US,
|
||||
ISP_IOCTL_CMD_AE_ANALOG_GAIN,
|
||||
ISP_IOCTL_CMD_AE_EXPOSURE_LINE,
|
||||
ISP_IOCTL_CMD_AE_CONFIG_INTERVAL,
|
||||
ISP_IOCTL_CMD_AE_DAY_NIGHT_BV,
|
||||
ISP_IOCTL_CMD_AE_SCENE_LUT,
|
||||
ISP_IOCTL_CMD_AE_LOWLIGHT_PARAM,
|
||||
ISP_IOCTL_CMD_AE_FRAME_MAX,
|
||||
ISP_IOCTL_CMD_AE_LOCK_PARAM,
|
||||
ISP_IOCTL_CMD_AE_REDUCE_FPS,
|
||||
ISP_IOCTL_CMD_LOWLIGHT_LSB_GAIN_EN,
|
||||
ISP_IOCTL_CMD_LOWLIGHT_LSB_GAIN_4HI_FPS,
|
||||
ISP_IOCTL_CMD_LOWLIGHT_LSB_GAIN_4LO_FPS,
|
||||
ISP_IOCTL_CMD_HIST_HS_BIN_THR,
|
||||
ISP_IOCTL_CMD_AE_LUMA_TARGET,
|
||||
ISP_IOCTL_CMD_AE_LUMA_WEIGHT,
|
||||
ISP_IOCTL_CMD_AE_ABL_LUMA_MAX,
|
||||
ISP_IOCTL_CMD_AE_POS_THR,
|
||||
ISP_IOCTL_CMD_AE_HIST_THR,
|
||||
ISP_IOCTL_CMD_AE_AOE_EXPO_GAIN,
|
||||
ISP_IOCTL_CMD_AE_ABL_LOCK_THR,
|
||||
ISP_IOCTL_CMD_AE_BRIGHT_DARK_PIXEL_RATIO,
|
||||
ISP_IOCTL_CMD_AE_ABL_DARK_BRIGHT_POS_THR,
|
||||
ISP_IOCTL_CMD_AE_AOE_DARK_BRIGHT_POS_THR,
|
||||
ISP_IOCTL_CMD_AE_ABL_GAIN_MODE,
|
||||
ISP_IOCTL_CMD_AE_ABL_EXPO_LINE_RATIO,
|
||||
ISP_IOCTL_CMD_AE_ABL_EXPO_GAIN_THR,
|
||||
ISP_IOCTL_CMD_AE_ABL_BV_THR,
|
||||
ISP_IOCTL_CMD_AE_AOE_BV_THR,
|
||||
ISP_IOCTL_CMD_AE_HIST_PIXEL_THR,
|
||||
ISP_IOCTL_CMD_AE_STG_PARAM,
|
||||
ISP_IOCTL_CMD_AE_EV_OFFSET_LUT,
|
||||
ISP_IOCTL_CMD_AE_EV_OFFSET_TYPE,
|
||||
ISP_IOCTL_CMD_AE_CROP_RANGE,
|
||||
ISP_IOCTL_CMD_HIST_CROP_RANGE,
|
||||
ISP_IOCTL_CMD_CCM_ARRAY,
|
||||
ISP_IOCTL_CMD_BLC_PARAM,
|
||||
ISP_IOCTL_CMD_MD_WINDOW_PARAM,
|
||||
ISP_IOCTL_CMD_MD_DETECT_PARAM,
|
||||
ISP_IOCTL_CMD_CSC_PARAM,
|
||||
ISP_IOCTL_CMD_DPC_PARAM,
|
||||
ISP_IOCTL_CMD_CE_YUV_RANGE,
|
||||
ISP_IOCTL_CMD_CE_LUMA,
|
||||
ISP_IOCTL_CMD_CE_SATURATION,
|
||||
ISP_IOCTL_CMD_CE_CONTRAST,
|
||||
ISP_IOCTL_CMD_CE_HUE,
|
||||
ISP_IOCTL_CMD_CE_OFFSET_PARAM,
|
||||
ISP_IOCTL_CMD_CE_ADJ_BY_BV_PARAM,
|
||||
ISP_IOCTL_CMD_SHARP_PARAM,
|
||||
ISP_IOCTL_CMD_RAWNR_MAP,
|
||||
ISP_IOCTL_CMD_YUVNR_MAP,
|
||||
ISP_IOCTL_CMD_CSUPP_MAP,
|
||||
ISP_IOCTL_CMD_Y_GAMMA_TUNNING,
|
||||
ISP_IOCTL_CMD_RGB_GAMMA_TUNNING,
|
||||
ISP_IOCTL_CMD_LSC_TUNNING,
|
||||
ISP_IOCTL_CMD_GET_Y_GAMMA,
|
||||
ISP_IOCTL_CMD_GET_RGB_GAMMA,
|
||||
ISP_IOCTL_CMD_GET_LSC,
|
||||
ISP_IOCTL_CMD_GIC_PARAM,
|
||||
ISP_IOCTL_CMD_LUMA_CA_PARAM,
|
||||
ISP_IOCTL_CMD_3DNR_ENABLE,
|
||||
ISP_IOCTL_CMD_LHS_MAP,
|
||||
ISP_IOCTL_CMD_GET_SENSOR_RAW,
|
||||
ISP_IOCTL_CMD_DUMP_SRAM_PARAM,
|
||||
ISP_IOCTL_CMD_DUMP_REG_PARAM,
|
||||
ISP_IOCTL_CMD_CONFIG_SRAM_PARAM,
|
||||
ISP_IOCTL_CMD_FUNC_ENABLE,
|
||||
ISP_IOCTL_CMD_WDR_EN,
|
||||
ISP_IOCTL_CMD_WDR_NOISE_FLOOR,
|
||||
ISP_IOCTL_CMD_WDR_TUNNING,
|
||||
ISP_IOCTL_CMD_YUV_RANGE,
|
||||
ISP_IOCTL_CMD_CE_ADJ_BY_BV,
|
||||
ISP_IOCTL_CMD_GAMMA_BY_BV_PARAM,
|
||||
ISP_IOCTL_CMD_GAMMA_BY_BV_ENABLE,
|
||||
ISP_IOCTL_CMD_FPS_OPT,
|
||||
ISP_IOCTL_CMD_GET_AWB_YCBCR,
|
||||
ISP_IOCTL_CMD_GET_AWB_GAIN,
|
||||
ISP_IOCTL_CMD_GET_AE_EXPOSURE_LINE,
|
||||
ISP_IOCTL_CMD_GET_AE_EXPOSURE_GAIN,
|
||||
ISP_IOCTL_CMD_GET_AE_TARGET,
|
||||
ISP_IOCTL_CMD_GET_AE_LUMA_AVG,
|
||||
ISP_IOCTL_CMD_GET_SENSOR_YGAMMA,
|
||||
ISP_IOCTL_CMD_DYN_YGAMMA_OPT,
|
||||
ISP_IOCTL_CMD_SENSOR_DEINIT,
|
||||
ISP_IOCTL_CMD_GET_AWB_RGB,
|
||||
ISP_IOCTL_CMD_GET_ISP_IRCUT_STAT,
|
||||
};
|
||||
|
||||
enum isp_module_clk {
|
||||
ISP_MODULE_CLK_320M = 1,
|
||||
ISP_MODULE_CLK_240M,
|
||||
ISP_MODULE_CLK_160M,
|
||||
ISP_MODULE_CLK_120M,
|
||||
ISP_MODULE_CLK_080M,
|
||||
ISP_MODULE_CLK_060M,
|
||||
};
|
||||
|
||||
enum isp_ioctl_ret_type {
|
||||
RET_TYPE_SUCC,
|
||||
RET_TYPE_INVALID_VALUE,//invalid_value,
|
||||
RET_TYPE_
|
||||
};
|
||||
|
||||
enum isp_ev_offset {
|
||||
ISP_EV_OFFSET_SUB_6,
|
||||
ISP_EV_OFFSET_SUB_5,
|
||||
ISP_EV_OFFSET_SUB_4,
|
||||
ISP_EV_OFFSET_SUB_3,
|
||||
ISP_EV_OFFSET_SUB_2,
|
||||
ISP_EV_OFFSET_SUB_1,
|
||||
ISP_EV_OFFSET_ADD_0,
|
||||
ISP_EV_OFFSET_ADD_1,
|
||||
ISP_EV_OFFSET_ADD_2,
|
||||
ISP_EV_OFFSET_ADD_3,
|
||||
ISP_EV_OFFSET_ADD_4,
|
||||
ISP_EV_OFFSET_ADD_5,
|
||||
ISP_EV_OFFSET_ADD_6,
|
||||
};
|
||||
|
||||
enum isp_awb_mode {
|
||||
ISP_AWB_MODE_AUTO,
|
||||
ISP_AWB_MODE_OVERCAST_SKY,
|
||||
ISP_AWB_MODE_CLOUDY_SKY,
|
||||
ISP_AWB_MODE_SUNNY_SKY,
|
||||
};
|
||||
|
||||
struct isp_awb_mode_param {
|
||||
uint16 awb_mode;
|
||||
uint16 awb_gain_r, awb_gain_gr, awb_gain_gb, awb_gain_b;
|
||||
};
|
||||
|
||||
struct isp_exposure_opt {
|
||||
scatter_data data;
|
||||
uint32 analog_gain : 16,
|
||||
cmd_len : 8,
|
||||
devid_id : 8;
|
||||
uint32 slave_id : 16,
|
||||
reverse_en : 4,
|
||||
mirror_en : 4,
|
||||
img_operation : 8;
|
||||
uint32 exposure_line;
|
||||
uint8 chg_fps_flag;
|
||||
uint16 frame_length;
|
||||
int32 config_flag;
|
||||
};
|
||||
|
||||
struct isp_sensor_opt
|
||||
{
|
||||
scatter_data data;
|
||||
uint32 devid_id : 8,
|
||||
slave_id : 8,
|
||||
reverse_en : 4,
|
||||
mirror_en : 4,
|
||||
cmd_len : 8;
|
||||
uint32 curr_length ;
|
||||
uint32 total_length;
|
||||
};
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*isp_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
typedef void (*isp_ae_func)(struct isp_exposure_opt *param);
|
||||
typedef void (*sensor_img_opt)(struct isp_sensor_opt *p_opt);
|
||||
typedef void (*sensor_fps_opt)(struct isp_sensor_opt *p_opt);
|
||||
|
||||
/* ISP api for user */
|
||||
struct isp_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct isp_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct isp_device *isp, enum isp_module_clk clk_type, enum isp_input_fifo fifo_type);
|
||||
int32(*close)(struct isp_device *isp);
|
||||
int32(*ioctl)(struct isp_device *isp, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct isp_device *isp, uint32 irq_flag, isp_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct isp_device *isp, uint32 irq_flag);
|
||||
int32(*calculate)(struct isp_device *isp, struct isp_exposure_opt **cfg);
|
||||
};
|
||||
|
||||
|
||||
int32 isp_open(struct isp_device *isp, enum isp_module_clk clk_type, enum isp_input_fifo fifo_type);
|
||||
int32 isp_close(struct isp_device *isp);
|
||||
int32 isp_ioctl(struct isp_device *isp, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 isp_calculate(struct isp_device *isp, struct isp_exposure_opt **p_cfg);
|
||||
int32 isp_request_irq(struct isp_device *isp, uint32 irq_flag, isp_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32 isp_release_irq(struct isp_device *isp, uint32 irq_flag);
|
||||
int32 isp_get_status(struct isp_device *isp);
|
||||
int32 isp_y_gamma_init(struct isp_device *isp, uint32 y_gamma_addr);
|
||||
int32 isp_rgb_gamma_init(struct isp_device *isp, uint32 rgb_gamma_addr);
|
||||
int32 isp_clk_divide_init(struct isp_device *isp, uint32 clk_type);
|
||||
int32 isp_fifo_init(struct isp_device *isp, uint32 fifo_type);
|
||||
int32 isp_sensor_init(struct isp_device *isp, enum sensor_type type, enum isp_input_dat_src sensor_src, uint32 sensor_config);
|
||||
int32 isp_crop_input_size(struct isp_device *isp, uint32 start_v, uint32 start_h, uint32 end_v, uint32 end_h, enum sensor_type type);
|
||||
int32 isp_crop_output_size(struct isp_device *isp, uint32 start_v, uint32 start_h, uint32 end_v, uint32 end_h, enum sensor_type type);
|
||||
int32 isp_sensor_iic_devid_init(struct isp_device *isp, uint32 devid_id, enum sensor_type type);
|
||||
int32 isp_sensor_iic_cmd_init(struct isp_device *isp, uint32 cmd_id, enum sensor_type type);
|
||||
int32 isp_sensor_slave_index(struct isp_device *isp);
|
||||
int32 isp_black_white_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_mirror_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_reverse_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_luma_ca_init(struct isp_device *isp, uint32 *addr, uint32 strength_value, enum sensor_type type);
|
||||
|
||||
int32 isp_awb_mannul_mode_map(struct isp_device *isp, uint32 map_addr);
|
||||
int32 isp_awb_mannul_mode_type(struct isp_device *isp, enum isp_awb_mode mannul_type, enum sensor_type type);
|
||||
int32 isp_awb_gain_type(struct isp_device *isp, uint32 gain_type, enum sensor_type type);
|
||||
int32 isp_awb_control_step_config(struct isp_device *isp, uint16 coarse, uint16 fine, enum sensor_type type);
|
||||
int32 isp_awb_control_thr_config(struct isp_device *isp, uint16 coarse_thr, uint16 hi_thr, uint16 lo_thr, uint16 rgb_thr, uint16 yuv_thr, enum sensor_type type);
|
||||
int32 isp_awb_wp_expect_val(struct isp_device *isp, uint32 cb_target, uint32 cr_target, enum sensor_type type);
|
||||
int32 isp_awb_rgb_constraint(struct isp_device *isp, uint32 r_max, uint32 g_max, uint32 b_max, enum sensor_type type);
|
||||
int32 isp_awb_cbcr_constraint(struct isp_device *isp, uint32 cb_min, uint32 cr_min, uint32 sum_val, enum sensor_type type);
|
||||
int32 isp_awb_cbcr_constraintf(struct isp_device *isp, uint32 cb_min, uint32 cr_min, uint32 sum_val, enum sensor_type type);
|
||||
int32 isp_awb_cbcr_constraint_restrain(struct isp_device *isp, uint32 param, enum sensor_type type);
|
||||
int32 isp_awb_wp_constraint(struct isp_device *isp, uint32 wp_min, uint32 wp_max, enum sensor_type type);
|
||||
int32 isp_awb_measure_mode_config(struct isp_device *isp, uint32 mode, enum sensor_type type);
|
||||
int32 isp_awb_auto_config(struct isp_device *isp, uint32 enable, uint32 *gain_buf, enum sensor_type type);
|
||||
int32 isp_awb_fine_constraint_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_awb_coarse_constraint_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_awb_gain_constraint(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_awb_gain_coarse_constraint(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_awb_gain_fine_constraint(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_awb_crop_range(struct isp_device *isp, uint32 start_v, uint32 start_h, uint32 end_v, uint32 end_h, enum sensor_type type);
|
||||
int32 isp_get_awb_ycbcr(struct isp_device *isp, uint32 *arr_ycbcr, enum sensor_type type);
|
||||
int32 isp_get_awb_rb_gain(struct isp_device *isp, uint32 *arr_rbgain, enum sensor_type type);
|
||||
int32 isp_get_awb_rgb(struct isp_device *isp, uint32 *arr_rgb, enum sensor_type type);
|
||||
|
||||
int32 isp_get_isp_ircut_statistics(struct isp_device *isp, ISP_IRCUT_STAT *isp_stat, enum sensor_type type);
|
||||
|
||||
int32 isp_get_current_bv(struct isp_device *isp, uint32 *bv, enum sensor_type type);
|
||||
int32 isp_get_ae_exp_line(struct isp_device *isp, uint32 *line, enum sensor_type type);
|
||||
int32 isp_get_ae_exp_gain(struct isp_device *isp, uint32 *gain, enum sensor_type type);
|
||||
int32 isp_get_ae_target(struct isp_device *isp, uint32 *target, enum sensor_type type);
|
||||
int32 isp_get_ae_luma_avg(struct isp_device *isp, uint32 *luma_avg, enum sensor_type type);
|
||||
|
||||
int32 isp_ae_manul_config(struct isp_device *isp, uint32 target, uint32 analog_gain, uint32 expo_line, enum sensor_type type);
|
||||
int32 isp_ae_row_time(struct isp_device *isp, uint32 row_us, enum sensor_type type);
|
||||
int32 isp_ae_analog_gain(struct isp_device *isp, uint32 max_gain, uint32 min_gain, enum sensor_type type);
|
||||
int32 isp_ae_exposure_line(struct isp_device *isp, uint32 max_line, uint32 min_line, uint32 def_line, enum sensor_type type);
|
||||
int32 isp_ae_interval_config(struct isp_device *isp, uint32 cnt, enum sensor_type type);
|
||||
int32 isp_ae_day_night_bv(struct isp_device *isp, uint32 day_bv, uint32 night_bv, enum sensor_type type);
|
||||
int32 isp_ae_scene_lut(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_ae_lowlight_param(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_ae_frame_max(struct isp_device *isp, uint32 frame_max, uint32 vb, enum sensor_type type);
|
||||
int32 isp_ae_lock_param(struct isp_device *isp, uint32 cnt, uint32 diff, uint32 alpha, enum sensor_type type);
|
||||
int32 isp_ae_reduce_fps(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_ae_lowlight_gain_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_ae_lowlight_gain_high_gain(struct isp_device *isp, uint32 gain, enum sensor_type type);
|
||||
int32 isp_ae_lowlight_gain_low_gain(struct isp_device *isp, uint32 gain, enum sensor_type type);
|
||||
int32 isp_ae_hist_hs_bin_thr(struct isp_device *isp, uint32 hs_bin_thr, enum sensor_type type);
|
||||
|
||||
int32 isp_ae_luma_target_config(struct isp_device *isp, uint32 luma_target, enum sensor_type type);
|
||||
int32 isp_ae_luma_weight_config(struct isp_device *isp, uint32 luma_weight_sum, uint32 *luma_weight, enum sensor_type type);
|
||||
int32 isp_ae_abl_luma_max(struct isp_device *isp, uint32 max, enum sensor_type type);
|
||||
int32 isp_ae_pos_thr(struct isp_device *isp, uint32 dark_thr, enum sensor_type type);
|
||||
int32 isp_ae_hist_thr(struct isp_device *isp, uint32 val1, uint32 val2, enum sensor_type type);
|
||||
int32 isp_ae_aoe_gain(struct isp_device *isp, uint32 val1, uint32 val2, enum sensor_type type);
|
||||
int32 isp_ae_abl_lock(struct isp_device *isp, uint32 diff_ratio, uint32 dark_pos_thr, uint32 bright_pos_thr, enum sensor_type type);
|
||||
int32 isp_ae_brihgt_dark_pixel_ratio(struct isp_device *isp, uint32 bright_low, uint32 bright_high, uint32 dark_low, uint32 dark_high, enum sensor_type type);
|
||||
int32 isp_ae_abl_dark_bright_pos_ratio(struct isp_device *isp, uint32 dark_low, uint32 dark_high, uint32 bright_thr, enum sensor_type type);
|
||||
int32 isp_ae_aoe_dark_bright_pos_ratio(struct isp_device *isp, uint32 dark_thr, uint32 bright_thr, enum sensor_type type);
|
||||
int32 isp_ae_abl_gain_type(struct isp_device *isp, uint32 abl_gain_type, enum sensor_type type);
|
||||
int32 isp_ae_abl_expo_gain_set(struct isp_device *isp, uint32 low, uint32 high, enum sensor_type type);
|
||||
int32 isp_ae_abl_expo_line_ratio(struct isp_device *isp, uint32 low, uint32 high, enum sensor_type type);
|
||||
int32 isp_ae_abl_bv_thr(struct isp_device *isp, uint32 low, uint32 high, enum sensor_type type);
|
||||
int32 isp_ae_aoe_bv_thr(struct isp_device *isp, uint32 low, uint32 high, enum sensor_type type);
|
||||
int32 isp_ae_hist_pixel_thr(struct isp_device *isp, uint32 upper, uint32 upper_hs, uint32 lower, enum sensor_type type);
|
||||
int32 isp_ae_stg_param(struct isp_device *isp, uint32 stg_mode, uint32 ratio_slope, uint32 max_offset, enum sensor_type type);
|
||||
int32 isp_ae_ev_offset_lut(struct isp_device *isp, uint32 lut_addr);
|
||||
int32 isp_ae_ev_offset_type(struct isp_device *isp, enum isp_ev_offset offset_type, enum sensor_type type);
|
||||
int32 isp_ae_crop_range(struct isp_device *isp, uint32 data, enum sensor_type type);
|
||||
int32 isp_hist_crop_range(struct isp_device *isp, uint32 data, enum sensor_type type);
|
||||
|
||||
int32 isp_ccm_config(struct isp_device *isp, uint32 *ccm_array, enum sensor_type type);
|
||||
int32 isp_blc_config(struct isp_device *isp, uint32 *blc_array, enum sensor_type type);
|
||||
int32 isp_md_window_config(struct isp_device *isp, uint32 win_start_h, uint32 win_start_v, uint32 win_end_h, uint32 win_end_v, enum sensor_type type);
|
||||
int32 isp_md_param_config(struct isp_device *isp, uint32 frame_val, uint32 block_val, uint32 frame_cnt, enum sensor_type type);
|
||||
int32 isp_csc_config(struct isp_device *isp, uint32 *config_addr, enum sensor_type type);
|
||||
int32 isp_dpc_config(struct isp_device *isp, uint32 *config_addr, enum sensor_type type);
|
||||
int32 isp_ce_yuv_range(struct isp_device *isp, uint32 range, enum sensor_type type);
|
||||
int32 isp_ce_luma_config(struct isp_device *isp, uint32 luma_val, enum sensor_type type);
|
||||
int32 isp_ce_saturation_config(struct isp_device *isp, uint32 luma_val, enum sensor_type type);
|
||||
int32 isp_ce_contrast_config(struct isp_device *isp, uint32 contrast, enum sensor_type type);
|
||||
int32 isp_ce_hue_config(struct isp_device *isp, uint32 hue, enum sensor_type type);
|
||||
int32 isp_ce_offset_config(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_ce_adj_by_bv_param(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_sharp_param(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_rawnr_map(struct isp_device *isp, uint32 map_num, uint32 map_start, uint32 map_data_addr, enum sensor_type type);
|
||||
int32 isp_yuvnr_map(struct isp_device *isp, uint32 map_num, uint32 map_start, uint32 map_data_addr, enum sensor_type type);
|
||||
int32 isp_csupp_map(struct isp_device *isp, uint32 map_num, uint32 map_start, uint32 map_data_addr, enum sensor_type type);
|
||||
int32 isp_y_gamma_tunning(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_rgb_gamma_tunning(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_lsc_tunning(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_3dnr_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_gic_init(struct isp_device *isp, uint32 param_addr, enum sensor_type type);
|
||||
int32 isp_lhs_map(struct isp_device *isp, uint32 map_num, uint32 map_start, uint32 map_data_addr, enum sensor_type type);
|
||||
int32 isp_sensor_param_config(struct isp_device *isp, uint32 addr);
|
||||
int32 isp_sensor_sram_param_config(struct isp_device *isp, uint32 channel, uint32 addr);
|
||||
int32 isp_sensor_func_enable(struct isp_device *isp, uint32 channel, uint32 data);
|
||||
int32 isp_wdr_en_config(struct isp_device *isp, uint32 wdr_en, enum sensor_type type);
|
||||
int32 isp_wdr_noise_floor_config(struct isp_device *isp, uint32 cfg_noise_floor, uint32 cfg_noise_floor_out, enum sensor_type type);
|
||||
int32 isp_wdr_tunning(struct isp_device *isp, uint32 addr, enum sensor_type type);
|
||||
int32 isp_yuv_range(struct isp_device *isp, enum isp_yuv_range range_type);
|
||||
int32 isp_ce_adj_by_bv_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_gamma_by_bv_enable(struct isp_device *isp, uint32 enable, enum sensor_type type);
|
||||
int32 isp_gamma_by_bv_param(struct isp_device *isp, uint32 data, enum sensor_type type);
|
||||
int32 isp_dyn_gamma_param(struct isp_device *isp, uint32 dyn_gamma_en, uint32 ygamma_opt, enum sensor_type type);
|
||||
int32 isp_sensor_fps_opt(struct isp_device *isp, float fps, enum sensor_type type);
|
||||
int32 isp_sensor_deinit(struct isp_device *isp, enum sensor_type type);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
458
sdk/include/hal/isp_param.h
Normal file
458
sdk/include/hal/isp_param.h
Normal file
@@ -0,0 +1,458 @@
|
||||
#ifndef _ISP_PARAM_H_
|
||||
#define _ISP_PARAM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "osal/string.h"
|
||||
#include "sys_config.h"
|
||||
|
||||
typedef void *(*ispcfg_malloc)(int size);
|
||||
typedef void (*ispcfg_free)(void *ptr);
|
||||
|
||||
|
||||
#define NUM_CURVES 5
|
||||
#define LUT_SIZE 64
|
||||
|
||||
#define ISPCFG_MAGIC 0xb103
|
||||
|
||||
#define BV2RAWNR_ARRAY_NUM (11)
|
||||
#define BV2YUVNR_ARRAY_NUM ( 6)
|
||||
#define BV2CSUPP_ARRAY_NUM ( 3)
|
||||
#define LOCAL_HUE_SAT_COLOR ( 9)
|
||||
#define BV2COLENH_ARRAY_NUM ( 8)
|
||||
#define BV2GAMMA_ARRAY_NUM ( 8)
|
||||
|
||||
enum awb_meas_mode{
|
||||
AWB_MEAS_MODE_YUV = 0,
|
||||
AWB_MEAS_MODE_RGB = 1,
|
||||
AWB_MEAS_MODE_YUV_NEW = 2,
|
||||
};
|
||||
|
||||
enum awb_config_mode {
|
||||
AWB_MODE_MANUAL = 0,
|
||||
AWB_MODE_AUTO = 1,
|
||||
};
|
||||
|
||||
enum awb_gain_type {
|
||||
AWB_GAIN_TYPE_AWB = 0,
|
||||
AWB_GAIN_TYPE_RGB = 1,
|
||||
AWB_GAIN_TYPE_BOTH = 2,
|
||||
};
|
||||
|
||||
enum awb_formula_type{
|
||||
AWB_FORMULA_SRC,
|
||||
AWB_FORMULA_DIFF,
|
||||
};
|
||||
|
||||
enum isp_info_src_type {
|
||||
ISP_INFO_SRC_TYPE_CODE_PARAM = 0,
|
||||
ISP_INFO_SRC_TYPE_CODE_DOC,
|
||||
ISP_INFO_SRC_TYPE_TUNNING,
|
||||
};
|
||||
|
||||
struct isp_func_cfg {
|
||||
uint32 test_pattern_en : 1, // 0
|
||||
dma_flush_en : 1,
|
||||
ifa_table_en : 1,
|
||||
blc_en : 1,
|
||||
lsc_en : 1,
|
||||
af_en : 1, // 5
|
||||
dehaze_en : 1,
|
||||
dpc_en : 1,
|
||||
bnr_en : 1,
|
||||
gic_en : 1,
|
||||
awb_en : 1, // 10
|
||||
ccm_en : 1,
|
||||
y_gamma_en : 1,
|
||||
rgb_gamma_en : 1,
|
||||
sharpen_en : 1,
|
||||
ynr_en : 1, // 15
|
||||
cnr_en : 1,
|
||||
ae_en : 1,
|
||||
hist_en : 1,
|
||||
ce_en : 1,
|
||||
md_en : 1, // 20
|
||||
csupp_en : 1,
|
||||
luma_ca_en : 1,
|
||||
adj_hue_en : 1,
|
||||
lsc_tab_en : 1, // 25
|
||||
input_format : 1,
|
||||
reserved : 2;
|
||||
};
|
||||
|
||||
#define AWB_CLIP_MAX_SECTION 8
|
||||
typedef struct hgisp_awb_constraint {
|
||||
// awbclip
|
||||
uint32 section_num;
|
||||
uint32 color_temp[AWB_CLIP_MAX_SECTION];
|
||||
float sec_line_slope[AWB_CLIP_MAX_SECTION];
|
||||
float sec_line_offset[AWB_CLIP_MAX_SECTION];
|
||||
float sec_line_sqrtk2add1[AWB_CLIP_MAX_SECTION];
|
||||
float center_line_slope[AWB_CLIP_MAX_SECTION - 1];
|
||||
float center_line_offset[AWB_CLIP_MAX_SECTION - 1];
|
||||
float lower_line_slope[AWB_CLIP_MAX_SECTION - 1];
|
||||
float lower_line_offset[AWB_CLIP_MAX_SECTION - 1];
|
||||
float upper_line_slope[AWB_CLIP_MAX_SECTION - 1];
|
||||
float upper_line_offset[AWB_CLIP_MAX_SECTION - 1];
|
||||
float corner_limit[AWB_CLIP_MAX_SECTION];
|
||||
}AWB_CONSTRAINT;
|
||||
|
||||
typedef struct hgisp_awb_coarse_constraint {
|
||||
float coarse_min_bg, coarse_lb_bg, coarse_rt_bg, coarse_max_bg;
|
||||
float coarse_min_rg, coarse_lb_rg, coarse_rt_rg, coarse_max_rg;
|
||||
}AWB_COARSE_CONSTRAINT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
// channel r gr gb b
|
||||
uint16 default_gain[4];
|
||||
uint16 awb_min_gain[4];
|
||||
uint16 awb_max_gain[4];
|
||||
// awb coarse polygon constraint
|
||||
AWB_COARSE_CONSTRAINT coarse_constraint;
|
||||
AWB_CONSTRAINT constraint;
|
||||
}_Sensor_AWB;
|
||||
|
||||
typedef struct hgisp_cfg_awb {
|
||||
uint32 cr_target : 16, cb_target : 16;
|
||||
uint32 front_cr_val : 8, back_cr_val : 8, cons_cr_max : 8, cons_cr_min : 8;
|
||||
uint32 front_cb_val : 8, back_cb_val : 8, cons_cb_max : 8, cons_cb_min : 8;
|
||||
uint32 front_uv_sum : 8, back_uv_sum : 8, cons_uv_max : 8, cons_uv_min : 8;
|
||||
uint32 back_cb_max : 8, back_cr_max : 8, back_uv_max : 8, reserved1 : 8;
|
||||
uint32 back_cb_min : 8, back_cr_min : 8, back_uv_min : 8, reserved2 : 8;
|
||||
int32 lock_hi_thr : 8, lock_lo_thr : 8, reversed0 : 16;
|
||||
uint32 coarse_scale : 8, coarse_thr : 8, fine_step : 8, stable_thr : 8;
|
||||
uint32 cbcr_thr : 8, awb_cent_cons_en : 8, awb_back_cons_en : 8, reserved3 : 8;
|
||||
uint32 awb_auto_en : 4, awb_fine_cons_en : 4, awb_meas_mode : 3, awb_gain_type : 3, awb_formula : 2, awb_wp_max : 8, awb_wp_min : 8;
|
||||
uint32 awb_r_max : 8, awb_g_max : 8, awb_b_max : 8, awb_precision : 4, awb_coarse_cons_en : 4;
|
||||
uint16 manual_gain[4];
|
||||
float awb_back_wp_min_ratio;
|
||||
uint32 awb_crop_pixel_start_v : 16, awb_crop_pixel_start_h : 16;
|
||||
uint32 awb_crop_pixel_end_v : 16, awb_crop_pixel_end_h : 16;
|
||||
_Sensor_AWB sensor_awb;
|
||||
}TYPE_HGISP_CFG_AWB;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
float wdr_bv[8]; // bv分段点, 用于控制每段的wdr_max_ns_slope,
|
||||
float max_ns_slope[8]; // 每段bv, 允许的最大的noise floor映射的斜率, 设置范围[1.0~3.0]
|
||||
float max_shadow_slope[8]; // 每段bv, 允许的最大的shadow映射的斜率, 设置范围[1.0~1.5]
|
||||
}_Sensor_WDR;
|
||||
|
||||
typedef struct hgisp_cfg_wdr {
|
||||
uint32 auto_noise_floor_out : 8, // auto_noise_floor_out : 打开自动计算噪声抑制输出控制点功能 wdr_en:是否使能wdr
|
||||
wdr_en : 8, //WDR使能,isp tuning时需要设0
|
||||
dynamic_gamma_en : 8, //动态y_gamma使能,isp tuning时需要设0
|
||||
y_gamma_opt : 8; //0是自动y_gamma,1,2,3,4,5是选择曲线
|
||||
float temporal_smooth_alpha; // 帧间平滑控制, alpha越小，帧间亮度越稳定，但对场景变化响应越慢。典型值范围: 0.05 ~ 0.2
|
||||
uint16 noise_floor; // 噪声抑制输入控制点
|
||||
uint16 noise_floor_out; // 噪声抑制输出控制点
|
||||
uint16 shadow_boost_target; // 暗部提亮的目标值(10 bit空间)
|
||||
uint16 highlight_compress_target; // 高光压缩的目标值(10 bit空间)
|
||||
float min_ns_percentile; // 用于自动计算噪声抑制输出控制点, 获取指定最小百分位处的噪声的统计值
|
||||
float max_ns_percentile; // 用于自动计算噪声抑制输出控制点, 获取指定最大百分位处的噪声的统计值
|
||||
_Sensor_WDR sensor_wdr;
|
||||
} TYPE_HGISP_CFG_WDR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
float row_time_us;
|
||||
uint32 max_analog_gain : 16,
|
||||
min_analog_gain : 16;
|
||||
uint32 max_exposure_line : 16,
|
||||
min_exposure_line : 16;
|
||||
uint32 default_exposure_line : 16,
|
||||
expo_frame_interval : 8,
|
||||
min_frame_vb : 8;
|
||||
float to_day_bv;
|
||||
float to_night_bv;
|
||||
uint8 dark_scene_target_lut[2];
|
||||
uint8 hs_scene_limit_lut[2];
|
||||
float dark_scene_bv_lut[2];
|
||||
float hs_scene_bv_lut[2];
|
||||
float lowlight_lsb_bv_lut[8];
|
||||
uint8 lowlight_lsb_gain_lut[8];
|
||||
uint32 curr_fps : 16, max_frame_length : 16;
|
||||
}_Sensor_AE;
|
||||
|
||||
typedef struct hgisp_cfg_ae {
|
||||
uint32 luma_target : 16, luma_weight_sum : 16;
|
||||
uint8 luma_weight[25];
|
||||
uint8 exposure_alpha, reserved1, reserved2;
|
||||
uint32 ae_lock_cnt : 8,
|
||||
ae_lock_tolerance : 8,
|
||||
ae_manual_en : 8,
|
||||
reduce_fps_en : 8;
|
||||
uint32 lowlight_lsb_gain_en : 8,
|
||||
lowlight_lsb_gain_4hi_fps : 8,
|
||||
lowlight_lsb_gain_4lo_fps : 8,
|
||||
hist_hs_bin_thr : 8;
|
||||
float hist_upper_hs_pixel_ratio; // [0, 1] »ý·ÖÖ±·½Í¼ÁÁ²¿Ö¸¶¨Î»ÖõÄÏñËØÊýÁ¿, ÓÃÓÚµ÷ÕûAEÄ¿±êÖµ¡£
|
||||
float hist_upper_pixel_ratio; // not use
|
||||
float hist_lower_pixel_ratio; // not use
|
||||
|
||||
uint8 abl_luma_target_max;
|
||||
uint8 dark_pos_thr_max;
|
||||
uint8 abl_hist_thr[2];
|
||||
float abl_diff_ratio;
|
||||
uint32 abl_dark_pos_diff_thr : 8, // [0,61] ablÆعâËø¶¨ãÐÖµ2£ºµ±µ÷Õûµ½ºÏÊÊÆعâºó£¬Èç¹û°µÇøȨÖØÖµ±ä»¯Ð¡ÓÚ´ËãÐÖµ £¬abl Target½«Ëø¶¨£¬±£³Ö²»±ä¡£
|
||||
abl_bright_pos_diff_thr : 8, // [0,61] ablÆعâËø¶¨ãÐÖµ3£ºµ±µ÷Õûµ½ºÏÊÊÆعâºó£¬Èç¹ûÁÁÇøȨÖØÖµ±ä»¯Ð¡ÓÚ´ËãÐÖµ £¬abl Target½«Ëø¶¨£¬±£³Ö²»±ä¡£
|
||||
reserved3 : 16;
|
||||
float bright_pixel_high_ratio;
|
||||
float bright_pixel_sub_ratio; // [0, 1] Ö±·½Í¼ÁÁÏñËØÊý×ÔÊÊÓ¦Öµ£¨%£©¡£
|
||||
float dark_pixel_low_ratio;
|
||||
float dark_pixel_high_ratio;
|
||||
uint32 abl_dark_pos_low_wthr : 8, // [0,61] abl°µÇøλÖÃȨÖØ×îСãÐÖµ¡£
|
||||
abl_dark_pos_add_wthr : 8, // [0,61] abl°µÇøλÖÃȨÖØ×ÔÊÊÓ¦Öµ¡£
|
||||
reversed4 : 16;
|
||||
float bright_pos_adjust_ratio;
|
||||
uint32 aoe_bright_pos_wthr : 8, // [0,61] aoeÁÁÇøλÖÃȨÖØãÐÖµ¡£
|
||||
aoe_dark_pos_wthr : 8, // [0,61] aoe°µÇøλÖÃȨÖØãÐÖµ¡£
|
||||
abl_bv_gain_sel : 8, // ablÅжÏÑ¡Ôñ£º 0£ºÔöÒ棻 1£ºbv
|
||||
reserved5 : 8;
|
||||
float abl_expo_line_low_ratio;
|
||||
float abl_expo_line_high_ratio;
|
||||
uint32 abl_expo_gain_low_thr; // [0, ana_gain_max] ablÔöÒæÅжϡ£
|
||||
uint32 abl_expo_gain_high_thr; // [0, ana_gain_max] ablÔöÒæÅжϡ£
|
||||
float abl_bv_thr[2];
|
||||
float aoe_bv_thr[2];
|
||||
uint16 aoe_expo_gain_thr[2]; // [0, ana_gain_max] aoeÔöÒæÅжϡ£
|
||||
uint32 stg_mode : 8, // ×Ô¶¯Æعâ²ßÂÔ 0£º¸ß¹âÓÅÏÈ£» 1£ºµÍ¹âÓÅÏÈ
|
||||
stg_max_offset : 8, // fix(0,16,8), ÖµÔ½´ó£¬roi¶ÔȨÖصÄÓ°ÏìÔ½´ó¡£
|
||||
stg_ratio_slope : 16; // fix(0,8,0)£¬ roi¶ÔȨÖØÓ°ÏìµÄ×î´ó³Ì¶È
|
||||
|
||||
uint32 ae_crop_start_v : 16, ae_crop_start_h : 16; // need to reduce 1.
|
||||
uint32 ae_crop_size_v : 16, ae_crop_size_h : 16; // NO need to reduce 1.
|
||||
uint32 hist_crop_start_v : 16, hist_crop_start_h : 16; // NO need to reduce 1.
|
||||
uint32 hist_crop_end_v : 16, hist_crop_end_h : 16; // NO need to reduce 1.
|
||||
_Sensor_AE sensor_ae;
|
||||
|
||||
} TYPE_HGISP_CFG_AE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int16 c00, c01, c02, c10, c11, c12, c20, c21, c22, c30, c31, c32;
|
||||
}_Sensor_CCM;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16 gr, gb, r, b;
|
||||
}_Sensor_BLC;
|
||||
|
||||
typedef struct hgisp_md_param {
|
||||
uint32 win_start_h : 16,
|
||||
win_start_v : 16;
|
||||
uint32 win_end_h : 16,
|
||||
win_end_v : 16;
|
||||
uint32 frame_value : 16,
|
||||
block_value : 8,
|
||||
frame_interval : 8;
|
||||
}_Sensor_MD;
|
||||
|
||||
typedef struct {
|
||||
uint32 adj_by_bv : 8, reversed : 24;
|
||||
float bv[BV2GAMMA_ARRAY_NUM];
|
||||
uint8 y_alpha[BV2GAMMA_ARRAY_NUM];
|
||||
uint8 rgb_alpha[BV2GAMMA_ARRAY_NUM];
|
||||
}_Sensor_GAMMA_BV;
|
||||
|
||||
typedef struct hgisp_csc_param {
|
||||
uint32 rgb2yuv_gamut : 8, yuv2rgb_in_gamut : 8, yuv2rgb_out_gamut : 8, rgb2yuv_range : 8;
|
||||
uint32 yuv2rgb_in_range : 8, yuv2rgb_out_range : 8, y_gamma_alpha : 8, rgb_gamma_alpha : 8;
|
||||
_Sensor_GAMMA_BV *gamma_alpha_map;
|
||||
}_Sensor_CSC;
|
||||
|
||||
typedef struct hgisp_dpc_param {
|
||||
uint32 static_psram_addr;
|
||||
uint32 white_threshold : 8,
|
||||
black_threshold : 8,
|
||||
sensitivity_value : 8,
|
||||
white_threshold_min : 8;
|
||||
uint32 black_threshold_min : 8,
|
||||
dynamic_white_strength : 4,
|
||||
dynamic_black_strength : 4,
|
||||
reserved0 : 16;
|
||||
}_Sensor_DPC;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8 U_luma_thr_lo, U_luma_slop_lo, U_luma_shfb_lo, U_luma_gmin_lo;
|
||||
uint8 U_luma_thr_hi, U_luma_slop_hi, U_luma_shfb_hi, U_luma_gmin_hi;
|
||||
uint8 V_luma_thr_lo, V_luma_slop_lo, V_luma_shfb_lo, V_luma_gmin_lo;
|
||||
uint8 V_luma_thr_hi, V_luma_slop_hi, V_luma_shfb_hi, V_luma_gmin_hi;
|
||||
uint8 chroma_thr_lo, chroma_slop_lo, chroma_shfb_lo, chroma_gmin_lo;
|
||||
}_Sensor_CSUPP;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32 filt_alpha : 8,
|
||||
shrink_thr : 8,
|
||||
filt_clip_hi : 8,
|
||||
filt_clip_lo : 8;
|
||||
uint32 sp_thr2 : 8,
|
||||
sp_thr1 : 8,
|
||||
enha_clip_hi : 8,
|
||||
enha_clip_lo : 8;
|
||||
uint32 e1 : 8, e2 : 8, e3 : 8, reserved0 : 8;
|
||||
uint32 k0 : 8, k1 : 8, k2 : 8, k3 : 8;
|
||||
uint32 y1 : 8, y2 : 8, y3 : 8, reserved1 : 8;
|
||||
int32 filt_w11 : 16, filt_w12 : 16;
|
||||
int32 filt_w13 : 16, filt_w21 : 16;
|
||||
int32 filt_w22 : 16, filt_w23 : 16;
|
||||
int32 filt_w31 : 16, filt_w32 : 16;
|
||||
int32 filt_w33 : 16, reserved2 : 16;
|
||||
uint32 filt_type : 8, filt_sbit : 8, lpf_scale : 8, reserved3 : 8;
|
||||
uint8 strength_lut[2]; uint8 reserved4, reserved5;
|
||||
float strength_bv_lut[2];
|
||||
}_Sensor_SHARP;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8 y_thr_tal0,y_thr_tal1,y_thr_tal2,y_thr_tal3,y_thr_tal4,y_thr_tal5,y_thr_tal6,y_thr_tal7;
|
||||
uint8 y_alfa, c_alfa, y_win_size, reserved0;
|
||||
}_Sensor_YUVNR;
|
||||
|
||||
typedef struct {
|
||||
float bv;
|
||||
int16 hue, reserved0;
|
||||
uint8 luma, contrast, saturation, reserved1;
|
||||
}_Sensor_COLENH_BV;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8 yuv_range; // narrow : 0 full : 1
|
||||
uint8 luma; // range: 0 ~ 100
|
||||
uint8 contrast; // range: 0 ~ 100
|
||||
uint8 saturation; // range: 0 ~ 100
|
||||
int16 hue; // range: -180 ~ 180'
|
||||
int16 reserved0;
|
||||
int16 ce_in_ofs_y, ce_in_ofs_cb, ce_in_ofs_cr; // range: -128 ~ 128
|
||||
int16 ce_out_ofs_y, ce_out_ofs_cb, ce_out_ofs_cr; // range: -128 ~ 128
|
||||
uint32 adj_by_bv_en : 1, reserved1 : 31;
|
||||
_Sensor_COLENH_BV *bv2colenh_map;
|
||||
}_Sensor_COLENH;
|
||||
|
||||
typedef struct {
|
||||
_Sensor_COLENH sensor_ce;
|
||||
_Sensor_COLENH_BV bv2colenh_map[BV2COLENH_ARRAY_NUM];
|
||||
}_Sensor_BV2COLENH;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
float bv;
|
||||
uint8 bnr_range_weight_index;
|
||||
uint16 bnr_invksigma;
|
||||
uint8 bnr_intensity_threshold;
|
||||
uint8 yuvnr_idx;
|
||||
uint8 csupp_idx;
|
||||
uint8 h264_3dnr_lev;
|
||||
uint8 h264_3dnr_en;
|
||||
}_Sensor_BV2NR;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32 *p_lsc_tbl;
|
||||
}_Sensor_LSC;
|
||||
|
||||
|
||||
typedef struct{
|
||||
float bv;
|
||||
uint32 packed_lut[LUT_SIZE];
|
||||
} _Sensor_YGAMMA;
|
||||
|
||||
typedef struct {
|
||||
_Sensor_YGAMMA local_ygamma_map[NUM_CURVES];
|
||||
}_Sensor_YGAMMA_MAP;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16 region_lower, region_center, region_upper, hue_value, sat_value, reserved0;
|
||||
} _Sensor_LHS;
|
||||
|
||||
struct hgisp_head_info {
|
||||
uint16 magic_num , version , sensor_flag , sensor_num;
|
||||
uint16 basic_size, param_size, y_gamma_size, rgb_gamma_size, lsc_size;
|
||||
uint16 basic_crc , param_crc , y_gamma_crc , rgb_gamma_crc , lsc_crc ;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
uint32 bv3dnr : 8, change : 8, reserved0 : 16;
|
||||
_Sensor_BV2NR bv2rawnr_map[BV2RAWNR_ARRAY_NUM];
|
||||
_Sensor_YUVNR bv2yuvnr_map[BV2YUVNR_ARRAY_NUM];
|
||||
_Sensor_CSUPP bv2csupp_map[BV2CSUPP_ARRAY_NUM];
|
||||
}_Sensor_NR;
|
||||
|
||||
typedef struct {
|
||||
uint8 w_thres, w_slope, w_str, mu_thres, mu_slope, reserved0, reserved1, reserved2;
|
||||
}_Sensor_GIC;
|
||||
|
||||
typedef struct {
|
||||
_Sensor_LHS local_hue_sat_map[LOCAL_HUE_SAT_COLOR];
|
||||
}_Sensor_LHS_MAP;
|
||||
|
||||
struct hgisp_param_info {
|
||||
struct isp_func_cfg enable_param;
|
||||
TYPE_HGISP_CFG_AWB awb_param;
|
||||
struct hgisp_cfg_ae cfg_ae;
|
||||
_Sensor_CCM ccm_param;
|
||||
_Sensor_BLC blc_param;
|
||||
_Sensor_MD md_param;
|
||||
_Sensor_CSC csc_param;
|
||||
_Sensor_GAMMA_BV gamma_param;
|
||||
_Sensor_DPC dpc_param;
|
||||
_Sensor_BV2COLENH ce_param;
|
||||
_Sensor_SHARP sharp_param;
|
||||
_Sensor_NR nr_param;
|
||||
_Sensor_GIC gic_param;
|
||||
_Sensor_LHS_MAP lhs_param;
|
||||
TYPE_HGISP_CFG_WDR config_wdr;
|
||||
ispcfg_malloc malloc;
|
||||
ispcfg_free free;
|
||||
_Sensor_YGAMMA_MAP y_gamma;
|
||||
uint32 *rgb_gamma;
|
||||
uint32 *lsc_tbl;
|
||||
};
|
||||
|
||||
struct hgisp_basic_info {
|
||||
uint32 sensor_name[5];
|
||||
uint32 mirror : 8,
|
||||
reverse : 8,
|
||||
curr_mirror : 8,
|
||||
curr_reverse : 8;
|
||||
uint32 img_operation : 8,
|
||||
reserved : 24;
|
||||
uint32 sensor_size_v : 16,
|
||||
sensor_size_h : 16;
|
||||
uint32 input_size_v : 16,
|
||||
input_size_h : 16;
|
||||
uint32 input_size_startv : 16,
|
||||
input_size_starth : 16;
|
||||
uint32 crop_size_v : 16,
|
||||
crop_size_h : 16;
|
||||
uint32 crop_size_startv : 16,
|
||||
crop_size_starth : 16;
|
||||
uint32 bayer_type : 8,
|
||||
input_type : 8,
|
||||
format_type : 8,
|
||||
sensor_index : 8;
|
||||
uint32 init_addr;
|
||||
uint32 offset;
|
||||
};
|
||||
|
||||
struct hgisp_sensor_info {
|
||||
uint32 info_src;
|
||||
struct hgisp_head_info head_info;
|
||||
struct hgisp_basic_info sensor_basic;
|
||||
struct hgisp_param_info sensor_param;
|
||||
};
|
||||
|
||||
struct hgisp_sensor_init {
|
||||
struct hgisp_sensor_info sensor_info[ISP_SUPPORT_SENSOR_MAX_NUM];
|
||||
};
|
||||
void *isp_sensor_param_load(uint16 *buff);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
58
sdk/include/hal/isp_tunning.h
Normal file
58
sdk/include/hal/isp_tunning.h
Normal file
@@ -0,0 +1,58 @@
|
||||
#ifndef _ISP_PARAM_H_
|
||||
#define _ISP_PARAM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "osal/string.h"
|
||||
#include "osal/semaphore.h"
|
||||
#include "osal/mutex.h"
|
||||
#include "rtthread.h"
|
||||
|
||||
enum tunning_img_type {
|
||||
TUNNING_IMG_JPEG,
|
||||
TUNNING_IMG_H264,
|
||||
};
|
||||
|
||||
enum {
|
||||
TUNNING_ERR_CODE_RIGHT = 0,
|
||||
TUNNING_ERR_CODE_GET_PARAM_ERR,
|
||||
TUNNING_ERR_CODE_CFG_PARAM_ERR,
|
||||
TUNNING_ERR_CODE_MALLOC_ERR,
|
||||
};
|
||||
|
||||
|
||||
#define TUNNING_PACKAGE_INFO_SIZE (2 + 2 + 4 + 2 + 2 + 4) // tunning_head + tunning_code + data_size + data_crc + package_crc + line_break
|
||||
#define TUNNING_PACKET_SIZE (2*1024) // package_data + package_crc(uint16) + package_line_break(uint16)
|
||||
|
||||
#define TUNNING_IMG_MSI "tunning_video_msi"
|
||||
|
||||
struct isp_tunnning_dev {
|
||||
struct os_semaphore usb_write_sema;
|
||||
struct os_semaphore usb_cmd_sema;
|
||||
scatter_data write_data;
|
||||
struct isp_device *p_isp;
|
||||
struct dual_device *p_dual;
|
||||
struct msi *video_msi;
|
||||
struct msi *v_msi;
|
||||
rt_device_t device;
|
||||
rt_ssize_t (*write_handle)(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
|
||||
uint32 *p_data;
|
||||
uint16 cmd_head;
|
||||
uint16 cmd_num;
|
||||
uint16 cmd_channel;
|
||||
uint16 cmd_size;
|
||||
uint16 tunning_head;
|
||||
uint16 tunning_succ;
|
||||
uint16 tunning_err;
|
||||
uint32 backup_addr;
|
||||
uint16 response[6];
|
||||
uint16 message_head[8];
|
||||
};
|
||||
void isp_tunning_init();
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
98
sdk/include/hal/jpeg.h
Normal file
98
sdk/include/hal/jpeg.h
Normal file
@@ -0,0 +1,98 @@
|
||||
#ifndef _HAL_JPEG_H_
|
||||
#define _HAL_JPEG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum jpg_device_irq_flag {
|
||||
JPG_IRQ_FLAG_JPG_DONE = BIT(0),
|
||||
JPG_IRQ_FLAG_JPG_BUF_FULL = BIT(1),
|
||||
JPG_IRQ_FLAG_ERROR = BIT(2),
|
||||
JPG_IRQ_FLAG_PIXEL_DONE = BIT(3),
|
||||
JPG_IRQ_FLAG_TIME_OUT = BIT(4),
|
||||
};
|
||||
|
||||
enum jpg_ioctl_cmd {
|
||||
JPG_IOCTL_CMD_IS_ONLINE,
|
||||
JPG_IOCTL_CMD_SET_ADR,
|
||||
JPG_IOCTL_CMD_SET_QT,
|
||||
JPG_IOCTL_CMD_SET_SIZE,
|
||||
JPG_IOCTL_CMD_SET_SRC_FROM,
|
||||
JPG_IOCTL_CMD_UPDATE_QT,
|
||||
JPG_IOCTL_CMD_DECODE_TAG,
|
||||
JPG_IOCTL_CMD_OPEN_DBG,
|
||||
JPG_IOCTL_CMD_SOFT_FRAME_START,
|
||||
JPG_IOCTL_CMD_SOFT_KICK,
|
||||
JPG_IOCTL_CMD_HW_CHK,
|
||||
JPG_IOCTL_CMD_IS_IDLE,
|
||||
JPG_IOCTL_CMD_BUFF_INIT,
|
||||
JPG_IOCTL_CMD_SET_SOFT_Y,
|
||||
JPG_IOCTL_CMD_SET_SOFT_UV,
|
||||
JPG_IOCTL_CMD_TIMEOUT_CNT,
|
||||
JPG_IOCTL_CMD_TIMEOUT_EN,
|
||||
JPG_IOCTL_CMD_DECAUTO_RUN_EN,
|
||||
JPG_IOCTL_CMD_DEC_LEN_CFG_EN,
|
||||
JPG_IOCTL_CMD_DEC_FLUSH_EN,
|
||||
JPG_IOCTL_CMD_CODEC_RESET,
|
||||
JPG_IOCTL_CMD_SET_DLEN,
|
||||
JPG_IOCTL_CMD_VSYNC_DLY,
|
||||
JPG_IOCTL_CMD_SET_READY,
|
||||
JPG_IOCTL_CMD_SET_OE_SELECT,
|
||||
JPG_IOCTL_CMD_SET_OE,
|
||||
JPG_IOCTL_CMD_GET_OE,
|
||||
};
|
||||
|
||||
|
||||
typedef int32(*jpg_irq_hdl)(uint32 irq_flag, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
struct jpg_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct jpeg_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct jpg_device *jpg);
|
||||
int32(*close)(struct jpg_device *jpg);
|
||||
int32(*suspend)(struct jpg_device *jpg);
|
||||
int32(*resume)(struct jpg_device *jpg);
|
||||
int32(*init)(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
|
||||
int32(*decode)(struct jpg_device *jpg,uint32 photo,uint32_t len);
|
||||
int32(*ioctl)(struct jpg_device *jpg, enum jpg_ioctl_cmd cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
|
||||
int32(*release_irq)(struct jpg_device *jpg, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 jpg_open(struct jpg_device *jpg);
|
||||
int32 jpg_close(struct jpg_device *jpg);
|
||||
int32 jpg_init(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
|
||||
int32 jpg_updata_dqt(struct jpg_device *p_jpg, uint32 *dqtbuf);
|
||||
int32 jpg_suspend(struct jpg_device *jpg);
|
||||
int32 jpg_resume(struct jpg_device *jpg);
|
||||
int32 jpg_set_size(struct jpg_device *p_jpg, uint32 h, uint32 w);
|
||||
int32 jpg_set_addr(struct jpg_device *jpg, uint32 addr, uint32 buflen);
|
||||
int32 jpg_set_qt(struct jpg_device *jpg, uint32 qt);
|
||||
int32 jpg_open_debug(struct jpg_device *p_jpg, uint8 enable);
|
||||
int32 jpg_soft_kick(struct jpg_device *p_jpg, uint8 kick);
|
||||
int32 jpg_decode_target(struct jpg_device *p_jpg, uint8 to_scaler);
|
||||
int32 jpg_decode_photo(struct jpg_device *p_jpg, uint32 photo, uint32 len);
|
||||
int32 jpg_request_irq(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flags, void *irq_data);
|
||||
int32 jpg_release_irq(struct jpg_device *jpg, uint32 irq_flags);
|
||||
int32 jpg_set_data_from(struct jpg_device *p_jpg, uint8 src_from);
|
||||
int32 jpg_set_hw_check(struct jpg_device *p_jpg, uint8 enable);
|
||||
int32 jpg_is_online(struct jpg_device *p_jpg);
|
||||
int32 jpg_is_idle(struct jpg_device *p_jpg);
|
||||
int32 jpg_set_ready(struct jpg_device *p_jpg);
|
||||
int32 jpg_select_oe_using(struct jpg_device *p_jpg,uint8_t enable,uint8_t oe);
|
||||
int32 jpg_get_oe_ready(struct jpg_device *p_jpg);
|
||||
int32 jpg_set_vsync_dly(struct jpg_device *p_jpg,uint8_t enable);
|
||||
int32 jpg_set_oe_state(struct jpg_device *p_jpg,uint8_t oe);
|
||||
int32 jpg_dec_len_cfg_enable(struct jpg_device *p_jpg, uint8 enable);
|
||||
int32 jpg_timeout_cfg_enable(struct jpg_device *p_jpg, uint8 enable);
|
||||
int32 jpg_timeout_cfg(struct jpg_device *p_jpg, uint32 timeout);
|
||||
int32 jpg_auto_rekick_cfg(struct jpg_device *p_jpg, uint8 enable);
|
||||
int32 jpg_try_dec_cfg(struct jpg_device *p_jpg, uint8 enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
676
sdk/include/hal/lcdc.h
Normal file
676
sdk/include/hal/lcdc.h
Normal file
@@ -0,0 +1,676 @@
|
||||
#ifndef HAL_LCDC_H
|
||||
#define HAL_LCDC_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*lcdc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum lcdc_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_TIMEOUT_INF,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_AUTO_KICK_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROT_PSRAM_BURST_SW,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_QSPI_DW4,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_TXCMD_AUTO,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_SPI_DUMMY_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DSI_TEAR_REQUEST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DSI_REG_UPDATE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DSI_DPI_COLORM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DSI_DPI_SHUT_DN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_EDSI_ITF_SELECT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_CLK_ALWAY_ON,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_CONSTRAST_SATURATION_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_CONSTRAST_SATURATION_VAL,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_GAMMA_RGB_ADR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_CCM_GAMMA_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_COLOR_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_BUS_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_INTERFACE_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_COLRARRAY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_LCD_VAILD_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_LCD_VISIBLE_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_SIGNAL_CONFIG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_MCU_SIGNAL_CONFIG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_INVALID_LINE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VALID_DOT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_HLW_VLW,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VIDEO_BIG_ENDIAN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_TE_EDGE_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VIDEO_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P0_ROTATE_Y_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P0_ROTATE_U_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P0_ROTATE_V_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P1_ROTATE_Y_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P1_ROTATE_U_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P1_ROTATE_V_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_P0P1_ROTATE_START_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_P0_UP,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_P0_P1_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_LINE_BUF_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_LINE_BUF_Y,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_LINE_BUF_U,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_LINE_BUF_V,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_MIRROR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_ROTATE_SET_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VIDEO_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VIDEO_START_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_VIDEO_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_START_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_LUTDMA_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_DMA_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_DMA_LEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_FORMAT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ALPHA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_HEAD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_DIAP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_CFG,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_TRANS_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_DST_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_SRC_LEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_GET_OSD_ENC_DST_LEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_OSD_ENC_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DITHER_LINEBUF,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_DITHER_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_MCU_CPU_WRITE,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_MCU_CPU_READ,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_REG_CPU_WRITE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_CLK_GATHER,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_CS_LOCK_TIME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SCREEN_SHOT_START,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SCREEN_SHOT_FORMAT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SCREEN_YUVADR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_OSD_USE_SRAM_FIFO_ENABLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_OSD_USE_SPEC_COLOR_ALPHA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_OSD_SRAM_FIFO_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_CLK_STATUS_IS_OK,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
LCDC_SET_START_RUN,
|
||||
};
|
||||
|
||||
|
||||
enum lcdc_color_mode {
|
||||
LCD_MODE_565 = 16,
|
||||
LCD_MODE_666 = 18,
|
||||
LCD_MODE_888 = 24,
|
||||
};
|
||||
|
||||
enum lcdc_bus_width {
|
||||
LCD_BUS_WIDTH_1 = 1,
|
||||
LCD_BUS_WIDTH_2 = 2,
|
||||
LCD_BUS_WIDTH_4 = 4,
|
||||
LCD_BUS_WIDTH_5 = 5,
|
||||
LCD_BUS_WIDTH_6 = 6,
|
||||
LCD_BUS_WIDTH_8 = 8,
|
||||
LCD_BUS_WIDTH_9 = 9,
|
||||
LCD_BUS_WIDTH_12 = 12,
|
||||
LCD_BUS_WIDTH_16 = 16,
|
||||
LCD_BUS_WIDTH_18 = 18,
|
||||
LCD_BUS_WIDTH_24 = 24,
|
||||
};
|
||||
|
||||
enum lcdc_interface_mode {
|
||||
LCD_BUS_RGB,
|
||||
LCD_BUS_I80,
|
||||
LCD_BUS_I68,
|
||||
LCD_BUS_MIPI,
|
||||
LCD_BUS_SPI3,
|
||||
LCD_BUS_SPI4,
|
||||
LCD_BUS_QSPI,
|
||||
};
|
||||
|
||||
enum lcdc_rotate_mode {
|
||||
LCD_ROTATE_0,
|
||||
LCD_ROTATE_90,
|
||||
LCD_ROTATE_180,
|
||||
LCD_ROTATE_270,
|
||||
};
|
||||
|
||||
enum lcdc_video_mode {
|
||||
VIDEO_FROM_SCALE,
|
||||
VIDEO_FROM_MEMORY_NO_ROTATE,
|
||||
VIDEO_FROM_MEMORY_ROTATE,
|
||||
VIDEO_FROM_SCALE2_DEC,
|
||||
};
|
||||
|
||||
enum lcdc_osd_format {
|
||||
OSD_RGB_256,
|
||||
OSD_RGB_565,
|
||||
OSD_RGB_888,
|
||||
};
|
||||
|
||||
|
||||
struct lcdc_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct lcdc_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct lcdc_device *lcdc_dev);
|
||||
int32(*suspend)(struct lcdc_device *lcdc_dev);
|
||||
int32(*resume)(struct lcdc_device *lcdc_dev);
|
||||
int32(*deinit)(struct lcdc_device *lcdc_dev);
|
||||
int32(*baudrate)(struct lcdc_device *lcdc_dev, uint32 baudrate);
|
||||
int32(*open)(struct lcdc_device *lcdc_dev);
|
||||
int32(*close)(struct lcdc_device *lcdc_dev);
|
||||
int32(*ioctl)(struct lcdc_device *lcdc_dev, enum lcdc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag, lcdc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int32 lcdc_suspend(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_resume(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_init(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_deinit(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_open(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_close(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_request_irq(struct lcdc_device *p_lcdc, uint32 irq_flags, lcdc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 lcdc_release_irq(struct lcdc_device *p_lcdc, uint32 irq_flags);
|
||||
int32 lcdc_set_baudrate(struct lcdc_device *p_lcdc, uint32 mclk);
|
||||
int32 lcdc_set_color_mode(struct lcdc_device *p_lcdc, enum lcdc_color_mode cm);
|
||||
int32 lcdc_set_bus_width(struct lcdc_device *p_lcdc, enum lcdc_bus_width bw);
|
||||
int32 lcdc_set_interface(struct lcdc_device *p_lcdc, enum lcdc_interface_mode im);
|
||||
int32 lcdc_set_colrarray(struct lcdc_device *p_lcdc, uint8 colrarray);
|
||||
int32 lcdc_set_lcd_vaild_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
|
||||
int32 lcdc_set_lcd_visible_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
|
||||
int32 lcdc_signal_config(struct lcdc_device *p_lcdc, uint8 vs_en,uint8 hs_en,uint8 de_en,uint8 vs_inv,uint8 hs_inv,uint8 de_inv,uint8 clk_inv);
|
||||
int32 lcdc_mcu_signal_config(struct lcdc_device *p_lcdc, uint8 value);
|
||||
int32 lcdc_set_invalid_line(struct lcdc_device *p_lcdc, uint8 invalid_line);
|
||||
int32 lcdc_set_valid_dot(struct lcdc_device *p_lcdc, uint32 w_start,uint32 h_start);
|
||||
int32 lcdc_set_hlw_vlw(struct lcdc_device *p_lcdc, uint32 hlw,uint32 vlw);
|
||||
int32 lcdc_set_bigendian(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_set_video_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
|
||||
int32 lcdc_set_p0_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
|
||||
int32 lcdc_set_p0_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
|
||||
int32 lcdc_set_p0_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
|
||||
int32 lcdc_set_p1_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
|
||||
int32 lcdc_set_p1_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
|
||||
int32 lcdc_set_p1_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
|
||||
int32 lcdc_set_rotate_p0_up(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_set_rotate_p0p1_start_location(struct lcdc_device *p_lcdc, uint32 x0,uint32 y0,uint32 x1,uint32 y1);
|
||||
int32 lcdc_set_rotate_linebuf_num(struct lcdc_device *p_lcdc, uint32 linebuf);
|
||||
int32 lcdc_set_rotate_linebuf_y_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
|
||||
int32 lcdc_set_rotate_linebuf_u_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
|
||||
int32 lcdc_set_rotate_linebuf_v_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
|
||||
int32 lcdc_set_rotate_mirror(struct lcdc_device *p_lcdc, uint8 mirror,enum lcdc_rotate_mode rotate);
|
||||
int32 lcdc_set_rotate_p0p1_size(struct lcdc_device *p_lcdc, uint32 w0,uint32 h0,uint32 w1,uint32 h1);
|
||||
int32 lcdc_set_video_data_from(struct lcdc_device *p_lcdc, enum lcdc_video_mode vm);
|
||||
int32 lcdc_set_video_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
|
||||
int32 lcdc_set_video_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_set_osd_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
|
||||
int32 lcdc_set_osd_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
|
||||
int32 lcdc_set_osd_dma_addr(struct lcdc_device *p_lcdc, uint32 addr);
|
||||
int32 lcdc_set_osd_lut_addr(struct lcdc_device *p_lcdc, uint32 addr);
|
||||
int32 lcdc_set_osd_dma_len(struct lcdc_device *p_lcdc, uint32 len);
|
||||
int32 lcdc_set_osd_format(struct lcdc_device *p_lcdc, enum lcdc_osd_format osd_format);
|
||||
int32 lcdc_set_osd_alpha(struct lcdc_device *p_lcdc, uint32 alpha);
|
||||
int32 lcdc_set_osd_enc_head(struct lcdc_device *p_lcdc, uint32 head, uint32 head_tran);
|
||||
int32 lcdc_set_osd_enc_diap(struct lcdc_device *p_lcdc, uint32 diap, uint32 diap_tran);
|
||||
int32 lcdc_set_osd_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_set_osd_enc_src_addr(struct lcdc_device *p_lcdc, uint32 addr);
|
||||
int32 lcdc_set_osd_enc_dst_addr(struct lcdc_device *p_lcdc, uint32 addr);
|
||||
int32 lcdc_set_p0p1_enable(struct lcdc_device *p_lcdc, uint8 p0_en,uint8 p1_en);
|
||||
int32 lcdc_set_osd_enc_src_len(struct lcdc_device *p_lcdc, uint32 len);
|
||||
int32 lcdc_get_osd_enc_dst_len(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_osd_enc_start_run(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_set_start_run(struct lcdc_device *p_lcdc);
|
||||
int32 lcdc_video_enable_constrast_saturation(struct lcdc_device *p_lcdc, uint8 constrast,uint8 saturation);
|
||||
int32 lcdc_video_constrast_saturation_val(struct lcdc_device *p_lcdc, uint32 saturation,uint32 constrast);
|
||||
int32 lcdc_video_enable_ccm_gamma(struct lcdc_device *p_lcdc, uint8 ccm, uint8 gamma);
|
||||
int32 lcdc_mcu_write_reg(struct lcdc_device *p_lcdc,uint8 data);
|
||||
int32 lcdc_mcu_write_data(struct lcdc_device *p_lcdc,uint8 data);
|
||||
int32 lcdc_video_enable_auto_ks(struct lcdc_device *p_lcdc, uint8 enable);
|
||||
int32 lcdc_set_timeout_info(struct lcdc_device *p_lcdc, uint8 enable,uint8 timeout);
|
||||
int32 lcdc_set_osd_enc_cfg(struct lcdc_device *p_lcdc, uint32 head, uint32 diap);
|
||||
int32 lcdc_reg_write_data(struct lcdc_device *p_lcdc,uint8 cmdlen,uint8 reglen, uint8 *buf);
|
||||
int32 lcdc_reg_read_data(struct lcdc_device *p_lcdc,uint8 cmdlen,uint8 reglen, uint8 *buf);
|
||||
int32 lcdc_rot_burst_dw16(struct lcdc_device *p_lcdc, uint8 dw16);
|
||||
int32 lcdc_qspi_cmd_dw4(struct lcdc_device *p_lcdc, uint8 dw4);
|
||||
int32 lcdc_cmd_auto_send(struct lcdc_device *p_lcdc, uint32 cmd0, uint32 cmd1);
|
||||
int32 lcdc_spi_dummy_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dsi_tear_request(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dsi_reg_update(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dsi_dpi_colorm(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dsi_dpi_shutdown(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dsi_select_edpi_or_dpi(struct lcdc_device *p_lcdc, uint8 edpi);
|
||||
int32 lcdc_clock_alway_on(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_gamma_rgb_table(struct lcdc_device *p_lcdc, uint32 radr,uint32 gadr,uint32 badr);
|
||||
int32 lcdc_te_edge_cfg(struct lcdc_device *p_lcdc, uint8 pullup);
|
||||
int32 lcdc_osd_enc_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_osd_trans_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_dither_linebuf(struct lcdc_device *p_lcdc, uint32 lineaddr);
|
||||
int32 lcdc_dither_en(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_clk_gather_select(struct lcdc_device *p_lcdc, uint8 pull);
|
||||
int32 lcdc_screen_start(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_screen_format(struct lcdc_device *p_lcdc, uint8 format);
|
||||
int32 lcdc_screen_yuv_addr(struct lcdc_device *p_lcdc, uint32 radr,uint32 gadr,uint32 badr);
|
||||
int32 lcdc_spi_cs_lock_time(struct lcdc_device *p_lcdc, uint8 cs_setup,uint8 cs_hold,uint8 cs_high);
|
||||
int32 lcdc_osd_sram_fifo_enable(struct lcdc_device *p_lcdc, uint8 en);
|
||||
int32 lcdc_osd_sram_fifo_addr(struct lcdc_device *p_lcdc, uint32 start, uint32 end);
|
||||
int32 lcdc_osd_spec_color_alpha(struct lcdc_device *p_lcdc, uint8 enable, uint32 color, uint32 alpha);
|
||||
int32 lcdc_get_clk_status(struct lcdc_device *p_lcdc);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
350
sdk/include/hal/led.h
Normal file
350
sdk/include/hal/led.h
Normal file
@@ -0,0 +1,350 @@
|
||||
#ifndef _HAL_LED_H_
|
||||
#define _HAL_LED_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief LED work_mode type
|
||||
*/
|
||||
enum led_work_mode {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Work mode for common anode digital tube
|
||||
*/
|
||||
LED_WORK_MODE_COMMON_ANODE,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Work mode for common cathode digital tube
|
||||
*/
|
||||
LED_WORK_MODE_COMMON_CATHODE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief LED seg_cnt type
|
||||
*/
|
||||
enum led_seg_cnt {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 1 piece
|
||||
*/
|
||||
LED_SEG_CNT_1,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 2 piece
|
||||
*/
|
||||
LED_SEG_CNT_2,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 3 piece
|
||||
*/
|
||||
LED_SEG_CNT_3,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 4 piece
|
||||
*/
|
||||
LED_SEG_CNT_4,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 5 piece
|
||||
*/
|
||||
LED_SEG_CNT_5,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 6 piece
|
||||
*/
|
||||
LED_SEG_CNT_6,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 7 piece
|
||||
*/
|
||||
LED_SEG_CNT_7,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 8 piece
|
||||
*/
|
||||
LED_SEG_CNT_8,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 9 piece
|
||||
*/
|
||||
LED_SEG_CNT_9,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 10 piece
|
||||
*/
|
||||
LED_SEG_CNT_10,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 11 piece
|
||||
*/
|
||||
LED_SEG_CNT_11,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of segument: 12 piece
|
||||
*/
|
||||
LED_SEG_CNT_12,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief LED com_cnt type
|
||||
*/
|
||||
enum led_com_cnt {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 1 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_1,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 2 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_2,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 3 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_3,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 4 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_4,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 5 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_5,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 6 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_6,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 7 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_7,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Amount of com: 8 piece
|
||||
*@ Note:
|
||||
* It is also position for "led_open" function's parameter
|
||||
*/
|
||||
LED_COM_CNT_8,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief LED irq_flag type
|
||||
*/
|
||||
enum led_irq_flag {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* emmm...
|
||||
*/
|
||||
LED_IRQ_FLAG_INT = BIT(0),
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief LED ioctl_cmd type
|
||||
*/
|
||||
enum led_ioctl_cmd {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
* Set scan frequency and set the length of time
|
||||
*/
|
||||
LED_IOCTL_CMD_SET_SCAN_FREQ,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*led_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* LED api for user */
|
||||
struct led_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct led_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
|
||||
int32(*on)(struct led_device *led, uint32 num, enum led_com_cnt pos);
|
||||
int32(*off)(struct led_device *led, enum led_com_cnt pos);
|
||||
int32(*close)(struct led_device *led);
|
||||
int32(*ioctl)(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct led_device *led, enum led_irq_flag irq_flag);
|
||||
};
|
||||
|
||||
|
||||
/* LED API functions */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief led_open
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note This function must be called before any led driver operations.
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param work_mode The tube.work mode setting - see "enum led_work_mode".
|
||||
* @param seg_cnt The tube's segmument amounts - see "enum led_seg_cnt".
|
||||
* @param com_cnt The tube's com amounts - see "enum led_com_cnt".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_open(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
|
||||
|
||||
/**
|
||||
* @brief led_on
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param num What does the user want to display the numbers, must be 0~9.
|
||||
* @param pos Where does the user want to display the numbers - see "enum led_com_cnt".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_on(struct led_device *led, uint32 num, enum led_com_cnt pos);
|
||||
|
||||
/**
|
||||
* @brief led_off
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param num What does the user want to display the numbers, must be 0~9.
|
||||
* @param pos Where does the user want to display the numbers - see "enum led_com_cnt".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_off(struct led_device *led, enum led_com_cnt pos);
|
||||
|
||||
|
||||
/**
|
||||
* @brief led_close
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_close(struct led_device *led);
|
||||
|
||||
/**
|
||||
* @brief led_ioctl
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param ioctl_cmd The ioctl command - - see "enum led_ioctl_cmd".
|
||||
* @param param1 The parameter to function.
|
||||
* @param param2 The parameter to function.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_ioctl(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
|
||||
/**
|
||||
* @brief led_request_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param irq_flag The type of interrupt - see"enum led_irq_flag".
|
||||
* @param irqhdl The interrupt function.
|
||||
* @param irq_data The parameter of the interrupt function
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_request_irq(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
|
||||
|
||||
/**
|
||||
* @brief led_release_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param led The address of led device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 led_release_irq(struct led_device *led, enum led_irq_flag irq_flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
86
sdk/include/hal/netdev.h
Normal file
86
sdk/include/hal/netdev.h
Normal file
@@ -0,0 +1,86 @@
|
||||
#ifndef _HAL_NETDEVICE_H_
|
||||
#define _HAL_NETDEVICE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum netdev_events {
|
||||
NETDEV_EVT_LINK_STATUS_CHANGE,
|
||||
};
|
||||
|
||||
enum netdev_link_status {
|
||||
NETDEV_LINK_DOWN,
|
||||
NETDEV_LINK_UP,
|
||||
};
|
||||
|
||||
enum netdev_phy_event {
|
||||
NETDEV_PHY_EVENT_LINK_CHANGED,
|
||||
};
|
||||
|
||||
enum netdev_ioctl_cmd {
|
||||
NETDEV_IOCTL_GET_ADDR,
|
||||
NETDEV_IOCTL_SET_ADDR,
|
||||
NETDEV_IOCTL_GET_LINK_STATUS,
|
||||
NETDEV_IOCTL_GET_LINK_SPEED,
|
||||
NETDEV_IOCTL_FORCE_LINK,
|
||||
NETDEV_IOCTL_SET_FILTER_MAC,
|
||||
NETDEV_IOCTL_SET_WIFI_MODE,
|
||||
NETDEV_IOCTL_HOOK_INPUTDATA,
|
||||
NETDEV_IOCTL_ENABLE_WIFIBRIDGE,
|
||||
NETDEV_IOCTL_ENABLE_ICMPMNTR,
|
||||
NETDEV_IOCTL_CLEAR_ROUTETBL,
|
||||
NETDEV_IOCTL_SET_MCAST_FIREWALL,
|
||||
NETDEV_IOCTL_SET_TX_NONBLOCK,
|
||||
};
|
||||
|
||||
struct netdev;
|
||||
|
||||
typedef void (*netdev_input_cb)(struct netdev *ndev, uint8 *data, uint32 size, void *priv);
|
||||
typedef void (*netdev_event_cb)(struct netdev *ndev, uint32 event, uint32 param, void *priv);
|
||||
|
||||
struct netdev {
|
||||
struct dev_obj dev;
|
||||
void *stack_data;
|
||||
uint64 rx_bytes, tx_bytes;
|
||||
};
|
||||
|
||||
struct netdev_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
|
||||
int32(*close)(struct netdev *ndev);
|
||||
int32(*ioctl)(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*send_data)(struct netdev *ndev, uint8 *p_data, uint32 size);
|
||||
int32(*send_scatter_data)(struct netdev *ndev, scatter_data *data, uint32 count);
|
||||
int32(*mdio_write)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
|
||||
int32(*mdio_read)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
|
||||
void (*phy_event)(void *phydev, uint32 event, uint32 param1, uint32 param2);
|
||||
};
|
||||
|
||||
int32 netdev_open(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
|
||||
int32 netdev_close(struct netdev *ndev);
|
||||
int32 netdev_send_data(struct netdev *ndev, uint8 *p_data, uint32 size);
|
||||
int32 netdev_send_scatter_data(struct netdev *ndev, scatter_data *p_data, uint32 count);
|
||||
int32 netdev_ioctl(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 netdev_mdio_write(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
|
||||
int32 netdev_mdio_read(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
|
||||
|
||||
#define netdev_link_speed(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_SPEED, 0, 0)
|
||||
#define netdev_link_status(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_STATUS, 0, 0)
|
||||
#define netdev_set_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_SET_ADDR, (uint32)addr, 0)
|
||||
#define netdev_get_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_GET_ADDR, (uint32)addr, 0)
|
||||
#define netdev_force_link(ndev, link_speed, duplex_flag) netdev_ioctl(ndev, NETDEV_IOCTL_FORCE_LINK, link_speed, duplex_flag)
|
||||
#define netdev_set_filter_mac(ndev, mac_table, size) netdev_ioctl(ndev, NETDEV_IOCTL_SET_FILTER_MAC, (uint32)mac_table, (uint32)size)
|
||||
#define netdev_set_wifi_mode(ndev, mode) netdev_ioctl(ndev, NETDEV_IOCTL_SET_WIFI_MODE, mode, 0)
|
||||
#define netdev_hook_inputdata(ndev, data, len) netdev_ioctl(ndev, NETDEV_IOCTL_HOOK_INPUTDATA, data, len)
|
||||
#define netdev_set_wifi_bridge(ndev, en) netdev_ioctl(ndev, NETDEV_IOCTL_ENABLE_WIFIBRIDGE, en, 0)
|
||||
#define netdev_clear_routetbl(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_CLEAR_ROUTETBL, 0, 0)
|
||||
#define netdev_set_mcastfw(ndev, tot_1s, each_1s) netdev_ioctl(ndev, NETDEV_IOCTL_SET_MCAST_FIREWALL, tot_1s, each_1s)
|
||||
#define netdev_set_tx_nonblock(ndev, nonblock) netdev_ioctl(ndev, NETDEV_IOCTL_SET_TX_NONBLOCK, nonblock, 0)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
56
sdk/include/hal/of.h
Normal file
56
sdk/include/hal/of.h
Normal file
@@ -0,0 +1,56 @@
|
||||
#ifndef HAL_OF_H
|
||||
#define HAL_OF_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum of_instr_mode {
|
||||
CUSADA8_INIT_ZERO,
|
||||
CUSADA8_INIT_ACC,
|
||||
CUHADD8_AVG,
|
||||
};
|
||||
|
||||
enum of_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OF_INSTR_MODE,
|
||||
|
||||
CAL_PIXEL_NUM,
|
||||
|
||||
CAL_ROW_NUM,
|
||||
|
||||
SET_ROW_SIZE,
|
||||
|
||||
SET_OF_ADDR,
|
||||
|
||||
GET_CAL_ACC,
|
||||
};
|
||||
|
||||
struct of_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct of_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct of_device *of_dev);
|
||||
int32(*deinit)(struct of_device *of_dev);
|
||||
int32(*ioctl)(struct of_device *of_dev, enum of_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
};
|
||||
|
||||
|
||||
int32 of_init(struct of_device *p_of);
|
||||
int32 of_deinit(struct of_device *p_of);
|
||||
int32 of_set_instr_mode(struct of_device *p_of,enum of_instr_mode instr_format);
|
||||
int32 of_set_pixel_num(struct of_device *p_of,uint32 pixel_num);
|
||||
int32 of_set_row_num(struct of_device *p_of,uint32 row_num);
|
||||
int32 of_set_row_size(struct of_device *p_of,uint32 row_size);
|
||||
int32 of_set_addr(struct of_device *p_of,uint32 addr0,uint32 addr1);
|
||||
int32 of_get_acc(struct of_device *p_of);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
79
sdk/include/hal/osd_enc.h
Normal file
79
sdk/include/hal/osd_enc.h
Normal file
@@ -0,0 +1,79 @@
|
||||
#ifndef HAL_OSD_ENC_H
|
||||
#define HAL_OSD_ENC_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef int32(*osdenc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
enum osdenc_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_TRAN_IDENT_TRANS,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_ENC_ADR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_SET_ENC_RLEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_SET_ENC_FORMAT,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_GET_ENC_DLEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
OSD_IOCTL_SET_ENC_RUN,
|
||||
};
|
||||
|
||||
struct osdenc_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct osdenc_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct osdenc_device *osd_dev);
|
||||
int32(*suspend)(struct osdenc_device *osd_dev);
|
||||
int32(*resume)(struct osdenc_device *osd_dev);
|
||||
int32(*close)(struct osdenc_device *osd_dev);
|
||||
int32(*ioctl)(struct osdenc_device *osd_dev, enum osdenc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct osdenc_device *osd_dev, uint32 irq_flag, osdenc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct osdenc_device *osd_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 osd_enc_suspend(struct osdenc_device *p_osd);
|
||||
int32 osd_enc_resume(struct osdenc_device *p_osd);
|
||||
int32 osd_enc_open(struct osdenc_device *p_osd);
|
||||
int32 osd_enc_close(struct osdenc_device *p_osd);
|
||||
int32 osd_enc_tran_config(struct osdenc_device *p_osd,uint32 head,uint32 head_tran,uint32 diap,uint32 diap_tran);
|
||||
int32 osd_enc_addr(struct osdenc_device *p_osd,uint32 src,uint32 des);
|
||||
int32 osd_enc_src_len(struct osdenc_device *p_osd,uint32 len);
|
||||
int32 osd_enc_set_format(struct osdenc_device *p_osd,uint8 isrgb565);
|
||||
int32 osd_enc_run(struct osdenc_device *p_osd);
|
||||
int32 osd_enc_request_irq(struct osdenc_device *p_osd, uint32 irq_flags, osdenc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 osd_enc_release_irq(struct osdenc_device *p_osd, uint32 irq_flags);
|
||||
int32 osd_enc_dlen(struct osdenc_device *p_osd);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
119
sdk/include/hal/para_in.h
Normal file
119
sdk/include/hal/para_in.h
Normal file
@@ -0,0 +1,119 @@
|
||||
#ifndef HAL_PARA_IN_H
|
||||
#define HAL_PARA_IN_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef int32(*para_in_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param, uint32 param2);
|
||||
|
||||
enum para_in_dev_irqs {
|
||||
FRM_RX_DOWN_ISR = BIT(0),
|
||||
OFOV_ISR = BIT(1),
|
||||
IFOV_ISR = BIT(2),
|
||||
VSYNC_ERR_ISR = BIT(3),
|
||||
HSYNC_ERR_ISR = BIT(4),
|
||||
ESAV_ERR_ISR = BIT(5),
|
||||
TIMEOUT_ISR = BIT(6),
|
||||
};
|
||||
|
||||
enum para_in_intf {
|
||||
PARA_IN_BT601 = 0,
|
||||
PARA_IN_BT656,
|
||||
PARA_IN_BT1120,
|
||||
};
|
||||
|
||||
enum para_in_dev_fmt {
|
||||
PARA_IN_YUV = 0,
|
||||
PARA_IN_YCrCb,
|
||||
};
|
||||
|
||||
// VPP/ISP 与 PARA IN 模式顺序相反
|
||||
enum para_in_dev_yuv_sequence {
|
||||
U_Y1_V_Y2 = 0,
|
||||
V_Y1_U_Y2,
|
||||
Y1_U_Y2_V,
|
||||
Y1_V_Y2_U,
|
||||
U_Y2_V_Y1,
|
||||
V_Y2_U_Y1,
|
||||
Y2_U_Y1_V,
|
||||
Y2_V_Y1_U,
|
||||
};
|
||||
|
||||
enum para_in_ioctl_cmd{
|
||||
PARA_IN_SET_PARAMS = 0,
|
||||
PARA_IN_SET_TIMEOUT_EN,
|
||||
PARA_IN_SET_TIMEOUT_TIME,
|
||||
PARA_IN_SET_VHSYNC_EN,
|
||||
PARA_IN_SET_HSYNC_POL,
|
||||
PARA_IN_SET_VSYNC_POL,
|
||||
PARA_IN_SMAP_CLK_SEL,
|
||||
PARA_IN_INTF_SEL,
|
||||
PARA_IN_YUV_SEL,
|
||||
PARA_IN_SET_OUTPUT_SEQUENCE,
|
||||
PARA_IN_SET_INPUT_SEQUENCE,
|
||||
PARA_IN_FRT_VSYNC_SEL,
|
||||
PARA_IN_SAV_AHEAD,
|
||||
PARA_IN_RC_ST_DTC_MODE,
|
||||
PARA_IN_ESAV_ERR_DTC_EN,
|
||||
PARA_IN_SET_CON_EN,
|
||||
};
|
||||
|
||||
enum para_in_samp_edge{
|
||||
PARA_IN_RISING_EDGE = 0,
|
||||
PARA_IN_FALLING_EDGE,
|
||||
};
|
||||
|
||||
typedef struct PARA_IN_SENSOR_REG_INFO
|
||||
{
|
||||
unsigned char reg_addr;
|
||||
unsigned char value;
|
||||
} _PARA_IN_SENSOR_REG_INFO;
|
||||
|
||||
#define PARA_IN_REG_END {0xFF,0xFF}
|
||||
|
||||
struct para_in_params {
|
||||
uint32_t act_hblk; //ACT_HBLK : 有效行非有效数据长度（注：若有数据含有EAV，SAV需加上EAV与SAV长度。）
|
||||
uint32_t act_lpot_num; //ACT_LPOT_NUM : 有效行的真实数据点数（注：若一行的真实数据点数为720个，则有效数据长度为720 X 2。）
|
||||
uint32_t act_hf_frm_num; //ACT_HF_FRM_NUM : 半帧图像的有效行数
|
||||
uint8_t frt_fblk; //FRT_FBLK : 逐行数据的第一段消隐行数（注：至少为1）
|
||||
uint8_t sec_sblk; //SEC_SBLK : 逐行数据的第二段消隐行数（注：至少为1）
|
||||
uint32_t width;
|
||||
uint32_t height;
|
||||
uint8_t data_format; //para_in_intf (BT601 / BT656 / BT1120)
|
||||
uint8_t in_yuv_sequence; //para_in_dev_yuv_sequence 输入YUV顺序
|
||||
uint8_t out_yuv_sequence; //para_in_dev_yuv_sequence 输出YUV顺序
|
||||
uint8_t out_yuv_format; //para_in_dev_fmt
|
||||
uint8_t smap_edge; //para_in_samp_edge 采样边沿
|
||||
uint8_t vs_pol; //0: 高电平有效 1：低电平有效
|
||||
uint8_t hs_pol; //0: 高电平有效 1：低电平有效
|
||||
uint8_t i2c_dev_addr;
|
||||
uint8_t i2c_id_addr1;
|
||||
uint8_t i2c_id_addr2;
|
||||
uint16_t i2c_id;
|
||||
_PARA_IN_SENSOR_REG_INFO *i2c_init_table;
|
||||
};
|
||||
typedef struct para_in_params _Sensor_Para_in_Init;
|
||||
|
||||
struct para_in_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct para_in_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct para_in_device *para_in_dev);
|
||||
int32(*close)(struct para_in_device *para_in_dev);
|
||||
int32(*ioctl)(struct para_in_device *para_in_dev, enum para_in_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct para_in_device *para_in_dev, uint32 irq_flag, para_in_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct para_in_device *para_in_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 para_in_open(struct para_in_device *p_dev);
|
||||
int32 para_in_close(struct para_in_device *p_dev);
|
||||
int32 para_in_ioctl(struct para_in_device *p_dev, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 para_in_request_irq(struct para_in_device *p_dev, uint32 irq_flags, para_in_irq_hdl handle, uint32 data);
|
||||
int32 para_in_release_irq(struct para_in_device *p_dev, uint32 irq_flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
198
sdk/include/hal/pdm.h
Normal file
198
sdk/include/hal/pdm.h
Normal file
@@ -0,0 +1,198 @@
|
||||
#ifndef _HAL_PDM_H_
|
||||
#define _HAL_PDM_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief pdm sample frequency type
|
||||
*/
|
||||
enum pdm_sample_freq {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm sample frequency: 8K
|
||||
*/
|
||||
PDM_SAMPLE_FREQ_8K,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm sample frequency: 16K
|
||||
*/
|
||||
PDM_SAMPLE_FREQ_16K,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm sample frequency: 32K
|
||||
*/
|
||||
PDM_SAMPLE_FREQ_32K,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm sample frequency: 48K
|
||||
*/
|
||||
PDM_SAMPLE_FREQ_48K,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pdm channel of working mode type
|
||||
*/
|
||||
enum pdm_channel {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* channel of working mode: left channel
|
||||
*/
|
||||
PDM_CHANNEL_LEFT,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* channel of working mode: right channel
|
||||
*/
|
||||
PDM_CHANNEL_RIGHT,
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* channel of working mode: stereo channel
|
||||
*/
|
||||
PDM_CHANNEL_STEREO,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pdm interrupt type
|
||||
*/
|
||||
enum pdm_irq_flag {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm module receive data half of buf len
|
||||
*/
|
||||
PDM_IRQ_FLAG_DMA_HF = BIT(0),
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* pdm module receive data full of buf len
|
||||
*/
|
||||
PDM_IRQ_FLAG_DMA_OV = BIT(1),
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pdm ioctl cmd
|
||||
*/
|
||||
enum pdm_ioctl_cmd {
|
||||
/*! Compatible version: V0
|
||||
*@Describe:
|
||||
* Left and right channels interchange
|
||||
*/
|
||||
PDM_IOCTL_CMD_LR_CHANNEL_INTERCHANGE,
|
||||
};
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*pdm_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* PDM api for user */
|
||||
struct pdm_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct pdm_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32 (*open )(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
|
||||
int32 (*read )(struct pdm_device *pdm, void *buf, uint32 len);
|
||||
int32 (*close )(struct pdm_device *pdm);
|
||||
int32 (*request_irq)(struct pdm_device *pdm, enum pdm_irq_flag, pdm_irq_hdl irq_hdl, uint32 data);
|
||||
int32 (*release_irq)(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
|
||||
int32 (*ioctl )(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
|
||||
};
|
||||
|
||||
/* PDM API functions */
|
||||
|
||||
/**
|
||||
* @brief pdm_open
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @note This function must be called before any pdm driver operations.
|
||||
*
|
||||
* @param pdm The address of pdm device in the RTOS.
|
||||
* @param freq PDM sample frequency setting - see "enum pdm_sample_freq".
|
||||
* @param channel PDM channel of working mode setting - see "enum pdm_channel".
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_open(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pdm_read
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @note Turn PDM module on.
|
||||
*
|
||||
* @param pdm The address of pdm device in the RTOS.
|
||||
* @param buf The pointer of receive buf.
|
||||
* @param channel PDM module receive length.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_read(struct pdm_device *pdm, void *buf, uint32 len);
|
||||
|
||||
/**
|
||||
* @brief pdm_close
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @note Turn PDM module off.
|
||||
*
|
||||
* @param pdm The address of pdm device in the RTOS.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_close(struct pdm_device *pdm);
|
||||
|
||||
/**
|
||||
* @brief pdm_request_irq.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param pdm The address of PDM device in the RTOS.
|
||||
* @param irq_flag The type of interrupt - see"enum pdm_irq_flag".
|
||||
* @param irqhdl The interrupt function.
|
||||
* @param irq_data The parameters of the interrupt function
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_request_irq(struct pdm_device *pdm, enum pdm_irq_flag flag, pdm_irq_hdl irq_hdl, uint32 data);
|
||||
|
||||
/**
|
||||
* @brief pdm_release_irq.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param pdm The address of PDM device in the RTOS.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_release_irq(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
|
||||
|
||||
/**
|
||||
* @brief pdm_ioctl.
|
||||
*
|
||||
* @Compatible version: V0
|
||||
*
|
||||
* @param pdm The address of PDM device in the RTOS.
|
||||
* @param cmd Control command - see"enum pdm_ioctl_cmd".
|
||||
* @param param Parameters required to execute the current Control command.
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pdm_ioctl(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
102
sdk/include/hal/prc.h
Normal file
102
sdk/include/hal/prc.h
Normal file
@@ -0,0 +1,102 @@
|
||||
#ifndef HAL_PRC_H
|
||||
#define HAL_PRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* User interrupt handle */
|
||||
typedef int32(*prc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum prc_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_WIDTH,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_YUV_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_SET_SRC_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_FIRST_KICK,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PRC_IOCTL_CMD_KICK,
|
||||
|
||||
};
|
||||
|
||||
|
||||
struct prc_device {
|
||||
struct dev_obj dev;
|
||||
|
||||
};
|
||||
|
||||
struct prc_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct prc_device *prc_dev);
|
||||
int32(*suspend)(struct prc_device *prc_dev);
|
||||
int32(*resume)(struct prc_device *prc_dev);
|
||||
int32(*deinit)(struct prc_device *prc_dev);
|
||||
int32(*ioctl)(struct prc_device *prc_dev, enum prc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct prc_device *prc_dev, uint32 irq_flag, prc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct prc_device *prc_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 prc_suspend(struct prc_device *p_prc);
|
||||
int32 prc_resume(struct prc_device *p_prc);
|
||||
int32 prc_set_width(struct prc_device *p_prc, uint32 width);
|
||||
int32 prc_set_yuv_mode(struct prc_device *p_prc, uint32 mode);
|
||||
int32 prc_set_yaddr(struct prc_device *p_prc, uint32 addr);
|
||||
int32 prc_set_uaddr(struct prc_device *p_prc, uint32 addr);
|
||||
int32 prc_set_vaddr(struct prc_device *p_prc, uint32 addr);
|
||||
int32 prc_set_src_addr(struct prc_device *p_prc, uint32 addr);
|
||||
int32 prc_first_start(struct prc_device *p_prc);
|
||||
int32 prc_run(struct prc_device *p_prc);
|
||||
int32 prc_init(struct prc_device *p_prc);
|
||||
int32 prc_deinit(struct prc_device *p_prc);
|
||||
int32 prc_request_irq(struct prc_device *p_prc, uint32 irq_flags, prc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 prc_release_irq(struct prc_device *p_prc, uint32 irq_flags);
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
294
sdk/include/hal/pwm.h
Normal file
294
sdk/include/hal/pwm.h
Normal file
@@ -0,0 +1,294 @@
|
||||
#ifndef _HAL_PWM_H_
|
||||
#define _HAL_PWM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PWM channel type
|
||||
*/
|
||||
enum pwm_channel {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_0,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_1,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_2,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_3,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_4,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_CHANNEL_5,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief PWM irq_flag type
|
||||
*/
|
||||
enum pwm_irq_flag {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_IRQ_FLAG_COMPARE,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_IRQ_FLAG_PERIOD,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief PWM ioctl_cmd type
|
||||
*/
|
||||
enum pwm_ioctl_cmd {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_IOCTL_CMD_SET_PERIOD_DUTY,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_IOCTL_CMD_SET_SINGLE_INCREAM,
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
PWM_IOCTL_CMD_SET_INCREAM_DECREASE,
|
||||
|
||||
/*!
|
||||
* @brief: Set prescaler
|
||||
* @note:
|
||||
* 0x0：1/1
|
||||
* 0x1：1/2
|
||||
* 0x2：1/4
|
||||
* 0x3：1/8
|
||||
* 0x4：1/16
|
||||
* 0x5：1/32
|
||||
* 0x6：1/64
|
||||
* 0x7：1/128
|
||||
*/
|
||||
PWM_IOCTL_CMD_SET_PRESCALER,
|
||||
|
||||
/*!
|
||||
* @brief: Configure period and duty immediately
|
||||
*/
|
||||
PWM_IOCTL_CMD_SET_PERIOD_DUTY_IMMEDIATELY,
|
||||
};
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*pwm_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* PWM api for user */
|
||||
struct pwm_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct pwm_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*init)(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt);
|
||||
int32(*deinit)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
int32(*start)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
int32(*stop)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
int32(*suspend)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
int32(*resume)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
int32(*ioctl)(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data);
|
||||
int32(*release_irq)(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
};
|
||||
|
||||
|
||||
/* PWM API functions */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief pwm_init
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_init(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt);
|
||||
|
||||
/**
|
||||
* @brief pwm_deinit
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_deinit(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pwm_start
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_start(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pwm_stop
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_stop(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pwm_suspend channel
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_suspend(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pwm_resume channel
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_resume(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
/**
|
||||
* @brief pwm_ioctl
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_ioctl(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
|
||||
/**
|
||||
* @brief pwm_request_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_request_irq(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data);
|
||||
|
||||
/**
|
||||
* @brief pwm_release_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param pwm The address of pwm device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 pwm_release_irq(struct pwm_device *pwm, enum pwm_channel channel);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
50
sdk/include/hal/rotate.h
Normal file
50
sdk/include/hal/rotate.h
Normal file
@@ -0,0 +1,50 @@
|
||||
#ifndef HAL_ROTATE_H
|
||||
#define HAL_ROTATE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum rotate_ioctl_cmd {
|
||||
ROTATE_IOCTL_CMD_SET_ANALE_RUN,
|
||||
|
||||
ROTATE_IOCTL_CMD_SET_SIZE,
|
||||
|
||||
ROTATE_IOCTL_CMD_SET_ADDR,
|
||||
|
||||
ROTATE_IOCTL_CMD_GET_STA,
|
||||
};
|
||||
|
||||
enum rotate_angle {
|
||||
ROT_90,
|
||||
ROT_180,
|
||||
ROT_270,
|
||||
ROT_90_SQR,
|
||||
};
|
||||
|
||||
enum rotate_bw {
|
||||
ROT_16B,
|
||||
ROT_32B,
|
||||
};
|
||||
|
||||
struct rotate_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct rotate_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*ioctl)(struct rotate_device *rotate_dev, enum rotate_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
};
|
||||
|
||||
|
||||
|
||||
int32 rotate_set_addr(struct rotate_device *p_rot, uint32_t src, uint32_t des);
|
||||
int32 rotate_set_size(struct rotate_device *p_rot, uint16_t w, uint16_t h);
|
||||
int32 rotate_run(struct rotate_device *p_rot, uint8_t angle, uint8_t bit_width);
|
||||
int32 rotate_get_sta(struct rotate_device *p_rot);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
203
sdk/include/hal/rtc.h
Normal file
203
sdk/include/hal/rtc.h
Normal file
@@ -0,0 +1,203 @@
|
||||
#ifndef _RTC_H
|
||||
#define _RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief RTC week type
|
||||
*/
|
||||
enum rtc_week_type {
|
||||
MONDAY = 1,
|
||||
TUESDAY = 2,
|
||||
WEDNESDAY = 3,
|
||||
THURSDAY = 4,
|
||||
FRIDAY = 5,
|
||||
SATURDAY = 6,
|
||||
SUNDAY = 0,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief RTC time type
|
||||
*/
|
||||
struct rtc_time_type {
|
||||
uint16 year;
|
||||
uint8 month;
|
||||
uint8 date;
|
||||
uint8 week;
|
||||
uint8 hour;
|
||||
uint8 minute;
|
||||
uint8 second;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief RTC ioctl_cmd type
|
||||
*/
|
||||
enum rtc_ioctl_cmd {
|
||||
RES,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief RTC irq_flag type
|
||||
*/
|
||||
enum rtc_irq_flag {
|
||||
|
||||
/*! Compatible version: V0;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
RTC_IRQ_FLAG_SECOND = BIT(0),
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef void (*rtc_irq_hdl)(uint32 irq, uint32 irq_data);
|
||||
|
||||
/* RTC api for user */
|
||||
struct rtc_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct rtc_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
int32(*close)(struct rtc_device *rtc);
|
||||
int32(*set_time)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
int32(*get_time)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
int32(*ioctl)(struct rtc_device *rtc, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct rtc_device *rtc, uint32 irq_flag, rtc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct rtc_device *rtc, uint32 irq_flag);
|
||||
};
|
||||
|
||||
/* RTC API functions */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief rtc_open
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_open(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
|
||||
/**
|
||||
* @brief rtc_close
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_close(struct rtc_device *rtc);
|
||||
|
||||
/**
|
||||
* @brief rtc_set_time
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_set_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
|
||||
/**
|
||||
* @brief rtc_get_time
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_get_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
|
||||
|
||||
/**
|
||||
* @brief rtc_ioctl
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_ioctl(struct rtc_device *rtc, uint32 cmd, uint32 param1, uint32 param2);
|
||||
|
||||
/**
|
||||
* @brief rtc_request_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_request_irq(struct rtc_device *rtc, uint32 irq_flag, rtc_irq_hdl irq_hdl, uint32 irq_data);
|
||||
|
||||
/**
|
||||
* @brief rtc_release_irq
|
||||
*
|
||||
* @Compatible version: V0;
|
||||
*
|
||||
* @note .
|
||||
*
|
||||
* @param rtc The address of rtc device in the RTOS.
|
||||
* @param .
|
||||
* @param .
|
||||
*
|
||||
* @return
|
||||
* - RET_OK Success
|
||||
* - RET_ERR Fail
|
||||
*/
|
||||
int32 rtc_release_irq(struct rtc_device *rtc, uint32 irq_flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
279
sdk/include/hal/scale.h
Normal file
279
sdk/include/hal/scale.h
Normal file
@@ -0,0 +1,279 @@
|
||||
#ifndef HAL_SCALE_H
|
||||
#define HAL_SCALE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*scale_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
enum scale_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_IN_OUT_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_STEP,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_OUT2SRAM_FRAME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_INPUT_STREAM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SRAM_ROTATE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SRAM_MIRROR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_PSRAM_BURST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_START_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_SRAMBUF_WLEN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_IN_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_IN_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_IN_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_OUT_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_OUT_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_OUT_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_LINEBUF_YUV_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_INBUF_YUV_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_LINE_BUF_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_SRAM_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_DMA_TO_MEMORY,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_DATA_FROM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_BOTH_MJPG_H264,
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_INPUT_FORMAT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_INPUT_IS_FRAMEBUF,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_OUTPUT_FORMAT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_GET_INBUF_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_INBUF_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_NEW_FRAME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_SET_END_FRAME,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_GET_HEIGH_CNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_GET_INPUT_WIDTH,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_GET_INPUT_HIGH,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
SCALE_IOCTL_CMD_GET_IS_OPEN,
|
||||
};
|
||||
|
||||
|
||||
struct scale_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct scale_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct scale_device *scale_dev);
|
||||
int32(*suspend)(struct scale_device *scale_dev);
|
||||
int32(*resume)(struct scale_device *scale_dev);
|
||||
int32(*close)(struct scale_device *scale_dev);
|
||||
int32(*ioctl)(struct scale_device *scale_dev, enum scale_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct scale_device *scale_dev, uint32 irq_flag, scale_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct scale_device *scale_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
typedef enum {
|
||||
MJPEG_DEC,
|
||||
H264_DEC,
|
||||
FRAME_YUV420P,
|
||||
FRAME_YUV422P,
|
||||
FRAME_YUV444P,
|
||||
FRAME_RGB888P
|
||||
}SCALE2_FORMAT;
|
||||
|
||||
int32 scale_suspend(struct scale_device *p_scale);
|
||||
int32 scale_resume(struct scale_device *p_scale);
|
||||
int32 scale_open(struct scale_device *p_scale);
|
||||
int32 scale_close(struct scale_device *p_scale);
|
||||
int32 scale_request_irq(struct scale_device *p_scale, uint32 irq_flags, scale_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 scale_release_irq(struct scale_device *p_scale, uint32 irq_flags);
|
||||
int32 scale_set_in_out_size(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h);
|
||||
int32 scale_set_step(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h);
|
||||
int32 scale_set_start_addr(struct scale_device *p_scale, uint32 s_x,uint32 s_y);
|
||||
int32 scale_set_srambuf_wlen(struct scale_device *p_scale, uint32 wlen);
|
||||
int32 scale_set_in_yaddr(struct scale_device *p_scale, uint32 yaddr);
|
||||
int32 scale_set_in_uaddr(struct scale_device *p_scale, uint32 uaddr);
|
||||
int32 scale_set_in_vaddr(struct scale_device *p_scale, uint32 vaddr);
|
||||
int32 scale_set_out_yaddr(struct scale_device *p_scale, uint32 yaddr);
|
||||
int32 scale_set_out_uaddr(struct scale_device *p_scale, uint32 uaddr);
|
||||
int32 scale_set_out_vaddr(struct scale_device *p_scale, uint32 vaddr);
|
||||
int32 scale_set_line_buf_num(struct scale_device *p_scale, uint32 num);
|
||||
int32 scale_set_line_buf_addr(struct scale_device *p_scale, uint32 addr);
|
||||
int32 scale_set_dma_to_memory(struct scale_device *p_scale, uint32 en);
|
||||
int32 scale_set_data_from_vpp(struct scale_device *p_scale, uint32 en);
|
||||
int32 scale_get_inbuf_num(struct scale_device *p_scale);
|
||||
int32 scale_set_inbuf_num(struct scale_device *p_scale,uint32 num,uint32 start_line);
|
||||
int32 scale_set_new_frame(struct scale_device *p_scale,uint8 en);
|
||||
int32 scale_set_end_frame(struct scale_device *p_scale,uint8 en);
|
||||
int32 scale_get_heigh_cnt(struct scale_device *p_scale);
|
||||
int32 scale_set_input_stream(struct scale_device *p_scale,uint8 stream);
|
||||
int32 scale_set_output_sram_or_frame(struct scale_device *p_scale,uint8 out_to_sram);
|
||||
int32 scale_set_rotate_cfg(struct scale_device *p_scale,uint8 rotate);
|
||||
int32 scale_set_mirror(struct scale_device *p_scale,uint8 mirror);
|
||||
int32 scale_set_psram_burst(struct scale_device *p_scale,uint8 pbus);
|
||||
int32 scale_linebuf_yuv_addr(struct scale_device *p_scale, uint32 yadr,uint32 uadr,uint32 vadr);
|
||||
int32 scale_set_input_yuv_addr(struct scale_device *p_scale, uint32 yadr,uint32 uadr,uint32 vadr);
|
||||
int32 scale_set_input_format(struct scale_device *p_scale,uint8 format);
|
||||
int32 scale_is_allframe_or_linebuf(struct scale_device *p_scale,uint8 isframebuf);
|
||||
int32 scale_set_output_format(struct scale_device *p_scale,uint8 format);
|
||||
int32 scale_get_is_open(struct scale_device *p_scale);
|
||||
int32 scale_set_both_mjpg_h264(struct scale_device *p_scale,uint8 en);
|
||||
int32 scale_get_input_width(struct scale_device *p_scale);
|
||||
int32 scale_get_input_high(struct scale_device *p_scale);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
70
sdk/include/hal/sdio_slave.h
Normal file
70
sdk/include/hal/sdio_slave.h
Normal file
@@ -0,0 +1,70 @@
|
||||
#ifndef _HAL_SDIO_SLAVE_H_
|
||||
#define _HAL_SDIO_SLAVE_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum sdio_slave_flags {
|
||||
SDIO_SLAVE_FLAG_4BIT = BIT(0),
|
||||
};
|
||||
|
||||
enum sdio_slave_speed {
|
||||
SDIO_SLAVE_SPEED_1M,
|
||||
SDIO_SLAVE_SPEED_2M,
|
||||
SDIO_SLAVE_SPEED_4M,
|
||||
SDIO_SLAVE_SPEED_8M,
|
||||
SDIO_SLAVE_SPEED_12M,
|
||||
SDIO_SLAVE_SPEED_24M,
|
||||
SDIO_SLAVE_SPEED_48M,
|
||||
|
||||
SDIO_SLAVE_SPEED_NUM,
|
||||
};
|
||||
|
||||
enum sdio_slave_irqs {
|
||||
SDIO_SLAVE_IRQ_RX = BIT(0),
|
||||
SDIO_SLAVE_IRQ_RX_OVERFLOW = BIT(1),
|
||||
SDIO_SLAVE_IRQ_RX_CRC_ERR = BIT(2),
|
||||
SDIO_SLAVE_IRQ_TX_DONE = BIT(3),
|
||||
SDIO_SLAVE_IRQ_TX_ERR = BIT(4),
|
||||
SDIO_SLAVE_IRQ_RESET = BIT(5),
|
||||
};
|
||||
|
||||
enum sdio_slave_ioctl_cmd {
|
||||
SDIO_SLAVE_IO_CMD_RESET,
|
||||
SDIO_SLAVE_IO_CMD_MNTR_RDYSTAT,
|
||||
SDIO_SLAVE_IO_CMD_SET_USER_REG0,
|
||||
SDIO_SLAVE_IO_CMD_SET_USER_REG1,
|
||||
SDIO_SLAVE_IO_CMD_SET_USER_REG2,
|
||||
|
||||
};
|
||||
|
||||
typedef void (*sdio_slave_irq_hdl)(uint32 irq, uint32 param1, uint32 param2, uint32 param3);
|
||||
|
||||
struct sdio_slave {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct sdios_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct sdio_slave *slave, enum sdio_slave_speed speed, uint32 flags);
|
||||
int32(*close)(struct sdio_slave *slave);
|
||||
int32(*ioctl)(struct sdio_slave *slave, int32 cmd, uint32 param);
|
||||
int32(*read)(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
|
||||
int32(*write)(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
|
||||
int32(*write_scatter)(struct sdio_slave *slave, scatter_data *data, uint32 count, int8 sync);
|
||||
int32(*request_irq)(struct sdio_slave *slave, sdio_slave_irq_hdl irqhdl, uint32 data);
|
||||
};
|
||||
|
||||
int32 sdio_slave_open(struct sdio_slave *slave, enum sdio_slave_speed speed, uint32 flags);
|
||||
int32 sdio_slave_close(struct sdio_slave *slave);
|
||||
int32 sdio_slave_write(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
|
||||
int32 sdio_slave_write_scatter(struct sdio_slave *slave, scatter_data *data, uint32 count, int8 sync);
|
||||
int32 sdio_slave_read(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
|
||||
int32 sdio_slave_ioctl(struct sdio_slave *slave, uint32 cmd, uint32 param);
|
||||
int32 sdio_slave_request_irq(struct sdio_slave *slave, sdio_slave_irq_hdl handle, uint32 data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
64
sdk/include/hal/sha.h
Normal file
64
sdk/include/hal/sha.h
Normal file
@@ -0,0 +1,64 @@
|
||||
#ifndef _HAL_SHA_H_
|
||||
#define _HAL_SHA_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct sha_dev {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
enum sha_ioctl_cmd {
|
||||
SHA_IOCTL_CMD_START,
|
||||
SHA_IOCTL_CMD_END,
|
||||
SHA_IOCTL_CMD_RESET,
|
||||
SHA_IOCTL_GET_CTX,
|
||||
SHA_IOCTL_PUT_CTX,
|
||||
SHA_IOCTL_RELOAD_CTX,
|
||||
};
|
||||
|
||||
typedef enum _SHA_TYPE {
|
||||
T_SHA1,
|
||||
T_SHA256,
|
||||
} SHA_TYPE;
|
||||
|
||||
struct sha_ctx {
|
||||
SHA_TYPE type;
|
||||
uint32_t state[8];
|
||||
uint8_t buf[64];
|
||||
uint32_t dlen;
|
||||
unsigned long long bit_len;
|
||||
};
|
||||
|
||||
struct sha_req {
|
||||
SHA_TYPE type;
|
||||
uint32_t *state;
|
||||
uint8_t *input;
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
struct sha_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32 (*init)(struct sha_dev *dev, SHA_TYPE type);
|
||||
int32 (*update)(struct sha_dev *dev, uint8 *input, uint32 len);
|
||||
int32 (*final)(struct sha_dev *dev, uint8 *output);
|
||||
int32 (*xform)(struct sha_dev *dev, struct sha_req *req);
|
||||
int32 (*ioctl)(struct sha_dev *dev, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 (*requset_irq)(struct sha_dev *dev, void *irq_handle, void *args);
|
||||
int32 (*release_irq)(struct sha_dev *dev);
|
||||
};
|
||||
|
||||
int32 sha_ioctl(struct sha_dev *dev, uint32 cmd, uint32 para);
|
||||
int32 sha_init(struct sha_dev *dev, SHA_TYPE type);
|
||||
int32 sha_update(struct sha_dev *dev, uint8 *input, uint32 len);
|
||||
int32 sha_final(struct sha_dev *dev, uint8 *output);
|
||||
int32 sha_xform(struct sha_dev *dev, struct sha_req *req);
|
||||
int32 sha_requset_irq(struct sha_dev *dev, void *irq_handle, void *args);
|
||||
int32 sha_release_irq(struct sha_dev *dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
351
sdk/include/hal/spi.h
Normal file
351
sdk/include/hal/spi.h
Normal file
@@ -0,0 +1,351 @@
|
||||
#ifndef _HAL_SPI_H_
|
||||
#define _HAL_SPI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief spi working mode type
|
||||
*/
|
||||
enum spi_work_mode {
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* The host mode of SPI
|
||||
*/
|
||||
SPI_MASTER_MODE,
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* The slave mode of SPI
|
||||
*/
|
||||
SPI_SLAVE_MODE,
|
||||
|
||||
/*! Compatible version: V1
|
||||
*@Describe:
|
||||
* The slave FSM mode of SPI0, only for spi0
|
||||
*/
|
||||
SPI_SLAVE_FSM_MODE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi wire mode
|
||||
*/
|
||||
enum spi_wire_mode {
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* The wire_single_mode of SPI, contain: CLK; CS; IO0
|
||||
* A CLK transmits 1bit of data
|
||||
*/
|
||||
SPI_WIRE_SINGLE_MODE,
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1
|
||||
* A CLK transmits 1bit of data
|
||||
*/
|
||||
SPI_WIRE_NORMAL_MODE,
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1
|
||||
* A CLK transmits 2bit of data
|
||||
*/
|
||||
SPI_WIRE_DUAL_MODE,
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1; IO2; IO3
|
||||
* A CLK transmits 4bit of data
|
||||
*/
|
||||
SPI_WIRE_QUAD_MODE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi clock mode
|
||||
*/
|
||||
enum spi_clk_mode {
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Inactive state of serial clock is low, serial clock toggles in middle of first data bit
|
||||
*/
|
||||
SPI_CPOL_0_CPHA_0 = 0,
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Inactive state of serial clock is low, serial clock toggles at start of first data bit
|
||||
*/
|
||||
SPI_CPOL_0_CPHA_1 = 1,
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Inactive state of serial clock is high, serial clock toggles in middle of first data bit
|
||||
*/
|
||||
SPI_CPOL_1_CPHA_0 = 2,
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Inactive state of serial clock is high, serial clock toggles at start of first data bit
|
||||
*/
|
||||
SPI_CPOL_1_CPHA_1 = 3,
|
||||
|
||||
SPI_CLK_MODE_0 = SPI_CPOL_0_CPHA_0, /*!< Equal to \ref SPI_CPOL_0_CPHA_0 */
|
||||
SPI_CLK_MODE_1 = SPI_CPOL_0_CPHA_1, /*!< Equal to \ref SPI_CPOL_0_CPHA_1 */
|
||||
SPI_CLK_MODE_2 = SPI_CPOL_1_CPHA_0, /*!< Equal to \ref SPI_CPOL_1_CPHA_0 */
|
||||
SPI_CLK_MODE_3 = SPI_CPOL_1_CPHA_1 /*!< Equal to \ref SPI_CPOL_1_CPHA_1 */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi ioctl cmd
|
||||
*
|
||||
*/
|
||||
enum spi_ioctl_cmd {
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* SPI line mode setting
|
||||
*/
|
||||
SPI_WIRE_MODE_SET,
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* Get SPI line mode current setting
|
||||
*/
|
||||
SPI_WIRE_MODE_GET,
|
||||
|
||||
/*! Compatible version: V1
|
||||
*@Describe:
|
||||
* SPI host sampling delay
|
||||
*/
|
||||
SPI_SAMPLE_DELAY,
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* Set SPI frame size
|
||||
*/
|
||||
SPI_SET_FRAME_SIZE,
|
||||
|
||||
/*! Compatible version: V1
|
||||
*@Describe:
|
||||
* Sets the length threshold for using DMA, unit: byte
|
||||
*/
|
||||
SPI_SET_LEN_THRESHOLD,
|
||||
|
||||
/*! Set SPI CS value.
|
||||
*/
|
||||
SPI_SET_CS,
|
||||
|
||||
/*! Set SPI uses none cs pin.
|
||||
*/
|
||||
SPI_CFG_SET_NONE_CS,
|
||||
|
||||
/*! Read DMA RX cnt.
|
||||
*/
|
||||
SPI_READ_DMA_RX_CNT,
|
||||
|
||||
/*! Kick SPI dma rx.
|
||||
*/
|
||||
SPI_KICK_DMA_RX,
|
||||
|
||||
/*! Kick SPI dma tx.
|
||||
*/
|
||||
SPI_KICK_DMA_TX,
|
||||
|
||||
/*! set SPI write/read timeout.
|
||||
*/
|
||||
SPI_SET_TIMEOUT,
|
||||
|
||||
/*! set SPI LSB/MSB first.
|
||||
*/
|
||||
SPI_SET_LSB_FIRST,
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_SET_ADR,
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_ERASE_4KB,
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_ERASE_64KB,
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_ERASE_SECURITY_REG,
|
||||
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_PROGRAM_SECURITY_REG,
|
||||
|
||||
|
||||
/*!
|
||||
* Only for XIP
|
||||
*/
|
||||
SPI_XIP_READ_SECURITY_REG,
|
||||
|
||||
|
||||
SPI_SET_SLAVE_SW_RESERVED,
|
||||
|
||||
/*
|
||||
* spi sensor
|
||||
*/
|
||||
SPI_SENSOR_VSYNC_TIMEOUT,
|
||||
|
||||
SPI_SENSOR_VSYNC_HEAD_CNT,
|
||||
|
||||
SPI_SENSOR_VSYNC_EN,
|
||||
|
||||
SPI_SENSOR_HSYNC_TIMEOUT,
|
||||
|
||||
SPI_SENSOR_HSYNC_HEAD_CNT,
|
||||
|
||||
SPI_SENSOR_BUF_LEN,
|
||||
|
||||
SPI_SENSOR_SET_ADR0,
|
||||
|
||||
SPI_SENSOR_SET_ADR1,
|
||||
|
||||
SPI_SENSOR_PINGPANG_EN,
|
||||
|
||||
SPI_HIGH_SPEED_CFG,
|
||||
|
||||
SPI_KICK_DMA_EN,
|
||||
|
||||
SPI_RX_TIMEOUT_CFG,
|
||||
|
||||
SPI_SENSOR_LINE_LEN_CFG,
|
||||
|
||||
//新增加命令都往后添加
|
||||
SPI_XIP_CUSTOM_READ_CMD,
|
||||
SPI_XIP_CUSTOM_WRITE_CMD,
|
||||
SPI_XIP_CUSTOM_ERASE_CMD,
|
||||
|
||||
SPI_GET_DMA_PENDING,
|
||||
|
||||
SPI_CLEAR_DMA_PENDING,
|
||||
SPI_XIP_CUSTOM_WP_RANGE_CMD,
|
||||
SPI_XIP_CUSTOM_WP_EN_CMD,
|
||||
SPI_XIP_CUSTOM_DIS_ENCRY_RANGE0,
|
||||
SPI_XIP_CUSTOM_DIS_ENCRY_RANGE1,
|
||||
SPI_XIP_CUSTOM_SET_REMAP, //配置reamp地址,SPI_XIP_CUSTOM_SET_ENCRYPT要配置1才能生效
|
||||
SPI_XIP_CUSTOM_SET_ENCRYPT, //配置是否要强行加密
|
||||
SPI_XIP_CUSTOM_CFG_RUN_OFFSET,
|
||||
SPI_XIP_CUSTOM_CFG_ENCRYPT,
|
||||
SPI_XIP_GET_SPI_ADDR, //传入flash绝对地址,返回代码相对地址(比如传入0,返回0x18000000,如果返回0,就是错误的意思,remap一定要比绝对地址小)
|
||||
|
||||
SPI_XIP_REG_OPT,
|
||||
|
||||
SPI_XIP_DMA_LOCK,
|
||||
SPI_XIP_DMA_UNLOCK,
|
||||
|
||||
SPI_XIP_WIP_SUSPEND,
|
||||
SPI_XIP_WIP_RESUME,
|
||||
SPI_XIP_WIP_SYNC,
|
||||
|
||||
SPI_XIP_DTR_INIT,
|
||||
SPI_XIP_DTR_EN,
|
||||
|
||||
SPI_XIP_REGS_OPT,
|
||||
|
||||
SPI_XIP_LOCK,
|
||||
SPI_XIP_UNLOCK,
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
enum xip_opcode_cmd {
|
||||
XIP_READ,
|
||||
XIP_WRITE,
|
||||
XIP_ERASE,
|
||||
XIP_SECURITY_ERASE,
|
||||
XIP_SECURITY_WRITE,
|
||||
XIP_SECURITY_READ,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief spi interrupt
|
||||
*
|
||||
*/
|
||||
|
||||
enum spi_irq_flag {
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Transmits the currently configured length of tx data done
|
||||
*/
|
||||
SPI_IRQ_FLAG_TX_DONE = BIT(0),
|
||||
|
||||
/*! Compatible version: V0; V1; V2
|
||||
*@Describe:
|
||||
* Transmits the currently configured length of rx data done
|
||||
*/
|
||||
SPI_IRQ_FLAG_RX_DONE = BIT(1),
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* The received buffer is full, max: 40bit
|
||||
*/
|
||||
SPI_IRQ_FLAG_FIFO_OVERFLOW = BIT(2),
|
||||
|
||||
/*! Compatible version: V0; V1
|
||||
*@Describe:
|
||||
* Dectect the CS rising
|
||||
*/
|
||||
SPI_IRQ_FLAG_CS_RISING = BIT(3),
|
||||
|
||||
SPI_IRQ_FLAG_SLAVE_FSM_READ_STATUS = BIT(4),
|
||||
|
||||
SPI_IRQ_FLAG_SLAVE_FSM_WRONG_CMD = BIT(5),
|
||||
|
||||
SPI_IRQ_FLAG_RX_TIMEOUT = BIT(6),
|
||||
|
||||
SPI_IRQ_FLAG_RESET = BIT(7),
|
||||
};
|
||||
|
||||
|
||||
typedef void (*spi_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
|
||||
struct spi_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct spi_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct spi_device *p_spi, uint32 clk_freq, uint32 work_mode, uint32 wire_mode, uint32 clk_mode);
|
||||
int32(*close)(struct spi_device *p_spi);
|
||||
int32(*ioctl)(struct spi_device *p_spi, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*read)(struct spi_device *p_spi, void *buf, uint32 size);
|
||||
int32(*write)(struct spi_device *p_spi, const void *buf, uint32 size);
|
||||
int32(*write_scatter)(struct spi_device *p_spi, const scatter_data *data, uint32 count);
|
||||
int32(*request_irq)(struct spi_device *p_spi, uint32 irq_flag, spi_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct spi_device *spi, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 spi_open(struct spi_device *p_spi, uint32 clk_freq, uint32 work_mode, uint32 wire_mode, uint32 clk_mode);
|
||||
int32 spi_close(struct spi_device *p_spi);
|
||||
int32 spi_ioctl(struct spi_device *p_spi, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 spi_read(struct spi_device *p_spi, void *buf, uint32 size);
|
||||
int32 spi_write(struct spi_device *p_spi, const void *buf, uint32 size);
|
||||
int32 spi_write_scatter(struct spi_device *p_spi, const scatter_data *data, uint32 count);
|
||||
int32 spi_set_cs(struct spi_device *p_spi, uint32 cs, uint32 value);
|
||||
int32 spi_request_irq(struct spi_device *p_spi, uint32 irq_flag, spi_irq_hdl irqhdl, uint32 irq_data);
|
||||
int32 spi_release_irq(struct spi_device *spi, uint32 irq_flag);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
153
sdk/include/hal/spi_nor.h
Normal file
153
sdk/include/hal/spi_nor.h
Normal file
@@ -0,0 +1,153 @@
|
||||
#ifndef _HAL_SPI_NOR_H_
|
||||
#define _HAL_SPI_NOR_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "osal/mutex.h"
|
||||
#include "osal/atomic.h"
|
||||
|
||||
|
||||
/**
|
||||
* @brief spi nor mode
|
||||
*/
|
||||
enum spi_nor_mode {
|
||||
SPI_NOR_NORMAL_SPI_MODE,
|
||||
SPI_NOR_DUAL_SPI_MODE,
|
||||
SPI_NOR_QUAD_SPI_MODE,
|
||||
SPI_NOR_QPI_MODE,
|
||||
SPI_NOR_XIP_MODE,
|
||||
};
|
||||
|
||||
struct spi_nor_flash;
|
||||
|
||||
enum spi_nor_cmd {
|
||||
SPI_NOR_CMD_READ_JEDEC_ID,
|
||||
SPI_NOR_CMD_POWER_DOWN,
|
||||
SPI_NOR_CMD_POWER_UP,
|
||||
|
||||
SPI_NOR_CMD_COSTUM_ERASE,
|
||||
SPI_NOR_CMD_COSTUM_READ,
|
||||
SPI_NOR_CMD_COSTUM_WRITE,
|
||||
|
||||
SPI_NOR_CMD_SEC_ERASE,
|
||||
SPI_NOR_CMD_SEC_PROGRAM,
|
||||
SPI_NOR_CMD_SEC_READ,
|
||||
|
||||
SPI_NOR_CMD_SUSPEND,
|
||||
SPI_NOR_CMD_RESUME,
|
||||
|
||||
SPI_NOR_CMD_4B_ADDR,
|
||||
};
|
||||
|
||||
enum spi_nor_erase_mode {
|
||||
SPI_NOR_ERASE_SECTOR,
|
||||
SPI_NOR_ERASE_BLOCK,
|
||||
SPI_NOR_ERASE_CHIP,
|
||||
};
|
||||
|
||||
struct spi_nor_bus {
|
||||
void (*open)(struct spi_nor_flash *flash);
|
||||
void (*close)(struct spi_nor_flash *flash);
|
||||
void (*erase)(struct spi_nor_flash *flash, uint32 mode, uint32 addr);
|
||||
void (*read)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
|
||||
void (*program)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
|
||||
int32(*ioctl)(struct spi_nor_flash *flash, uint32_t cmd, uint32_t param1, uint32_t param2);
|
||||
};
|
||||
|
||||
struct spi_nor_regval {
|
||||
uint8 *buff;
|
||||
uint32 size;
|
||||
};
|
||||
|
||||
struct bpreg_cfg {
|
||||
uint8_t srx : 2,
|
||||
len : 3,
|
||||
idx : 3;
|
||||
uint8_t val;
|
||||
uint8_t mask;
|
||||
};
|
||||
|
||||
struct bp_area {
|
||||
uint8_t bpv:4,
|
||||
sec:1,
|
||||
tb :1,
|
||||
rev:2;
|
||||
uint32_t area[2];
|
||||
};
|
||||
|
||||
struct bp_info {
|
||||
uint32_t area_cnt : 9,
|
||||
disable_cmp : 1,
|
||||
tb_shift : 5,
|
||||
cmp_shift : 5,
|
||||
pre_cmd : 8,
|
||||
rev : 4;
|
||||
struct bp_area *areas;
|
||||
};
|
||||
|
||||
struct spi_nor_flash {
|
||||
struct dev_obj dev;
|
||||
os_mutex_t lock;
|
||||
atomic_t ref;
|
||||
enum spi_nor_mode mode;
|
||||
uint32 size, sector_size, page_size, block_size;
|
||||
uint32 bp_partition_size; //块保护分区大小
|
||||
uint32 vendor_id, product_id;
|
||||
const struct spi_nor_bus *bus;
|
||||
struct spi_device *spidev;
|
||||
struct {
|
||||
uint32 clk, clk_mode, wire_mode, cs;
|
||||
} spi_config;
|
||||
struct bpreg_cfg bpbk[4];
|
||||
struct bp_info *bpi;
|
||||
int (*bp_conv) (
|
||||
struct spi_nor_flash *flash,
|
||||
uint32_t addrl, uint32_t addru,
|
||||
struct bpreg_cfg *bp
|
||||
);
|
||||
uint8_t bits_of_addr;
|
||||
};
|
||||
|
||||
const struct spi_nor_bus *spi_nor_bus_get(enum spi_nor_mode mode);
|
||||
|
||||
int32 spi_nor_open(struct spi_nor_flash *flash);
|
||||
|
||||
void spi_nor_close(struct spi_nor_flash *flash);
|
||||
|
||||
void spi_nor_read(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 len);
|
||||
|
||||
void spi_nor_write(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 len);
|
||||
|
||||
void spi_nor_sector_erase(struct spi_nor_flash *flash, uint32 sector_addr);
|
||||
|
||||
void spi_nor_block_erase(struct spi_nor_flash *flash, uint32 block_addr);
|
||||
|
||||
void spi_nor_chip_erase(struct spi_nor_flash *flash);
|
||||
|
||||
void spi_nor_sec_erase(struct spi_nor_flash *flash, uint32 addr);
|
||||
|
||||
void spi_nor_sec_program(struct spi_nor_flash *flash, uint32 addr, struct spi_nor_regval *values);
|
||||
|
||||
void spi_nor_sec_read(struct spi_nor_flash *flash, uint32 addr, struct spi_nor_regval *values);
|
||||
|
||||
void spi_nor_custom_read(struct spi_nor_flash *flash, void *param);
|
||||
|
||||
void spi_nor_custom_write(struct spi_nor_flash *flash, void *param);
|
||||
|
||||
void spi_nor_custom_erase(struct spi_nor_flash *flash, void *param);
|
||||
|
||||
void spi_nor_power_down(struct spi_nor_flash *flash);
|
||||
|
||||
void spi_nor_power_up(struct spi_nor_flash *flash);
|
||||
|
||||
void spi_nor_read_jedec_id(struct spi_nor_flash *flash, uint8 *buff);
|
||||
|
||||
int32 spi_nor_attach(struct spi_nor_flash *flash, uint32 dev_id);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
59
sdk/include/hal/sysaes.h
Normal file
59
sdk/include/hal/sysaes.h
Normal file
@@ -0,0 +1,59 @@
|
||||
#ifndef _HAL_SYSAES_H_
|
||||
#define _HAL_SYSAES_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*----- AES Control Codes: Mode Parameters: Key length -----*/
|
||||
|
||||
|
||||
|
||||
enum SYSAES_KEY_LEN {
|
||||
AES_KEY_LEN_BIT_128,
|
||||
AES_KEY_LEN_BIT_192,
|
||||
AES_KEY_LEN_BIT_256,
|
||||
};
|
||||
|
||||
|
||||
enum SYSAES_MODE {
|
||||
AES_MODE_ECB,
|
||||
AES_MODE_CBC,
|
||||
AES_MODE_CTR,
|
||||
// AES_MODE_CFB1,
|
||||
// AES_MODE_CFB8,
|
||||
// AES_MODE_CFB128,
|
||||
// AES_MODE_OFB,
|
||||
// AES_MODE_CTR,
|
||||
};
|
||||
|
||||
#define AES_BLOCK_SIZE 16
|
||||
|
||||
struct sysaes_para {
|
||||
uint8 mode; /* enum SYSAES_MODE */
|
||||
uint8 key_len; /* enum SYSAES_KEY_LEN */
|
||||
uint8 *src;
|
||||
uint8 *dest;
|
||||
uint32 aes_len; /* v1-v2 blocks, v3 bytes */
|
||||
uint8 key[32];
|
||||
uint8 *iv; /* AES_BLOCK_SIZE : 16 */
|
||||
};
|
||||
|
||||
struct sysaes_dev {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct aes_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*encrypt)(struct sysaes_dev *dev, struct sysaes_para *para);
|
||||
int32(*decrypt)(struct sysaes_dev *dev, struct sysaes_para *para);
|
||||
};
|
||||
|
||||
int32 sysaes_encrypt(struct sysaes_dev *dev, struct sysaes_para *para);
|
||||
int32 sysaes_decrypt(struct sysaes_dev *dev, struct sysaes_para *para);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _HAL_SYSAES_H_ */
|
||||
|
||||
88
sdk/include/hal/timer_device.h
Normal file
88
sdk/include/hal/timer_device.h
Normal file
@@ -0,0 +1,88 @@
|
||||
#ifndef _HAL_TIMER_DEVICE_H_
|
||||
#define _HAL_TIMER_DEVICE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief timer type
|
||||
*/
|
||||
enum timer_type {
|
||||
TIMER_TYPE_ONCE,
|
||||
|
||||
TIMER_TYPE_PERIODIC,
|
||||
};
|
||||
|
||||
enum timer_ioctl_cmd {
|
||||
TIMER_GET_TIMESTAMP,
|
||||
|
||||
TIMER_CALC_TIME_DIFF_US,
|
||||
|
||||
/*
|
||||
* configure the prescaler of clk
|
||||
*/
|
||||
TIMER_SET_CLK_PSC,
|
||||
|
||||
/*
|
||||
* configure type the slave mode
|
||||
*/
|
||||
TIMER_SET_SLAVE_MODE,
|
||||
|
||||
TIMER_SET_PERIOD,
|
||||
|
||||
TIMER_SET_CLK_SRC,
|
||||
};
|
||||
|
||||
enum timer_irq_flag {
|
||||
/*!
|
||||
* @brief Interrupt: Timer timeout intterupt.
|
||||
* @note
|
||||
*
|
||||
*/
|
||||
TIMER_IRQ_FLAG_TIMEOUT = BIT(0),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: Timer receives has been reset.
|
||||
* @note
|
||||
* Possible need to reset parameters.
|
||||
*/
|
||||
TIMER_IRQ_FLAG_RESET = BIT(1),
|
||||
};
|
||||
|
||||
typedef void (*timer_irq_hdl)(uint32 irq_data, uint32 irq_flag);
|
||||
|
||||
struct timer_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct timer_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct timer_device *timer, enum timer_type type, uint32 flags);
|
||||
int32(*close)(struct timer_device *timer);
|
||||
int32(*start)(struct timer_device *timer, uint32 tmo_us, timer_irq_hdl hdl, uint32 data);
|
||||
int32(*stop)(struct timer_device *timer);
|
||||
int32(*suspend)(struct timer_device *timer);
|
||||
int32(*resume)(struct timer_device *timer);
|
||||
int32(*ioctl)(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct timer_device *timer, uint32 irq_flag, timer_irq_hdl hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct timer_device *timer, uint32 irq_flag);
|
||||
};
|
||||
|
||||
int32 timer_device_open(struct timer_device *timer, enum timer_type mode, uint32 flags);
|
||||
int32 timer_device_close(struct timer_device *timer);
|
||||
int32 timer_device_start(struct timer_device *timer, uint32 period_sysclkpd_cnt, timer_irq_hdl hdl, uint32 irq_data);
|
||||
int32 timer_device_stop(struct timer_device *timer);
|
||||
int32 timer_device_suspend(struct timer_device *timer);
|
||||
int32 timer_device_resume(struct timer_device *timer);
|
||||
int32 timer_device_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32 timer_request_irq(struct timer_device *timer, uint32 irq_flag, timer_irq_hdl hdl, uint32 irq_data);
|
||||
int32 timer_release_irq(struct timer_device *timer, uint32 irq_flag);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
88
sdk/include/hal/tk.h
Normal file
88
sdk/include/hal/tk.h
Normal file
@@ -0,0 +1,88 @@
|
||||
#ifndef _HAL_TK_H_
|
||||
#define _HAL_TK_H_
|
||||
#include "typesdef.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum touchkey_ioctl_cmd
|
||||
{
|
||||
TK_IOCTL_CMD_NONE = 0,
|
||||
};
|
||||
|
||||
enum touchkey_irq_flag
|
||||
{
|
||||
TK_IRQ_FLAG_GET_KEY_VALUE = BIT(0),
|
||||
};
|
||||
|
||||
enum touchkey_key_num
|
||||
{
|
||||
TK_KEY_TYPE_LONG = BIT(26),
|
||||
TK_KEY_TYPE_NONE = BIT(27),
|
||||
};
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32 (*tk_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2, uint32 param3);
|
||||
|
||||
struct hgtk_param
|
||||
{
|
||||
unsigned char __tk_index ;
|
||||
unsigned char __tk_cs_en ;
|
||||
unsigned char __tk_use_num ;
|
||||
unsigned char __tk_long_key ;
|
||||
unsigned char __tk_adjust_en ;
|
||||
unsigned char param [14] ;
|
||||
unsigned char config[17] ;
|
||||
volatile unsigned char __time_base_cnt ;
|
||||
volatile unsigned char __tk_ch_cnt_0[6];
|
||||
volatile unsigned char __tk_ch_cnt_1[6];
|
||||
volatile unsigned char __tk_ch_cnt_2[6];
|
||||
volatile unsigned char __tk_ch_cnt_3[6];
|
||||
volatile unsigned char __tk_ch_cnt_4[6];
|
||||
volatile unsigned char __tk_ch_cnt_5[6];
|
||||
volatile unsigned char __tk_ch_cnt_6[6];
|
||||
volatile unsigned char __tk_ch_cnt_7[6];
|
||||
volatile unsigned char __tk_ch_index[6];
|
||||
|
||||
unsigned short __tk_adjust_time ;
|
||||
unsigned short __tk_adjust_diff_valu ;
|
||||
unsigned short __tk_valid_time ;
|
||||
unsigned short __tk_long_key_time ;
|
||||
unsigned short __tk_noise_value ;
|
||||
volatile unsigned short __tk_i_set[6] ;
|
||||
volatile unsigned short __tk_ch_fth[6] ;
|
||||
volatile unsigned short __tk_ch_data_0[6] ;
|
||||
volatile unsigned short __tk_ch_data_1[6] ;
|
||||
volatile unsigned short __tk_ch_data_2[6] ;
|
||||
volatile unsigned short __tk_ch_data_3[6] ;
|
||||
volatile unsigned short __tk_ch_data_4[6] ;
|
||||
volatile unsigned short __tk_ch_data_5[6] ;
|
||||
volatile unsigned short __tk_ch_data_6[6] ;
|
||||
volatile unsigned short __tk_ch_data_7[6] ;
|
||||
volatile unsigned short __tk_ch_data_8[6] ;
|
||||
unsigned long __tk_adjust_line ;
|
||||
};
|
||||
|
||||
struct tk_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct tk_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open) (struct tk_device *tk);
|
||||
int32(*close) (struct tk_device *tk);
|
||||
int32(*ioctl) (struct tk_device *tk, enum touchkey_ioctl_cmd ioctl_cmd, uint32 param);
|
||||
int32(*request_irq)(struct tk_device *tk, tk_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
|
||||
int32(*release_irq)(struct tk_device *tk, enum touchkey_irq_flag irq_flag);
|
||||
};
|
||||
|
||||
int32 tk_open(struct tk_device *tk);
|
||||
int32 tk_ioctl(struct tk_device *tk, enum touchkey_ioctl_cmd ioctl_cmd, uint32 param);
|
||||
int32 tk_irq_request(struct tk_device *tk, tk_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
|
||||
int32 tk_irq_release(struct tk_device *tk, uint32 irq_flag);
|
||||
int32 tk_close(struct tk_device *tk);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
321
sdk/include/hal/uart.h
Normal file
321
sdk/include/hal/uart.h
Normal file
@@ -0,0 +1,321 @@
|
||||
/**
|
||||
* @file uart.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @brief UART HAL driver
|
||||
* @version 1.0.0
|
||||
* @date 2021-8-30
|
||||
*
|
||||
* @copyright Copyright (c) 2021 HUGE-IC
|
||||
*/
|
||||
#ifndef _HAL_UART_H_
|
||||
#define _HAL_UART_H_
|
||||
#include "typesdef.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup Docxygenid_UART_enum UART enum
|
||||
* @ingroup Docxygenid_UART_Driver
|
||||
* @brief UART enumeration description.
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART mode.
|
||||
*/
|
||||
enum uart_mode {
|
||||
|
||||
/*! Set UART to full duplex mode.
|
||||
*/
|
||||
UART_MODE_DUPLEX,
|
||||
|
||||
/*! Set UART to simplex_tx mode.
|
||||
*/
|
||||
UART_MODE_SIMPLEX_TX,
|
||||
|
||||
/*! Set UART to simplex_rx mode.
|
||||
*/
|
||||
UART_MODE_SIMPLEX_RX,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART parity.
|
||||
*/
|
||||
enum uart_parity {
|
||||
|
||||
/*! Set UART to no parity mode.
|
||||
*/
|
||||
UART_PARITY_NONE,
|
||||
|
||||
/*! Set UART to odd parity mode.
|
||||
*/
|
||||
UART_PARITY_ODD,
|
||||
|
||||
/*! Set UART to even parity mode.
|
||||
*/
|
||||
UART_PARITY_EVEN,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART stop bit.
|
||||
*/
|
||||
enum uart_stop_bit {
|
||||
|
||||
/*! Set UART stop bit to 1bit.
|
||||
*/
|
||||
UART_STOP_BIT_1,
|
||||
|
||||
/*! Set UART stop bit to 1.5bit.
|
||||
*/
|
||||
UART_STOP_BIT_1_5,
|
||||
|
||||
/*! Set UART stop bit to 2bit.
|
||||
*/
|
||||
UART_STOP_BIT_2,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART data bit.
|
||||
*/
|
||||
enum uart_data_bit {
|
||||
|
||||
/*! Set UART data bit to 5bit.
|
||||
*/
|
||||
UART_DATA_BIT_5,
|
||||
|
||||
/*! Set UART data bit to 6bit.
|
||||
*/
|
||||
UART_DATA_BIT_6,
|
||||
|
||||
/*! Set UART data bit to 7bit.
|
||||
*/
|
||||
UART_DATA_BIT_7,
|
||||
|
||||
/*! Set UART data bit to 8bit.
|
||||
*/
|
||||
UART_DATA_BIT_8,
|
||||
|
||||
/*! Set UART data bit to 9bit.
|
||||
*/
|
||||
UART_DATA_BIT_9,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART irq flag.
|
||||
*/
|
||||
enum uart_irq_flag {
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: send a frame of data done.
|
||||
* @note
|
||||
* If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
|
||||
* if the data bit is 9bit, one frame of data is 9bit.
|
||||
*/
|
||||
UART_IRQ_FLAG_TX_BYTE = BIT(0),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: time is up, no data has been received yet.
|
||||
* @note
|
||||
* This interrupt is only used for UART receive.
|
||||
*/
|
||||
UART_IRQ_FLAG_TIME_OUT = BIT(1),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: UART send done using DMA.
|
||||
* @note
|
||||
* Before configuring this interrupt,\n
|
||||
* you need to use @ref uart_ioctl() function to enable DMA.
|
||||
*/
|
||||
UART_IRQ_FLAG_DMA_TX_DONE = BIT(2),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: UART receive done using DMA.
|
||||
* @note
|
||||
* Before configuring this interrupt,\n
|
||||
* you need to use @ref uart_ioctl() function to enable DMA.
|
||||
*/
|
||||
UART_IRQ_FLAG_DMA_RX_DONE = BIT(3),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: UART receives a frame of data error.
|
||||
* @note
|
||||
* - If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
|
||||
* if the data bit is 9bit, one frame of data is 9bit.
|
||||
* - A frame of data error, usually means that the number of stop bits of \n
|
||||
* a frame of data does not match the expected number of bits.
|
||||
*/
|
||||
UART_IRQ_FLAG_FRAME_ERR = BIT(4),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: UART receives a frame of data done.
|
||||
* @note
|
||||
* If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
|
||||
* if the data bit is 9bit, one frame of data is 9bit.
|
||||
*/
|
||||
UART_IRQ_FLAG_RX_BYTE = BIT(5),
|
||||
|
||||
/*!
|
||||
* @brief Interrupt: UART receives has been reset.
|
||||
* @note
|
||||
* Possible need to reset parameters or resend data.
|
||||
*/
|
||||
UART_IRQ_FLAG_RESET = BIT(6),
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for UART irq flag
|
||||
*/
|
||||
enum uart_ioctl_cmd {
|
||||
|
||||
/*!
|
||||
* @brief Set the baudrate of the UART.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_BAUDRATE,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART data bits.
|
||||
* @note
|
||||
* reference @ref uart_data_bit.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_DATA_BIT,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART parity mode.
|
||||
* @note
|
||||
* reference @ref uart_parity.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_PARITY,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART stop bit.
|
||||
* @note
|
||||
* reference @ref uart_stop_bit.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_STOP_BIT,
|
||||
|
||||
/*!
|
||||
* @brief Set the timeout.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_TIME_OUT,
|
||||
|
||||
/*!
|
||||
* @brief Set whether the UART uses DMA to send.
|
||||
*/
|
||||
UART_IOCTL_CMD_USE_DMA,
|
||||
|
||||
/*!
|
||||
* @brief Set UART work mode.
|
||||
* @note
|
||||
* reference @ref uart_mode.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_WORK_MODE,
|
||||
|
||||
/*!
|
||||
* @brief Query whether the UART DATA reg ready.
|
||||
*/
|
||||
UART_IOCTL_CMD_DATA_RDY,
|
||||
|
||||
/*!
|
||||
* @brief
|
||||
* Disable this uart tx by cpu, and turn to use dma.
|
||||
* @note
|
||||
* Only use for UART4/5.
|
||||
*/
|
||||
UART_IOCTL_CMD_DISABLE_DEBUG_SELECTION,
|
||||
|
||||
/*!
|
||||
* @brief Enable the UART rs485 mode.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_RS485_EN,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART rs485 DET.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_RS485_DET,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART rs485 TAT.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_RS485_TAT,
|
||||
|
||||
/*!
|
||||
* @brief Set the UART rs485 DE and RE polarity.
|
||||
*/
|
||||
UART_IOCTL_CMD_SET_RS485DRE_POL,
|
||||
};
|
||||
|
||||
|
||||
/** @} Docxygenid_UART_enum*/
|
||||
|
||||
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*uart_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
|
||||
|
||||
|
||||
/** @defgroup Docxygenid_UART_structure UART structure
|
||||
* @ingroup Docxygenid_UART_Driver
|
||||
* @brief UART structure description
|
||||
* @note
|
||||
* User better not modify the structure.
|
||||
* @{
|
||||
*/
|
||||
|
||||
struct uart_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct uart_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct uart_device *uart, uint32 baudrate);
|
||||
int32(*close)(struct uart_device *uart);
|
||||
int32(*putc)(struct uart_device *uart, int8 value);
|
||||
uint8(*getc)(struct uart_device *uart);
|
||||
int32(*puts)(struct uart_device *uart, uint8 *buf, uint32 len);
|
||||
int32(*gets)(struct uart_device *uart, uint8 *buf, uint32 len);
|
||||
int32(*ioctl)(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct uart_device *uart, uart_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
|
||||
int32(*release_irq)(struct uart_device *uart, uint32 irq_flag);
|
||||
};
|
||||
|
||||
/** @} Docxygenid_UART_structure*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Docxygenid_UART_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Open uart with baudrate and the default configuration.
|
||||
* @param uart : UART handle. Usually use @ref dev_get() function to get the handle.
|
||||
* @param baudrate : Configure the baudrate for UART.
|
||||
* @return
|
||||
* - RET_OK : UART module open successfully.
|
||||
* - RET_ERR : UART module open unsuccessfully.
|
||||
* @note
|
||||
* The default configuration is full duplex mode, no parity mode,\n
|
||||
* data bit is 8bit, stop bit is 1bit.If you need to change the configuration,\n
|
||||
* you can use the @ref uart_ioctl function to make changes after initialization is complete.
|
||||
*/
|
||||
int32 uart_open(struct uart_device *uart, uint32 baudrate);
|
||||
int32 uart_close(struct uart_device *uart);
|
||||
int32 uart_putc(struct uart_device *uart, int8 value);
|
||||
uint8 uart_getc(struct uart_device *uart);
|
||||
int32 uart_puts(struct uart_device *uart, uint8 *buf, uint32 len);
|
||||
int32 uart_gets(struct uart_device *uart, uint8 *buf, uint32 len);
|
||||
int32 uart_ioctl(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32 uart_request_irq(struct uart_device *uart, uart_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
|
||||
int32 uart_release_irq(struct uart_device *uart, uint32 irq_flag);
|
||||
|
||||
/** @} Docxygenid_UART_functions*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
1034
sdk/include/hal/usb_ch9.h
Normal file
1034
sdk/include/hal/usb_ch9.h
Normal file
File diff suppressed because it is too large
Load Diff
138
sdk/include/hal/usb_device.h
Normal file
138
sdk/include/hal/usb_device.h
Normal file
@@ -0,0 +1,138 @@
|
||||
#ifndef _HAL_USB_DEVICE_H_
|
||||
#define _HAL_USB_DEVICE_H_
|
||||
|
||||
#include "usb_ch9.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BULK_EP 1
|
||||
#define WIFI_EP 1
|
||||
#define ISO_EP 2
|
||||
#define HID_EP 2
|
||||
|
||||
|
||||
enum usb_dev_irqs {
|
||||
USB_DEV_RESET_IRQ,
|
||||
USB_DEV_SUSPEND_IRQ,
|
||||
USB_DEV_RESUME_IRQ,
|
||||
USB_DEV_SOF_IRQ,
|
||||
USB_DEV_CTL_IRQ,
|
||||
USB_EP_RX_IRQ,
|
||||
USB_EP_TX_IRQ,
|
||||
USB_CONNECT,
|
||||
USB_DISCONNECT,
|
||||
USB_BABBLE,
|
||||
USB_XACT_ERR,
|
||||
USB_DEV_VBUS_ERR,
|
||||
};
|
||||
|
||||
enum usb_dev_io_cmd {
|
||||
USB_DEV_IO_CMD_AUTO_TX_NULL_PKT_ENABLE,
|
||||
USB_DEV_IO_CMD_AUTO_TX_NULL_PKT_DISABLE,
|
||||
USB_DEV_IO_CMD_REMOTE_WAKEUP,
|
||||
|
||||
/* this function need call after attatch & before open
|
||||
* msg[1:0] : vid
|
||||
* msg[3:2] : pid
|
||||
*/
|
||||
USB_DEV_IO_CMD_SET_ID,
|
||||
USB_HOST_HY_TUNE_EN,
|
||||
USB_HOST_SET_HY_TUNE,
|
||||
USB_HOST_SET_TX_VERF,
|
||||
USB_HOST_SET_TX_SLIVER,
|
||||
USB_HOST_GET_TX_SLIVER,
|
||||
USB_HOST_SET_SLIVER_TOG_EN,
|
||||
USB_HOST_SET_RX_SLIVER,
|
||||
USB_HOST_GET_RX_SLIVER,
|
||||
USB_HOST_KICK_EP_DMA,
|
||||
USB_HOST_GET_RX_DMA_LEN,
|
||||
USB_HOST_ISO_IS_CRC_ERR,
|
||||
USB_HOST_GET_DMA_IRQ_VECTOR,
|
||||
USB_HOST_SET_TX_INTERVAL,
|
||||
USB_HOST_SET_RX_INTERVAL,
|
||||
USB_HOST_GET_BUS_SPEED,
|
||||
};
|
||||
|
||||
enum usb_device_ep_dir {
|
||||
USB_CORE_HOST_EP_RX = 0,
|
||||
USB_CORE_HOST_EP_TX,
|
||||
};
|
||||
|
||||
struct usb_device_dma_cfg {
|
||||
uint8_t ep_index;
|
||||
uint8_t ep_dir;
|
||||
uint32_t* dma_addr;
|
||||
uint32_t dma_len;
|
||||
};
|
||||
|
||||
struct usb_device_ep_cfg {
|
||||
uint8 ep_id;
|
||||
uint8 ep_type;
|
||||
uint8 ep_dir_tx;
|
||||
uint16 max_packet_size_hs;
|
||||
uint16 max_packet_size_fs;
|
||||
};
|
||||
|
||||
struct usb_device_cfg {
|
||||
uint16 vid; /* usb device VID */
|
||||
uint16 pid; /* usb device PID */
|
||||
uint8 speed; /* not used */
|
||||
uint8 *p_device_descriptor; /* usb device descriptor */
|
||||
uint8 *p_config_descriptor_head; /* usb config descriptor generic header */
|
||||
uint8 *p_config_desc_hs; /* usb config descriptor */
|
||||
uint8 *p_config_desc_fs; /* usb config descriptor */
|
||||
uint16 config_desc_len; /* usb config descriptor total len */
|
||||
uint8 interface_num;
|
||||
|
||||
uint8 *p_language_id;
|
||||
uint16 language_id_len;
|
||||
uint8 *p_str_manufacturer;
|
||||
uint16 str_manufacturer_len;
|
||||
uint8 *p_str_product;
|
||||
uint16 str_product_len;
|
||||
uint8 *p_str_serial_number;
|
||||
uint16 str_serial_number_len;
|
||||
|
||||
uint8 ep_nums;
|
||||
struct usb_device_ep_cfg ep_cfg[8]; /* must same with config_desc */
|
||||
};
|
||||
|
||||
typedef uint32 (*usbdev_irq_hdl)(uint32 irq, uint32 param1, uint32 param2, uint32 param3);
|
||||
|
||||
struct usb_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct usb_hal_ops{
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct usb_device *p_usb_d, struct usb_device_cfg *p_usbdev_cfg);
|
||||
int32(*close)(struct usb_device *p_usb_d);
|
||||
int32(*read)(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
|
||||
int32(*write)(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
|
||||
int32(*write_scatter)(struct usb_device *p_usb_d, uint8 ep, scatter_data *data, uint32 count, uint8 sync);
|
||||
int32(*ioctl)(struct usb_device *p_usb_d, uint32 cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct usb_device *p_usb_d, usbdev_irq_hdl irqhdl, uint32 data);
|
||||
};
|
||||
|
||||
int32 usb_device_open(struct usb_device *p_usb_d, struct usb_device_cfg * p_usbdev_cfg);
|
||||
|
||||
int32 usb_device_close(struct usb_device *p_usb_d);
|
||||
|
||||
int32 usb_device_write(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
|
||||
|
||||
int32 usb_device_write_scatter(struct usb_device *p_usb_d, uint8 ep, scatter_data *data, uint32 count, uint8 sync);
|
||||
|
||||
int32 usb_device_read(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
|
||||
|
||||
int32 usb_device_ioctl(struct usb_device *p_usb_d, uint32 cmd, uint32 param1, uint32 param2);
|
||||
|
||||
int32 usb_device_request_irq(struct usb_device *p_usb_d, usbdev_irq_hdl handle, uint32 data);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
549
sdk/include/hal/vpp.h
Normal file
549
sdk/include/hal/vpp.h
Normal file
@@ -0,0 +1,549 @@
|
||||
#ifndef HAL_VPP_H
|
||||
#define HAL_VPP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* User interrupt handle */
|
||||
typedef int32(*vpp_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
|
||||
|
||||
/**
|
||||
* @brief UART ioctl_cmd type
|
||||
*/
|
||||
enum vpp_ioctl_cmd {
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_DIS_UV_MODE,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_THRESHOLD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_RC,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_RC,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_COLOR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_COLOR,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_BMPADR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_BMPADR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_LOCATED,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_LOCATED,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_CONTRAST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_CONTRAST,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_SIZE_AND_NUM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_IDX,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_TAKE_PHOTO_LINEBUF,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_PHOTO_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK1_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_DET_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_ALL_FRAME_OR_WINDOW,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_CALBUF,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_RANGE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_BLK_THRESHOLD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_FRAME_THRESHOLD,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MOTION_FRAME_INTERVAL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_IFP_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_IFP_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_SIZE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_YCBCR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF0_CNT,
|
||||
|
||||
VPP_IOCTL_CMD_BUF0_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_CNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_SHRINK,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_INPUT_INTERFACE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF0_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF0_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF0_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_BUF1_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_ITP_Y_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_ITP_U_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_ITP_V_ADDR,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_ITP_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_ITP_AUTO_CLOSE,
|
||||
|
||||
VPP_IOCTL_CMD_ISP_CONFIG,
|
||||
|
||||
VPP_IOCTL_CMD_GET_STA,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_FTUSB3_EN,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_PSRAM_YCNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_PSRAM_UVCNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_PSRAM1_YCNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_PSRAM1_UVCNT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_FRAME_SAVE_NO_SRAM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_F1_SAVE_NO_SRAM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F0_IS_PSRAM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F1_IS_PSRAM,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F0_IS_ENABLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F1_IS_ENABLE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F1_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_F1_SHRINK,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SRAMBUFF_CNT_MODE,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SCALEBUF_SELECT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_SCALE1BUF_SELECT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GET_SCALE3BUF_SELECT,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_GEN420_BUF_SEL,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_THRESHOLD,
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_COLOR,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_HADR,
|
||||
|
||||
|
||||
/*! Compatible version: V2;
|
||||
*@ Describe:
|
||||
*
|
||||
*/
|
||||
VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_MODE,
|
||||
|
||||
VPP_IOCTL_CMD_IS_CLOSED,
|
||||
};
|
||||
|
||||
struct vpp_device {
|
||||
struct dev_obj dev;
|
||||
};
|
||||
|
||||
struct vpp_hal_ops {
|
||||
struct devobj_ops ops;
|
||||
int32(*open)(struct vpp_device *vpp_dev);
|
||||
int32(*suspend)(struct vpp_device *vpp_dev);
|
||||
int32(*resume)(struct vpp_device *vpp_dev);
|
||||
int32(*close)(struct vpp_device *vpp_dev);
|
||||
int32(*ioctl)(struct vpp_device *vpp_dev, enum vpp_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
|
||||
int32(*request_irq)(struct vpp_device *vpp_dev, uint32 irq_flag, vpp_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32(*release_irq)(struct vpp_device *vpp_dev, uint32 irq_flag);
|
||||
};
|
||||
|
||||
|
||||
int32 vpp_suspend(struct vpp_device *p_vpp);
|
||||
int32 vpp_resume(struct vpp_device *p_vpp);
|
||||
int32 vpp_request_irq(struct vpp_device *p_vpp, uint32 irq_flags, vpp_irq_hdl irq_hdl, uint32 irq_data);
|
||||
int32 vpp_release_irq(struct vpp_device *p_vpp, uint32 irq_flags);
|
||||
int32 vpp_open(struct vpp_device *p_vpp);
|
||||
int32 vpp_close(struct vpp_device *p_vpp);
|
||||
int32 vpp_dis_uv_mode(struct vpp_device *p_vpp,uint8 enable_buf0,uint8 enable_buf1);
|
||||
int32 vpp_set_threshold(struct vpp_device *p_vpp,uint32 dlt,uint32 dht);
|
||||
int32 vpp_set_water0_rc(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_water1_rc(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_water0_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v);
|
||||
int32 vpp_set_water1_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v);
|
||||
int32 vpp_set_water0_bitmap(struct vpp_device *p_vpp,uint32 bitmap);
|
||||
int32 vpp_set_water1_bitmap(struct vpp_device *p_vpp,uint32 bitmap);
|
||||
int32 vpp_set_water0_locate(struct vpp_device *p_vpp,uint8 x,uint8 y);
|
||||
int32 vpp_set_water1_locate(struct vpp_device *p_vpp,uint8 x,uint8 y);
|
||||
int32 vpp_set_water0_contrast(struct vpp_device *p_vpp,uint8 contrast);
|
||||
int32 vpp_set_water1_contrast(struct vpp_device *p_vpp,uint8 contrast);
|
||||
int32 vpp_set_watermark0_charsize_and_num(struct vpp_device *p_vpp,uint8 w,uint8 h,uint8 num);
|
||||
int32 vpp_set_watermark0_idx(struct vpp_device *p_vpp,uint8 index_num,uint8 index);
|
||||
int32 vpp_set_watermark1_size(struct vpp_device *p_vpp,uint8 w,uint8 h);
|
||||
int32 vpp_set_watermark0_mode(struct vpp_device *p_vpp,uint8 mode);
|
||||
int32 vpp_set_watermark1_mode(struct vpp_device *p_vpp,uint8 mode);
|
||||
int32 vpp_set_watermark0_enable(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_watermark1_enable(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_motion_det_enable(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_motion_calbuf(struct vpp_device *p_vpp,uint32 calbuf);
|
||||
int32 vpp_set_motion_range(struct vpp_device *p_vpp,uint16 x_s,uint16 y_s,uint16 x_e,uint16 y_e);
|
||||
int32 vpp_set_motion_blk_threshold(struct vpp_device *p_vpp,uint8 threshold);
|
||||
int32 vpp_set_motion_frame_threshold(struct vpp_device *p_vpp,uint32 threshold);
|
||||
int32 vpp_set_ifp_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_ifp_en(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_mode(struct vpp_device *p_vpp,uint8 mode);
|
||||
int32 vpp_set_video_size(struct vpp_device *p_vpp,uint32 w,uint32 h);
|
||||
int32 vpp_set_ycbcr(struct vpp_device *p_vpp,uint8 ycbcr);
|
||||
int32 vpp_set_buf0_count(struct vpp_device *p_vpp,uint8 cnt);
|
||||
int32 vpp_set_buf0_en(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_buf1_count(struct vpp_device *p_vpp,uint8 cnt);
|
||||
int32 vpp_set_buf1_en(struct vpp_device *p_vpp,uint8 enable);
|
||||
int32 vpp_set_buf1_shrink(struct vpp_device *p_vpp,uint8 half);
|
||||
int32 vpp_set_input_interface(struct vpp_device *p_vpp,uint8 mode);
|
||||
int32 vpp_set_buf0_y_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_buf0_u_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_buf0_v_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_buf1_y_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_buf1_u_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_buf1_v_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_itp_y_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_itp_u_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_itp_v_addr(struct vpp_device *p_vpp,uint32 addr);
|
||||
int32 vpp_set_itp_linebuf(struct vpp_device *p_vpp,uint32 linebuf);
|
||||
int32 vpp_set_itp_enable(struct vpp_device *p_vpp,uint8 en);
|
||||
int32 vpp_set_itp_auto_close(struct vpp_device *p_vpp,uint8 en);
|
||||
int32 vpp_set_isp_config(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_status(struct vpp_device *p_vpp);
|
||||
int32 vpp_set_motion_all_frame(struct vpp_device *p_vpp,uint32 allframe);
|
||||
int32 vpp_set_motion_frame_interval(struct vpp_device *p_vpp,uint8 interval);
|
||||
int32 vpp_set_ftusb30_enable(struct vpp_device *p_vpp,uint8 en);
|
||||
int32 vpp_set_nosram_buf_enable(struct vpp_device *p_vpp,uint8 vppbuf);
|
||||
int32 vpp_set_sram_buf_mode(struct vpp_device *p_vpp,uint8 vppbuf0,uint8 vppbuf1);
|
||||
int32 vpp_set_scale_buf_select(struct vpp_device *p_vpp,uint8 scale1,uint8 scale3);
|
||||
int32 vpp_set_psram_ycnt(struct vpp_device *p_vpp,uint32 w,uint32 h);
|
||||
int32 vpp_set_psram1_uvcnt(struct vpp_device *p_vpp,uint32 w,uint32 h);
|
||||
int32 vpp_set_psram1_ycnt(struct vpp_device *p_vpp,uint32 w,uint32 h);
|
||||
int32 vpp_set_psram_uvcnt(struct vpp_device *p_vpp,uint32 w,uint32 h);
|
||||
int32 vpp_set_nosram_buf1_enable(struct vpp_device *p_vpp,uint8 en);
|
||||
int32 vpp_set_gen420_buf_sel(struct vpp_device *p_vpp,uint8 buf);
|
||||
int32 vpp_set_watermark0_auto_rc_threshold(struct vpp_device *p_vpp,uint32 cth,uint32 hth);
|
||||
int32 vpp_set_watermark0_auto_rc(struct vpp_device *p_vpp,uint32 en,uint8 y,uint8 u,uint8 v);
|
||||
int32 vpp_set_watermark0_auto_rc_sram_adr(struct vpp_device *p_vpp,uint32 adr);
|
||||
int32 vpp_set_watermark_auto_rc_mode(struct vpp_device *p_vpp,uint8 mode);
|
||||
|
||||
int32 vpp_get_f0_is_psram(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_f1_is_psram(struct vpp_device *p_vpp);
|
||||
int32 vpp_f0_is_enable(struct vpp_device *p_vpp);
|
||||
int32 vpp_f1_is_enable(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_f1_mode(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_f1_shrink(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_scale1_buf_select(struct vpp_device *p_vpp);
|
||||
int32 vpp_get_scale3_buf_select(struct vpp_device *p_vpp);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
Reference in New Issue
Block a user