Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
387
sdk/include/dev/dma/dw_dmac.h
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387
sdk/include/dev/dma/dw_dmac.h
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@@ -0,0 +1,387 @@
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#ifndef _DW_DMAC_H_
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#define _DW_DMAC_H_
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#include "hal/dma.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*! max dmac hardware channel
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*/
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#define DW_DMAC_MAX_DMAC_CHN 4
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/*! max dmac hardware channel mask
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*/
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#define DW_DMAC_MAX_DMAC_CHN_MASK 0xF
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/**
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* @brief DMAC controller (IP)
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*/
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struct dw_dmac_hw_ch {
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__IO uint32 SARL;
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__IO uint32 SARH;
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__IO uint32 DARL;
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__IO uint32 DARH;
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__IO uint32 FIFO0[2]; //LLPL,LLPH, NO USE
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__IO uint32 CTLL;
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__IO uint32 CTLH;
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__IO uint32 FIFO1[8]; //SSTATL,SSTATH,DSTATL,DSTATH,SSTATARL,SSTATARH,DSTATARL,DSTATARH
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__IO uint32 CFGL;
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__IO uint32 CFGH;
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__IO uint32 SGRL;
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__IO uint32 SGRH;
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__IO uint32 DSRL;
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__IO uint32 DSRH;
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};
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/**
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* @brief DMAC
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*/
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struct hgdma_dw_hw {
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struct dw_dmac_hw_ch CH[4];
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__IO uint32 FIFO0[22*4];
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__IO uint32 RawTfrL;
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__IO uint32 RawTfrH;
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__IO uint32 RawBlockL;
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__IO uint32 RawBlockH;
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__IO uint32 RawSrcTranL;
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__IO uint32 RawSrcTranH;
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__IO uint32 RawDstTranL;
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__IO uint32 RawDstTranH;
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__IO uint32 RawErrL;
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__IO uint32 RawErrH;
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__IO uint32 FIFO1[5*2];
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__IO uint32 MaskTfrL;
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__IO uint32 MaskTfrH;
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__IO uint32 MaskBlockL;
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__IO uint32 MaskBlockH;
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__IO uint32 MaskSrcTranL;
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__IO uint32 MaskSrcTranH;
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__IO uint32 MaskDstTranL;
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__IO uint32 MaskDstTranH;
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__IO uint32 MaskErrL;
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__IO uint32 MaskErrH;
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__IO uint32 ClearTfrL;
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__IO uint32 ClearTfrH;
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__IO uint32 ClearBlockL;
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__IO uint32 ClearBlockH;
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__IO uint32 ClearSrcTranL;
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__IO uint32 ClearSrcTranH;
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__IO uint32 ClearDstTranL;
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__IO uint32 ClearDstTranH;
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__IO uint32 ClearErrL;
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__IO uint32 ClearErrH;
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__IO uint32 FIFO2[2];
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__IO uint32 ReqSrcRegL;
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__IO uint32 ReqSrcRegH;
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__IO uint32 ReqDstRegL;
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__IO uint32 ReqDstRegH;
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__IO uint32 SglReqSrcRegL;
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__IO uint32 SglReqSrcRegH;
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__IO uint32 SglReqDstRegL;
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__IO uint32 SglReqDstRegH;
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__IO uint32 LstSrcRegL;
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__IO uint32 LstSrcRegH;
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__IO uint32 LstDstRegL;
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__IO uint32 LstDstRegH;
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__IO uint32 DmaCfgRegL;
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__IO uint32 DmaCfgRegH;
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__IO uint32 ChEnRegL;
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__IO uint32 ChEnRegH;
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__IO uint32 FIFO3[2];
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__IO uint32 DmaTestRegL;
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__IO uint32 DmaTestRegH;
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};
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struct hgdma_dw {
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struct dma_device dev;
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struct hgdma_dw_hw *hw;
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uint32 irq_num;
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uint32 opened;
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os_semaphore_t mem_chn;
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os_semaphore_t dev_chn;
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os_mutex_t dev_mutex;
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dma_irq_hdl irq_hdl[DW_DMAC_MAX_DMAC_CHN];
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uint32 irq_data[DW_DMAC_MAX_DMAC_CHN];
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uint32 state[DW_DMAC_MAX_DMAC_CHN];
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uint32 chn_used_flag;
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};
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/** @brief DW DMAC register constant table definition
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* @{
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*/
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/***** DW_PARAMS Register *****/
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/*! number of channels
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*/
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#define DW_DMAC_PARAMS_NR_CHAN 4
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/*! number of AHB masters
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*/
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#define DW_DMAC_PARAMS_NR_MASTER 2
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/***** DWC_PARAMS Register *****/
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/*! multi block transfer
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*/
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#define DW_DMACC_PARAMS_MBLK_EN 11
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/***** CTLx Register *****/
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/*! irqs enabled
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*/
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#define DW_DMAC_CTLL_INT_EN (1UL << 0)
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/*! The size of each element of destination transmission.
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*/
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#define DW_DMAC_CTLL_DST_WIDTH(n) (((n)&0x7) << 1)
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/*! The size of each element of source transmission.
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*/
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#define DW_DMAC_CTLL_SRC_WIDTH(n) (((n)&0x7) << 4)
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/*! Indicates destination address how to change on every source transfer.
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*/
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#define DW_DMAC_CTLL_DST_DIR(n) (((n)&0x3) << 7)
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/*! Indicates source address how to change on every source transfer.
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*/
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#define DW_DMAC_CTLL_SRC_DIR(n) (((n)&0x3) << 9)
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/*! Number of data items to be written to de destination every time.
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*/
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#define DW_DMAC_CTLL_DST_MSIZE(n) (((n)&0x7) << 11)
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/*! Number of data items to be read from the source every time.
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*/
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#define DW_DMAC_CTLL_SRC_MSIZE(n) (((n)&0x7) << 14)
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/*! src gather
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*/
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#define DW_DMAC_CTLL_S_GATH_EN (1UL << 17)
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/* dst scatter
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*/
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//#define DW_DMAC_CTLL_D_SCAT_EN (1UL << 18)
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/*! Transfer type and flow control.
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*/
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#define DW_DMAC_CTLL_FC(n) (((n)&0x7) << 20)
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/*! dst master select : 1 for memory, 0 for peripherals
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*/
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#define DW_DMAC_CTLL_DMS(n) (((n)&0x3) << 23)
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/*! src master select : 1 for memory, 0 for peripherals
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*/
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#define DW_DMAC_CTLL_SMS(n) (((n)&0x3) << 25)
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/* dest block chain
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*/
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//#define DW_DMAC_CTLL_LLP_D_EN (1UL << 27)
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/* src block chain
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*/
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//#define DW_DMAC_CTLL_LLP_S_EN (1UL << 28)
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/***** CTL_HI Register *****/
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/*! Block transfer done
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*/
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#define DW_DMAC_CTLH_DONE (0x00001000)
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/*! Block transfer size. The max block size is 4095.
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*/
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#define DW_DMAC_CTLH_BLOCK_TS_MASK (0x00000FFF)
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/***** CFG_LO Register *****/
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/*! Channel priority mask
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*/
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#define DW_DMAC_CFGL_CH_PRIOR_MASK (0x7UL << 5)
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/*! Channel priority
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*/
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#define DW_DMAC_CFGL_CH_PRIOR(n) (((n)&0x7) << 5)
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/*! Channle Suspend. Suspends all DMA data transfers from the source until this
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* bit is cleared.
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*/
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#define DW_DMAC_CFGL_CH_SUSP (1UL << 8)
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/*! Indicates if there is data left in the channel FIFO.
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*/
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#define DW_DMAC_CFGL_FIFO_EMPTY (1UL << 9)
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/*! Destination software or hardware handshaking select.
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*/
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#define DW_DMAC_CFGL_HS_DST (1UL << 10)
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/*! Source software or hardware handshaking select.
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*/
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#define DW_DMAC_CFGL_HS_SRC (1UL << 11)
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//#define DW_DMAC_CFGL_LOCK_CH_LEVEL(n) (((n)&0x3) << 12)
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//#define DW_DMAC_CFGL_LOCK_BUS_LEVEL(n) (((n)&0x3) << 14)
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//#define DW_DMAC_CFGL_LOCK_CH (1UL << 16)
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//#define DW_DMAC_CFGL_LOCK_BUS (1UL << 17)
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/*! Destination handshaking interface polarity.
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*/
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#define DW_DMAC_CFGL_HS_DST_POL (1UL << 18)
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/*! Source handshaking interface polarity.
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*/
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#define DW_DMAC_CFGL_HS_SRC_POL (1UL << 19)
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/*! Maximum AMBA burst length that is used for DMA transfers on this channel.
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*/
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#define DW_DMAC_CFGL_MAX_BURST(n) (((n)&0x2FF) << 20)
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/*! Automatic source reload.
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*/
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#define DW_DMAC_CFGL_RELOAD_SAR (1UL << 30)
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/*! Automatic desination reload.
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*/
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#define DW_DMAC_CFGL_RELOAD_DAR (1UL << 31)
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/***** CFG_HI Register *****/
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/*! Flow control mode.
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*/
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#define DW_DMAC_CFGH_FCMODE (1UL << 0)
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/*! FIFO mode select.
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*/
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#define DW_DMAC_CFGH_FIFO_MODE (1UL << 1)
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/*! Protection control.
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*/
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#define DW_DMAC_CFGH_PROTCTL(n) (((n)&0x7) << 2)
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//#define DW_DMAC_CFGH_DS_UPD_EN (1UL << 5)
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//#define DW_DMAC_CFGH_SS_UPD_EN (1UL << 6)
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/*! Assigns a hardware handshaking interface to the source of channel.
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*/
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#define DW_DMAC_CFGH_SRC_PER(n) (((n)&0xF) << 7)
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/*! Assigns a hardware handshaking interface to the destination of channel.
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*/
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#define DW_DMAC_CFGH_DST_PER(n) (((n)&0xF) << 11)
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/***** SGR Register *****/
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/*! Source gather interval.
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*/
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#define DW_DMAC_SGR_SGI(n) (((n)&0xFFFFF) << 0)
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/*! Source gather count.
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*/
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#define DW_DMAC_SGR_SGC(n) (((n)&0xF) << 20)
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/***** DSR Register *****/
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//#define DW_DMAC_DSR_DSI(x) (((n)&0xFFFFF) << 0)
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//#define DW_DMAC_DSR_DSC(x) (((n)&0xF) << 20)
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/***** DmaCfgReg Register *****/
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/*! dmac enable.
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*/
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#define DW_DMAC_CFG_DMA_EN (1UL << 0)
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/***** ChEnRegL/MaskTfrL/MaskErrL/MaskDstTranL/MaskSrcTranL/MaskBlockL/ Register *****/
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/*! Source gather count.
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*/
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#define DW_DMAC_WRITE_EN(n) ((1 << (n+8)) | (1 << n))
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/*! Source gather count.
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*/
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#define DW_DMAC_WRITE_DIS(n) (1 << (n+8))
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#define DW_DMAC_XFER_DONE(n) (1 << (n))
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#define DW_DMAC_XFER_ERR(n) (1 << (n+8))
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/**
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* @}
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*/
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/** @brief DW DMAC external constant definition
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* @{
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*/
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/**
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* @breif Number of data items to be transferred(of width TR_WIDTH)
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*/
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enum dw_dmac_msize {
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/*! damc data width : 1 TR_WIDTH
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*/
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DW_DMAC_MSIZE_1,
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/*! damc data width : 4 TR_WIDTH
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*/
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DW_DMAC_MSIZE_4,
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/*! damc data width : 8 TR_WIDTH
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*/
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DW_DMAC_MSIZE_8,
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// The following MSIZE is not supported.
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// DW_DMAC_MSIZE_16,
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// DW_DMAC_MSIZE_32,
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// DW_DMAC_MSIZE_64,
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// DW_DMAC_MSIZE_128,
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// DW_DMAC_MSIZE_256,
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};
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/**
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* @brief The size of each element of destination transmission. The unit is bit.
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*/
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enum dw_dmac_tr_width {
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/*! damc xfer width : 8 bit
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*/
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DW_DMAC_TR_8,
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/*! damc xfer width : 16bit
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*/
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DW_DMAC_TR_16,
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/*! damc xfer width : 32bit
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*/
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DW_DMAC_TR_32,
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// The following TR_WIDTH is not supported.0
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// DW_DMAC_TR_64,
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// DW_DMAC_TR_128,
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// DW_DMAC_TR_256,
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};
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/**
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* @brief Indicates destination address how to change on every source transfer.
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*/
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enum dw_dmac_addr_dir {
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/*! Increment
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*/
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DW_DMAC_ADDR_INC,
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/*! Decrement
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*/
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DW_DMAC_ADDR_DEC,
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/*! No change
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*/
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DW_DMAC_ADDR_NO_CHANGE,
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};
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/**
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* @breif flow controller
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@verbatim
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-------------------------------------------------------------------------------
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CTLL.TT_FC Field Transfer Type Flow Controller
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-------------------------------------------------------------------------------
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000 Memory to Memory DW_anb_dmac
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001 Memory to Peripheral DW_anb_dmac
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010 Peripheral to Memory DW_anb_dmac
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011 Peripheral to Peripheral DW_anb_dmac
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100 Peripheral to Memory Peripheral
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101 Peripheral to Peripheral Source Peripheral
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110 Memory to Peripheral Peripheral
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111 Peripheral to Peripheral Destination Peripheral
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@endverbatim
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*/
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enum dw_dmac_fc {
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/*! Memory to Memory
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*/
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DW_DMAC_FC_D_M2M,
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/*! Memory to Peripheral
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*/
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DW_DMAC_FC_D_M2P,
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/*! Peripheral to Memory
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*/
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DW_DMAC_FC_D_P2M,
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/*! Peripheral to Peripheral
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*/
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DW_DMAC_FC_D_P2P,
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// The following flow control is not supported.
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// DW_DMAC_FC_P_P2M,
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// DW_DMAC_FC_SP_P2P,
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// DW_DMAC_FC_P_M2P,
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// DW_DMAC_FC_DP_P2P,
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};
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/**
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* @}
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*/
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int32 dw_dmac_search_src_id(uint32 addr);
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int32 dw_dmac_search_dest_id(uint32 addr);
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int32 dw_dmac_attach(uint32 dev_id, struct hgdma_dw *dmac);
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#ifdef __cplusplus
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}
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#endif
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#endif
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82
sdk/include/dev/dma/hg_m2m_dma.h
Normal file
82
sdk/include/dev/dma/hg_m2m_dma.h
Normal file
@@ -0,0 +1,82 @@
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#ifndef _HG_M2M_DMA_H_
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#define _HG_M2M_DMA_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef TXW82X
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#define HG_M2M_DMA_NUM (CONFI_CORE_M2M_DMA ? 2 : 3)
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#define HG_M2M_DMA_MAX_LEN (1<<20)
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#else
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#define HG_M2M_DMA_NUM 2
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#define HG_M2M_DMA_MAX_LEN (64<<10)
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#endif
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/**
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* @brief M2M_DMA
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*/
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struct mem_dma_ch {
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__IO uint32 DMA_CON;
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__IO uint32 DMA_SAIE;
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__IO uint32 DMA_DATA;
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__IO uint32 DMA_SADR;
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__IO uint32 DMA_TADR;
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__IO uint32 DMA_DLEN;
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#ifdef TXW81X
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__IO uint32 DMA_ISIZE;
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#endif
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};
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struct mem_dma_hw {
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struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
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};
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struct mem_dma_dev {
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struct dma_device dev;
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struct mem_dma_hw *hw;
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uint32 irq_num[HG_M2M_DMA_NUM];
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uint32 busy_flag : 8,
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dma1_status : 1,
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dma1_mutex : 1,
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suspend : 1,
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reserved : 21;
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struct os_semaphore done[HG_M2M_DMA_NUM];
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};
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/** @brief M2M DMA register constant table definition
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* @{
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*/
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/***** DMA_CON *****/
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#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
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#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
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#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
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#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
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#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
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#define HG_M2M_DMA_CON_DTE (1UL << 0)
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/***** DMA_SAIE *****/
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#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
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#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
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/***** DMA_ISIZE *****/
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#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
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#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
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/***** DMA_DLEN *****/
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#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
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#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
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/**
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* @}
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*/
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||||
|
||||
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
82
sdk/include/dev/dma/hg_m2m_dma_core1.h
Normal file
82
sdk/include/dev/dma/hg_m2m_dma_core1.h
Normal file
@@ -0,0 +1,82 @@
|
||||
#ifndef _HG_M2M_DMA_H_
|
||||
#define _HG_M2M_DMA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef TXW82X
|
||||
#define HG_M2M_DMA_NUM 1
|
||||
#define HG_M2M_DMA_MAX_LEN (1<<20)
|
||||
#else
|
||||
#define HG_M2M_DMA_NUM 2
|
||||
#define HG_M2M_DMA_MAX_LEN (64<<10)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief M2M_DMA
|
||||
*/
|
||||
struct mem_dma_ch {
|
||||
__IO uint32 DMA_CON;
|
||||
__IO uint32 DMA_SAIE;
|
||||
__IO uint32 DMA_DATA;
|
||||
__IO uint32 DMA_SADR;
|
||||
__IO uint32 DMA_TADR;
|
||||
__IO uint32 DMA_DLEN;
|
||||
#ifdef TXW81X
|
||||
__IO uint32 DMA_ISIZE;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mem_dma_hw {
|
||||
struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
|
||||
};
|
||||
|
||||
struct mem_dma_dev {
|
||||
struct dma_device dev;
|
||||
struct mem_dma_hw *hw;
|
||||
uint32 irq_num[HG_M2M_DMA_NUM];
|
||||
uint32 busy_flag : 8,
|
||||
dma1_status : 1,
|
||||
dma1_mutex : 1,
|
||||
suspend : 1,
|
||||
reserved : 21;
|
||||
struct os_semaphore done[HG_M2M_DMA_NUM];
|
||||
};
|
||||
|
||||
|
||||
/** @brief M2M DMA register constant table definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***** DMA_CON *****/
|
||||
#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
|
||||
#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
|
||||
#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
|
||||
#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
|
||||
#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
|
||||
#define HG_M2M_DMA_CON_DTE (1UL << 0)
|
||||
|
||||
/***** DMA_SAIE *****/
|
||||
#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
|
||||
#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
|
||||
|
||||
/***** DMA_ISIZE *****/
|
||||
#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
|
||||
#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
|
||||
|
||||
/***** DMA_DLEN *****/
|
||||
#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
|
||||
#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user