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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
commit e76462eeb7
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61
sdk/include/dev/adc/hgadc_v0.h Normal file
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#ifndef _HGADC_V0_H
#define _HGADC_V0_H
#include "hal/adc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgadc_v0;
typedef struct _adc_channel_data {
/* pointer of config function */
int32 (*func)(struct hgadc_v0 *dev, uint32 channel, uint32 enable);
/* channel */
uint16 channel;
}adc_channel_data;
typedef struct _adc_channel_node {
/* data type */
adc_channel_data data;
/* for list opreation */
struct _adc_channel_node *next;
/* channel amount */
uint8 channel_amount;
}adc_channel_node;
struct hgadc_v0 {
struct adc_device dev;
uint32 hw;
adc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t adc_lock;
os_semaphore_t adc_done;
adc_channel_node head_node;
uint32 refer_vddi;
uint32 refer_vddi_adc_data;
uint32 refer_tsensor;
uint32 refer_adda_vref;
uint32 rf_vddi_en:1,
opened :1,
irq_en :1;
};
int32 hgadc_v0_attach(uint32 dev_id, struct hgadc_v0 *adc);
#ifdef __cplusplus
}
#endif
#endif

82
sdk/include/dev/adc/hgadc_v1.h Normal file
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#ifndef _HGADC_V1_H
#define _HGADC_V1_H
#include "hal/adc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgadc_v1;
typedef struct _adc_channel_data {
/* pointer of config function */
int32 (*func)(struct hgadc_v1 *dev, uint32 channel, uint32 enable);
/* channel */
uint16 channel;
/* sel for hw*/
uint32 sel;
uint16 sch_vdd;
}adc_channel_data;
typedef struct _adc_channel_node {
/* data type */
adc_channel_data data;
/* for list opreation */
struct _adc_channel_node *next;
/* channel amount */
uint8 channel_amount;
}adc_channel_node;
struct hgadc_v1 {
struct adc_device dev;
uint32 hw;
adc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t adc_lock;
os_semaphore_t adc_done;
adc_channel_node head_node;
adc_channel_node *cur_node;
uint32 refer_vddi;
uint32 refer_vddi_adc_data;
uint32 refer_tsensor;
uint32 refer_pmu_tsensor;
uint32 refer_adda_vref;
uint32 ref_temp;
int32 adkey_range;
uint32 rf_vddi_en:1,
opened :1,
irq_en :1;
};
struct hgadc_v1_hw;
void saradc_pri_channel_config(struct hgadc_v1_hw *hw, uint8 pri_chanx_en,uint8 pri_chan_sel,uint8 pri_trg_sel);
void saradc_pri_channel_clr_pending(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void saradc_pri_channel_kick(struct hgadc_v1_hw *hw);
uint16 saradc_pri_channel_get_pending(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void saradc_pri_channel_disable(struct hgadc_v1_hw *hw, uint8 pri_chanx_en);
uint16 saradc_pri_channel_get_raw_data(struct hgadc_v1_hw *hw, uint8 pri_chan_sel);
void sar_adc_sample_one_channel(uint32 channel, uint32 *raw_data);
void saradc_channel_disable(struct hgadc_v1_hw *hw, uint8 chanx_en);
uint16 saradc_one_channel_single_kick(struct hgadc_v1_hw *hw);
uint16 saradc_channel_get_raw_data(struct hgadc_v1_hw *hw, uint8 chan_en);
uint16 saradc_channel_get_pending(struct hgadc_v1_hw *hw, uint8 chan_en);
void saradc_channel_config(struct hgadc_v1_hw *hw, uint8 chanx_en,uint8 smp_mode_sel,uint8 chan_sel,uint8 trg_sel);
void saradc_channel_clr_pending(struct hgadc_v1_hw *hw, uint8 chan_en);
int32 hgadc_v1_attach(uint32 dev_id, struct hgadc_v1 *adc);
#ifdef __cplusplus
}
#endif
#endif

131
sdk/include/dev/audio/ausys.h Normal file
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#ifndef _AUSYS_H
#define _AUSYS_H
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------
* AUSYS DA platform APIs
*----------------------------------*/
enum ausys_da_platform {
AUSYS_AUDA,
AUSYS_IIS0,
AUSYS_IIS1,
};
enum ausys_da_msg_type {
//FIFO empty message
AUSYS_DA_MSG_FIFO_FULL = BIT(0),
//FIFO full message
AUSYS_DA_MSG_FIFO_EMPTY = BIT(1),
//DA successfully play once
AUSYS_DA_MSG_PLAY_DONE = BIT(2),
//DA successfully play half
AUSYS_DA_MSG_PLAY_HALF = BIT(3),
};
struct ausys_da_msg_content {
uint32 fifo_next_addr;
uint32 fifo_next_len;
};
struct ausys_da_msg {
enum ausys_da_msg_type type;
struct ausys_da_msg_content da_content;
void *user_content;
};
int32 ausys_da_put(void* buf, uint32 bytes);
int32 ausys_da_play(void);
int32 ausys_da_change_sample_rate(uint32 sample_rate);
int32 ausys_da_change_volume(uint32 percent_0to100);
int32 ausys_da_get_cur_volume(uint32 *percent_0to100);
int32 ausys_da_register_msg(enum ausys_da_msg_type msg_type);
int32 ausys_da_unregister_msg(enum ausys_da_msg_type msg_type);
int32 ausys_da_get_msg(struct ausys_da_msg *msg, uint32 tmo_ms);
int32 ausys_da_ioctl(enum ausys_da_platform platform, uint32 cmd, uint32 arg0, uint32 arg1);
int32 ausys_da_deinit(void);
int32 ausys_da_init(
uint32 sample_rate,
uint32 sample_bits,
uint32 channel,
enum ausys_da_platform platform,
uint32 buf_bytes,
uint32 per_buf_bytes,
uint32 play_null_bytes
);
/*----------------------------------
* AUSYS AD platform APIs
*----------------------------------*/
enum ausys_ad_platform {
AUSYS_AUAD,
AUSYS_PDM,
AUSYS_IIS_SLAVER0,
AUSYS_IIS_SLAVER1,
};
enum ausys_ad_msg_type {
//AD successfully play once
AUSYS_AD_MSG_PLAY_DONE = BIT(0),
//AD successfully play half
AUSYS_AD_MSG_PLAY_HALF = BIT(1),
};
struct ausys_ad_msg_content {
uint32 fifo_next_addr;
uint32 fifo_next_len;
uint32 fifo_cur_addr;
uint32 fifo_cur_len;
};
struct ausys_ad_msg {
enum ausys_ad_msg_type type;
struct ausys_ad_msg_content ad_content;
void *user_content;
};
/*!
* type of user call back handle
*/
typedef void (*type_ausys_ad_user_cb)(void* buf, uint32 bytes, uint32 res);
int32 ausys_ad_record(enum ausys_ad_platform platform);
int32 ausys_ad_register_msg(enum ausys_ad_platform platform, enum ausys_ad_msg_type msg_type);
int32 ausys_ad_unregister_msg(enum ausys_ad_platform platform, enum ausys_ad_msg_type msg_type);
int32 ausys_ad_get_msg(enum ausys_ad_platform platform, struct ausys_ad_msg *msg, uint32 tmo_ms);
int32 ausys_ad_ioctl(enum ausys_ad_platform platform, uint32 cmd, uint32 arg0, uint32 arg1);
int32 ausys_ad_deinit(enum ausys_ad_platform platform);
int32 ausys_ad_init(
enum ausys_ad_platform platform,
uint32 sample_rate,
uint32 sample_bits,
uint32 channel,
uint32 buf_bytes,
uint32 per_buf_bytes,
type_ausys_ad_user_cb user_cb,
uint32 user_data
);
#ifdef __cplusplus
}
#endif
#endif

14
sdk/include/dev/audio/ausys_ad.h Normal file
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#ifndef __AUSYS_AD_H
#define __AUSYS_AD_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

21
sdk/include/dev/audio/ausys_config.h Normal file
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#ifndef __AUSYS_CONFIG_H
#define __AUSYS_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
*
*/
#ifdef __cplusplus
}
#endif
#endif

26
sdk/include/dev/audio/ausys_da.h Normal file
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#ifndef __AUSYS_DA_H
#define __AUSYS_DA_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
* DA platform test mode cmd
*/
enum ausys_da_test {
AUSYS_DA_TEST_OPEN,
AUSYS_DA_TEST_CLOSE,
AUSYS_DA_TEST_PLAY_SINE,
};
int32 ausys_da_test_mode(uint32 cmd, uint32 param1, uint32 param2, uint32 param3);
#ifdef __cplusplus
}
#endif
#endif

49
sdk/include/dev/audio/ausys_debug.h Normal file
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#ifndef __AUSYS_DEBUG_H
#define __AUSYS_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#define AUSYS_DEBUG(fmt, args...) //_os_printf(fmt, ##args)
#define AUSYS_INFO(fmt, ...) \
do{ \
os_printf("ausys info:"fmt,##__VA_ARGS__); \
}while(0);
#define AUSYS_ERR(fmt, ...) \
do{ \
os_printf("ausys err:"fmt,##__VA_ARGS__); \
os_printf("Func:%s Line:%d LR=0x%x\r\n", \
__func__,__LINE__, (uint32)RETURN_ADDR()); \
}while(0);
#define AUSYS_WARNING(fmt, ...) \
do{ \
os_printf("ausys warning:"fmt,##__VA_ARGS__); \
}while(0);
#define AUSYS_ASSERT(expr, info) \
do { \
if (expr) { \
AUSYS_ERR(info); \
return RET_ERR; \
} \
} while(0);
#define AUSYS_PRINT_ARRAY(buf, len) do{\
uint8 *p_print = (uint8 *)buf;\
_os_printf("\r\n");\
for (uint32 __ii=1; __ii<=len; __ii++) {\
_os_printf("%02x ", p_print[__ii-1]);\
if (((__ii)%16 == 0)) _os_printf("\r\n");\
}\
_os_printf("\r\n");\
}while(0);
#ifdef __cplusplus
}
#endif
#endif

17
sdk/include/dev/audio/ausys_eq.h Normal file
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#ifndef __AUSYS_EQ_H
#define __AUSYS_EQ_H
#ifdef __cplusplus
extern "C" {
#endif
#define EQ_COEFF_NUM (50)
extern const int32 eq_coeff_origin[50];
#ifdef __cplusplus
}
#endif
#endif

56
sdk/include/dev/audio/ausys_queue.h Normal file
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#ifndef __AUSYS_QUEUE_H
#define __AUSYS_QUEUE_H
#ifdef __cplusplus
extern "C" {
#endif
struct __ausys_queue_elem {
uint32 addr;
uint32 bytes;
};
typedef struct __ausys_queue_ctrl{
uint32 elem_num;
uint16 head;
uint16 tail;
uint16 per_bytes;
uint16 sta_init:1,
sta_none:1;
void *p_malloc;
void *p_use;
struct __ausys_queue_elem *p_queue;
}TYPE_AUSYS_QUEUE;
int32 ausys_queue_create(TYPE_AUSYS_QUEUE *ausys_queue, uint32 total_bytes, uint32 per_bytes);
int32 ausys_queue_destroy(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_elem_ent(TYPE_AUSYS_QUEUE *ausys_queue, void *buf, uint32 bytes, uint32 need_cpy);
int32 ausys_queue_elem_del(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_tail_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_tail_len(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_first_half(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_second_half(TYPE_AUSYS_QUEUE *ausys_queue);
void ausys_queue_clr_head_all(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_head_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_head_len(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_index_addr(TYPE_AUSYS_QUEUE *ausys_queue, uint32 index);
uint32 ausys_queue_get_index_len(TYPE_AUSYS_QUEUE *ausys_queue, uint32 index);
uint32 ausys_queue_get_head_index(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_tail_index(TYPE_AUSYS_QUEUE *ausys_queue);
void *ausys_queue_get_headnext_addr(TYPE_AUSYS_QUEUE *ausys_queue);
uint32 ausys_queue_get_headnext_len(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_is_empty(TYPE_AUSYS_QUEUE *ausys_queue);
int32 ausys_queue_is_full(TYPE_AUSYS_QUEUE *ausys_queue);
#ifdef __cplusplus
}
#endif
#endif

20
sdk/include/dev/audio/ausys_test.h Normal file
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#ifndef __AUSYS_TEST_H
#define __AUSYS_TEST_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

208
sdk/include/dev/audio/components/ad/auadc.h Normal file
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#ifndef _AUADC_H
#define _AUADC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUADC sample_rate type
*/
enum auadc_sample_rate {
AUADC_SAMPLE_RATE_8K,
AUADC_SAMPLE_RATE_11_025K,
AUADC_SAMPLE_RATE_16K,
AUADC_SAMPLE_RATE_12K,
AUADC_SAMPLE_RATE_22_05K,
AUADC_SAMPLE_RATE_24K,
AUADC_SAMPLE_RATE_32K,
AUADC_SAMPLE_RATE_44_1K,
AUADC_SAMPLE_RATE_48K,
};
/**
* @brief AUADC irq_flag type
*/
enum auadc_irq_flag {
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUADC ioctl_cmd type
*/
enum auadc_ioctl_cmd {
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUADC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUADC_IOCTL_CMD_SET_ANALOG_GAIN,
};
/* User interrupt handle */
typedef void (*auadc_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUADCC api for user */
struct auadc_device {
struct dev_obj dev;
};
/* AUADC api for user */
struct auadc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32(*close)(struct auadc_device *auadc);
int32(*read)(struct auadc_device *auadc, void* buf, uint32 bytes);
int32(*ioctl)(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
};
/* AUADC API functions */
/**
* @brief auadc_open
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
/**
* @brief auadc_close
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_close(struct auadc_device *auadc);
/**
* @brief auadc_read
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_read(struct auadc_device *auadc, void* buf, uint32 bytes);
/**
* @brief auadc_ioctl
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auadc_request_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auadc_release_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

21
sdk/include/dev/audio/components/ad/hg_auadc_v0.h Normal file
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#ifndef _HG_AUADC_V0_H_
#define _HG_AUADC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auadc_v0_init(struct auadc_device *auadc);
int32 hg_auadc_v0_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32 hg_auadc_v0_close(struct auadc_device *auadc);
int32 hg_auadc_v0_read(struct auadc_device *auadc, void* buf, uint32 bytes);
int32 hg_auadc_v0_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auadc_v0_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auadc_v0_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

181
sdk/include/dev/audio/components/alaw/aualaw.h Normal file
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#ifndef _AUALAW_H
#define _AUALAW_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUALAW irq_flag type
*/
enum aualaw_irq_flag {
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUALAW ioctl_cmd type
*/
enum aualaw_ioctl_cmd {
/*!
* @brief:
*
*/
AUALAW_IOCTL_CMD_NONE,
};
/* User interrupt handle */
typedef void (*aualaw_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUALAW api for user */
struct aualaw_device {
struct dev_obj dev;
};
struct aualaw_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aualaw_device *aualaw);
int32(*close)(struct aualaw_device *aualaw);
int32(*encode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*decode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*ioctl)(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
};
/* AUALAW API functions */
/**
* @brief aualaw_open
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_open(struct aualaw_device *aualaw);
/**
* @brief aualaw_close
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_close(struct aualaw_device *aualaw);
/**
* @brief aualaw_encode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_decode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_ioctl
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aualaw_request_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aualaw_release_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

22
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#ifndef _HG_AUALAW_V0_H_
#define _HG_AUALAW_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aualaw_v0_init(void);
int32 hg_aualaw_v0_open(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_close(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aualaw_v0_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aualaw_v0_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

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#ifndef _AUASRC_H
#define _AUASRC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUASRC ioctl_cmd type
*/
enum auasrc_ioctl_cmd {
/*!
* @brief:
*
*/
AUASRC_IOCTL_CMD_NONE,
};
/* AUASRC api for user */
struct auasrc_device {
struct dev_obj dev;
};
struct auasrc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auasrc_device *auasrc);
int32(*close)(struct auasrc_device *auasrc);
int32(*run)(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
int32(*ioctl)(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUASRC API functions */
/**
* @brief auasrc_open
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_open(struct auasrc_device *auasrc);
/**
* @brief auasrc_close
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_close(struct auasrc_device *auasrc);
/**
* @brief auasrc_encode
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_run(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
/**
* @brief auasrc_ioctl
*
*
* @note .
*
* @param auasrc The address of auasrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auasrc_ioctl(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

21
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#ifndef _HG_AUASRC_V0_H_
#define _HG_AUASRC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auasrc_v0_init(void);
int32 hg_auasrc_v0_open(struct auasrc_device *auasrc);
int32 hg_auasrc_v0_close(struct auasrc_device *auasrc);
int32 hg_auasrc_v0_run(struct auasrc_device *auasrc, uint32 hz_from, uint32 hz_to);
int32 hg_auasrc_v0_ioctl(struct auasrc_device *auasrc, enum auasrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
void hg_auasrc_v0_adjust_sample_ofs(void);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUASRC_V0_H_ */

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#ifndef _AUDAC_H
#define _AUDAC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUDAC sample_rate type
*/
enum audac_sample_rate {
AUDAC_SAMPLE_RATE_8K,
AUDAC_SAMPLE_RATE_11_025K,
AUDAC_SAMPLE_RATE_12K,
AUDAC_SAMPLE_RATE_16K,
AUDAC_SAMPLE_RATE_22_05K,
AUDAC_SAMPLE_RATE_24K,
AUDAC_SAMPLE_RATE_32K,
AUDAC_SAMPLE_RATE_44_1K,
AUDAC_SAMPLE_RATE_48K,
};
/**
* @brief AUDAC irq_flag type
*/
enum audac_irq_flag {
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUDAC ioctl_cmd type
*/
enum audac_ioctl_cmd {
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUDAC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUDAC_IOCTL_CMD_SET_ANALOG_GAIN,
/*!
* @brief: Soft mute
*
*/
AUDAC_IOCTL_CMD_SOFT_MUTE,
/*!
* @brief: Change sample rate
* @note :
* 1.Ensure DAC is muted by special method
* 2.You should call "audac_write" API after using this cmd
*
*/
AUDAC_IOCTL_CMD_CHANGE_SAMPLE_RATE,
AUDAC_IOCTL_CMD_GET_DIGITAL_GAIN,
};
/* User interrupt handle */
typedef void (*audac_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUDAC api for user */
struct audac_device {
struct dev_obj dev;
};
struct audac_hal_ops {
struct devobj_ops ops;
int32(*open)(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32(*close)(struct audac_device *audac);
int32(*write)(struct audac_device *audac, void* buf, uint32 bytes);
int32(*ioctl)(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag);
};
/* AUDAC API functions */
/**
* @brief audac_open
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
/**
* @brief audac_close
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_close(struct audac_device *audac);
/**
* @brief audac_write
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_write(struct audac_device *audac, void* buf, uint32 bytes);
/**
* @brief audac_ioctl
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief audac_request_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief audac_release_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_AUDAC_V0_H_
#define _HG_AUDAC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_audac_v0_init(struct audac_device *audac);
int32 hg_audac_v0_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32 hg_audac_v0_close(struct audac_device *audac);
int32 hg_audac_v0_write(struct audac_device *audac, void* buf, uint32 bytes);
int32 hg_audac_v0_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_audac_v0_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_audac_v0_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

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#ifndef _AUDRC_H
#define _AUDRC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUDRC ioctl_cmd type
*/
enum audrc_ioctl_cmd {
/*!
* @brief:
*
*/
AUDRC_IOCTL_CMD_NONE,
};
/* AUDRC api for user */
struct audrc_device {
struct dev_obj dev;
};
struct audrc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct audrc_device *audrc);
int32(*close)(struct audrc_device *audrc);
int32(*run)(struct audrc_device *audrc, void *p_content, uint32 bytes);
int32(*ioctl)(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUDRC API functions */
/**
* @brief audrc_open
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_open(struct audrc_device *audrc);
/**
* @brief audrc_close
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_close(struct audrc_device *audrc);
/**
* @brief audrc_encode
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_run(struct audrc_device *audrc, void *p_content, uint32 bytes);
/**
* @brief audrc_ioctl
*
*
* @note .
*
* @param audrc The address of audrc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audrc_ioctl(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

19
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#ifndef _HG_AUDRC_V0_H_
#define _HG_AUDRC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_audrc_v0_init(void);
int32 hg_audrc_v0_open(struct audrc_device *audrc);
int32 hg_audrc_v0_close(struct audrc_device *audrc);
int32 hg_audrc_v0_run(struct audrc_device *audrc, void *p_content, uint32 bytes);
int32 hg_audrc_v0_ioctl(struct audrc_device *audrc, enum audrc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUDRC_V0_H_ */

212
sdk/include/dev/audio/components/dsd1793/dsd1793.h Normal file
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/**
******************************************************************************
* @file E:\work\venus_v2\SW\trunk\verify\test\audio\dsd1793.h
* @author Troy
* @version V1.0.0
* @date 01-31-2023
* @brief This file contains all the dsd1793 firmware functions.
******************************************************************************
* @attention
*
*
*
*
*
******************************************************************************
*/
#ifndef __DSD1793_H
#define __DSD1793_H
#ifdef __cplusplus
extern "C" {
#endif
#if 1
/*!
* IIC config
*/
//PIN ADDR1, PIN ADDR0
//00, 01, 10, 11
#define DSD1793_PIN_ADDR0 (0)
#define DSD1793_PIN_ADDR1 (0)
#define DSD1793_DSD_MODE (1)
#define DSD1793_PCM_MODE (0)
#define DSD1793_IIC (HG_I2C1_DEVID)
#define DSD1793_IIC_DEVICE_ADDR ((0x4<<4) | (0xC | (DSD1793_PIN_ADDR1) | (DSD1793_PIN_ADDR0)))
#define DSD1793_IIC_SCL_PIN (PC_13)
#define DSD1793_IIC_SDA_PIN (PC_14)
#if 0
//#define DSD1793_IIC_SCL_GPIO_PORT (GPIOC)
//#define DSD1793_IIC_SCL_PIN_NUM (13)
//#define DSD1793_IIC_SDA_GPIO_PORT (GPIOC)
//#define DSD1793_IIC_SDA_PIN_NUM (14)
//#define DSD1793_IIC_SCL_PIN_BIT (BIT(DSD1793_IIC_SCL_PIN_NUM))
//#define DSD1793_IIC_SDA_PIN_BIT (BIT(DSD1793_IIC_SDA_PIN_NUM))
#define SMAPLE_FRQUENCY (48000)
#define OVER_SAMPLE_RATE (192)
#define __SYSCLK (SYS_CLK)
#define SCK_IIS (0)
#define SCK_TIMER (0)
#define DSD1793_SCK_GPIO_PORT (GPIOD)
#define DSD1793_SCK_GPIO_PIN_NUM (14)
#define DSD1793_SCK_GPIO_PIN_BIT (BIT(DSD1793_SCK_GPIO_PIN_NUM))
#define __dsd1793_iic_module_init()\
do{\
TYPE_LL_IIC_INIT _init;\
TYPE_LL_IIC_CFG _cfg;\
memset(&_cfg, 0, sizeof(TYPE_LL_IIC_CFG));\
memset(&_init, 0, sizeof(TYPE_LL_IIC_INIT));\
_cfg.presc = 8;\
_cfg.scldel = 15;\
_cfg.sdadel = 15;\
_cfg.scll = 31;\
_cfg.sclh = 31;\
_cfg.work_mode = LL_IIC_MASTER_MODE;\
ll_iic_init(DSD1793_IIC, &_init);\
ll_iic_config(DSD1793_IIC, &_cfg);\
}while(0);
#define __dsd1793_iic_io_init()\
do{\
ll_gpio_iomap_inout_config(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OUT_SPI2_SCK_OUT,\
LL_GPIO_IN_SPI2_SCK_IN);\
ll_gpio_iomap_inout_config(DSD1793_IIC_SDA_GPIO_PORT, DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OUT_SPI2_IO0_OUT,\
LL_GPIO_IN_SPI2_IO0_IN);\
ll_gpio_ospeed_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OSPEED_3);\
ll_gpio_ospeed_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OSPEED_3);\
ll_gpio_pull_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
ll_gpio_pull_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
ll_gpio_bit_set(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_BIT);\
ll_gpio_bit_set(DSD1793_IIC_SDA_GPIO_PORT,DSD1793_IIC_SDA_PIN_BIT);\
}while(0);
#if (SCK_IIS)
#define __dsd1793_sck_init()\
do{\
TYPE_LL_IIS_INIT _init;\
TYPE_LL_IIS_CFG _cfg;\
memset(&_init, 0, sizeof(TYPE_LL_IIS_INIT));\
memset(&_cfg, 0, sizeof(TYPE_LL_IIS_CFG));\
_cfg.mode = LL_IIS_MASTER_MODE;\
_cfg.work_mode = LL_IIS_SIMPLEX_TX;\
_cfg.channel_mode = LL_IIS_STEREO_MODE;\
_cfg.ws_pol = LL_IIS_LOW_FOR_LEFT_CHANNEL;\
_cfg.bck_pol = LL_IIS_SAMPLE_IN_RISING_EDGE;\
_cfg.data_format = LL_IIS_STANDARD_MODE;\
_cfg.mclk_sel = LL_IIS_MCLK_SEL_SYS_PLL;\
_cfg.mclk_output = LL_IIS_MCLK_OUT_ENABLE;\
_cfg.mclk_div = 16;\
_cfg.baudrate = 29;\
_cfg.ws = 31;\
_cfg.bit = 31;\
ll_gpio_iomap_inout_config(DSD1793_SCK_GPIO_PORT, DSD1793_SCK_GPIO_PIN_NUM, LL_GPIO_OUT_IIS0_MCLK_OUT , LL_GPIO_IN_IIS0_MCLK_IN__LCD_D19_IN_MASK2_6);\
ll_iis_config(IIS0, &_cfg);\
}while(0);
#endif
#if (SCK_TIMER)
#define __dsd1793_sck_init()\
do{\
TYPE_LL_TIMER_CFG _timer_cfg;\
TYPE_LL_TIMER_INIT _timer_init_cfg;\
memset(&_timer_cfg, 0, sizeof(TYPE_LL_TIMER_CFG));\
memset(&_timer_init_cfg, 0, sizeof(TYPE_LL_TIMER_INIT));\
ll_timer_init(TIMER0, &_timer_init_cfg);\
_timer_cfg.work_mode_sel = LL_TIMER_MODE_PWM;\
_timer_cfg.in_src_sel = LL_TIMER_IN_SRC_SYS_CLK;\
_timer_cfg.prescaler_sel = 0;\
_timer_cfg.period_val = (__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE)) - 1;\
_timer_cfg.pwm_val = ((__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE))/2) - 1;\
_timer_cfg.count_val = 0;\
ll_timer_config(TIMER0, &_timer_cfg);;\
ll_gpio_ospeed_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), 7);\
ll_gpio_iomap_output_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), LL_GPIO_OUT_M1_9_LCD_DATA_O_12__TMR0_PWM_OUT);\
ll_timer_start(TIMER0);\
}while(0);
#endif
#define __dsd1793_iic_write_1byte(data)\
do{\
ll_iic_master_tx(DSD1793_IIC, data, LL_IIC_NONE_FLAG);\
}while(0);
#define __dsd1793_iic_read_1byte(data)\
do{\
data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_NONE_FLAG);\
}while(0);
#define __dsd1793_iic_write(reg, p_data, len)\
do{\
uint8 *__p_data = (uint8 *)p_data;\
if(__p_data){\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
__dsd1793_iic_write_1byte(reg);\
if(len){\
for(uint16 __len=0; __len<len-1; __len++){\
__dsd1793_iic_write_1byte(*__p_data++);\
}\
}\
ll_iic_master_tx(DSD1793_IIC, *__p_data, LL_IIC_STOP_FLAG);\
}\
}while(0);
#define __dsd1793_iic_read(reg, p_data, len)\
do{\
uint8 *__p_data = (uint8 *)p_data;\
if(__p_data){\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
__dsd1793_iic_write_1byte(reg);\
ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 1, LL_IIC_START_FLAG);\
if(len){\
for(uint16 __len=0; __len<len-1; __len++){\
__dsd1793_iic_read_1byte(*__p_data++);\
}\
}\
*__p_data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_STOP_FLAG | LL_IIC_NACK_FLAG);\
}\
}while(0);
#endif
#define __dsd1793_delay_ms(x) os_sleep_ms(x)
/*!
* DSD1793 reg index define
*/
#define DSD1793_REG16 16
#define DSD1793_REG17 17
#define DSD1793_REG18 18
#define DSD1793_REG19 19
#define DSD1793_REG20 20
#define DSD1793_REG21 21
#define DSD1793_REG22 22
void dsd1793_reg_write_l8bit(uint16 reg, uint16 val_l8bit);
void dsd1793_reg_read_l8bit(uint16 reg, uint16 *val_l8bit);
void dsd1793_init(void);
#endif
#ifdef __cplusplus
}
#endif
#endif
/******************************** END OF FILE *****/

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#ifndef _AUEQ_H
#define _AUEQ_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUEQ ioctl_cmd type
*/
enum aueq_ioctl_cmd {
/*!
* @brief:
*
*/
AUEQ_IOCTL_CMD_NONE,
};
/* AUEQ api for user */
struct aueq_device {
struct dev_obj dev;
};
struct aueq_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32(*close)(struct aueq_device *aueq);
int32(*run)(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32(*ioctl)(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUEQ API functions */
/**
* @brief aueq_open
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
/**
* @brief aueq_close
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_close(struct aueq_device *aueq);
/**
* @brief aueq_encode
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
/**
* @brief aueq_ioctl
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef BIQUAD_FILTER_H
#define BIQUAD_FILTER_H
typedef int s32, S32;
typedef unsigned int u32, U32, uint;
typedef long long int s64, S64;
typedef unsigned long long u64, U64;
typedef short int s16, S16;
typedef unsigned short int u16, U16;
typedef signed char s8, S8;
typedef unsigned char u8, U8;
//模拟64bit芯片运算
int CLIP_INT24(int in);
int CLIP_INT16(int in);
void ML0(s32 x, s32 y);
void MLA(s32 x, s32 y);
void MSB(s32 x, s32 y);
s32 MLZ(s32 n);
s32 MLZ_QUICK(s32 n);
s32 MLZ_FIX(s32 n);
u32 get_acc_64_high_32(void);
u32 get_acc_64_low_32(void);
typedef struct {
int b[3];
int a[2];
int x[2];
int y[2];
int fixed_point_num;
} TYPE_BIQUAD_FILTER;
int biquad_filter_calc(TYPE_BIQUAD_FILTER *filter_ctl, int x);
//void biquad_filter_ctl_init(TYPE_BIQUAD_FILTER *filter_ctl, int fixed_point_num);
#if 0
void eq_lpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_hpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_bpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_notch_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_apf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_peaking_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_low_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_high_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
#endif
#endif /* BIQUAD_FILTER_H */

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sdk/include/dev/audio/components/eq/coeff_type.h Normal file
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#ifndef _COEFF_TYPE_H
#define _COEFF_TYPE_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
* @brief coefficient configuration
* @note
* only for software.
* a example of coefficient for 5 band:
* struct aueq_cfg cfg[5];
* cfg[0].b[0] = 0.1;
* cfg[0].b[1] = 0.3;
* ...
* cfg[1].b[1] = 0.6;
*/
struct aueq_cfg_5band{
double b[3];
double a[2];
};
/*!
* @brief coefficient configuration
* @note
* only for chip.
*/
struct aueq_cfg_10band{
int32 coeff[50];
};
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _EQ_COEFF_H
#define _EQ_COEFF_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

19
sdk/include/dev/audio/components/eq/hg_aueq_v0.h Normal file
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#ifndef _HG_AUEQ_V0_H_
#define _HG_AUEQ_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aueq_v0_init(void);
int32 hg_aueq_v0_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v0_close(struct aueq_device *aueq);
int32 hg_aueq_v0_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v0_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUEQ_V0_H_ */

19
sdk/include/dev/audio/components/eq/hg_aueq_v1.h Normal file
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#ifndef _HG_AUEQ_V1_H_
#define _HG_AUEQ_V1_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aueq_v1_init(void);
int32 hg_aueq_v1_open(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v1_close(struct aueq_device *aueq);
int32 hg_aueq_v1_run(struct aueq_device *aueq, void* p_content, uint32 bytes);
int32 hg_aueq_v1_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUEQ_V0_H_ */

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#ifndef _AUFADE_H
#define _AUFADE_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUFADE calculate mode types
*/
enum aufade_mode {
AUFADE_IN = BIT(0),
AUFADE_OUT = BIT(1),
};
/**
* @brief AUFADE irq_flag type
*/
enum aufade_irq_flag {
/*!
* @brief:
*
*/
AUFADE_IRQ_FLAG_NONE = BIT(0),
};
/**
* @brief AUFADE ioctl_cmd type
*/
enum aufade_ioctl_cmd {
AUFADE_IOCTL_CMD_GET_CURRENT_VOL = BIT(0),
AUFADE_IOCTL_CMD_CHECK_IS_DONE = BIT(1),
};
/* User interrupt handle */
typedef void (*aufade_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUFADE api for user */
struct aufade_device {
struct dev_obj dev;
};
struct aufade_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aufade_device *aufade);
int32(*close)(struct aufade_device *aufade);
int32(*start)(struct aufade_device *aufade, uint32 from, uint32 to);
int32(*ioctl)(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
};
/* AUFADE API functions */
/**
* @brief aufade_open
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_open(struct aufade_device *aufade);
/**
* @brief aufade_close
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_close(struct aufade_device *aufade);
/**
* @brief aufade_start
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_start(struct aufade_device *aufade, uint32 from, uint32 to);
/**
* @brief aufade_ioctl
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aufade_request_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aufade_release_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
int32 aufade_get_cur_vol(struct aufade_device *aufade, uint32 *vol);
int32 aufade_check_is_done(struct aufade_device *aufade, uint32 *result);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/audio/components/fade/hg_aufade_v0.h Normal file
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#ifndef _HG_AUFADE_V0_H_
#define _HG_AUFADE_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aufade_v0_init(void);
int32 hg_aufade_v0_open(struct aufade_device *aufade);
int32 hg_aufade_v0_close(struct aufade_device *aufade);
int32 hg_aufade_v0_start(struct aufade_device *aufade, uint32 from, uint32 to);
int32 hg_aufade_v0_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aufade_v0_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aufade_v0_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUFADE_V0_H_ */

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sdk/include/dev/audio/components/hg_audio_v0.h Normal file
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#ifndef _HG_AUDIO_V0_H_
#define _HG_AUDIO_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
/*!
* Type of device
*/
#define AUDIO_TYPE_AUADC BIT(0)
#define AUDIO_TYPE_AUDAC BIT(1)
#define AUDIO_TYPE_AUHS BIT(2)
#define AUDIO_TYPE_AUVAD BIT(3)
#define AUDIO_TYPE_AUALAW BIT(4)
#define AUDIO_TYPE_AUFADE BIT(5)
#define AUDIO_TYPE_AUEQ BIT(6)
#define AUDIO_TYPE_AUASRC BIT(7)
#define AUDIO_TYPE_AUDRC BIT(8)
/** @brief AUDIO operating handle structure
* @{
*/
/*!
* Common dat areas struct
*/
union __comm_dat{
uint32 comm;
struct {
uint32 adc_en :1,
dac_en :1,
hs_en :1,
alaw_en :1,
vad_en :1,
aufade_en :1,
eq_en :1,
asrc_en :1,
drc_en :1,
ana_power_on :1,
ana_power_adc_on :1,
ana_power_dac_on :1,
ana_rc_cali_ok :1,
ana_driver_version :2,
ana_rfb_level :2,
ana_rin_level :2;
} comm_bits;
};
struct hg_audio_v0 {
/* Pointer of device */
struct dev_obj dev;
uint32 hw;
/* common areas */
union __comm_dat comm_dat;
/* Pointer of common areas */
void *p_comm;
void *irq_hdl;
uint32 irq_data;
uint16 irq_num;
/* Type of device */
uint16 dev_type;
};
int32 hg_audio_v0_attach(uint32 dev_id, struct hg_audio_v0 *audio);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

89
sdk/include/dev/audio/components/hw/hg_audio_ana_cfg.h Normal file
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#ifndef __HG_AUDIO_ANA_CFG_H
#define __HG_AUDIO_ANA_CFG_H
#ifdef __cplusplus
extern "C" {
#endif
//DAC+PGA
#define DAC_DRIVER_VERSION0 (0x0)
//1bit PWM
#define DAC_DRIVER_VERSION1 (0x1)
//DAC
#define DAC_DRIVER_VERSION2 (0x2)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_44_1K (1)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_48K (2)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_32K (3)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_16K (4)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_8K (5)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_11_025K (6)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_22_05K (7)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_24K (8)
#define __AUDIO_ADC_ANA_CFG_SAMPLE_RATE_12K (10)
/*!
* mic type: difference
*/
#define __AUDIO_ADC_ANA_CFG_MIC_TYPE_DIFF (1)
/*!
* mic type: single ended
*/
#define __AUDIO_ADC_ANA_CFG_MIC_TYPE_SINGE (2)
struct __audio_adc_ana_cfg {
uint16 sample_rate;
uint16 mic_type;
uint8 set_rfb;
uint8 set_rin;
};
struct __audio_dac_ana_cfg {
uint16 driver_version;
};
struct __audio_comm_ana_cfg {
union {
uint32 comm;
struct {
uint32 audio_ref1 :6,
audio_ref2 :6,
audio_c2 :6;
}comm_bits;
};
};
struct __audio_dac_digital_cfg {
uint32 target_vol;
};
struct __audio_dac_digital_cfg dac_digital_cfg;
struct __audio_ana_cfg {
struct __audio_adc_ana_cfg adc;
struct __audio_dac_ana_cfg dac;
struct __audio_comm_ana_cfg comm;
};
void audio_ana_config_power_on(void *cfg);
void audio_ana_config_power_off(void *cfg);
void audio_ana_config_adc_on(void *cfg);
void audio_ana_config_adc_off(void *cfg);
void audio_ana_config_dac_on(void *cfg);
void audio_ana_config_dac_off(void *cfg);
void audio_ana_config_dac_voice_off(void *cfg);
void audio_ana_config_dac_voice_on(void *cfg);
void audio_ana_config_rc_cali(void *cfg);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/audio/components/hw/hg_audio_v0_hw.h Normal file
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#ifndef _HG_AUDIO_V0_HW_H
#define _HG_AUDIO_V0_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
*DIGI_PATH_CTL
*/
#define LL_AUDIO_DIGI_PATH_CTL_ADC_MODE(x) (((x)&0x3) << (0x1e))
#define LL_AUDIO_DIGI_PATH_CTL_DAC_MODE(x) (((x)&0x3) << (0x1c))
#define LL_AUDIO_DIGI_PATH_CTL_DRC_DIRECT_EN(x) (((x)&0x1) << (0x1b))
#define LL_AUDIO_DIGI_PATH_CTL_ASRC_DIRECT_EN(x) (((x)&0x1) << (0x1a))
#define LL_AUDIO_DIGI_PATH_CTL_EQ_DIRECT_EN(x) (((x)&0x1) << (0x19))
#define LL_AUDIO_DIGI_PATH_CTL_XU_SET(x) (((x)&0x7) << (0xe ))
#define LL_AUDIO_DIGI_PATH_CTL_ALPHA_SEL(x) (((x)&0x3) << (0xc ))
#define LL_AUDIO_DIGI_PATH_CTL_MXS_DWA_EN(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_DIGI_PATH_CTL_VOLEN(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_DIGI_PATH_CTL_AGCEN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DIGI_PATH_CTL_ADCHP(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_DIGI_PATH_CTL_DACM(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_DIGI_PATH_CTL_ADCEN(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DIGI_PATH_CTL_DACEN(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_CTL
*/
#define LL_AUDIO_DAC_DMA_CTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_DMA_CTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_DMA_CTL_SKIPDATA(x) (((x)&0x3) << (0x6 ))
#define LL_AUDIO_DAC_DMA_CTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DAC_DMA_CTL_DATAMODE(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_DMA_CTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_DMA_CTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_WCTL
*/
#define LL_AUDIO_DAC_DMA_WCTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_DMA_WCTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_DMA_WCTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_DAC_DMA_WCTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_DMA_WCTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*ADC_DMA_CTL
*/
#define LL_AUDIO_ADC_DMA_CTL_TH1(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_ADC_DMA_CTL_TH0(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_ADC_DMA_CTL_RELOAD(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_ADC_DMA_CTL_DMASTOP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_ADC_DMA_CTL_DMASTART(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_DMA_STADR
*/
#define LL_AUDIO_DAC_DMA_STADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*DAC_DMA_WSTADR
*/
#define LL_AUDIO_DAC_DMA_WSTADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*ADC_DMA_STADR
*/
#define LL_AUDIO_ADC_DMA_STADR_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*DAC_DMA_LEN
*/
#define LL_AUDIO_DAC_DMA_LEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_DMA_WLEN
*/
#define LL_AUDIO_DAC_DMA_WLEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*ADC_DMA_LEN
*/
#define LL_AUDIO_ADC_DMA_LEN_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_SAMP_IDX
*/
#define LL_AUDIO_DAC_SAMP_IDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*DAC_SAMP_WIDX
*/
#define LL_AUDIO_DAC_SAMP_WIDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*ADC_SAMP_IDX
*/
#define LL_AUDIO_ADC_SAMP_IDX_IDX(x) (((x)&0xffff) << (0x0 ))
/*!
*AUDIO_IP
*/
#define LL_AUDIO_AUDIO_IP_DAC_WR_TH1IP(x) (((x)&0x1) << (0x15))
#define LL_AUDIO_AUDIO_IP_DAC_WR_TH0IP(x) (((x)&0x1) << (0x14))
#define LL_AUDIO_AUDIO_IP_DAC_WR_DONEIP(x) (((x)&0x1) << (0x13))
#define LL_AUDIO_AUDIO_IP_CORDIC_OVIP(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_AUDIO_IP_VOL_OVIP(x) (((x)&0x1) << (0x11))
#define LL_AUDIO_AUDIO_IP_HS_DMAOVIP(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_AUDIO_IP_HS_DMAHFIP(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_AUDIO_IP_CODEC_DMAOVIP(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_AUDIO_IP_CODEC_DMAHFIP(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_AUDIO_IP_VAD_WINOVIP(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_AUDIO_IP_VAD_DMAOVIP(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_AUDIO_IP_VAD_DMAHFIP(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_AUDIO_IP_VAD_ZCRIP(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_AUDIO_IP_VAD_POWER1IP(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_AUDIO_IP_VAD_POWER0IP(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_AUDIO_IP_VADIP(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_AUDIO_IP_ADCTH1IP(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_AUDIO_IP_ADCTH0IP(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_AUDIO_IP_ADCDONEIP(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_AUDIO_IP_DACTH1IP(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_AUDIO_IP_DACTH0IP(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_AUDIO_IP_DACDONEIP(x) (((x)&0x1) << (0x0 ))
/*!
*AUDIO_IE
*/
#define LL_AUDIO_AUDIO_IE_CORDIC_OVIE(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_AUDIO_IE_HS_DMAOVIE(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_AUDIO_IE_HS_DMAHFIE(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_AUDIO_IE_CODEC_DMAOVIE(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_AUDIO_IE_CODEC_DMAHFIE(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_AUDIO_IE_VAD_WINOVIE(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_AUDIO_IE_VAD_DMAOVIE(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_AUDIO_IE_VAD_DMAHFIE(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_AUDIO_IE_VAD_ZCRIE(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_AUDIO_IE_VAD_POWER1IE(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_AUDIO_IE_VAD_POWER0IE(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_AUDIO_IE_VADIE(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_AUDIO_IE_ADCTH1IE(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_AUDIO_IE_ADCTH0IE(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_AUDIO_IE_ADCDONEIE(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_AUDIO_IE_DACTH1IE(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_AUDIO_IE_DACTH0IE(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_AUDIO_IE_DACDONEIE(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_FLT_CTL
*/
#define LL_AUDIO_DAC_FLT_CTL_SDM_DC(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_DAC_FLT_CTL_SDM_GAIN(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_DAC_FLT_CTL_HK_SEL(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_DAC_FLT_CTL_MASH_SEL(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_DAC_FLT_CTL_ANA_CLK_SEL(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_DAC_FLT_CTL_PDM_OUT_EN(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_DAC_FLT_CTL_NOISE_WIDTH(x) (((x)&0x1f) << (0x7 ))
#define LL_AUDIO_DAC_FLT_CTL_NOSIE_EN(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_DAC_FLT_CTL_OSR_SEL(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_FLT_CTL_BAND_SEL(x) (((x)&0x3) << (0x0 ))
/*!
*DAC_MIX_CTL
*/
#define LL_AUDIO_DAC_MIX_CTL_RGAIN(x) (((x)&0xff) << (0x8 ))
#define LL_AUDIO_DAC_MIX_CTL_LGAIN(x) (((x)&0xff) << (0x0 ))
/*!
*DAC_VOL_CTL0
*/
#define LL_AUDIO_DAC_VOL_CTL0_D_VOL(x) (((x)&0x7fff) << (0x11))
#define LL_AUDIO_DAC_VOL_CTL0_S_VOL(x) (((x)&0x7fff) << (0x2 ))
#define LL_AUDIO_DAC_VOL_CTL0_VOL_DIR(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_DAC_VOL_CTL0_VOL_KICK(x) (((x)&0x1) << (0x0 ))
/*!
*DAC_VOL_CTL1
*/
#define LL_AUDIO_DAC_VOL_CTL1_DAC_VOL(x) (((x)&0x7fff) << (0x4 ))
#define LL_AUDIO_DAC_VOL_CTL1_VOL_STEP(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_DAC_VOL_CTL1_VOL_SAMP(x) (((x)&0x3) << (0x0 ))
/*!
*ADC_FLT_CTL
*/
#define LL_AUDIO_ADC_FLT_CTL_ADCGAIN(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_ADC_FLT_CTL_XU_SET(x) (((x)&0x7) << (0x15))
#define LL_AUDIO_ADC_FLT_CTL_SMP_CYC(x) (((x)&0x3) << (0x13))
#define LL_AUDIO_ADC_FLT_CTL_ANA_CLK_SEL(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_ADC_FLT_CTL_ALPHA_SET(x) (((x)&0x3) << (0x9 ))
#define LL_AUDIO_ADC_FLT_CTL_MXS_DWA_EN(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_ADC_FLT_CTL_MXS_DWA_CLK_EN(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_ADC_FLT_CTL_NOSIE_EN(x) (((x)&0x1) << (0x6 ))
#define LL_AUDIO_ADC_FLT_CTL_X2_MODE_EN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_ADC_FLT_CTL_OSR_SEL(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_ADC_FLT_CTL_BAND_SEL(x) (((x)&0x3) << (0x0 ))
/*!
*DAC_ANA_CTL
*/
#define LL_AUDIO_DAC_ANA_CTL_TESTEN(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_DAC_ANA_CTL_SELVCM(x) (((x)&0x7f) << (0x14))
#define LL_AUDIO_DAC_ANA_CTL_DAC_EN(x) (((x)&0x1) << (0x13))
#define LL_AUDIO_DAC_ANA_CTL_DACOUTPD(x) (((x)&0x1) << (0x12))
#define LL_AUDIO_DAC_ANA_CTL_EN_COREOP(x) (((x)&0x1) << (0x11))
#define LL_AUDIO_DAC_ANA_CTL_EN_OUTPUTOP(x) (((x)&0x1) << (0x10))
#define LL_AUDIO_DAC_ANA_CTL_EN_VCM(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_DAC_ANA_CTL_MUTE(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_DAC_ANA_CTL_VCMPD(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_DAC_ANA_CTL_GSET(x) (((x)&0x3) << (0xb ))
#define LL_AUDIO_DAC_ANA_CTL_GSEL(x) (((x)&0x7) << (0x8 ))
#define LL_AUDIO_DAC_ANA_CTL_ISET(x) (((x)&0xff) << (0x0 ))
/*!
*ADC_ANA_CTL0
*/
#define LL_AUDIO_ADC_ANA_CTL0_SEL_REFSOURCE(x) (((x)&0x3) << (0x1e))
#define LL_AUDIO_ADC_ANA_CTL0_EN_VCMLPF(x) (((x)&0x1) << (0x1d))
#define LL_AUDIO_ADC_ANA_CTL0_SW_VCM2PAD(x) (((x)&0x1) << (0x1c))
#define LL_AUDIO_ADC_ANA_CTL0_EN_V2I(x) (((x)&0x1) << (0x1b))
#define LL_AUDIO_ADC_ANA_CTL0_EN_LDO27(x) (((x)&0x1) << (0x1a))
#define LL_AUDIO_ADC_ANA_CTL0_EN_BG(x) (((x)&0x1) << (0x19))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VCC27AU(x) (((x)&0x7) << (0x16))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VREF100(x) (((x)&0xf) << (0x12))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_VCMAU(x) (((x)&0xf) << (0xe ))
#define LL_AUDIO_ADC_ANA_CTL0_TEST_KICK_P(x) (((x)&0x1) << (0xd ))
#define LL_AUDIO_ADC_ANA_CTL0_TEST_KICK_N(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_ADC_ANA_CTL0_SW_PGA2ADC(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_ADC_ANA_CTL0_SW_PAD2ADC(x) (((x)&0x1) << (0xa ))
#define LL_AUDIO_ADC_ANA_CTL0_EN_AUADC(x) (((x)&0x1) << (0x9 ))
#define LL_AUDIO_ADC_ANA_CTL0_EN_AUADCBIAS(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_LDO11VOLT(x) (((x)&0xf) << (0x4 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_SDDIV(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_ADC_ANA_CTL0_SEL_LDO11R1(x) (((x)&0x3) << (0x0 ))
/*!
*ADC_ANA_CTL1
*/
#define LL_AUDIO_ADC_ANA_CTL1_TEST_OK_N(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_ADC_ANA_CTL1_TEST_OK_P(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_ADC_ANA_CTL1_TEST_EN(x) (((x)&0x1) << (0x0 ))
/*!
*ADC_ANA_CTL2
*/
#define LL_AUDIO_ADC_ANA_CTL2_RESERVED(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*MIC_ANA_CTL0
*/
#define LL_AUDIO_MIC_ANA_CTL0_EN_PGASEM(x) (((x)&0x1) << (0x8 ))
#define LL_AUDIO_MIC_ANA_CTL0_EN_PGADFM(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_MIC_ANA_CTL0_SATOPGA(x) (((x)&0x7) << (0x4 ))
#define LL_AUDIO_MIC_ANA_CTL0_SEL_PGA2RIN(x) (((x)&0x3) << (0x2 ))
#define LL_AUDIO_MIC_ANA_CTL0_SEL_PGA1RIN(x) (((x)&0x3) << (0x0 ))
/*!
*MIC_ANA_CTL1
*/
#define LL_AUDIO_MIC_ANA_CTL1_RESERVED(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*VAD_CTL0
*/
#define LL_AUDIO_VAD_CTL0_SIGN_CALC_EN(x) (((x)&0x1) << (0xf ))
#define LL_AUDIO_VAD_CTL0_AUTO_CLR_EN(x) (((x)&0x1) << (0xe ))
#define LL_AUDIO_VAD_CTL0_WAIT_SPAC_TIME(x) (((x)&0xff) << (0x6 ))
#define LL_AUDIO_VAD_CTL0_ZCR_OV0_EN(x) (((x)&0x1) << (0x5 ))
#define LL_AUDIO_VAD_CTL0_POWER_OV1_EN(x) (((x)&0x1) << (0x4 ))
#define LL_AUDIO_VAD_CTL0_POWER_OV0_EN(x) (((x)&0x1) << (0x3 ))
#define LL_AUDIO_VAD_CTL0_AUTO_MODE_EN(x) (((x)&0x1) << (0x2 ))
#define LL_AUDIO_VAD_CTL0_VAD_KICK(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_VAD_CTL0_VADEN(x) (((x)&0x1) << (0x0 ))
/*!
*VAD_CTL1
*/
#define LL_AUDIO_VAD_CTL1_POWER_TH1(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_VAD_CTL1_POWER_TH0(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_CTL2
*/
#define LL_AUDIO_VAD_CTL2_ZCR_TH0(x) (((x)&0xff) << (0x18))
#define LL_AUDIO_VAD_CTL2_WINDOW_NUM(x) (((x)&0xff) << (0x10))
#define LL_AUDIO_VAD_CTL2_WINDOW_LEN(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_DMA_CTL
*/
#define LL_AUDIO_VAD_DMA_CTL_DMA_SHITF(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_DMA_STADR
*/
#define LL_AUDIO_VAD_DMA_STADR_DMA_STADR(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*VAD_DMA_CNT
*/
#define LL_AUDIO_VAD_DMA_CNT_ZCR_RES(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_VAD_DMA_CNT_DMA_CNT(x) (((x)&0xffff) << (0x0 ))
/*!
*VAD_STA
*/
#define LL_AUDIO_VAD_STA_POWER_RES_DB(x) (((x)&0xffffffff)<< (0x0 ))
/*!
*CORDIC_CTL0
*/
#define LL_AUDIO_CORDIC_CTL0_THETA(x) (((x)&0xffff) << (0x1 ))
#define LL_AUDIO_CORDIC_CTL0_CORDIC_KICK(x) (((x)&0x1) << (0x0 ))
/*!
*CORDIC_STA
*/
#define LL_AUDIO_CORDIC_STA_COS_DATA(x) (((x)&0xffff) << (0x10))
#define LL_AUDIO_CORDIC_STA_SIN_DATA(x) (((x)&0xffff) << (0x0 ))
/*!
*EQ_CON0
*/
#define LL_AUDIO_EQ_CON0_EQ_GAIN(x) (((x)&0x1fff) << (0xd ))
#define LL_AUDIO_EQ_CON0_EQ_COEFF_SW(x) (((x)&0x1) << (0xc ))
#define LL_AUDIO_EQ_CON0_EQ_ROUND_MODE(x) (((x)&0x1) << (0xb ))
#define LL_AUDIO_EQ_CON0_EQ_DSM_EN(x) (((x)&0x3ff) << (0x1 ))
#define LL_AUDIO_EQ_CON0_EQ_EN(x) (((x)&0x1) << (0x0 ))
/*!
*EQ_CON1
*/
#define LL_AUDIO_EQ_CON1_EQ_COEFF_RD(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_WR(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_WDATA(x) (((x)&0x3fffff) << (0x8 ))
#define LL_AUDIO_EQ_CON1_EQ_COEFF_SEL(x) (((x)&0x1) << (0x7 ))
#define LL_AUDIO_EQ_CON1_EQ_ADDR(x) (((x)&0x7f) << (0x0 ))
/*!
*EQ_CON2
*/
#define LL_AUDIO_EQ_CON2_EQ_DONE(x) (((x)&0x1) << (0x1f))
#define LL_AUDIO_EQ_CON2_EQ_SW_DONE(x) (((x)&0x1) << (0x1e))
#define LL_AUDIO_EQ_CON2_EQ_COEFF_NUM(x) (((x)&0x1) << (0x1d))
#define LL_AUDIO_EQ_CON2_EQ_COEFF_RDATA(x) (((x)&0x3fffff) << (0x0 ))
/*!
*ASRC_CON0
*/
#define LL_AUDIO_ASRC_CON0_SAMPLE_OFS(x) (((x)&0x3fffff) << (0xa ))
#define LL_AUDIO_ASRC_CON0_SAMPLE_CNT(x) (((x)&0x1ff) << (0x1 ))
#define LL_AUDIO_ASRC_CON0_ASRC_EN(x) (((x)&0x1) << (0x0 ))
/*!
*ASRC_STA
*/
#define LL_AUDIO_ASRC_STA_FIFO_FULL(x) (((x)&0x1) << (0x1 ))
#define LL_AUDIO_ASRC_STA_FIFO_EMPTY(x) (((x)&0x1) << (0x0 ))
/*!
*DRC_CON0
*/
#define LL_AUDIO_DRC_CON0_KNEE1_OP(x) (((x)&0x7f) << (0x19))
#define LL_AUDIO_DRC_CON0_KNEE1_IP(x) (((x)&0x1f) << (0x14))
#define LL_AUDIO_DRC_CON0_NOISE_SLOPE(x) (((x)&0x3) << (0x12))
#define LL_AUDIO_DRC_CON0_SLOPE1(x) (((x)&0x7) << (0xf ))
#define LL_AUDIO_DRC_CON0_SLOPE0(x) (((x)&0x7) << (0xc ))
#define LL_AUDIO_DRC_CON0_RC_SET(x) (((x)&0x1f) << (0x7 ))
#define LL_AUDIO_DRC_CON0_ATK_SET(x) (((x)&0x1f) << (0x2 ))
#define LL_AUDIO_DRC_CON0_DRC_EN(x) (((x)&0x1) << (0x0 ))
/*!
*DRC_CON1
*/
#define LL_AUDIO_DRC_CON1_NOISE_MIN_GAIN(x) (((x)&0x1f) << (0xf ))
#define LL_AUDIO_DRC_CON1_MAX_GAIN(x) (((x)&0x3) << (0xd ))
#define LL_AUDIO_DRC_CON1_MIN_GAIN(x) (((x)&0x7) << (0xa ))
#define LL_AUDIO_DRC_CON1_KNEE2_OP(x) (((x)&0x1f) << (0x5 ))
#define LL_AUDIO_DRC_CON1_KNEE2_IP(x) (((x)&0x1f) << (0x0 ))
struct hg_audio_hw_v0 {
__IO uint32 DIGI_PATH_CTL ; // 0x0
__IO uint32 DAC_DMA_CTL ; // 0x4
__IO uint32 DAC_DMA_STADR ; // 0x8
__IO uint32 DAC_DMA_LEN ; // 0xc
__IO uint32 DAC_SAMP_IDX ; // 0x10
__IO uint32 DAC_DMA_WCTL ; // 0x14
__IO uint32 DAC_DMA_WSTADR ; // 0x18
__IO uint32 DAC_DMA_WLEN ; // 0x1c
__IO uint32 DAC_SAMP_WIDX ; // 0x20
__IO uint32 DAC_FLT_CTL ; // 0x24
__IO uint32 DAC_MIX_CTL ; // 0x28
__IO uint32 DAC_VOL_CTL0 ; // 0x2c
__IO uint32 DAC_VOL_CTL1 ; // 0x30
__IO uint32 reserve0[51] ; // 0x34-0xfc
__IO uint32 ADC_DMA_CTL ; // 0x100
__IO uint32 ADC_DMA_STADR ; // 0x104
__IO uint32 ADC_DMA_LEN ; // 0x108
__IO uint32 ADC_SAMP_IDX ; // 0x10c
__IO uint32 ADC_FLT_CTL ; // 0x110
__IO uint32 AUDIO_IP ; // 0x114
__IO uint32 AUDIO_IE ; // 0x118
__IO uint32 ADC_RCCAL_CON ; // 0x11c
__IO uint32 ADC_RCCAL_STA ; // 0x120
__IO uint32 reserve1[55] ; // 0x124-0x1fc
__IO uint32 ADC_ANA_CTL0 ; // 0x200
__IO uint32 ADC_ANA_CTL1 ; // 0x204
__IO uint32 AMP_ANA_CTL0 ; // 0x208
__IO uint32 AMP_ANA_CTL1 ; // 0x20c
__IO uint32 DAC_ANA_CTL0 ; // 0x210
__IO uint32 DAC_ANA_CTL1 ; // 0x214
__IO uint32 PA_ANA_CTL0 ; // 0x218
__IO uint32 PA_ANA_CTL1 ; // 0x21c
__IO uint32 BIAS_ANA_CTL0 ; // 0x220
__IO uint32 BIAS_ANA_CTL1 ; // 0x224
__IO uint32 reserve2[54] ; // 0x228-0x2fc
__IO uint32 VAD_CTL0 ; // 0x300
__IO uint32 VAD_CTL1 ; // 0x304
__IO uint32 VAD_CTL2 ; // 0x308
__IO uint32 VAD_DMA_CTL ; // 0x30c
__IO uint32 VAD_DMA_STADR ; // 0x310
__IO uint32 VAD_DMA_CNT ; // 0x314
__IO uint32 VAD_STA ; // 0x318
__IO uint32 reserve3[281] ; // 0x31c-0x77c
__IO uint32 INCGAINTH3_0 ; // 0x780
__IO uint32 INCGAINTH5_4 ; // 0x784
__IO uint32 REDGAINTH3_0 ; // 0x788
__IO uint32 REDGAINTH5_4 ; // 0x78c
__IO uint32 GAINVAL3_0 ; // 0x790
__IO uint32 GAINVAL6_4 ; // 0x794
__IO uint32 AGC_CTL0 ; // 0x798
__IO uint32 AGC_CTL1 ; // 0x79c
__IO uint32 CODEC_CTL ; // 0x7a0
__IO uint32 CODEC_DMA_STADR ; // 0x7a4
__IO uint32 CODEC_DMA_DSTADR ; // 0x7a8
__IO uint32 CODEC_DMA_LEN ; // 0x7ac
__IO uint32 CODEC_DMA_CNT ; // 0x7b0
__IO uint32 HS_CTL0 ; // 0x7b4
__IO uint32 HS_CTL1 ; // 0x7b8
__IO uint32 HS_DMA_STADR ; // 0x7bc
__IO uint32 HS_DMA_DSTADR ; // 0x7c0
__IO uint32 HS_DMA_LEN ; // 0x7c4
__IO uint32 HS_DMA_CNT ; // 0x7c8
};
struct hg_aueq_hw_v0 {
__IO uint32 EQ_CON0;
__IO uint32 EQ_CON1;
__IO uint32 EQ_CON2;
};
struct hg_auasrc_hw_v0 {
__IO uint32 ASRC_CON0;
__IO uint32 ASRC_STA;
};
struct hg_audrc_hw_v0 {
__IO uint32 DRC_CON0;
__IO uint32 DRC_CON1;
};
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUDIO_V0_HW_H */

203
sdk/include/dev/audio/components/vad/auvad.h Normal file
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@@ -0,0 +1,203 @@
#ifndef _AUVAD_H
#define _AUVAD_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUVAD calculate mode types
*/
enum auvad_calc_mode {
AUVAD_CALC_MODE_ENERGY = BIT(0),
AUVAD_CALC_MODE_ZCR = BIT(1),
};
/**
* @brief AUVAD irq_flag type
*/
enum auvad_irq_flag {
/*!
* @brief:
*
*/
NONE = BIT(0),
};
/**
* @brief AUVAD ioctl_cmd type
*/
enum auvad_ioctl_cmd {
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_CALC_MODE,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH0,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH1,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_ZCR,
};
/* User interrupt handle */
typedef void (*auvad_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUVAD api for user */
struct auvad_device {
struct dev_obj dev;
};
struct auvad_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32(*close)(struct auvad_device *auvad);
int32(*calc)(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32(*ioctl)(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
};
/* AUVAD API functions */
/**
* @brief auvad_open
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
/**
* @brief auvad_close
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_close(struct auvad_device *auvad);
/**
* @brief auvad_encode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_encode(struct auvad_device *auvad, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief auvad_decode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
/**
* @brief auvad_ioctl
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auvad_request_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auvad_release_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif

21
sdk/include/dev/audio/components/vad/hg_auvad_v0.h Normal file
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#ifndef _HG_AUVAD_V0_H_
#define _HG_AUVAD_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auvad_v0_init(void);
int32 hg_auvad_v0_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32 hg_auvad_v0_close(struct auvad_device *auvad);
int32 hg_auvad_v0_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32 hg_auvad_v0_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auvad_v0_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auvad_v0_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUVAD_V0_H_ */

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#ifndef _HGCAPTURE_V0_H
#define _HGCAPTURE_V0_H
#include "hal/capture.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGCAPTURE_MAX_CAPTURE_CHANNEL 4
enum hgcapture_v0_func_cmd {
HGCAPTURE_V0_FUNC_CMD_MASK = BIT(7),
HGCAPTURE_V0_FUNC_CMD_INIT = HGCAPTURE_V0_FUNC_CMD_MASK | 1,
HGCAPTURE_V0_FUNC_CMD_DEINIT = HGCAPTURE_V0_FUNC_CMD_MASK | 2,
HGCAPTURE_V0_FUNC_CMD_START = HGCAPTURE_V0_FUNC_CMD_MASK | 3,
HGCAPTURE_V0_FUNC_CMD_STOP = HGCAPTURE_V0_FUNC_CMD_MASK | 4,
/* IOCTL CMD */
/* IRQ_FLAG */
HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE = HGCAPTURE_V0_FUNC_CMD_MASK | 5,
HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW = HGCAPTURE_V0_FUNC_CMD_MASK | 6,
HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ = HGCAPTURE_V0_FUNC_CMD_MASK | 7,
HGCAPTURE_V0_FUNC_CMD_SUSPEND = HGCAPTURE_V0_FUNC_CMD_MASK | 8,
HGCAPTURE_V0_FUNC_CMD_RESUME = HGCAPTURE_V0_FUNC_CMD_MASK | 9,
};
struct hgcapture_v0_config {
uint32 irq_data;
capture_irq_hdl irq_hdl;
uint16 func_cmd;
/* Only for config REG in lower layer code */
uint16 cap_sel:1,
cap_pol:1;
};
struct hgcapture_v0 {
struct capture_device dev;
void *channel[HGCAPTURE_MAX_CAPTURE_CHANNEL];
uint8 opened[HGCAPTURE_MAX_CAPTURE_CHANNEL];
};
int32 hgcapture_v0_attach(uint32 dev_id, struct hgcapture_v0 *capture);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_CRC_H_
#define _HG_CRC_H_
#include "hal/crc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_crc {
struct crc_dev dev;
void *hw;
os_mutex_t hold;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
uint16 cookie;
};
int32 hg_crc_attach(uint32 dev_id, struct hg_crc *crc_c);
#ifdef __cplusplus
}
#endif
#endif /* _HG_CRC_H_ */

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#ifndef HG_CSC_H
#define HG_CSC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/csc.h"
typedef enum {
CSC_DONE_IRQ,
CSC_IRQ_NUM
}CSC_IRQ_E;
struct hgcsc {
struct csc_device dev;
uint32 hw;
csc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hgcsc_attach(uint32 dev_id, struct hgcsc *csc);
#endif

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#ifndef HG_DVP_H
#define HG_DVP_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dvp.h"
#ifdef TXW80X
typedef enum {
HSIE_ISR = 0,
VSIE_ISR,
SSCIE_EIGHT_ISR,
FHFIE_ISR,
FOVIE_ISR,
SIP_ISR,
JPEG_DONE,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
#ifdef TXW81X
typedef enum {
FOVIE_ISR = 0,
HSIP_ISR,
VSIP_ISR,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
#if TXW82X
typedef enum {
FOVIE_ISR = 0,
HSIP_ISR,
VSIP_ISR,
DVP_IRQ_NUM
}DVP_IRQ_E;
#endif
struct hgdvp {
struct dvp_device dev;
//struct hgdvp_hw *hw;
uint32 hw;
dvp_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgdvp_attach(uint32 dev_id, struct hgdvp *dvp);
#endif

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#ifndef _DW_DMAC_H_
#define _DW_DMAC_H_
#include "hal/dma.h"
#ifdef __cplusplus
extern "C" {
#endif
/*! max dmac hardware channel
*/
#define DW_DMAC_MAX_DMAC_CHN 4
/*! max dmac hardware channel mask
*/
#define DW_DMAC_MAX_DMAC_CHN_MASK 0xF
/**
* @brief DMAC controller (IP)
*/
struct dw_dmac_hw_ch {
__IO uint32 SARL;
__IO uint32 SARH;
__IO uint32 DARL;
__IO uint32 DARH;
__IO uint32 FIFO0[2]; //LLPL,LLPH, NO USE
__IO uint32 CTLL;
__IO uint32 CTLH;
__IO uint32 FIFO1[8]; //SSTATL,SSTATH,DSTATL,DSTATH,SSTATARL,SSTATARH,DSTATARL,DSTATARH
__IO uint32 CFGL;
__IO uint32 CFGH;
__IO uint32 SGRL;
__IO uint32 SGRH;
__IO uint32 DSRL;
__IO uint32 DSRH;
};
/**
* @brief DMAC
*/
struct hgdma_dw_hw {
struct dw_dmac_hw_ch CH[4];
__IO uint32 FIFO0[22*4];
__IO uint32 RawTfrL;
__IO uint32 RawTfrH;
__IO uint32 RawBlockL;
__IO uint32 RawBlockH;
__IO uint32 RawSrcTranL;
__IO uint32 RawSrcTranH;
__IO uint32 RawDstTranL;
__IO uint32 RawDstTranH;
__IO uint32 RawErrL;
__IO uint32 RawErrH;
__IO uint32 FIFO1[5*2];
__IO uint32 MaskTfrL;
__IO uint32 MaskTfrH;
__IO uint32 MaskBlockL;
__IO uint32 MaskBlockH;
__IO uint32 MaskSrcTranL;
__IO uint32 MaskSrcTranH;
__IO uint32 MaskDstTranL;
__IO uint32 MaskDstTranH;
__IO uint32 MaskErrL;
__IO uint32 MaskErrH;
__IO uint32 ClearTfrL;
__IO uint32 ClearTfrH;
__IO uint32 ClearBlockL;
__IO uint32 ClearBlockH;
__IO uint32 ClearSrcTranL;
__IO uint32 ClearSrcTranH;
__IO uint32 ClearDstTranL;
__IO uint32 ClearDstTranH;
__IO uint32 ClearErrL;
__IO uint32 ClearErrH;
__IO uint32 FIFO2[2];
__IO uint32 ReqSrcRegL;
__IO uint32 ReqSrcRegH;
__IO uint32 ReqDstRegL;
__IO uint32 ReqDstRegH;
__IO uint32 SglReqSrcRegL;
__IO uint32 SglReqSrcRegH;
__IO uint32 SglReqDstRegL;
__IO uint32 SglReqDstRegH;
__IO uint32 LstSrcRegL;
__IO uint32 LstSrcRegH;
__IO uint32 LstDstRegL;
__IO uint32 LstDstRegH;
__IO uint32 DmaCfgRegL;
__IO uint32 DmaCfgRegH;
__IO uint32 ChEnRegL;
__IO uint32 ChEnRegH;
__IO uint32 FIFO3[2];
__IO uint32 DmaTestRegL;
__IO uint32 DmaTestRegH;
};
struct hgdma_dw {
struct dma_device dev;
struct hgdma_dw_hw *hw;
uint32 irq_num;
uint32 opened;
os_semaphore_t mem_chn;
os_semaphore_t dev_chn;
os_mutex_t dev_mutex;
dma_irq_hdl irq_hdl[DW_DMAC_MAX_DMAC_CHN];
uint32 irq_data[DW_DMAC_MAX_DMAC_CHN];
uint32 state[DW_DMAC_MAX_DMAC_CHN];
uint32 chn_used_flag;
};
/** @brief DW DMAC register constant table definition
* @{
*/
/***** DW_PARAMS Register *****/
/*! number of channels
*/
#define DW_DMAC_PARAMS_NR_CHAN 4
/*! number of AHB masters
*/
#define DW_DMAC_PARAMS_NR_MASTER 2
/***** DWC_PARAMS Register *****/
/*! multi block transfer
*/
#define DW_DMACC_PARAMS_MBLK_EN 11
/***** CTLx Register *****/
/*! irqs enabled
*/
#define DW_DMAC_CTLL_INT_EN (1UL << 0)
/*! The size of each element of destination transmission.
*/
#define DW_DMAC_CTLL_DST_WIDTH(n) (((n)&0x7) << 1)
/*! The size of each element of source transmission.
*/
#define DW_DMAC_CTLL_SRC_WIDTH(n) (((n)&0x7) << 4)
/*! Indicates destination address how to change on every source transfer.
*/
#define DW_DMAC_CTLL_DST_DIR(n) (((n)&0x3) << 7)
/*! Indicates source address how to change on every source transfer.
*/
#define DW_DMAC_CTLL_SRC_DIR(n) (((n)&0x3) << 9)
/*! Number of data items to be written to de destination every time.
*/
#define DW_DMAC_CTLL_DST_MSIZE(n) (((n)&0x7) << 11)
/*! Number of data items to be read from the source every time.
*/
#define DW_DMAC_CTLL_SRC_MSIZE(n) (((n)&0x7) << 14)
/*! src gather
*/
#define DW_DMAC_CTLL_S_GATH_EN (1UL << 17)
/* dst scatter
*/
//#define DW_DMAC_CTLL_D_SCAT_EN (1UL << 18)
/*! Transfer type and flow control.
*/
#define DW_DMAC_CTLL_FC(n) (((n)&0x7) << 20)
/*! dst master select : 1 for memory, 0 for peripherals
*/
#define DW_DMAC_CTLL_DMS(n) (((n)&0x3) << 23)
/*! src master select : 1 for memory, 0 for peripherals
*/
#define DW_DMAC_CTLL_SMS(n) (((n)&0x3) << 25)
/* dest block chain
*/
//#define DW_DMAC_CTLL_LLP_D_EN (1UL << 27)
/* src block chain
*/
//#define DW_DMAC_CTLL_LLP_S_EN (1UL << 28)
/***** CTL_HI Register *****/
/*! Block transfer done
*/
#define DW_DMAC_CTLH_DONE (0x00001000)
/*! Block transfer size. The max block size is 4095.
*/
#define DW_DMAC_CTLH_BLOCK_TS_MASK (0x00000FFF)
/***** CFG_LO Register *****/
/*! Channel priority mask
*/
#define DW_DMAC_CFGL_CH_PRIOR_MASK (0x7UL << 5)
/*! Channel priority
*/
#define DW_DMAC_CFGL_CH_PRIOR(n) (((n)&0x7) << 5)
/*! Channle Suspend. Suspends all DMA data transfers from the source until this
* bit is cleared.
*/
#define DW_DMAC_CFGL_CH_SUSP (1UL << 8)
/*! Indicates if there is data left in the channel FIFO.
*/
#define DW_DMAC_CFGL_FIFO_EMPTY (1UL << 9)
/*! Destination software or hardware handshaking select.
*/
#define DW_DMAC_CFGL_HS_DST (1UL << 10)
/*! Source software or hardware handshaking select.
*/
#define DW_DMAC_CFGL_HS_SRC (1UL << 11)
//#define DW_DMAC_CFGL_LOCK_CH_LEVEL(n) (((n)&0x3) << 12)
//#define DW_DMAC_CFGL_LOCK_BUS_LEVEL(n) (((n)&0x3) << 14)
//#define DW_DMAC_CFGL_LOCK_CH (1UL << 16)
//#define DW_DMAC_CFGL_LOCK_BUS (1UL << 17)
/*! Destination handshaking interface polarity.
*/
#define DW_DMAC_CFGL_HS_DST_POL (1UL << 18)
/*! Source handshaking interface polarity.
*/
#define DW_DMAC_CFGL_HS_SRC_POL (1UL << 19)
/*! Maximum AMBA burst length that is used for DMA transfers on this channel.
*/
#define DW_DMAC_CFGL_MAX_BURST(n) (((n)&0x2FF) << 20)
/*! Automatic source reload.
*/
#define DW_DMAC_CFGL_RELOAD_SAR (1UL << 30)
/*! Automatic desination reload.
*/
#define DW_DMAC_CFGL_RELOAD_DAR (1UL << 31)
/***** CFG_HI Register *****/
/*! Flow control mode.
*/
#define DW_DMAC_CFGH_FCMODE (1UL << 0)
/*! FIFO mode select.
*/
#define DW_DMAC_CFGH_FIFO_MODE (1UL << 1)
/*! Protection control.
*/
#define DW_DMAC_CFGH_PROTCTL(n) (((n)&0x7) << 2)
//#define DW_DMAC_CFGH_DS_UPD_EN (1UL << 5)
//#define DW_DMAC_CFGH_SS_UPD_EN (1UL << 6)
/*! Assigns a hardware handshaking interface to the source of channel.
*/
#define DW_DMAC_CFGH_SRC_PER(n) (((n)&0xF) << 7)
/*! Assigns a hardware handshaking interface to the destination of channel.
*/
#define DW_DMAC_CFGH_DST_PER(n) (((n)&0xF) << 11)
/***** SGR Register *****/
/*! Source gather interval.
*/
#define DW_DMAC_SGR_SGI(n) (((n)&0xFFFFF) << 0)
/*! Source gather count.
*/
#define DW_DMAC_SGR_SGC(n) (((n)&0xF) << 20)
/***** DSR Register *****/
//#define DW_DMAC_DSR_DSI(x) (((n)&0xFFFFF) << 0)
//#define DW_DMAC_DSR_DSC(x) (((n)&0xF) << 20)
/***** DmaCfgReg Register *****/
/*! dmac enable.
*/
#define DW_DMAC_CFG_DMA_EN (1UL << 0)
/***** ChEnRegL/MaskTfrL/MaskErrL/MaskDstTranL/MaskSrcTranL/MaskBlockL/ Register *****/
/*! Source gather count.
*/
#define DW_DMAC_WRITE_EN(n) ((1 << (n+8)) | (1 << n))
/*! Source gather count.
*/
#define DW_DMAC_WRITE_DIS(n) (1 << (n+8))
#define DW_DMAC_XFER_DONE(n) (1 << (n))
#define DW_DMAC_XFER_ERR(n) (1 << (n+8))
/**
* @}
*/
/** @brief DW DMAC external constant definition
* @{
*/
/**
* @breif Number of data items to be transferred(of width TR_WIDTH)
*/
enum dw_dmac_msize {
/*! damc data width : 1 TR_WIDTH
*/
DW_DMAC_MSIZE_1,
/*! damc data width : 4 TR_WIDTH
*/
DW_DMAC_MSIZE_4,
/*! damc data width : 8 TR_WIDTH
*/
DW_DMAC_MSIZE_8,
// The following MSIZE is not supported.
// DW_DMAC_MSIZE_16,
// DW_DMAC_MSIZE_32,
// DW_DMAC_MSIZE_64,
// DW_DMAC_MSIZE_128,
// DW_DMAC_MSIZE_256,
};
/**
* @brief The size of each element of destination transmission. The unit is bit.
*/
enum dw_dmac_tr_width {
/*! damc xfer width : 8 bit
*/
DW_DMAC_TR_8,
/*! damc xfer width : 16bit
*/
DW_DMAC_TR_16,
/*! damc xfer width : 32bit
*/
DW_DMAC_TR_32,
// The following TR_WIDTH is not supported.0
// DW_DMAC_TR_64,
// DW_DMAC_TR_128,
// DW_DMAC_TR_256,
};
/**
* @brief Indicates destination address how to change on every source transfer.
*/
enum dw_dmac_addr_dir {
/*! Increment
*/
DW_DMAC_ADDR_INC,
/*! Decrement
*/
DW_DMAC_ADDR_DEC,
/*! No change
*/
DW_DMAC_ADDR_NO_CHANGE,
};
/**
* @breif flow controller
@verbatim
-------------------------------------------------------------------------------
CTLL.TT_FC Field Transfer Type Flow Controller
-------------------------------------------------------------------------------
000 Memory to Memory DW_anb_dmac
001 Memory to Peripheral DW_anb_dmac
010 Peripheral to Memory DW_anb_dmac
011 Peripheral to Peripheral DW_anb_dmac
100 Peripheral to Memory Peripheral
101 Peripheral to Peripheral Source Peripheral
110 Memory to Peripheral Peripheral
111 Peripheral to Peripheral Destination Peripheral
@endverbatim
*/
enum dw_dmac_fc {
/*! Memory to Memory
*/
DW_DMAC_FC_D_M2M,
/*! Memory to Peripheral
*/
DW_DMAC_FC_D_M2P,
/*! Peripheral to Memory
*/
DW_DMAC_FC_D_P2M,
/*! Peripheral to Peripheral
*/
DW_DMAC_FC_D_P2P,
// The following flow control is not supported.
// DW_DMAC_FC_P_P2M,
// DW_DMAC_FC_SP_P2P,
// DW_DMAC_FC_P_M2P,
// DW_DMAC_FC_DP_P2P,
};
/**
* @}
*/
int32 dw_dmac_search_src_id(uint32 addr);
int32 dw_dmac_search_dest_id(uint32 addr);
int32 dw_dmac_attach(uint32 dev_id, struct hgdma_dw *dmac);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_M2M_DMA_H_
#define _HG_M2M_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef TXW82X
#define HG_M2M_DMA_NUM (CONFI_CORE_M2M_DMA ? 2 : 3)
#define HG_M2M_DMA_MAX_LEN (1<<20)
#else
#define HG_M2M_DMA_NUM 2
#define HG_M2M_DMA_MAX_LEN (64<<10)
#endif
/**
* @brief M2M_DMA
*/
struct mem_dma_ch {
__IO uint32 DMA_CON;
__IO uint32 DMA_SAIE;
__IO uint32 DMA_DATA;
__IO uint32 DMA_SADR;
__IO uint32 DMA_TADR;
__IO uint32 DMA_DLEN;
#ifdef TXW81X
__IO uint32 DMA_ISIZE;
#endif
};
struct mem_dma_hw {
struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
};
struct mem_dma_dev {
struct dma_device dev;
struct mem_dma_hw *hw;
uint32 irq_num[HG_M2M_DMA_NUM];
uint32 busy_flag : 8,
dma1_status : 1,
dma1_mutex : 1,
suspend : 1,
reserved : 21;
struct os_semaphore done[HG_M2M_DMA_NUM];
};
/** @brief M2M DMA register constant table definition
* @{
*/
/***** DMA_CON *****/
#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
#define HG_M2M_DMA_CON_DTE (1UL << 0)
/***** DMA_SAIE *****/
#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
/***** DMA_ISIZE *****/
#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
/***** DMA_DLEN *****/
#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
/**
* @}
*/
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dma/hg_m2m_dma_core1.h Normal file
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#ifndef _HG_M2M_DMA_H_
#define _HG_M2M_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef TXW82X
#define HG_M2M_DMA_NUM 1
#define HG_M2M_DMA_MAX_LEN (1<<20)
#else
#define HG_M2M_DMA_NUM 2
#define HG_M2M_DMA_MAX_LEN (64<<10)
#endif
/**
* @brief M2M_DMA
*/
struct mem_dma_ch {
__IO uint32 DMA_CON;
__IO uint32 DMA_SAIE;
__IO uint32 DMA_DATA;
__IO uint32 DMA_SADR;
__IO uint32 DMA_TADR;
__IO uint32 DMA_DLEN;
#ifdef TXW81X
__IO uint32 DMA_ISIZE;
#endif
};
struct mem_dma_hw {
struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
};
struct mem_dma_dev {
struct dma_device dev;
struct mem_dma_hw *hw;
uint32 irq_num[HG_M2M_DMA_NUM];
uint32 busy_flag : 8,
dma1_status : 1,
dma1_mutex : 1,
suspend : 1,
reserved : 21;
struct os_semaphore done[HG_M2M_DMA_NUM];
};
/** @brief M2M DMA register constant table definition
* @{
*/
/***** DMA_CON *****/
#define HG_M2M_DMA_CON_ENDIAN_SET(n) ((n) << 3)
#define HG_M2M_DMA_CON_ENDIAN_RES (3UL << 3)
#define HG_M2M_DMA_CON_BLKCPY (2UL << 1)
#define HG_M2M_DMA_CON_MEMSET (1UL << 1)
#define HG_M2M_DMA_CON_MEMCPY (0UL << 1)
#define HG_M2M_DMA_CON_DTE (1UL << 0)
/***** DMA_SAIE *****/
#define HG_M2M_DMA_SAIE_TCIE (1UL << 16)
#define HG_M2M_DMA_SAIE_TCP_PENDING (1UL << 0)
/***** DMA_ISIZE *****/
#define HG_M2M_DMA_ISZIE_DST_WIDTH(n) ((n) << 16)
#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n) ((n) << 0)
/***** DMA_DLEN *****/
#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n) ((n) << 20)
#define HG_M2M_DMA_DLEN_BLK_WIDTH(n) ((n) << 0)
/**
* @}
*/
int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/dma2d/hg_dma2d_v0.h Normal file
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#ifndef _HG_DMA2D_V0_H_
#define _HG_DMA2D_V0_H_
#include "hal/dma2d.h"
#include "osal/mutex.h"
#include "osal/semaphore.h"
#ifdef __cplusplus
extern "C" {
#endif
enum {
DMA2D_COLOR_SIZE_ARGB8888 = 4,
DMA2D_COLOR_SIZE_RGB888 = 3,
DMA2D_COLOR_SIZE_RGB565 = 2,
DMA2D_COLOR_SIZE_ARGB1555 = 2,
DMA2D_COLOR_SIZE_ARGB4444 = 2,
DMA2D_COLOR_SIZE_L8 = 1,
DMA2D_COLOR_SIZE_AL44 = 1,
DMA2D_COLOR_SIZE_AL88 = 2,
DMA2D_COLOR_SIZE_L4 = 0,
DMA2D_COLOR_SIZE_A8 = 1,
DMA2D_COLOR_SIZE_A4 = 0,
};
enum {
DMA2D_MODE_MEMCPY = 0,
DMA2D_MODE_CONVERT = 1,
DMA2D_MODE_MIXTURE = 2,
DMA2D_MODE_MEMSET = 3,
DMA2D_MODE_MIXTURE_BG = 4,
DMA2D_MODE_MIXTURE_FG = 5,
};
enum {
DMA2D_CLUT_FLAG_FG = 0,
DMA2D_CLUT_FLAG_BG,
};
struct hgdma2d_v0 {
struct dma2d_device dev;
uint32 hw;
uint32 fgclut;
uint32 bgclut;
uint32 irq_num;
uint32 irq_data;
uint32 result_status;
dma2d_irq_hdl irq_hdl;
struct os_mutex done_lock;
struct os_semaphore done_sema;
uint32 done : 1,
dsleep : 1,
suspend : 1,
resume : 1,
fg_clut_flag : 1,
bg_clut_flag : 1,
reserved : 26;
};
int32 hgdma2d_v0_attach(uint32 dev_id, struct hgdma2d_v0 *dma2d);
#ifdef __cplusplus
}
#endif
#endif

32
sdk/include/dev/dual/hgdual_org.h Normal file
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#ifndef HG_DUAL_H
#define HG_DUAL_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dual_org.h"
typedef enum {
ORG0_SD_ISR = 0,
ORG1_SD_ISR,
ORG_RD_DONE_IE,
ORG_RD_SLOW_IE,
DORG_IRQ_NUM,
}DORG_IRQ_E;
struct hgdual {
struct dual_device dev;
uint32 hw;
dual_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
uint32 opened:1, use_dma:1, save : 3, change_done : 1;
};
int32 hgdual_attach(uint32 dev_id, struct hgdual *dual);
#endif

92
sdk/include/dev/emac/hg_gmac_eva_v2.h Normal file
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#ifndef _HG_GMAC_EVA_V2_H_
#define _HG_GMAC_EVA_V2_H_
#include "osal/task.h"
#include "lib/net/ethphy/eth_phy.h"
#include "hal/netdev.h"
#ifdef __cplusplus
extern "C" {
#endif
#define gmac_v2_dbg(fmt, ...) os_printf(fmt, ##__VA_ARGS__)
struct hg_gmac_data_v2 {
struct hg_gmac_v2_rx_descriptor volatile *p_rx_des;
struct hg_gmac_v2_tx_descriptor volatile *p_tx_des;
uint8 *p_rx_malloc;
uint8 *p_tx_malloc;
/*! In order not to splicing buf, the buf of the last RX descriptor
* should be able to fill one frame.
*/
/*!
* struct hg_gmac_v2_tx_descriptor rx_des[rx_des_num];
* uint8 rx_buf[rx_des_num-1][HG_GMAC_V2_RX_PER_BUF_SIZE];
* uint8 last_rx_buf[HG_GMAC_V2_RX_FRAME_MAX_SIZE];
*/
uint32 rx_des_num;
struct hg_gmac_v2_rx_descriptor *p_rx_des_buf;
uint8 *p_rx_buf;
/*!
* struct hg_gmac_v2_tx_descriptor tx_des[tx_des_num];
* uint8 tx_buf[tx_des_num][HG_GMAC_V2_TX_PER_BUF_SIZE];
*/
uint32 tx_des_num;
struct hg_gmac_v2_tx_descriptor *p_tx_des_buf;
uint8 *p_tx_buf;
};
struct hg_gmac_eva_v2_statistics {
uint32 tx_cnt;
uint32 rx_cnt;
uint32 ru_pending_cnt;
uint32 rx_err_cnt;
};
struct hg_gmac_eva_v2 {
struct netdev dev;
uint32 hw;
uint32 modbus_devid,
phy_devid,
crc_devid;
struct crc_dev *crcdev;
uint32 mdio_pin;
uint32 mdc_pin;
uint32 irq_num;
uint32 opened:1, tx_nonblock:1, rev:30;
uint32 rgmii_en;
struct hg_gmac_data_v2 ctrl_data;
uint8 mac_addr[6];
netdev_input_cb input_cb;
void *input_priv;
uint32 tx_buf_size;
uint32 rx_buf_size;
os_task_t receive_task;
struct ethernet_phy_device *phydev;
struct ethernet_mdio_bus *mdio_bus;
/* Save link information */
int32 speed;
int32 duplex;
int32 link_status;
os_semaphore_t receive_sema;
os_mutex_t mdio_mutex;
os_mutex_t send_mutex;
struct hg_gmac_eva_v2_statistics statistics;
};
int32 hg_gmac_v2_attach(uint32 dev_id, struct hg_gmac_eva_v2 *gmac);
int32 hg_gmac_v2_has_received_frame(struct netdev *ndev);
int32 hg_gmac_v2_receive_data(struct netdev *emac_dev);
#ifdef __cplusplus
}
#endif
#endif

22
sdk/include/dev/gen/hggen420.h Normal file
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#ifndef HG_GEN420_H
#define HG_GEN420_H
#include "hal/gen420.h"
typedef enum {
GEN420_DONE_ISR = 0,
GEN420_IRQ_NUM,
}GEN420_IRQ_E;
struct hggen420 {
struct gen420_device dev;
uint32 hw;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hggen420_attach(uint32 dev_id, struct hggen420 *gen420);
#endif

28
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#ifndef HG_GEN422_H
#define HG_GEN422_H
#include "hal/gen422.h"
typedef enum {
GEN422_GDONE_ISR = 0,
GEN422_RDONE_ISR,
GEN422_RD_SLOW_ISR,
GEN422_WR_SLOW_ISR,
GEN422_GEN_OV_ISR,
GEN422_IRQ_NUM,
}GEN422_IRQ_E;
struct hggen422 {
struct gen422_device dev;
uint32 hw;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hggen422_attach(uint32 dev_id, struct hggen422 *gen422);
#endif

101
sdk/include/dev/gpio/hggpio_v4.h Normal file
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#ifndef _HUGEIC_GPIO_V4_H_
#define _HUGEIC_GPIO_V4_H_
#include "hal/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGGPIO_V4_MAX_PINS (16)
#ifdef HG_GPIOA_BASE
#ifndef GPIOA_BASE
#define GPIOA_BASE HG_GPIOA_BASE
#endif
#endif
#ifdef HG_GPIOB_BASE
#ifndef GPIOB_BASE
#define GPIOB_BASE HG_GPIOB_BASE
#endif
#endif
#ifdef HG_GPIOC_BASE
#ifndef GPIOC_BASE
#define GPIOC_BASE HG_GPIOC_BASE
#endif
#endif
#ifdef HG_GPIOD_BASE
#ifndef GPIOD_BASE
#define GPIOD_BASE HG_GPIOD_BASE
#endif
#endif
#ifdef HG_GPIOE_BASE
#ifndef GPIOE_BASE
#define GPIOE_BASE HG_GPIOE_BASE
#endif
#endif
#ifdef TXW80X
#define INMAP_CONST_1 0x28
#define INMAP_CONST_0 0x29
#elif defined(TXW81X)
#define INMAP_CONST_1 0x2e
#define INMAP_CONST_0 0x2f
#elif defined(TXW82X)
#define INMAP_CONST_1 0x44
#define INMAP_CONST_0 0x45
#endif
struct gpio_bk{
__IO uint32_t MODE;
__IO uint32_t OTYPE;
__IO uint32_t OSPEEDL;
__IO uint32_t OSPEEDH;
__IO uint32_t PUPL;
__IO uint32_t PUPH;
__IO uint32_t PUDL;
__IO uint32_t PUDH;
__IO uint32_t ODAT;
__IO uint32_t AFRL;
__IO uint32_t AFRH;
__IO uint32_t IMK;
__IO uint32_t DEBEN;
__IO uint32_t AIOEN;
__IO uint32_t TRG0;
__IO uint32_t IEEN;
__IO uint32_t IOFUNCOUTCON0;
__IO uint32_t IOFUNCOUTCON1;
__IO uint32_t IOFUNCOUTCON2;
__IO uint32_t IOFUNCOUTCON3;
};
struct hggpio_v4 {
struct gpio_device dev;
uint32 hw;
uint32 comm_irq_num;
int32 pin_id[HGGPIO_V4_MAX_PINS];
gpio_irq_hdl irq_hdl[HGGPIO_V4_MAX_PINS];
uint32 pin_num[2];
uint8 irq_num;
uint32_t flag;
#ifdef CONFIG_SLEEP
struct gpio_bk bk;
#endif
};
struct hggpio_v4_hw;
int32 hggpio_v4_attach(uint32 dev_id, struct hggpio_v4 *gpio);
uint32_t hggpio_v4_mask_opa(struct hggpio_v4_hw *reg, uint32_t pin_num, enum gpio_iomap_out_func func_sel, uint32_t flag);
#ifdef __cplusplus
}
#endif
#endif

29
sdk/include/dev/gpio/hggpio_v5.h Normal file
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#ifndef _HUGEIC_GPIO_V5_H_
#define _HUGEIC_GPIO_V5_H_
#include "hal/gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGGPIO_V5_MAX_PINS (16)
struct hggpio_v5 {
struct gpio_device dev;
uint32 hw;
int32 pin_id[HGGPIO_V5_MAX_PINS];
gpio_irq_hdl irq_hdl[HGGPIO_V5_MAX_PINS];
uint32 pin_num[2];
uint8 irq_num;
};
int32 hggpio_v5_attach(uint32 dev_id, struct hggpio_v5 *gpio);
#ifdef __cplusplus
}
#endif
#endif

39
sdk/include/dev/h264/hg264.h Normal file
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#ifndef HG_H264_H
#define HG_H264_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/h264.h"
typedef enum {
H264_FRAME_DONE,
H264_BUF0_FULL,
H264_BUF1_FULL,
H264_SOFT_SLOW,
H264_FRAME_FAST,
H264_PIXEL_FAST,
H264_PIXEL_DONE,
H264_ENC_TIME_OUT,
H264_DEC_FRAME_ERR,
H264_BS_LEN_ERR,
H264_CFG_W_ERR,
H264_IRQ_NUM
}H264_IRQ_E;
struct hg264 {
struct h264_device dev;
uint32 hw;
h264_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
int32 addr_count;
volatile uint32 opened:1, use_dma:1,err:1, dsleep:1,h264_clt:1,h264_close_status:1,h264_oe_enable:1,h264_oe_used:1;
uint32 *cfg_backup;
};
int32 hg264_attach(uint32 dev_id, struct hg264 *lcdc);
#endif

66
sdk/include/dev/i2c/hgi2c_v1.h Normal file
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/**
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HGI2C_V1_H
#define __HGI2C_V1_H
#ifdef __cplusplus
extern "C" {
#endif
struct hgi2c_v1 {
struct i2c_device dev;
uint32 hw;
i2c_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
struct os_mutex i2c_lock;
struct os_semaphore i2c_done;
uint32 irq_tx_done_en : 1,
irq_rx_done_en : 1,
flag_tx_done : 1,
flag_rx_done : 1,
flag_table_done : 1,
flag_table_config_en : 1,
opened : 1,
dsleep : 1;
#ifdef CONFIG_SLEEP
struct {
__IO uint32_t con0;
__IO uint32_t con1;
__IO uint32_t timecon;
__IO uint32_t tdmalen;
__IO uint32_t rdmalen;
__IO uint32_t tstadr;
__IO uint32_t rstadr;
__IO uint32_t slavesta;
__IO uint32_t ownadrcon;
__IO uint32_t timeoutcon;
__IO uint32_t rxtimeoutcon;
__IO uint32_t rstadr1;
__IO uint32_t vsync_tcon;
__IO uint32_t hsync_tcon;
}bp_regs;
uint32 bp_irq_flags;
i2c_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
struct os_mutex bp_suspend_lock;
struct os_mutex bp_resume_lock;
#endif
};
int32 hgi2c_v1_attach(uint32 dev_id, struct hgi2c_v1 *hgi2c_s);
#ifdef __cplusplus
}
#endif
#endif //__HGI2C_V1_H
/*************************** (C) COPYRIGHT 2018 HUGE-IC ***** END OF FILE *****/

49
sdk/include/dev/i2s/hgi2s_v0.h Normal file
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#ifndef _HGI2S_V0_H_
#define _HGI2S_V0_H_
#include "hal/i2s.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief I2S operating handle structure
* @{
*/
struct hgi2s_v0 {
struct i2s_device dev ;
uint32 hw ;
i2s_irq_hdl irq_hdl ;
uint32 irq_data ;
uint16 irq_num ;
uint16 opened :1,
dsleep :1,
duplex_en:1;
#ifdef CONFIG_SLEEP
struct {
uint32 con;
uint32 bit_set;
uint32 baud;
uint32 ws_con;
uint32 dma_stadr;
uint32 dma_len;
}bp_regs;
uint32 bp_irq_flags;
i2s_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgi2s_v0_attach(uint32 dev_id, struct hgi2s_v0 *i2s);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */

81
sdk/include/dev/isp/hgisp_v0.h Normal file
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#ifndef _HGISP_V0_H_
#define _HGISP_V0_H_
#include "hal/isp.h"
#include "lib/video/dvp/cmos_sensor/csi.h"
#ifdef __cplusplus
extern "C" {
#endif
enum isp_data_type {
ISP_DAT_GAMMA_R = 0,
ISP_DAT_GAMMA_G,
ISP_DAT_GAMMA_B,
ISP_DAT_GAMMA_Y,
ISP_DAT_HIST_R = BIT(2),
ISP_DAT_HIST_G,
ISP_DAT_HIST_B,
ISP_DAT_HIST_Y,
ISP_DAT_LSC = BIT(3),
ISP_DAT_GTMO = BIT(4),
ISP_DAT_HDR_HIST0 = BIT(5),
ISP_DAT_HDR_HIST1 = BIT(6),
ISP_DAT_INFRA = BIT(7),
};
enum isp_data_size{
ISP_DAT_SINGLE_GAMMA_SIZE = 0x100,
ISP_DAT_HIST_SIZE = 0x400,
ISP_DAT_GAMMA_SIZE = 0x400,
ISP_DAT_LSC_SIZE = 0x990,
// ISP_DAT_GTMO_SIZE = 0x304,
// ISP_DAT_HDR_HIST0_SIZE = 0x2E0,
// ISP_DAT_HDR_HIST1_SIZE = 0x2E0,
ISP_DAT_GTMO_SIZE = 0x000,
ISP_DAT_HDR_HIST0_SIZE = 0x000,
ISP_DAT_HDR_HIST1_SIZE = 0x000,
};
enum{
LL_ISP_ENABLE_FUNC_GAMMA = BIT(0),
LL_ISP_ENABLE_FUNC_HIST = BIT(1),
LL_ISP_ENABLE_FUNC_LSC = BIT(2),
LL_ISP_ENABLE_FUNC_GTMO = BIT(3),
LL_ISP_ENABLE_FUNC_HDR_HIST0 = BIT(4),
LL_ISP_ENABLE_FUNC_HDR_HIST1 = BIT(5),
};
enum {
ISP_LUMA_CA_MODE_0,
ISP_LUMA_CA_MODE_IRON,
ISP_LUMA_CA_MODE_GLOWBOW,
ISP_LUMA_CA_MODE_RAINBOW,
};
/** @brief ISP operating handle structure
* @{
*/
struct hgisp_v0 {
struct isp_device dev ;
uint32 hw ;
uint32 data_hw ;
isp_irq_hdl irq_hdl ;
uint32 irq_data ;
uint32 slave_index : 16,
curr_index : 16 ;
uint32 irq_num : 16,
opened : 1,
dsleep : 1,
dma_en : 1,
reserved : 12;
uint16 i2c_devid[4];
uint16 i2c_opt[4];
uint32 module;
};
int32 hgisp_v0_attach(uint32 dev_id, struct hgisp_v0 *isp);
void image_isp_status();
#ifdef __cplusplus
}
#endif
#endif /* _HGISP_V0_H_ */

78
sdk/include/dev/jpg/hgjpg.h Normal file
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#ifndef HG_JPG_H
#define HG_JPG_H
#include "hal/jpeg.h"
//typedef int (*jgp_isr_func)(uint32);
//typedef int32 (*jpg_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param);
#ifdef TXW80X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
// JPG_READ_EMPTY,
// JPG_WRITE_FULL,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
#ifdef TXW81X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
JPG_PIXEL_DONE,
JPG_TIME_OUT,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
#if TXW82X
typedef enum {
DONE_IRQ,
JPG_OUTBUF_FULL,
JPG_BUF_ERR,
JPG_PIXEL_DONE,
JPG_TIME_OUT,
JPG_IRQ_NUM
}JPG_IRQ_E;
#endif
struct hgjpg {
struct jpg_device dev;
uint32 hw;
uint32 thw;
uint32 huf_hw;
//jpg_irq_hdl irq_hdl;
uint32 irq_num;
uint8 opened : 1,
jpg_run : 1,
decode : 1,
set_buf_len : 1;
uint8 addr_count;
uint8 deal_time;
uint32 *cfg_backup;
};
//int32 jpg_open(struct jpg_device *p_jpg);
//int32 jpg_close(struct jpg_device *p_jpg);
//int32 jpg_init(struct jpg_device *p_jpg,uint32 table_index,uint32 qt,uint32 buflen,uint32 head_reserver);
//int32 jpg_set_size(struct jpg_device *p_jpg,uint32 h,uint32 w);
//int32 jpg_set_len(struct jpg_device *p_jpg,uint32 buflen,uint32 head_reserver);
//int32 jpg_updata_dqt(struct jpg_device *p_jpg,uint32* dqtbuf);
//int32 jpg_set_addr(struct jpg_device *p_jpg,uint32 addr);
//int32 jpg_set_qt(struct jpg_device *p_jpg,uint32 qt);
//int32 jpg_get_len(struct jpg_device *p_jpg);
//int32 jpg_get_outbuf_num(struct jpg_device *p_jpg);
//int32 jpg_request_irq(struct jpg_device *p_jpg,uint32 irq, jgp_isr_func isr, void *dev_id);
//int32 jpg_release_irq(struct jpg_device *p_jpg,uint32 irq);
void hgjpg_attach(uint32 dev_id, struct hgjpg *jpg);
#endif

22
sdk/include/dev/lcdc/hgdsi.h Normal file
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#ifndef HG_DSI_H
#define HG_DSI_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dsi.h"
struct hgdsi {
struct dsi_device dev;
uint32 hw;
dsi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgdsi_attach(uint32 dev_id, struct hgdsi *dsi);
#endif

30
sdk/include/dev/lcdc/hglcdc.h Normal file
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#ifndef HG_LCDC_H
#define HG_LCDC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/lcdc.h"
typedef enum {
LCD_DONE_IRQ,
LCD_TE_IRQ,
OSD_EN_IRQ,
SCREEN_DONE_IRQ = OSD_EN_IRQ,
TIMEOUT_IRQ,
LCD_IRQ_NUM
}LCD_IRQ_E;
struct hglcdc {
struct lcdc_device dev;
uint32 hw;
lcdc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hglcdc_attach(uint32 dev_id, struct hglcdc *lcdc);
#endif

28
sdk/include/dev/led/hgled_v0.h Normal file
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#ifndef _HGLED_V0_H
#define _HGLED_V0_H
#include "hal/led.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgled_v0 {
struct led_device dev;
uint32 hw;
led_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 seg_cnt;
uint16 com_cnt;
uint32 tube_type;
uint32 opened;
};
int32 hgled_v0_attach(uint32 dev_id, struct hgled_v0 *led);
#ifdef __cplusplus
}
#endif
#endif

30
sdk/include/dev/mipi_csi/hgmipi_csi.h Normal file
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#ifndef HG_MIPI_CSI_H
#define HG_MIPI_CSI_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/dvp.h"
#include "hal/csi2.h"
typedef enum {
CSI2_FOVIE_ISR = 0,
CSI2_VSIP_ISR,
CSI2_HSIP_ISR,
MIPI_CSI_IRQ_NUM
}MIPI_CSI_IRQ_E;
struct hgmipi_csi {
struct mipi_csi_device dev;
uint32 hw;
mipi_csi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
int32 hgmipi_csi_attach(uint32 dev_id, struct hgmipi_csi *mipi_csi);
#endif

18
sdk/include/dev/of/hgof.h Normal file
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#ifndef HG_OF_H
#define HG_OF_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/of.h"
struct hgof {
struct of_device dev;
uint32 hw;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1;
};
void hgof_attach(uint32 dev_id, struct hgof *of);
#endif

27
sdk/include/dev/osd_enc/hgosd_enc.h Normal file
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#ifndef HG_OSD_ENC_H
#define HG_OSD_ENC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/osd_enc.h"
typedef enum {
ENC_DONE_IRQ,
ENC_IRQ_NUM
}OSD_ENC_IRQ_E;
struct hgosd {
struct osdenc_device dev;
uint32 hw;
osdenc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hgosdenc_attach(uint32 dev_id, struct hgosd *lcdc);
#endif

51
sdk/include/dev/para_in/hgpara_in.h Normal file
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#ifndef _HGPARA_IN_H
#define _HGPARA_IN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "devid.h"
#include "osal/semaphore.h"
#include "osal/mutex.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "hal/para_in.h"
struct hgpara_in_hw {
__IO uint32_t PARA_IN_CON;
__IO uint32_t PARA_IN_STA;
__IO uint32_t PARA_IN_ACT_SIZE;
__IO uint32_t PARA_IN_BLK_SIZE;
__IO uint32_t PARA_IN_TO_CON;
};
enum hgpara_in_flags {
HGPARA_IN_FLAGS_OPENED = BIT(0),
HGPARA_IN_FLAGS_READY = BIT(1),
HGPARA_IN_FLAGS_SUSPEND = BIT(2),
};
struct hgpara_in {
struct para_in_device dev;
struct hgpara_in_hw *hw;
para_in_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
//状态位
uint32 flags;
};
int32 hgpara_in_attach(uint32 dev_id, struct hgpara_in *p_para_in);
#ifdef __cplusplus
}
#endif
#endif

41
sdk/include/dev/pdm/hgpdm_v0.h Normal file
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#ifndef _HGPDM_V0_H_
#define _HGPDM_V0_H_
#include "hal/pdm.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgpdm_v0 {
struct pdm_device dev;
uint32 hw;
pdm_irq_hdl irq_hdl;
uint32 irq_data;
uint16 irq_num;
uint16 opened:1,
dsleep:1;
#ifdef CONFIG_SLEEP
struct {
uint32 con;
uint32 dmacon;
uint32 dmastadr;
uint32 dmalen;
}bp_regs;
uint32 bp_irq_flags;
pdm_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgpdm_v0_attach(uint32 dev_id, struct hgpdm_v0 *pdm);
#ifdef __cplusplus
}
#endif
#endif

29
sdk/include/dev/prc/hgprc.h Normal file
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#ifndef HG_PRC_H
#define HG_PRC_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/prc.h"
typedef enum {
PRC_ISR = 0,
PRC_IRQ_NUM,
}PRC_IRQ_E;
struct hgprc {
struct prc_device dev;
//struct hgdvp_hw *hw;
uint32 hw;
prc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1, dsleep:1;
uint32 *cfg_backup;
};
void hgprc_attach(uint32 dev_id, struct hgprc *prc);
#endif

58
sdk/include/dev/pwm/hgpwm_v0.h Normal file
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#ifndef _HGPWM_V0_H
#define _HGPWM_V0_H
#include "hal/pwm.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HGPWM_MAX_PWM_CHANNEL 6
enum hgpwm_v0_func_cmd {
HGPWM_V0_FUNC_CMD_MASK = BIT(6),
HGPWM_V0_FUNC_CMD_INIT = HGPWM_V0_FUNC_CMD_MASK | 1,
HGPWM_V0_FUNC_CMD_DEINIT = HGPWM_V0_FUNC_CMD_MASK | 2,
HGPWM_V0_FUNC_CMD_START = HGPWM_V0_FUNC_CMD_MASK | 3,
HGPWM_V0_FUNC_CMD_STOP = HGPWM_V0_FUNC_CMD_MASK | 4,
/* IOCTL CMD */
HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY = HGPWM_V0_FUNC_CMD_MASK | 5,
HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY = HGPWM_V0_FUNC_CMD_MASK | 6,
HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM = HGPWM_V0_FUNC_CMD_MASK | 7,
HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE = HGPWM_V0_FUNC_CMD_MASK | 8,
HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER = HGPWM_V0_FUNC_CMD_MASK | 14,
HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY = HGPWM_V0_FUNC_CMD_MASK | 15,
/* IRQ_FLAG */
HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE = HGPWM_V0_FUNC_CMD_MASK | 9,
HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD = HGPWM_V0_FUNC_CMD_MASK | 10,
HGPWM_V0_FUNC_CMD_RELEASE_IRQ = HGPWM_V0_FUNC_CMD_MASK | 11,
HGPWM_V0_FUNC_CMD_SUSPEND = HGPWM_V0_FUNC_CMD_MASK | 12,
HGPWM_V0_FUNC_CMD_RESUME = HGPWM_V0_FUNC_CMD_MASK | 13,
};
struct hgpwm_v0_config {
uint32 period;
uint32 duty;
pwm_irq_hdl irq_hdl;
uint32 irq_data;
uint32 func_cmd;
uint32 param1;
uint32 param2;
};
struct hgpwm_v0 {
struct pwm_device dev;
void *channel[HGPWM_MAX_PWM_CHANNEL];
uint8 opened[HGPWM_MAX_PWM_CHANNEL];
};
int32 hgpwm_v0_attach(uint32 dev_id, struct hgpwm_v0 *pwm);
#ifdef __cplusplus
}
#endif
#endif

17
sdk/include/dev/rotate/hgrotate.h Normal file
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#ifndef HG_ROTATE_H
#define HG_ROTATE_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/rotate.h"
struct hgrotate {
struct rotate_device dev;
uint32 hw;
uint32 opened:1, use_dma:1;
};
int32 hgrotate_attach(uint32 dev_id, struct hgrotate *rotate);
#endif

38
sdk/include/dev/rtc/hgrtc_v0.h Normal file
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#ifndef _HGRTC_V1_H
#define _HGRTC_V1_H
#include "hal/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgrtc_v0 {
struct rtc_device dev;
uint32 hw;
rtc_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
os_mutex_t os_lock_set_time;
os_mutex_t os_lock_get_time;
struct rtc_time_type time;
struct {
//1：闰年；0：平年
uint8 leap_year;
}time_ctrl;
uint8 irq_second:1,
opened :1;
};
int32 hgrtc_v0_attach(uint32 dev_id, struct hgrtc_v0 *rtc);
#ifdef __cplusplus
}
#endif
#endif

33
sdk/include/dev/scale/hgscale.h Normal file
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#ifndef HG_SCALE_H
#define HG_SCALE_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/scale.h"
typedef enum {
FRAME_END,
INBUF_OV,
ERROR_PEND,
SCALE_IRQ_NUM
}SCALE_IRQ_E;
struct hgscale {
struct scale_device dev;
uint32 hw;
scale_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
volatile uint32_t opened:1, use_dma:1, clk_en:1, dsleep:1,need_close:1;
uint32 *cfg_backup;
};
int32 hgscale1_attach(uint32 dev_id, struct hgscale *scale);
int32 hgscale2_attach(uint32 dev_id, struct hgscale *scale);
int32 hgscale3_attach(uint32 dev_id, struct hgscale *scale);
void scale_ov_isr(uint32 irq_flag,uint32 irq_data,uint32 param1);
#endif

37
sdk/include/dev/sdio/hgsdio20_slave.h Normal file
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#ifndef _HGSDIO20_SLAVE_H_
#define _HGSDIO20_SLAVE_H_
#include "hal/sdio_slave.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsdio20_slave {
struct sdio_slave dev;
void *hw;
sdio_slave_irq_hdl irq_hdl;
uint32 irq_data;
os_mutex_t tx_lock;
os_semaphore_t tx_done;
uint8 *rx_buff;
uint8 irq_num;
uint8 rst_irq_num;
uint8 flags;
uint8 opened: 1, rev: 7;
uint16 rx_len;
uint8 speed, rev2;
uint8 func0_cis[17];
uint8 func1_cis[53];
uint64 mntr_tick;
};
int32 hgsdio20_slave_attach(uint32 dev_id, struct hgsdio20_slave *slave);
#ifdef __cplusplus
}
#endif
#endif /* _HGSDIO20_SLAVE_H_ */

33
sdk/include/dev/sha/hgsha_v0.h Normal file
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#ifndef _HGSHA_V0_H_
#define _HGSHA_V0_H_
#include "hal/sha.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsha_v0 {
struct sha_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
os_semaphore_t using256;
uint32 irq_num;
uint32 alg_type;
volatile uint32 flags_busy_or_idle :1,
flags_in_the_interupt:1,
flags_got_result :1,
flags_first_pack :1,
flags_media_pack :1,
flags_in_multi_mode:1,
flags_last_mode :1,
flags_cur_mode :1;
void (*sha_irq_func)(void *args);
void *irq_func_data;
};
int32 hgsha_v0_attach(uint32 dev_id, struct hgsha_v0 *sha);
#endif /* _hgsha256_H_ */

26
sdk/include/dev/sha/hgsha_v1.h Normal file
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#ifndef _HGSHA_V0_H_
#define _HGSHA_V0_H_
#include "hal/sha.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgsha_v1 {
struct sha_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
void (*irq_func)(void *args);
void *irq_data;
struct sha_ctx ctx;
struct sha_ctx *pctx;
};
int32 hgsha_v1_attach(uint32 dev_id, struct hgsha_v1 *sha);
#endif /* _hgsha256_H_ */

15
sdk/include/dev/spi/hgic_sdspi.h Normal file
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#ifndef _HGIC_SDSPI_H_
#define _HGIC_SDSPI_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hgic_sdspi_attach(uint32 dev_id, uint32 spi_dev);
#ifdef __cplusplus
}
#endif
#endif

57
sdk/include/dev/spi/hgspi_v1.h Normal file
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#ifndef _HGSPI_V1_H_
#define _HGSPI_V1_H_
#include "hal/spi.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v1 {
struct spi_device dev;
uint32 hw;
uint32 irq_num;
spi_irq_hdl irq_hdl;
uint32 irq_data;
//os_mutex_t os_spi_tx_lock;
//os_mutex_t os_spi_rx_lock;
os_mutex_t os_spi_lock;
os_semaphore_t os_spi_tx_done;
os_semaphore_t os_spi_rx_done;
uint32 timeout;
uint16 len_threshold;
uint16 spi_tx_done :1,
spi_rx_done :1,
spi_irq_flag_tx_done :1,
spi_irq_flag_rx_done :1,
spi_tx_async :1,
spi_rx_async :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 con0;
uint32 con1;
uint32 baud;
uint32 tdmalen;
uint32 rdmalen;
uint32 tstadr;
uint32 rstadr;
uint32 slavesta;
uint32 ssp_dly;
}bp_regs;
uint32 bp_irq_flags;
spi_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgspi_v1_attach(uint32 dev_id, struct hgspi_v1 *p_spi);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V1_H_ */

28
sdk/include/dev/spi/hgspi_v2.h Normal file
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#ifndef _HGSPI_V2_H
#define _HGSPI_V2_H
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v2 {
struct spi_device dev;
uint32 hw ;
spi_irq_hdl irq_hdl ;
uint32 irq_data;
uint32 irq_num ;
uint16 opened ;
uint16 spi_irq_flag_tx_done: 1,
spi_irq_flag_rx_done: 1;
};
int32 hgspi_v2_attach(uint32 dev_id, struct hgspi_v2 *spi);
#ifdef __cplusplus
}
#endif
#endif

69
sdk/include/dev/spi/hgspi_v3.h Normal file
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#ifndef _HGSPI_V3_H_
#define _HGSPI_V3_H_
#include "hal/spi.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hgspi_v3 {
struct spi_device dev;
uint32 hw;
uint32 irq_num;
spi_irq_hdl irq_hdl;
uint32 irq_data;
//os_mutex_t os_spi_tx_lock;
//os_mutex_t os_spi_rx_lock;
os_mutex_t os_spi_lock;
os_semaphore_t os_spi_tx_done;
os_semaphore_t os_spi_rx_done;
uint32 timeout;
uint16 len_threshold;
uint16 spi_tx_done :1,
spi_rx_done :1,
spi_irq_flag_tx_done :1,
spi_irq_flag_rx_done :1,
spi_tx_async :1,
spi_rx_async :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 con0;
uint32 con1;
uint32 cmd_data;
uint32 timecon;
uint32 tdmalen;
uint32 rdmalen;
uint32 tdmacnt;
uint32 rdmacnt;
uint32 tstadr;
uint32 rstadr;
uint32 sta1;
uint32 sta2;
uint32 slavesta;
uint32 ownadrcon;
uint32 rbuf;
uint32 timeoutcon;
uint32 rxtimeoutcon;
uint32 rstadr1;
uint32 vsync_tcon;
uint32 hsync_tcon;
}bp_regs;
uint32 bp_irq_flags;
spi_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgspi_v3_attach(uint32 dev_id, struct hgspi_v3 *p_spi);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V3_H_ */

147
sdk/include/dev/spi/hgspi_xip.h Normal file
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#ifndef _HGSPI_XIP_H_
#define _HGSPI_XIP_H_
#include "hal/spi.h"
#include "osal/task.h"
#include "list.h"
#ifdef __cplusplus
extern "C" {
#endif
enum hgspi_xip_flags {
hgspi_xip_flags_ready,
hgspi_xip_flags_suspend,
hgspi_xip_flags_suspend_pasr,
hgspi_xip_flags_suspend_ulp,
hgspi_xip_flags_suspend_pd,
hgspi_xip_flags_wip,
hgspi_xip_flags_xip,
};
struct xip_wip {
uint32 addrl;
uint32 addru;
uint32 addr;
uint32 tsr :16,
trs :16;
uint32 tsus :16,
trus :16;
struct os_semaphore rc;
struct os_task task;
};
struct rdcfg_bk {
uint32_t rdinstr;
uint32_t rd_capt;
};
struct hgspi_xip {
struct spi_device dev;
uint32_t hw;
uint32_t ddr : 1,
nbp : 1,
xip : 1,
flags : 29;
uint32_t tms; //io timeout ms
uint16_t tdp : 8,
trst : 8;
struct xip_wip wip;
struct rdcfg_bk def_cfg;
struct rdcfg_bk dtr_cfg;
#ifdef CONFIG_SLEEP
uint32 regs[30];
#endif
};
struct hgcqspi {
//struct qspi_device dev;
void *hw;
uint32 irq_num;
//qspi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 opened;
uint32 flags;
};
struct hgxip_flash_custom_opa {
uint8_t dummys; //最大31,内部默认有24个dummys
uint8_t cmd;
uint16_t size;
uint32_t addr;
uint8_t *buf;
};
struct hgxip_flash_custom_read {
uint8_t dummys; //最大31,内部默认有24个dummys
uint8_t cmd;
uint16_t size;
uint32_t addr;
uint8_t *buf;
};
struct hgxip_flash_custom_write {
struct hgxip_flash_custom_opa opa;
};
struct hgxip_flash_reg_opt_param
{
uint8_t cmd;
/* write opt when pre_cmd is valid(0xFF != pre_cmd); e.g.: 0x06/0x50 */
uint8_t pre_cmd;
uint8_t len;
uint8_t *buf;
};
enum MSROM_FUNC
{
#ifdef TXW82X
MSROM_MEMSET,
MSROM_MEMCPY,
MSROM_MEMCMP,
MSROM_QSPI_CMD_BUSY_WAIT,
MSROM_HIGHPASS_FILTER_100HZ_ASM,
MSROM_QSPI_XIP_ERASE,
MSROM_QSPI_XIP_READ,
MSROM_QSPI_XIP_WRITE,
MSROM_QSPI_XIP_OPT_ENTER,
MSROM_QSPI_XIP_OPT_EXIT,
MSROM_QSPI_ENTER_XIP_MODE,
MSROM_QSPI_EXIT_XIP_MODE, // NULL?
MSROM_QSPI_STIG,
MSROM_QSPI_ENTER_4B,
MSROM_QSPI_EXIT_4B,
MSROM_OSPI_SEND_SEQ,
MSROM_SYSCLK_SET_BUT_QSPI_CHAOS_DO,
#else
MSROM_MEMSET,
MSROM_MEMCPY,
MSROM_MEMCMP,
MSROM_STRCASECMP,
MSROM_QSPI_CMD_BUSY_WAIT = MSROM_STRCASECMP,
MSROM_STRNCASECMP,
MSROM_HIGHPASS_FILTER_100HZ_ASM = MSROM_STRNCASECMP,
MSROM_QSPI_XIP_ERASE,
MSROM_QSPI_XIP_READ,
MSROM_QSPI_XIP_WRITE,
MSROM_QSPI_XIP_OPT_ENTER,
MSROM_QSPI_XIP_OPT_EXIT,
MSROM_QSPI_ENTER_XIP_MODE,
MSROM_QSPI_EXIT_XIP_MODE,
MSROM_QSPI_STIG,
MSROM_OSPI_PSRAM_MRR,
MSROM_OSPI_PSRAM_MRW,
MSROM_OSPI_STIG,
#endif
};
int32 hgspi_xip_attach(uint32 dev_id, struct hgspi_xip *p_spi);
uint32_t get_msrom_func(uint32_t func_code);
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V1_H_ */

23
sdk/include/dev/sysaes/hg_sysaes_v2.h Normal file
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#ifndef _HG_SYSAES_V2_H_
#define _HG_SYSAES_V2_H_
#include "hal/sysaes.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_sysaes_v2 {
struct sysaes_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
#ifdef CONFIG_SLEEP
uint32 *regs;
#endif
};
int32 hg_sysaes_v2_attach(uint32 dev_id, struct hg_sysaes_v2 *sysaes);
#endif /* _HG_SYSAES_V2_H_ */

20
sdk/include/dev/sysaes/hg_sysaes_v3.h Normal file
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#ifndef _HG_SYSAES_V3_H_
#define _HG_SYSAES_V3_H_
#include "hal/sysaes.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_sysaes_v3 {
struct sysaes_dev dev;
void *hw;
os_mutex_t lock;
os_semaphore_t done;
uint32 irq_num;
uint32 flags;
};
int32 hg_sysaes_v3_attach(uint32 dev_id, struct hg_sysaes_v3 *sysaes);
#endif /* _HG_SYSAES_V3_H_ */

107
sdk/include/dev/timer/hgtimer_v4.h Normal file
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#ifndef _HGTIMER_V4_H
#define _HGTIMER_V4_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V4_TYPE_ONCE BIT(0)
#define HGTIMER_V4_TYPE_PERIODIC BIT(1)
#define HGTIMER_V4_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V4_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V4_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V4_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V4_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V4_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V4_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V4_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
#define HGTIMER_V4_CAPTURE_FUNC_CMD_INIT HGCAPTURE_V0_FUNC_CMD_INIT
#define HGTIMER_V4_CAPTURE_FUNC_CMD_DEINIT HGCAPTURE_V0_FUNC_CMD_DEINIT
#define HGTIMER_V4_CAPTURE_FUNC_CMD_START HGCAPTURE_V0_FUNC_CMD_START
#define HGTIMER_V4_CAPTURE_FUNC_CMD_STOP HGCAPTURE_V0_FUNC_CMD_STOP
/* IOCTL CMD */
/* IRQ_FLAG */
#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
#define HGTIMER_V4_CAPTURE_FUNC_CMD_RELEASE_IRQ HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V4_CAPTURE_FUNC_CMD_SUSPEND HGCAPTURE_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V4_CAPTURE_FUNC_CMD_RESUME HGCAPTURE_V0_FUNC_CMD_RESUME
struct hgtimer_v4 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 tmr_con;
uint32 tmr_en;
uint32 tmr_ie;
uint32 tmr_cnt;
uint32 tmr_cap1;
uint32 tmr_cap2;
uint32 tmr_cap3;
uint32 tmr_cap4;
/* The following registers only for timer1 & timer2 */
uint32 tmr_dctl;
uint32 tmr_dadr;
uint32 tmr_dlen;
uint32 tmr_dcnt;
uint32 tmr_ir_bcnt;
}bp_regs;
uint32 bp_irq_flags;
#endif
};
int32 hgtimer_v4_attach(uint32 dev_id, struct hgtimer_v4 *timer);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HGTIMER_V5_H
#define _HGTIMER_V5_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V5_TYPE_ONCE BIT(0)
#define HGTIMER_V5_TYPE_PERIODIC BIT(1)
#define HGTIMER_V5_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V5_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V5_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V5_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V5_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V5_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V5_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_INIT BIT(30) | 1
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_DEINIT BIT(30) | 2
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_START BIT(30) | 3
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_STOP BIT(30) | 4
///* IOCTL CMD */
//
///* IRQ_FLAG */
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE BIT(30) | 7
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW BIT(30) | 8
//
//#define HGTIMER_V5_CAPTURE_FUNC_CMD_RELEASE_IRQ BIT(30) | 9
struct hgtimer_v5 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
//capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1;
};
int32 hgtimer_v5_attach(uint32 dev_id, struct hgtimer_v5 *timer);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HGTIMER_V7_H
#define _HGTIMER_V7_H
#include "hal/timer_device.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-----timer lower layer: counter mode-----*/
#define HGTIMER_V7_TYPE_ONCE BIT(0)
#define HGTIMER_V7_TYPE_PERIODIC BIT(1)
#define HGTIMER_V7_TYPE_COUNTER BIT(2)
/*----timer lower layer: PWM function cmd----*/
#define HGTIMER_V7_PWM_FUNC_CMD_INIT HGPWM_V0_FUNC_CMD_INIT
#define HGTIMER_V7_PWM_FUNC_CMD_DEINIT HGPWM_V0_FUNC_CMD_DEINIT
#define HGTIMER_V7_PWM_FUNC_CMD_START HGPWM_V0_FUNC_CMD_START
#define HGTIMER_V7_PWM_FUNC_CMD_STOP HGPWM_V0_FUNC_CMD_STOP
/* IOCTL CMD */
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PRESCALER HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
/* IRQ_FLAG */
#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
#define HGTIMER_V7_PWM_FUNC_CMD_RELEASE_IRQ HGPWM_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V7_PWM_FUNC_CMD_SUSPEND HGPWM_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V7_PWM_FUNC_CMD_RESUME HGPWM_V0_FUNC_CMD_RESUME
/*----timer lower layer: cap function cmd----*/
#define HGTIMER_V7_CAPTURE_FUNC_CMD_INIT HGCAPTURE_V0_FUNC_CMD_INIT
#define HGTIMER_V7_CAPTURE_FUNC_CMD_DEINIT HGCAPTURE_V0_FUNC_CMD_DEINIT
#define HGTIMER_V7_CAPTURE_FUNC_CMD_START HGCAPTURE_V0_FUNC_CMD_START
#define HGTIMER_V7_CAPTURE_FUNC_CMD_STOP HGCAPTURE_V0_FUNC_CMD_STOP
/* IOCTL CMD */
/* IRQ_FLAG */
#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
#define HGTIMER_V7_CAPTURE_FUNC_CMD_RELEASE_IRQ HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
#define HGTIMER_V7_CAPTURE_FUNC_CMD_SUSPEND HGCAPTURE_V0_FUNC_CMD_SUSPEND
#define HGTIMER_V7_CAPTURE_FUNC_CMD_RESUME HGCAPTURE_V0_FUNC_CMD_RESUME
struct hgtimer_v7 {
struct timer_device dev;
uint32 hw;
timer_irq_hdl _counter_irq_hdl;
pwm_irq_hdl _pwm_irq_hdl;
capture_irq_hdl _capture_irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint16 type;
uint16 counter_once_en :1,
counter_period_en:1,
counter_en :1,
pwm_en :1,
cap_en :1,
ir_en :1,
opened :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32 tmr_ctl;
uint32 tmr_cnt;
uint32 tmr_pr;
uint32 tmr_pwm;
}bp_regs;
uint32 bp_irq_flags;
timer_irq_hdl bp_irq_hdl_timer;
pwm_irq_hdl bp_irq_hdl_pwm;
capture_irq_hdl bp_irq_hdl_capture;
uint32 bp_irq_data_timer;
uint32 bp_irq_data_pwm;
uint32 bp_irq_data_capture;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgtimer_v7_attach(uint32 dev_id, struct hgtimer_v7 *timer);
#ifdef __cplusplus
}
#endif
#endif

99
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#ifndef __HG_TOUCHKEY_H
#define __HG_TOUCHKEY_H
enum tk_ioctl_cmd
{
//硬件寄存器配置
TK_IOCTL_CSRST_SET,
TK_IOCTL_CMPEN_SET,
TK_IOCTL_CMPRB_SET,
TK_IOCTL_RES_SET,
TK_IOCTL_CURR_SET,
TK_IOCTL_ANA_TEN_SET,
TK_IOCTL_VOLT_REF_SET,
TK_IOCTL_PSR_CNT_SET,
TK_IOCTL_PRE_CHARGE_TIME,
TK_IOCTL_PRE_DISCHARGE_TIME,
TK_IOCTL_CONV_TIME,
TK_IOCTL_CHANNLE_MODE,
TK_IOCTL_CHARGE_FRE_DIV,
TK_IOCTL_CHARGE_FRE0_DIV,
TK_IOCTL_CHARGE_FRE1_DIV,
TK_IOCTL_CHARGE_FRE2_DIV,
TK_IOCTL_CHARGE_FRE3_DIV,
TK_IOCTL_SHIELD_SET,
TK_IOCTL_SSC_BW,
TK_IOCTL_SSC_TYPE_SEL,
TK_IOCTL_AUTO_SCAN_EN,
TK_IOCTL_ADDR_SET,
TK_IOCTL_KICK,
//算法参数配置
TK_IOCTL_ADJUST_TIME,
TK_IOCTL_LONG_KEY_TIME,
TK_IOCTL_ADJUST_LINE,
TK_IOCTL_ADJUST_DIFF_VALU,
TK_IOCTL_USE_NUM,
TK_IOCTL_WATER_MODE,
TK_IOCTL_NM_NUM,
TK_IOCTL_NM_LEAVE_CNT,
TK_IOCTL_TP_EN,
TK_IOCTL_NOISE_VALUE,
TK_IOCTL_NM_CM_CNT,
TK_IOCTL_NM_CM_VALUE,
//系统级别的配置(类似信号量,timer等等)
TK_SCAN_SEM_HANDL,
TK_TIMER_HANDL,
};
enum tk_irq_flag
{
TK_SG_CONV_FLAG = BIT(0),
TK_CH_DONE_FLAG = BIT(1),
TK_SCAN_DONE_FLAG = BIT(2),
TK_DMA_FLAG = BIT(3),
TK_DMA_ERR_FLAG = BIT(4),
};
typedef int32 (*tk_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
struct tk_device {
struct dev_obj dev;
int32(*open)(struct tk_device *tk);
int32(*close)(struct tk_device *tk);
int32(*ioctl)(struct tk_device *tk, uint32 cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag, tk_irq_hdl irq_hdl, uint32 data);
int32(*release_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag);
};
//tk算法私有结构体
struct hgtk_algorithm
{
uint16 __tk_adjust_time;
uint16 __tk_valid_time;
uint16 __tk_adjust_line;
uint16 __tk_adjust_diff_valu;
uint16 __tk_use_num;
uint16 __tk_water_mode;
uint16 __tk_nm_num;
uint16 __tk_nm_leave_cnt;
uint16 __tk_tp_en;
uint16 __tk_noise_value;
uint16 __tk_nm_cm_cnt;
uint16 __tk_nm_cm_value;
};
struct hgtk_device {
struct tk_device dev ;
uint32 hw ;
tk_irq_hdl irq_hdl ;
uint32 irq_data;
uint32 irq_num ;
uint32 opened ;
void* timer;
void* sem;
struct hgtk_algorithm tk_pri;
};
#endif

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#ifndef _HGTOUCHKEY_V2_H
#define _HGTOUCHKEY_V2_H
#include "hal/tk.h"
#include "osal/work.h"
//#include "../driver/tk/hg_touchkey_v2_hw.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union _u_16 {
uint16 w;
struct {
uint8 h;
uint8 l;
} b;
} TYPE_U16;
typedef union _s_16 {
int16 w;
struct {
uint8 h;
uint8 l;
} b;
} TYPE_S16;
typedef struct _DW {
TYPE_S16 MSW;
TYPE_U16 LSW;
} TYPE_DW;
typedef union _u_32 {
uint32 w;
struct {
uint8 h_32;
uint8 h_24;
uint8 l_16;
uint8 l_8;
} b;
} TYPE_u32;
typedef union _u_32_bit {
uint32 w;
struct {
uint16 count;
uint16 scan_done_pend : 1,
data_normal_flag : 1,
baseline_int_flag :1,
cal_finsh_flag : 1,
adjust_done_peng : 1,
reserved : 11;
} b;
} TYPE_U32_BIT;
typedef enum {
TK_INIT = 0,
ADJUST_DONE,
DATA_INIT_DONE,
SCAN_DONE,
RE_ADJUST_DONE,
} TYPE_ENUM_STA;
typedef struct {
int16 b[3]; // 分子多项式的系数Numerator
int16 a[2]; // 分母多项式的系数Denominator
int16 fixed_point_num; // 移位bit数
} TYPE_BIQUAD_FILTER;
struct hgtk_algor{
uint8 __tk_long_key_flag;
uint8 __tk_ch_inc_flag;
uint8 __tk_mult_confirm_cnt;
uint8 __tk_noise_confirm_cnt;
uint8 __tk_next;
uint8 __tk_cm_cnt;
uint8 __tk_muli_key_cnt;
uint8 __tk_mult_noise_cnt;
int16 __tk_data_temp;
uint16 __tk_ms_cnt;
uint32 __tk_ch_en;
uint32 __tk_key_debug_flag;
uint32 __tk_key_flag;
uint32 __tk_key_flag_temp;
uint32 __tk_key_data;
TYPE_DW MUL_RES_1 ; // 4byte
TYPE_DW MUL_RES_2 ;
TYPE_DW MUL_RES_3 ;
TYPE_u32 UNION_ADDR;
TYPE_BIQUAD_FILTER iir_param;
TYPE_ENUM_STA __tk_run_sta;
TYPE_U32_BIT __tk_flag;
};
struct hgtouchkey_v2 {
struct tk_device dev;
uint32 hw;
uint32 alg;
tk_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, dsleep:1, printf_flag:1;
uint32 tk_config;
struct os_work tk_kick_work;
struct os_work tk_scan_work;
struct hgtk_algor tk_algori;
#ifdef CONFIG_SLEEP
uint32 *bp_regs;
uint32 bp_irq_flags;
os_mutex_t bp_suspend_lock;
os_mutex_t bp_resume_lock;
#endif
};
int32 hgtouchkey_v2_attach(uint32 dev_id, struct hgtouchkey_v2 *touchkey);
#ifdef __cplusplus
}
#endif
#endif

52
sdk/include/dev/tk/tk_simplify_algorithm.h Normal file
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/**
******************************************************************************
* @file tk_simplify_algorithm.h
* @author TAIXIN-IC Application Team
* @version V1.0.0
* @date 01-05-2021
* @brief This file contains all the GPIO LL firmware functions.
******************************************************************************
* @attention
*
* 用户不允许修改
*
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __LIB_TK_ALGORITHM_H
#define __LIB_TK_ALGORITHM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "dev/tk/hg_touchkey_v2.h"
/* Includes ------------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
// 用户不允许修改
extern void __tk_lib_init(struct hgtouchkey_v2 *tk);
extern int32 __tk_scan(struct os_work *work);
extern int32 __tk_ms_handler(struct os_work *work);
#define __CPU_NOP() {__NOP(); __NOP(); __NOP(); __NOP();}
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif // __LIB_TK_ALGORITHM_H__
/**
* @}
*/
/**
* @}
*/
/*************************** (C) COPYRIGHT 2021 TAIXIN-IC ***** END OF FILE ****/

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sdk/include/dev/uart/hguart_v2.h Normal file
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#ifndef _HGUART_V2_H
#define _HGUART_V2_H
#include "hal/uart.h"
#ifdef __cplusplus
extern "C" {
#endif
#define __PSRAM_ADDR_START (0x28000000)
#define __PSRAM_ADDR_END (0x28800000 + (0x1800000))
struct hguart_v2 {
struct uart_device dev;
uint32 hw;
uart_irq_hdl irq_hdl;
uint32 irq_data;
uint16 irq_num;
uint16 opened:1, dsleep:1, use_dma:1;
uint32 flag;
#ifdef CONFIG_SLEEP
struct {
uint32 con;
uint32 baud;
uint32 tstadr;
uint32 rstadr;
uint32 tdmalen;
uint32 rdmalen;
uint32 dmacon;
uint32 rs485_con;
uint32 rs485_det;
uint32 rs485_tat;
uint32 tocon;
}bp_regs;
#endif
};
int32 hguart_v2_attach(uint32 dev_id, struct hguart_v2 *uart);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/uart/hguart_v3.h Normal file
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#ifndef _HGUART_V3_H
#define _HGUART_V3_H
#ifdef __cplusplus
extern "C" {
#endif
/** @brief Simple uart operating handle structure
* @{
*/
struct hguart_v3 {
struct uart_device dev ;
uint32 hw ;
uart_irq_hdl irq_hdl ;
uint32 irq_data;
uint16 irq_num ;
uint16 opened ;
};
int32 hguart_v3_attach(uint32 dev_id, struct hguart_v3 *uart);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/uart/hguart_v4.h Normal file
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#ifndef _HGUART_V4_H
#define _HGUART_V4_H
#ifdef __cplusplus
extern "C" {
#endif
/** @brief Simple uart operating handle structure
* @{
*/
struct hguart_v4 {
struct uart_device dev;
uint32 hw;
uart_irq_hdl irq_hdl;
uint32 irq_data;
uint32 tx_total_byte;
uint32 tx_cur_byte;
uint8 *p_tx_buf;
struct os_semaphore sema_tx;
struct os_mutex mutex_tx;
struct os_mutex mutex_rx;
uint16 irq_num;
uint16 comm_irq_num;
uint16 opened :1,
use_dma :1,
irq_dma_tx:1,
irq_dma_rx:1,
debug_uart:1,
rs485_set :1,
dsleep :1;
#ifdef CONFIG_SLEEP
struct {
uint32_t con;
uint32_t baud;
uint32_t tocon;
uint32_t dmaadr;
uint32_t dmalen;
uint32_t dmacon;
}bp_regs;
uint32 bp_irq_flags;
uart_irq_hdl bp_irq_hdl;
uint32 bp_irq_data;
struct os_mutex bp_suspend_lock;
struct os_mutex bp_resume_lock;
#endif
};
int32 hguart_v4_attach(uint32 dev_id, struct hguart_v4 *uart);
#ifdef __cplusplus
}
#endif
#endif

200
sdk/include/dev/usb/hgusb20_v1_base.h Normal file
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/*****************************************************************************
* Module : usb
* File : usb.c
* Author :
* Function : USB驱动的一些公用模块
*****************************************************************************/
#ifndef USB20_H
#define USB20_H
#ifdef __cplusplus
extern "C" {
#endif
//typedef int8 bool;
#define USBIE_EN() //NVIC_EnableIRQ(USB_CTL_IRQn);
#define USBIE_DIS() //NVIC_DisableIRQ(USB_CTL_IRQn);
#define USB_REG_CRITICAL_ENTER() int32 ie = disable_irq();
#define USB_REG_CRITICAL_EXIT() enable_irq(ie);
//写USB SIE寄存器
#define write_usb_reg(reg_addr, reg_data) do {hw->SIE##reg_addr = reg_data;} while(0)
//void write_usb_reg_index(uint8_t index, uint32_t reg_addr, uint8_t reg_data);
#define write_usb_reg_index(index, reg_addr, reg_data)\
do {\
USB_REG_CRITICAL_ENTER();\
hw->SIEM_INDEX = index;\
*((volatile uint8_t *)((uint32_t)&hw->SIEM_FADDR + reg_addr)) = reg_data;\
USB_REG_CRITICAL_EXIT();\
} while(0)
//读USB SIE寄存器
#define read_usb_reg(reg_addr) (*((volatile uint8_t *)((uint32_t)&hw->SIE##reg_addr)))
//uint8_t read_usb_reg_index(uint8_t index, uint32_t reg_addr);
#define read_usb_reg_index(index, reg_addr, reg_data)\
do {\
USB_REG_CRITICAL_ENTER();\
hw->SIEM_INDEX = index;\
reg_data = *((volatile uint8_t *)((uint32_t)&hw->SIEM_FADDR + reg_addr));\
USB_REG_CRITICAL_EXIT();\
} while(0)
//USB当前状态机
enum {
USB_DEFAULT_STATE,
USB_ADDRESS_STATE,
USB_CONFIG_STATE
};
//EP0状态机
enum {
IDLE_STATE,
TRANSER_OVER_STATE,
TRANSFERING_STATE,
RECEIVING_STATE,
RECEIV_OVER_STATE,
};
//接收者
enum {
REQUEST_TO_DEVICE,
REQUEST_TO_INTERFACE,
REQUEST_TO_ENDPOINT
};
//设备描述符
enum {
DEVICE_DESCRIPTOR = 1,
CONFIGURATION_DESCRIPTOR,
STRING_DESCRIPTOR,
INTERFACE_DESCRIPTOR,
ENDPOINT_DESCRIPTOR,
DEVICE_QUALIFIER_DESCRIPTOR,
// OTHER_SPEED_CONFIG_DESCRIPTOR, USB 1.1没有该选项
INTERFACE_ASSOCIATION_DESCRIPTOR = 11,
HID_REPORT = 0x22,
BOS_DEVICE_DESCRIPTOR = 0xF,
WCID_DEVICE_DESCRIPTOR = 0xEE,
};
//Feature Selector
enum {
ENDPOINT_STALL,
REMOTE_WAKEUP,
TEST_MODE
};
//检测模式
enum {
USB_CHECK_HOST, //尝试主机检测
USB_CHECK_OTG, //尝试OTG检测，是否连接PC
USB_STABLE_HOST, //已成功检测为USB主机
USB_STABLE_DEVICE, //已成功检测为USB设备
};
//返回值
enum {
USB_CONNECTED_NONE, //未连接
USB_CONNECTED_PC, //连接PC，当Device
USB_CONNECTED_DEVICE, //外接U盘，当Host
};
//USB控制结构体
struct hgusb20_dev_ctrl {
//EP0接收的命令
struct {
uint8_t rtype;
uint8_t request;
uint16_t value;
uint16_t index;
uint16_t length;
} cmd;
uint8_t bus_high_speed : 1,
auto_tx_null_pkt : 1, //ep1 tx null packet for non-potocol xfer
hdr_req : 1,
error : 1,
reserved_bit : 4;
uint8_t test_mode;
uint8_t reg_usb_csr0;
uint8_t set_addr;
// struct {
// uint16_t vid; //VID
// uint16_t pid; //PID
// uint16_t ver; //Version
// } info;
};
struct hgusb20_dev_chk {
uint8_t check_mode;
uint8_t check_cnt;
uint8_t check_delay;
} ;
#define BYTE0(n) ((uint8_t)((uint16_t)(n)))
#define BYTE1(n) ((uint8_t)(((uint16_t)(n))>>8))
#define BYTE2(n) ((uint8_t)(((uint16_t)(((uint32_t)(n))>>8))>>8))
#define BYTE3(n) ((uint8_t)(((uint16_t)(((uint32_t)(n))>>16))>>8))
#define LOAD_U32B(p) ((((volatile uint8_t *)(p))[0]<<24) | (((volatile uint8_t *)(p))[1]<<16) | (((volatile uint8_t *)(p))[2]<<8) | (((volatile uint8_t *)(p))[3]<<0))
#define LOAD_U32L(p) ((((volatile uint8_t *)(p))[0]<<0) | (((volatile uint8_t *)(p))[1]<<8) | (((volatile uint8_t *)(p))[2]<<16)| (((volatile uint8_t *)(p))[3]<<24))
#define LOAD_U16B(p) ((((volatile uint8_t *)(p))[0]<<8) | (((volatile uint8_t *)(p))[1]<<0))
#define LOAD_U16L(p) ((((volatile uint8_t *)(p))[0]<<0) | (((volatile uint8_t *)(p))[1]<<8))
#define SAVE_U32B(p, num) do { \
((volatile uint8_t *)(p))[0] = BYTE3(num); \
((volatile uint8_t *)(p))[1] = BYTE2(num); \
((volatile uint8_t *)(p))[2] = BYTE1(num); \
((volatile uint8_t *)(p))[3] = BYTE0(num); \
} while(0)
#define SAVE_U32L(p, num) do { \
((volatile uint8_t *)(p))[0] = BYTE0(num); \
((volatile uint8_t *)(p))[1] = BYTE1(num); \
((volatile uint8_t *)(p))[2] = BYTE2(num); \
((volatile uint8_t *)(p))[3] = BYTE3(num); \
} while(0)
#define SAVE_U16B(p, num) do { \
((volatile uint8_t *)(p))[0] = BYTE1(num); \
((volatile uint8_t *)(p))[1] = BYTE0(num); \
} while(0)
#define SAVE_U16L(p, num) do { \
((volatile uint8_t *)(p))[0] = BYTE0(num); \
((volatile uint8_t *)(p))[1] = BYTE1(num); \
} while(0)
void hgusb20_write_usb_reg_index(uint32_t usb_dev_hw,uint32_t index,uint32_t reg_addr,uint32_t reg_data);
void hgusb20_read_usb_reg_index(uint32_t usb_dev_hw,uint32_t index,uint32_t reg_addr,uint32_t *reg_data);
uint32_t hgusb20_write_usb_reg(uint32_t usb_dev_hw,uint8_t reg_addr,uint8_t reg_data);
uint32_t hgusb20_read_usb_reg(uint32_t usb_dev_hw,uint32_t reg_addr);
void hgusb20_send_empty_packet(uint32_t usb_dev_hw);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/dev/usb/hgusb20_v1_dev_api.h Normal file
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@@ -0,0 +1,691 @@
#ifndef USB20_DEV_API_H
#define USB20_DEV_API_H
/// include & define here
#include "sys_config.h"
#include "hal/usb_device.h"
#include "dev/usb/hgusb20_v1_base.h"
#include "dev/usb/hgusb20_v1_dev_ep0.h"
#include "osal/work.h"
#include "osal/event.h"
#include "lib/common/rbuffer.h"
#define USB_DEV_DEBUG_ERR_ENABLE 0
#if USB_DEV_DEBUG_ERR_ENABLE
#define USB_DEV_ERR_PRINTF(fmt, args...) os_printf(fmt, ##args)
#else
#define USB_DEV_ERR_PRINTF(fmt, args...)
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* speed flags only host */
#define HGUSB20_FLAGS_HIGH_SPEED (0)
#define HGUSB20_FLAGS_FULL_SPEED (30)
#define USBDMA_RX_FLAG_RXING BIT(0)
#define USBDMA_RX_FLAG_OVERFLOW BIT(1)
#define USBDMA_RX_FLAG_FIFOFULL BIT(2)
#define USBDMA_TX_FLAG_TXING BIT(0)
#define USBDMA_TX_FLAG_NULLPACKET BIT(1)
#define USBDMA_TX_FLAG_MODE1 BIT(2)
typedef struct {
uint8 ep0_pkt;
uint16 time_out;
uint8 stall;
} type_usb_host;
typedef struct {
union {
struct {
uint8 dev_hub_addr : 7,
hub_mtt_en : 1;
};
uint8 usb_hub_addr;
} u_usb_hub_addr;
uint8 dev_hub_port;
uint8 dev_addr;
uint8 ep_host : 4,
ep_host_rsv : 4;
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_SPEED_DEFAULT 0x00
#define USB_ENDPOINT_SPEED_HIGH 0x01
#define USB_ENDPOINT_SPEED_FULL 0x02
#define USB_ENDPOINT_SPEED_LOW 0x03
uint8 ep_dev : 4,
ep_type : 2,
ep_speed : 2;
uint16 max_pkt_size;
} hgusb20_pipe_attr ;
typedef struct {
uint8 offset;
uint8 rx_len;
uint16 rx_total;
} type_ep0_ptr;
typedef enum {
UDISK_DEV = 1,
UVC_DEV
}USB_DEV_TYPE;
struct ep_trx_ctrl {
uint32 addr;
uint32 total_bytes;
uint32 max_packet_size;
uint32 cur_addr;
uint32 cur_counter;
uint32 last_counter;
uint32 tx_null_pkt_en;
uint32 tx_null_pkt_flag;
};
struct hgusb20_dev {
struct usb_device dev;
void *usb_hw;
long flags;
usbdev_irq_hdl irq_hdl;
uint8 *rx_buff;
uint32 rx_len;
uint32 irq_data;
struct usb_device_cfg *cfg;
uint8 *p_com_desc; /* usb descriptor */
uint8 *p_config_desc; /* usb descriptor */
uint16 vid; /* usb device VID */
uint16 pid; /* usb device PID */
/* basic */
struct hgusb20_dev_chk usb_chk;
struct hgusb20_dev_ctrl usb_ctrl;
struct hgusb20_dev_info usb_dev;
type_ep0_ptr ep0_ptr;
type_usb_host usb_host;
volatile uint32 usb_dma_int; /* dma intr status reg value */
volatile uint8 usb_rxdma_flag;
volatile uint8 usb_txdma_flag;
uint8 ep_irq_num;
uint8 dma_irq_num;
uint16_t usb_dev_flag;
uint8 usb_ep0_sbuf[8] __attribute__((aligned(4)));
/* case : usb continue send 64byte data, 2nd data NAK */
uint8 usb_ep0_rxbuf[68 + 68] __attribute__((aligned(4)));
uint8 usb_ep0_sta[8];
RBUFFER_DEF_R(rb, uint8);
struct os_work ep0_work;
/* trx_lock[00:15] for EP_IN */
/* trx_lock[15:31] for EP_OUT */
struct os_event trx_lock;
struct os_event trx_done;
struct ep_trx_ctrl ep_trans_ctrl[7];
struct ep_trx_ctrl ep_recevice_ctrl[7];
#ifdef CONFIG_SLEEP
uint32 sys_regs[4];
#endif
};
/* hgusb20_base */
/**
* @brief read usb register
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep :
* @param addr : register address offset
* @param data : data return
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_read_reg(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 *data);
/**
* @brief write usb register
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep :
* @param addr : register address offset
* @param data : data return
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_write_reg(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 data);
void hgusb20_switch_otg(struct hgusb20_dev *p_dev);
void hgusb20_switch_host(struct hgusb20_dev *p_dev);
void hgusb20_switch_stable_host(struct hgusb20_dev *p_dev);
void hgusb20_switch_stable_device(struct hgusb20_dev *p_dev);
void hgusb20_switch_stable_otg(struct hgusb20_dev *p_dev);
void hgusb20_intr_dis(struct hgusb20_dev *p_dev);
uint8_t hgusb20_connected(struct hgusb20_dev * p_dev);
uint32 hgusb20_get_rx_crc_error_cnt(struct hgusb20_dev *p_dev);
/**
* @brief usb ep rx data kick
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @param addr : data address
* @param len : data length
* @return : TRUE or FLASE
* @note use for host & device
*/
bool hgusb20_ep_rx_kick(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 len);
/**
* @brief usb ep tx data kick
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @param addr : data address
* @param len : data length
* @return : TRUE or FLASE
* @note use for host & device
*/
bool hgusb20_ep_tx_kick(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 len);
bool hgusb20_ep_rx_abort(struct hgusb20_dev *p_dev, uint8 ep);
bool hgusb20_ep_tx_abort(struct hgusb20_dev *p_dev, uint8 ep);
/**
* @brief usb ep get rx data length from dma
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @return : rx data length
* @note use for host & device
*/
uint32 hgusb20_ep_get_dma_rx_len(struct hgusb20_dev *p_dev, uint8 ep);
/**
* @brief usb ep get rx data length from sie
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @return : rx data length
* @note use for host & device
*/
uint32 hgusb20_ep_get_sie_rx_len(struct hgusb20_dev *p_dev, uint8 ep);
/**
* @brief usb ep get tx data length
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @return : tx data length (same with len in hgusb20_ep_tx_kick)
* @note use for host & device
*/
uint32 hgusb20_ep_get_tx_len(struct hgusb20_dev *p_dev, uint8 ep);
/**
* @brief check if usb device online
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* - TRUE : online.
* - FALSE : not online.
* @note : For USB Host
*/
bool hgusb20_is_device_online(struct hgusb20_dev *p_dev);
/**
* @brief check if usb host online
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* - TRUE : online.
* - FALSE : not online.
* @note : For USB Device
*/
bool hgusb20_is_host_online(struct hgusb20_dev *p_dev);
int32 hgusb20_is_host_mode(struct hgusb20_dev *p_dev);
/**
* @brief suspend usb device .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return :
* @note : For USB Host
*/
void hgusb20_host_suspend(struct hgusb20_dev *p_dev);
/**
* @brief resume usb device .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return :
* @note : For USB Host
*/
void hgusb20_host_resume(struct hgusb20_dev *p_dev);
/**
* @brief usb host set address(host address)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param addr :
* @return
* @note use after usb_host_set_address(device address) cmd
*/
void hgusb20_set_address(struct hgusb20_dev *p_dev, uint8 addr);
/**
* @brief usb host bus reset request
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
uint8 hgusb20_host_reset(struct hgusb20_dev *p_dev);
/**
* @brief remote_wakeup usb host .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return :
* @note : For USB Device
*/
void hgusb20_dev_remote_wakeup(struct hgusb20_dev *p_dev);
/* hgusb20_dev_api */
/**
* @brief attach usb device
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param dev_id :
* @return : err_code
* @note
*/
int32 hgusb20_dev_attach(uint32 dev_id, struct hgusb20_dev *p_dev);
/**
* @brief init usb to device mode .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* - RET_OK : Successfully.
* - RET_ERR : Failed.
* @note
*/
uint8 hgusb20_dev_init(struct hgusb20_dev *p_dev);
/**
* @brief exit usb to device mode .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* - RET_OK : Successfully.
* - RET_ERR : Failed.
* @note
*/
void hgusb20_dev_exit(struct hgusb20_dev *p_dev);
/**
* @brief usb device ep0 tx data stage handle:
* addr = p_dev->ep0_ptr; len = p_dev->ep0_len;
* 1、if buf is not NULL（first packet）, update p_dev->ep0_ptr & p_dev->ep0_len
* 2、TX one packet
* 3、data end if len != ep0_pkt
* 4、auto called repeat when last tx data done while (p_dev->usb_dev.ep0_state == TRANSER_OVER_STATE)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param buf : valid when first packet, set NULL when other packet
* @param len : valid when first packet, set 0 when other packet.
* @return
* - RET_OK : Successfully.
* - RET_ERR : Failed.
* @note : weak function, Users can use a strong statement function replace the weak statement function.
*/
bool hgusb20_dev_ep0_tx(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
/**
* @brief usb device ep0 tx one packet only
*/
bool hgusb20_dev_ep0_tx_rtt(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
bool hgusb20_dev_ep0_tx_abort(struct hgusb20_dev *p_dev);
/**
* @brief usb ep rx data stage handle
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : [1,2]
* @param addr : data address
* @param len : data length
* @return : TRUE or FLASE
* @note use for host & device
*/
bool hgusb20_dev_ep0_rx(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
/**
* @brief usb device ep0 rx one packet only
*/
bool hgusb20_dev_ep0_rx_rtt(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
bool hgusb20_dev_ep0_rx_abort(struct hgusb20_dev *p_dev);
/**
* @brief usb device clear_stall_flag
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
void hgusb20_dev_clear_stall_flag(struct hgusb20_dev *p_dev);
/**
* @brief usb device tx zero-packet & rx packet to usb_ep0_rxbuf
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
bool hgusb20_dev_ep0_clrrx_pkt0(struct hgusb20_dev *p_dev);
/**
* @brief usb device bus reset
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
void hgusb20_dev_reset(struct hgusb20_dev *p_dev);
/**
* @brief usb device stall_ep
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param epnum : epnum, set BIT(7) when tx endpiont.
* @return
* @note
*/
void hgusb20_dev_stall_ep(struct hgusb20_dev *p_dev, uint8 epnum);
/**
* @brief usb device clear stall_ep
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param epnum : epnum, set BIT(7) when tx endpiont.
* @return
* @note
*/
void hgusb20_dev_clear_ep(struct hgusb20_dev *p_dev, uint8 epnum);
/**
* @brief usb device ep reset all endpiont in ep_cfg
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
void hgusb20_dev_bot_reset(struct hgusb20_dev *p_dev);
/**
* @brief usb device cmd handle ：get descriptor
* 1、kick next rx to p_dev->usb_ep0_rxbuf
* 2、tx data(addr = buf, length = len)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_dev_ep0_descriptor(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
/**
* @brief usb device standard cmd handle
* 1、
* 2、handle DATA(IN or OUT)
* 3、STATUS(zero-len packet)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note : weak function, Users can use a strong statement function replace the weak statement function.
* these function is called by func "hgusb20_dev_ep0_standard"
*/
uint8 hgusb20_dev_cfg_desc_prepare(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_get_descriptor(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_get_configuration(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_set_configuration(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_get_interface(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_set_interface(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_set_address(struct hgusb20_dev *p_dev, uint8_t address);
__weak bool hgusb20_dev_ep0_get_status(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_clr_feature(struct hgusb20_dev *p_dev);
__weak bool hgusb20_dev_ep0_set_feature(struct hgusb20_dev *p_dev);
/**
* @brief usb device ep0 setup handle (standard cmd)
* 1、
* 2、handle DATA(IN or OUT)
* 3、STATUS(zero-len packet)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return : TRUE or FLASE
* @note : weak function, Users can use a strong statement function replace the weak statement function.
* the function is called by func "hgusb20_dev_ep0_request"
*/
__weak bool hgusb20_dev_ep0_standard(struct hgusb20_dev *p_dev);
//__weak bool hgusb20_dev_ep0_class_reset(struct hgusb20_dev *p_dev);
//__weak bool hgusb20_dev_ep0_class_get_lun(struct hgusb20_dev *p_dev);
//__weak bool hgusb20_dev_ep0_audio_sample_ctrl(struct hgusb20_dev *p_dev);
//__weak bool hgusb20_dev_ep0_audio_mute_ctrl(struct hgusb20_dev *p_dev);
//__weak bool hgusb20_dev_ep0_audio_volume_ctrl(struct hgusb20_dev *p_dev);
/**
* @brief usb device ep0 setup handle (class cmd)
* 1、
* 2、handle DATA(IN or OUT)
* 3、STATUS(zero-len packet)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return : TRUE or FLASE
* @note : weak function, Users can use a strong statement function replace the weak statement function.
* the function is called by func "hgusb20_dev_ep0_request"
*/
__weak bool hgusb20_dev_ep0_class(struct hgusb20_dev *p_dev);
/**
* @brief usb device ep0 setup handle (vendor cmd)
* 1、
* 2、handle DATA(IN or OUT)
* 3、STATUS(zero-len packet)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return : TRUE or FLASE
* @note : weak function, Users can use a strong statement function replace the weak statement function.
* the function is called by func "hgusb20_dev_ep0_request"
*/
__weak bool hgusb20_vendor_cmd(struct hgusb20_dev *p_dev);
/**
* @brief usb device ep0 setup handle
* 1、
* 2、handle DATA(IN or OUT)
* 3、STATUS(zero-len packet)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return : TRUE or FLASE
* @note : weak function, Users can use a strong statement function replace the weak statement function.
*
*/
__weak bool hgusb20_dev_ep0_request(struct hgusb20_dev *p_dev);
/**
* @brief usb device config state indication
* 1、 p_dev->usb_dev.cur_state = USB_CONFIG_STATE;
* 2、p_dev->flags |= BIT(HGUSB20_FLAGS_READY);
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return :
* @note : weak function, Users can use a strong statement function replace the weak statement function.
*
*/
__weak void hgusb20_dev_state_config(struct hgusb20_dev *p_dev);
///**
// * @brief usb device ep0 interrupt handle
// * @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
// * @return
// * @note : weak function, Users can use a strong statement function replace the weak statement function.
// * !! Don't recommend a strong statement function
// */
//__weak void hgusb20_dev_ep0_func(struct hgusb20_dev *p_dev);
/**
* @brief usb device endpoint init & deinit
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_addr : ep->ep_desc->bEndpointAddress
* @param max_pkt_size :ep->ep_desc->wMaxPacketSize
* @param attributes : ep->ep_desc->bmAttributes.
* @return :
* @note : weak function, Users can use a strong statement function replace the weak statement function.
*/
void hgusb20_dev_ep_init(struct hgusb20_dev *p_dev, uint8 ep_addr, uint16 max_pkt_size, uint8 attributes);
void hgusb20_dev_ep_deinit(struct hgusb20_dev *p_dev, uint8 ep_addr);
/**
* @brief usb device IN data kick （ tx data ）
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep : ep_num = ep->ep_desc->bEndpointAddress & 0x7F
* @param buff : word aligned
* @param len :
* @param sync : 1: sync(recommand) 0: async
* @return : error code
* @note : weak function, Users can use a strong statement function replace the weak statement function.
*/
int32 hgusb20_dev_write(struct usb_device *usb, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 hgusb20_dev_read(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 hgusb20_dev_close(struct usb_device *p_usb_d);
/* hgusb20_host_api */
/**
* @brief attach usb host
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param dev_id :
* @return : err_code
* @note
*/
int32 hgusb20_host_attach(uint32 dev_id, struct hgusb20_dev *p_dev);
/**
* @brief init usb to host mode .
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* - RET_OK : Successfully.
* - RET_ERR : Failed.
* @note
*/
bool hgusb20_host_init(struct hgusb20_dev *p_dev);
/**
* @brief usb host ep0 cmd request
* 1. SETUP: send setup packet , addr = p_dev->usb_ctrl.cmd, len = 8
* 2. DATA : addr = p_buf, len = p_dev->usb_ctrl.cmd.length for rx/tx(p_dev->usb_ctrl.cmd.rtype & USB_DIR_IN)
3. STA : if DATA tx null packet else rx null packet
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param p_buf : data buffer.
* @return : TRUE or FLASE
* @note Another choice user can realize function by calling "hgusb20_host_ep0_setup" & "hgusb20_host_ep0_rx" & "hgusb20_host_ep0_tx"
*/
bool usb_host_ep0_request(struct hgusb20_dev *p_dev, uint8 *pBuf);
/**
* @brief usb host ep0 send SETUP packet
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note
*/
uint32_t hgusb20_host_ep0_setup(struct hgusb20_dev *p_dev);
/**
* @brief usb host ep0 send IN packet & request a data packet
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @return
* @note addr = p_dev->usb_ep0_buf, len = p_dev->ep0_ptr.rx_len
*/
uint32_t hgusb20_host_ep0_rx(struct hgusb20_dev *p_dev, uint8 *pBuf, bool first_pkt);
/**
* @brief usb host ep0 send IN packet & request a data packet
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param len :
* @return
* @note addr = p_dev->usb_ep0_buf, len = p_dev->ep0_ptr.rx_len
*/
uint32_t hgusb20_host_ep0_tx(struct hgusb20_dev *p_dev, uint8 *pBuf, uint8 len);
/**
* @brief usb host endpiont init (TXW81X)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_host : ep pipe of host
* @param ep_dev : ep pipe of device
* @param ep_type : USB_ENDPOINT_XFERTYPE_MASK @ref usb_ch9.h
* @param max_pkt_size :
* @return
* @note
*/
void hgusb20_host_tx_ep_init(struct hgusb20_dev *p_dev, uint8 ep_host, uint8 ep_dev, uint8 ep_type, uint16 max_pkt_size);
void hgusb20_host_rx_ep_init(struct hgusb20_dev *p_dev, uint8 ep_host, uint8 ep_dev, uint8 ep_type, uint16 max_pkt_size);
/**
* @brief usb host pipe init (TXW82X)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param usb_pipe : ep pipe of host
* @return
* @note
*/
void hgusb20_host_tx_pipe_combine(struct hgusb20_dev *p_dev, hgusb20_pipe_attr *usb_pipe);
void hgusb20_host_rx_pipe_combine(struct hgusb20_dev *p_dev, hgusb20_pipe_attr *usb_pipe);
/**
* @brief hgusb20_host_clear_data_toggle
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [1,2]
* @param ep_type : EndpointDir BIT[7]：IN = 1, OUT = 0
* @return :
* @note
*/
void hgusb20_host_clear_data_toggle(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
/**
* @brief hgusb20_host_flush_fifo
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [1,2]
* @param ep_type : EndpointDir BIT[7]：IN = 1, OUT = 0
* @return :
* @note
*/
void hgusb20_host_flush_fifo(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
/**
* @brief usb host get stall status
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [0,2]
* @param ep_type : EndpointDir BIT[7]：IN = 1, OUT = 0
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_host_is_rx_stall(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
/**
* @brief usb host get xact error status (continous no response three times)
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [0,2]
* @param ep_type : EndpointDir BIT[7]：IN = 1, OUT = 0
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_host_is_xact_err(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
/**
* @brief usb host get nak timeout status
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [0,2]
* @param ep_type : EndpointDir BIT[7]：IN = 1, OUT = 0
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_host_is_nak_timeout(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
/**
* @brief usb host get rx crc status
* @param p_dev : hgusb20_dev use @ref dev_get() function to get the handle.
* @param ep_num : [0,2]
* @return : TRUE or FLASE
* @note
*/
bool hgusb20_host_is_crc_err(struct hgusb20_dev *p_dev, uint8 ep_num);
void hgusb20_host_reset_phy(struct hgusb20_dev * p_dev);
int32 hgusb20_host_set_interval(struct hgusb20_dev *p_dev, uint8_t ep_host, uint8_t mode, uint32_t interval);
void hgusb20_host_reset_ep_rxcsr(struct hgusb20_dev *p_dev, uint8 ep_num);
void hgusb20_host_reset_ep_txcsr(struct hgusb20_dev *p_dev, uint8 ep_num);
void hgusb20_host_hub_ep0_mange(struct hgusb20_dev *p_dev, hgusb20_pipe_attr *usb_pipe);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* USB_DEV_API_H */

69
sdk/include/dev/usb/hgusb20_v1_dev_ep0.h Normal file
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/*****************************************************************************
* Module : usb
* File : usb_dev.h
* Author :
* Function : USB Device驱动的一些定义
*****************************************************************************/
#ifndef USB20_DEV_H
#define USB20_DEV_H
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
#define USB_REQUEST_DIRECTION (p_dev->usb_ctrl.cmd.rtype & 0x80)
#define USB_REQUEST_TYPE (p_dev->usb_ctrl.cmd.rtype & 0x60)
#define USB_REQUEST_RECIPIENT (p_dev->usb_ctrl.cmd.rtype & 0x1f)
#define USB_REQUEST_ENDPOINT BYTE0(p_dev->usb_ctrl.cmd.index)
#define USB_REQUEST_TEST_INDEX BYTE1(p_dev->usb_ctrl.cmd.index)
#define USB_REQUEST_FEATURE_SELECTOR (p_dev->usb_ctrl.cmd.value)
#define USB_REQUEST_DESCRIPTOR_TYPE BYTE1(p_dev->usb_ctrl.cmd.value)
#define USB_REQUEST_DESCRIPTOR_INDEX BYTE0(p_dev->usb_ctrl.cmd.value)
#define USB_REQUEST_LENGTH (p_dev->usb_ctrl.cmd.length)
struct hgusb20_dev_info {
//uint8_t type; //设备类型
//uint8_t set_addr; //设地址
//uint8_t cfg_value; //Config Value, 用于Set Config与Get Config
uint8_t cur_state : 4, //USB当前状态机
ep0_state : 4; //EP0的状态机
uint8_t ep0_pkt; //EP0包大小
uint8_t *ep0_ptr; //当前发送指针
uint16_t ep0_len; //当前发送剩余
uint8_t *ep0_ptr_rx; //当前发送指针
uint16_t ep0_len_rx; //当前发送剩余
volatile uint8_t ep_tx_stall; //ep1 tx stall标志
volatile uint8_t ep_rx_stall; //ep1 rx stall标志
// uint8_t ep_num_rx;
// uint8_t ep_num_tx;
// uint8_t ep_rx_type;
// uint8_t ep_tx_type;
// uint16_t max_pkt_rx[MAX_EP];
// uint16_t max_pkt_tx[MAX_EP];
} ;
struct hgusb20_audio_ctrl {
uint8_t speaker_mute;
uint8_t mic_mute;
uint8_t volume;
/*
uint8_t *adc_root;
uint8_t *adc_end;
uint8_t *adc_ptr;
int16_t adc_cnt;
int16_t adc_total;
int8_t mic_speed;
*/
} ;
#ifdef __cplusplus
}
#endif
#endif

56
sdk/include/dev/usb/hgusb_dev_tbl.h Normal file
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/*****************************************************************************
* Module : usb
* File : usb_dev_tbl.h
* Author :
* Function : USB驱动的一些常量表的申明
*****************************************************************************/
#ifndef USB_DEV_TBL_H
#define USB_DEV_TBL_H
#define WCID_VENDOR_CODE 0xA0
#ifdef __cplusplus
extern "C" {
#endif
extern const uint8_t tbl_usb_device_descriptor[18];
extern const uint8_t tbl_usb_config_all_descriptor_gen[9];
extern const uint8_t tbl_usb_config_all_descriptor_wifi[23];
extern const uint8_t tbl_usb_config_all_descriptor_mass[23];
extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_head[19];
extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_speaker[31];
extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_mic[30];
extern const uint8_t tbl_usb_config_all_descriptor_speaker_stream[52];
extern const uint8_t tbl_usb_config_all_descriptor_mic_stream[52];
extern const uint8_t tbl_usb_config_all_descriptor_hid[25];
extern const uint8_t tbl_usb_hid_report_descriptor[33];
extern const uint8_t tbl_usb_language_id[4];
extern const uint8_t tbl_usb_str_manufacturer[16];
extern const uint8_t tbl_usb_str_product[28];
extern const uint8_t tbl_usb_str_serial_number[30];
extern const uint8_t tbl_scsi_inquiry_data[36];
/* bcdUSB = 2.0 */
extern const uint8_t tbl_winusb_device_descriptor[18];
extern const uint8_t tbl_winusb_compatible_id_feature_descriptor[40];
extern const uint8_t tbl_winncm_compatible_id_feature_descriptor[40];
extern const uint8_t tbl_rndis_compatible_id_feature_descriptor[40];
extern const uint8_t tbl_winusb_device_interface_guids[142];
extern const uint8_t tbl_net_device_interface_guids[142];
extern const uint8_t tbl_winncm_class_request_get_ntb_params[28];
extern const uint8_t tbl_winusb20_wcid_descriptor_set[162];
/* bcdUSB >= 2.01 , best 2.1 */
extern const uint8_t tbl_winusb20_wcidbos[33];
#ifdef __cplusplus
}
#endif
#endif

138
sdk/include/dev/usb/usb11_v0/hgusb11_v0_dev_api.h Normal file
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#ifndef _HG_USB11_V0_DEV_H
#define _HG_USB11_V0_DEV_H
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/usb_device.h"
enum hgusb11_device_flags {
HGUSB11_DEVICE_FLAGS_OPENED = BIT(0),
HGUSB11_DEVICE_FLAGS_READY = BIT(1),
HGUSB11_DEVICE_FLAGS_SUSPEND = BIT(2),
HGUSB11_DEVICE_FLAGS_DMA_MODE = BIT(3),
HGUSB11_DEVICE_FLAGS_SOFT_SUBPACKAGE = BIT(4),
};
/* USB通信控制块：USB Device Requests */
struct _usb_device_requests {
uint8 bmrequesttype;
uint8 brequest;
uint16 wvalue;
uint16 windex;
uint16 wlength;
};
/* USB EP0控制块：状态机 */
enum _usb_ep0_state {
USB_EP0_STATE_SETUP,
USB_EP0_STATE_OUT,
USB_EP0_STATE_IN,
USB_EP0_STATE_LAST_IN,
USB_EP0_STATE_LAST_OUT,
USB_EP0_STATE_STATUS_IN,
USB_EP0_STATE_STATUS_OUT,
USB_EP0_STATE_STALL,
};
/* USB EP0控制块 */
struct _usb_ep0_ctrl {
enum _usb_ep0_state ep0_state;
//本次要发送包的地址、总长度
uint8 *p_ep0_ptk2send;
uint32 ep0_ptk2send_size;
//偏移量和计数
uint32 ep0_ptk_counter;
uint32 ep0_buf_offset;
//单次发送包的最大长度
uint32 ep0_oneptk_max_size;
uint8 ep0_buf[1024] __attribute__((aligned(4))); //针对iso传输接收非word对齐的数据dma写入的情况 fix:修改64为1024
};
struct usb11_ep_trx_ctrl {
uint32 addr;
uint32 total_bytes;
uint32 max_packet_size;
uint32 cur_addr;
uint32 cur_counter;
uint32 last_counter;
};
union __comm_state{
uint32 comm;
struct {
uint32 dev_open : 1,
dev_host_mode : 1,
dev_device_mode : 1,
reserve : 29;
} comm_bits;
};
typedef union __comm_state hgusb11_dev_v0_comm;
struct hgusb11_dev {
struct usb_device dev;
void *usb_hw;
usbdev_irq_hdl irq_hdl;
uint32 irq_data;
uint8 ep_irq_num;
uint8 dma_irq_num;
/* common areas */
union __comm_state comm_dat;
/* Pointer of common areas */
void *p_comm;
/*
* USB EP0的控制块
*/
struct _usb_ep0_ctrl ep0_ctrl;
struct os_event trx_lock;
struct os_event trx_done;
struct usb11_ep_trx_ctrl ep_trans_ctrl[4];
struct usb11_ep_trx_ctrl ep_recevice_ctrl[4];
//状态位
uint32 flags;
};
int32 hgusb11_v0_dev_ep_set_stall(struct usb_device *p_usb_d, uint8 address);
int32 hgusb11_v0_dev_ep_clear_stall(struct usb_device *p_usb_d, uint8 address);
int32 hgusb11_v0_dev_set_address(struct usb_device *p_usb_d, uint8 address);
int32 hgusb11_v0_dev_set_config(struct usb_device *p_usb_d, uint8 address);
int32 hgusb11_v0_dev_ep_enable(struct usb_device *p_usb_d, uint8 ep, uint16 max_pkt_size, uint8 attributes);
int32 hgusb11_v0_dev_ep_disable(struct usb_device *p_usb_d, uint8 ep);
int32 hgusb11_v0_dev_ep_read(struct usb_device *p_usb_d, uint8 address, void *buffer);
int32 hgusb11_v0_dev_ep_read_prepare(struct usb_device *p_usb_d, uint8 address, void *buffer, uint32 size);
int32 hgusb11_v0_dev_read(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 hgusb11_v0_dev_ep_write(struct usb_device *p_usb_d, uint8 address, void *buffer, uint32 size);
int32 hgusb11_v0_dev_write(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 hgusb11_v0_dev_ep0_send_status(struct usb_device *p_usb_d);
int32 hgusb11_v0_dev_attach(uint32 dev_id, struct hgusb11_dev *p_dev);
int32 hgusb11_v0_dev_close(struct usb_device *p_usb_d);
#ifdef __cplusplus
}
#endif
#endif /* _HG_USB11_V0_DEV_H */

96
sdk/include/dev/usb/usb11_v0/hgusb11_v0_host_api.h Normal file
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#ifndef _HG_USB11_V0_HOST_H
#define _HG_USB11_V0_HOST_H
#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "osal/semaphore.h"
#include "osal/mutex.h"
#include "osal/event.h"
#include "hal/usb_device.h"
#include "dev/usb/usb11_v0/hgusb11_v0_dev_api.h"
#ifdef __cplusplus
extern "C" {
#endif
#define USB11_CORE_HOST_EP_RX 0
#define USB11_CORE_HOST_EP_TX 1
#define USB11_CORE_HOST_EP0_TIMEOUT 18000
#define USB11_EP_ATTR_CONTROL 0x00
#define USB11_EP_ATTR_ISOC 0x01
#define USB11_EP_ATTR_BULK 0x02
#define USB11_EP_ATTR_INT 0x03
#define USB11_EP_ATTR_TYPE_MASK 0x03
#define USB11_DIR_OUT 0
#define USB11_DIR_IN 0x80
enum hgusb11_host_flags {
HGUSB11_HOST_FLAGS_OPENED = BIT(0),
HGUSB11_HOST_FLAGS_READY = BIT(1),
HGUSB11_HOST_FLAGS_SUSPEND = BIT(2),
HGUSB11_HOST_FLAGS_DMA_MODE = BIT(3),
HGUSB11_HOST_FLAGS_SOFT_SUBPACKAGE = BIT(4),
};
enum hgusb11_host_speed_det {
HGUSB11_HOST_NONE = 0,
HGUSB11_HOST_FS,
HGUSB11_HOST_LS,
};
struct hgusb11_host {
struct usb_device dev;
void *usb_hw;
usbdev_irq_hdl irq_hdl;
uint32 irq_data;
uint8 ep_irq_num;
uint8 dma_irq_num;
/*
* USB EP0的控制块
*/
struct _usb_ep0_ctrl ep0_ctrl;
/* Pointer of common areas */
void * p_comm;
struct os_event trx_lock;
struct os_event trx_done;
struct usb11_ep_trx_ctrl ep_trans_ctrl[4];
struct usb11_ep_trx_ctrl ep_recevice_ctrl[4];
//状态位
uint32 flags;
};
int32 hgusb11_v0_host_dev_speed_detect();
int32 hgusb11_v0_host_set_address(uint8 addr);
int32 hgusb11_v0_host_reset();
int32 hgusb11_v0_host_is_ep_crc_err(uint8 ep_num);
int32 hgusb11_v0_host_is_rx_stall(uint8 ep_num, uint8 ep_type);
int32 hgusb11_v0_host_is_xact_err(uint8 ep_num, uint8 ep_type);
int32 hgusb11_v0_host_is_nak_timeout(uint8 ep_num, uint8 ep_type);
void hgusb11_v0_host_clear_data_toggle(uint8 ep_num, uint8 ep_type);
void hgusb11_v0_host_reset_ep_rxcsr(uint8 ep_num);
void hgusb11_v0_host_reset_ep_txcsr(uint8 ep_num);
int32 hgusb11_v0_host_ep_get_rx_dma_len(uint8 ep_num);
int32 hgusb11_v0_host_ep0_tx_kick(struct usb_device *p_usb_d, uint8 setup_pkt, uint8 *buf, uint32 len);
int32 hgusb11_v0_host_ep0_rx_kick(struct usb_device *p_usb_d, uint8* buf, uint32 len);
int32 hgusb11_v0_host_ep_init(struct usb_device *p_usb_d, uint8 tx_or_rx, uint8 ep_num, uint8 ep_addr, uint8 ep_type, uint32 max_pktsize);
int32 hgusb11_v0_host_set_ep_interval(uint8 tx_or_rx, uint8 ep_num, uint32 interval);
int32 hgusb11_v0_host_ep_rx_kick(struct usb_device *p_usb_d, uint8 ep_num, uint8 *buf, uint32 len);
int32 hgusb11_v0_host_ep_tx_kick(struct usb_device *p_usb_d, uint8 ep_num, uint8 *buf, uint32 len, uint8 setup_pkt);
int32 hgusb11_v0_host_ep_abort(struct usb_device *p_usb_d, uint8 tx_or_rx, uint8 ep_num);
int32 hgusb11_v0_host_attch(uint32 dev_id, struct hgusb11_host *p_dev);
#ifdef __cplusplus
}
#endif
#endif

402
sdk/include/dev/usb/uvc_host.h Normal file
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#ifndef _UVC_HOST_H
#define _UVC_HOST_H
#include "typesdef.h"
#include "list.h"
typedef enum
{
UVC_DESCRIPTOR_UNDEFINED=0,
UVC_HEADER,
UVC_INPUT_TERMINAL,
UVC_OUTPUT_TERMINAL,
UVC_SELECTOR_UNIT,
UVC_PROCESSING_UNIT,
UVC_EXTENSION_UNIT,
UVC_ENCODING_UNIT
}VC_Subtype;
typedef enum
{
VS_UNDEFINED=0,
VS_INPUT_HEADER,
VS_OUTPUT_HEADER,
VS_STILL_IMAGE_FRAME,
VS_FORMAT_UNCOMPRESSED,
VS_FRAME_UNCOMPRESSED,
VS_FORMAT_MJPEG,
VS_FRAME_MJPEG,
Reserved,
Reserved1,
VS_FORMAT_MPEG2TS,
Reserved2,
VS_FORMAT_DV,
VS_COLORFORMAT,
Reserved3,
Reserved4,
VS_FORMAT_FRAME_BASED,
VS_FRAME_FRAME_BASED,
VS_FORMAT_STREAM_BASED,
VS_FORMAT_H264,
VS_FRAME_H264,
VS_FORMAT_H264_SIMULCAST
}VS_Subtype;
// Standard Configuration Descriptor
typedef struct
{
uint8 length; // Size of descriptor in uint8
uint8 type; // Configuration
uint16 t_length; // Total length
uint8 num_intf; // Number of interface
uint8 cv; // bConfigurationValue
uint8 index; // iConfiguration
uint8 attr; // Configuration Characteristic
uint8 max_power; // Power config
} SCFG_DESC, *P_SCFG_DESC;
// Standard Interface Descriptor
typedef struct
{
uint8 length;
uint8 type;
uint8 num;
uint8 alt_tring;
uint8 end_points;
uint8 iclass;
uint8 sub;
uint8 proto;
uint8 index;
} SINTF_DESC, *P_INTF_DESC;
// Standard Device Descriptor
typedef struct
{
uint8 length;
uint8 descriptor_type;
uint16 bcd_usb;
uint8 device_class;
uint8 device_subclass;
uint8 device_protocol;
uint8 maxpacket_size0;
uint16 id_vendor;
uint16 id_product;
uint16 bcd_device;
uint8 manufacturer;
uint8 product;
uint8 serial_number;
uint8 num_configurations;
} SDEV_DESC, *P_DEV_DESC;
// Standard EndPoint Descriptor
typedef struct
{
uint8 length;
uint8 type;
uint8 ep_addr;
uint8 attr;
uint16 pay_load; // low-speed this must be 0x08
uint8 interval;
} SEP_DESC, *P_EP_DESC;
struct VC_PROCESS{
uint8 bLength;
uint8 bDescriptorType;
uint8 bDescriptorSubtype;
uint8 bUnitID;
uint8 bSourceID;
uint16 wMaxMultiplier;
uint8 bControlSize;
uint32 bmControls;
uint8 iProcessing;
}__attribute__((packed));
typedef struct{
uint8 bLength;
uint8 bDescriptorType;
uint8 bDescriptorSubtype;
uint8 bFrameIndex;
uint8 bmCapabilities;
uint16 wWidth;
uint16 wHeight;
}VS_FRAME;
typedef struct{
uint8 bLength;
uint8 bDescriptorType;
uint8 bDescriptorSubtype;
uint8 bFrameIndex;
uint8 bNumFrameDescriptors;
}VS_FORMAT;
typedef struct{
uint8 bLength;
uint8 bDescriptorType;
uint8 bDescriptorSubtype;
uint8 bNumFormats;
}VS_HEAD;
#define INTERFACE_Type 0x24
#define STRAME_O_CONTORL 0x04
#define ENDPOINT_DESC 0x05
#define VS_FAME_TYPE_MAXNUM 20
#define VS_FORMAT_TYPE_MAXNUM 2
#define __INTFS_STACK__ 32
#define IS_UVC_JPEG 1
#define USB_DEV_UVC_CLASS 0xef
#define USB_DEV_HUB_CLASS 0X09
#define UVC_SET_REQ 0x21
#define UVC_GET_REQ 0xA1
#define UVC_SET_CUR 0x01
#define UVC_GET_CUR 0x81
#define UVC_GET_MIN 0x82
#define UVC_GET_MAX 0x83
#define UVC_GET_RES 0x84
#define UVC_GET_LEN 0x85
#define UVC_GET_INFO 0x86
#define UVC_GET_DEF 0x87
#define UVC_CLASS 0x0e
#define UAC_CLASS 0x01
#define UVC_VGA 1
#define UVC_720P 2
typedef struct{
uint8 DesLen;
uint8 DescriptorType;
uint8 Subtype;
uint8 control_endpoint;
VS_HEAD vs_head;
VS_FRAME vs_frame[VS_FAME_TYPE_MAXNUM];
VS_FORMAT vs_format[VS_FORMAT_TYPE_MAXNUM];
uint8 vs_frame_num;
uint8 vs_format_num;
uint32 intfs_count;
uint32 edpt_count;
SINTF_DESC intfs[__INTFS_STACK__];
SEP_DESC edpt[__INTFS_STACK__];
struct VC_PROCESS vc_process;
uint8 control_intfs;
}UVC_DES;
typedef struct{
uint8 ep;
uint8 eptpye;
uint16 len;
}EP_DES;
typedef struct
{
uint8 ctyp;
uint8 cv;
uint8 epctl;
uint8 ctl_intfs;
uint8 ctl_altset;
uint8 ctl_pload;
uint8 ctl_ttyp;
uint8 ctl_interval;
uint8 epstrm;
uint8 strm_intfs;
uint8 strm_altset;
uint16 strm_pload;
uint8 strm_ttyp;
uint8 strm_interval;
}UVCDEV;
typedef struct{
uint8 ctl_intfs;
uint32 process_ctl;
uint8 process_unitID;
}UVC_PROCESS;
typedef struct {
uint8 ctl_val;
int16 info;
int16 max;
int16 min;
uint16 res;
int16 cur;
}UVC_PROC_REQ;
typedef struct{
UVC_PROC_REQ brightness;
UVC_PROC_REQ contrast;
UVC_PROC_REQ hue;
UVC_PROC_REQ saturation;
UVC_PROC_REQ sharpness;
UVC_PROC_REQ gamma;
UVC_PROC_REQ white_bal_temp;
UVC_PROC_REQ white_bal_comp;
UVC_PROC_REQ backlight_comp;
UVC_PROC_REQ gain;
UVC_PROC_REQ power_line_fre;
UVC_PROC_REQ hue_auto;
UVC_PROC_REQ white_bal_temp_auto;
UVC_PROC_REQ white_bal_comp_auto;
UVC_PROC_REQ digital_mult;
UVC_PROC_REQ digital_mult_limit;
UVC_PROC_REQ ana_video_stan;
UVC_PROC_REQ ana_lock_sta;
UVC_PROC_REQ contrast_auto;
}UVC_PROCESS_INFO;
typedef enum {
BRIGHTNESS,
CONTRAST,
HUE,
SATURATION,
SHARPNESS,
GAMMA,
WHITE_BAL_TEMP,
WHITE_BAL_COMP,
BACKLIGHT_COMP,
GAIN,
POWER_LINE_FRE,
HUE_AUTO,
WHITE_BAL_TEMP_AUTO,
WHITE_BAL_COMP_AUTO,
DIGITAL_MULT,
DIGITAL_MULT_LIMIT,
ANA_VIDEO_STAN,
ANA_LOCK_STA,
AONTRAST_AUTO
}UVC_PROCESS_ENUM;
typedef struct{
VS_FRAME vs_frame;
VS_FORMAT vs_format;
}UVC_SLEST;
struct VIDEO_COMMIT
{
uint16 bmhint;
uint8 bFormatIndex;
uint8 bFrameIndex;
uint32 dwFrameInterval;
uint16 wKeyFrameRate;
uint16 wPFrameRate;
uint16 wCompQuality;
uint16 wCompWindowSize;
uint16 wDelay;
uint32 dwMaxVideoFrameSize;
uint32 dwMaxPayloadTSize;
}__attribute__((packed));
typedef struct {
struct list_head list;
uint8 *cpbuff; //当前写入数据的地址
uint8 uvc_head[16];//one pack head data
uint8 frame_end; //frame结束标志，表示USB获取数据结束 0：进行中 1：正常结束 2：异常结束
uint32 tgl;
uint32 sta;
uint32 state; //frame状态，0：空闲 1：正在填充 2:可用 3:应用正在使用
uint32 frame_len; //帧长度
uint32 data_len;//one packe data len
uint32 head_len;//one packe head len
uint32 re_space;//当前所写的buff剩余空间
uint32 frame_counter;
}UVC_MANAGE;
typedef struct {
struct list_head list; //BLANK块节点互连
uint32 frame_counter; //此数据块代表的frame号
uint32 blank_len; //blank可使用的数据长度，最后一个数据块非满外，其他都满
uint32 re_space; //当前blank剩下多少空间可填
uint8 blank_loop; //blank计数，每一帧都从0开始增加，便于后面重组
uint8 *buf_ptr; //数据块指针
uint8 busy; //blank块状态，0：空闲 1：正在填充或者发送 2:可用
}UVC_BLANK;
typedef struct{
uint8 addr;
uint8 int_endpoint;
uint8 port_num;
uint8 connect_port;
}HUB_manage;
enum usb_host_io_cmd {
USB_HOST_IO_CMD_RESET, //usb复位
USB_HOST_IO_CMD_SET_CUR,
USB_HOST_IO_CMD_GET_CUR,
USB_HOST_IO_CMD_SET_IDX, //1:VGA, 2:720
};
struct uvc_user_arg
{
void *usb_dev;
uint32_t state; //0:可以创建任务 1:正在运行 2:等待任务删除
uint32_t uvc_format;
};
#define HUB_STATU_CONNECT (BIT(1))
#define HUB_STATU_RESTEND (BIT(1))
/**hub clear feature **/
#define PORT_CONNECT 0x10
#define PORT_ENABLE 0X01
#define CLEAR_PORT_REST 0x14
/**hub set feature **/
#define PORT_POWER 0X08
#define PORT_REST 0x04
#define UVC_EP 2
#define HUB_EP 1
#define UAC_EP 3
#define UVC2_EP 1
#define ISO_HEAD 0
#define BULK_HEAD 12
#define UVC_HEAD BULK_HEAD
#define UVC_HOST_NUM 2
void uvc_room_init(void *p_dev);
void usb_dma_irq(void * dev, uint8_t* uvc_rx_buff, uint8_t uvc_head_res, uint8_t ep_type);
//void usb_host_irq(typedef_usb_t *usb_sw);
void uvc_user();
void uvc_room_init_mjpeg();
void uvc_room_deinit_mjpeg();
void uvc_room_init_h264();
void uvc_room_deinit_h264(void);
void uvc_reset_dev(uint8_t en);
void uvc_reset_dev_mjpeg(uint8_t en);
void uvc_reset_dev_h264(uint8_t en);
void uvc_sema_init();
void uvc_sema_down(int32 tmo_ms);
void uvc_sema_up();
void uvc_app_user_init();
void force_reset_uvc_frame();
UVC_MANAGE* get_uvc_message_gloal();
uint32 get_uvc_frame_len();
uint8* get_uvc_buf();
uint8 free_uvc_blank(UVC_BLANK* uvc_b);
UVC_BLANK* get_uvc_blank();
#endif

37
sdk/include/dev/vpp/hgvpp.h Normal file
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#ifndef HG_VPP_H
#define HG_VPP_H
#include "tx_platform.h"
#include "list.h"
#include "dev.h"
#include "hal/vpp.h"
typedef enum {
HSIE_ISR = 0,
VSIE_ISR,
FRAME_DONE_ISR,
SCIE_ISR,
LOVIE_ISR,
IPF_OV_ISR,
MDPIE_ISR,
ITP_OV_ISR,
ITP_DONE_ISR,
VPP_IRQ_NUM,
}VPP_IRQ_E;
struct hgvpp {
struct vpp_device dev;
//struct hgdvp_hw *hw;
uint32 hw;
vpp_irq_hdl irq_hdl;
uint32 irq_data;
uint32 irq_num;
uint32 opened:1, use_dma:1,exit:1, dsleep:1;
uint32 *cfg_backup;
};
int32 hgvpp_attach(uint32 dev_id, struct hgvpp *vpp);
#endif

44
sdk/include/dev/wdt/hg_wdt_v1.h Normal file
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/**
* @file
* @author LeonLeeV
* @brief
* @version
* TXW80X; TXW81X
* @date 2023-08-07
*
* @copyright Copyright (c) 2023
*
*/
#ifndef _HGWDT_V1_H
#define _HGWDT_V1_H
#include "hal/watchdog.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hg_wdt_v1 {
struct watchdog_device dev;
void *hw;
wdt_irq_hdl irq_hdl;
uint32 irq_num;
uint32 flags;
};
int32 hg_wdt_v1_attach(uint32 dev_id, struct hg_wdt_v1 *watchdog);
#ifdef __cplusplus
}
#endif
#endif

31
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#ifndef _FMAC_DEV_H_
#define _FMAC_DEV_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hgic_fmac_attach(uint32 dev_id, int32 bus_type, const char *fw_data, uint8 reset_io);
int32 fmac_dev_open(struct netdev *ndev);
int32 fmac_dev_close(struct netdev *ndev);
int32 fmac_dev_set_work_mode(struct netdev *ndev, char *mode);
int32 fmac_dev_get_work_mode(struct netdev *ndev, char *buff);//buff size >= 12
int32 fmac_dev_set_ssid(struct netdev *ndev, char *ssid);
int32 fmac_dev_get_ssid(struct netdev *ndev, char *buff);//buff size >= 32
int32 fmac_dev_set_key_mgmt(struct netdev *ndev, char *key_mgmt);
int32 fmac_dev_get_key_mgmt(struct netdev *ndev, char *buff);//buff size >= 12
int32 fmac_dev_set_wpa_psk(struct netdev *ndev, char *psk);
int32 fmac_dev_get_wpa_psk(struct netdev *ndev, char *buff);//buff size >= 64
int32 fmac_dev_set_bss_bw(struct netdev *ndev, uint8 bss_bw);
int32 fmac_dev_set_chan_list(struct netdev *ndev, uint16 *chan_list, uint32 count);
int32 fmac_dev_set_paired_stas(struct netdev *ndev, uint8 *mac_list, uint32 count);
int32 fmac_dev_set_customer_dvrdata(struct netdev *ndev, uint16 cmd_id, uint8 *data, uint32 len); //可以自定义CMD ID
int32 fmac_dev_set_cust_driver_data(struct netdev *ndev, uint8 *data, uint32 len); //不能自定义CMD ID
#ifdef __cplusplus
}
#endif
#endif

15
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#ifndef _SMAC_DEV_H_
#define _SMAC_DEV_H_
#ifdef __cplusplus
extern "C" {
#endif
struct lmac_ops *hgic_smac_detect(uint8 bus_type, struct macbus_param *param, const char *fw_data, uint8 reset_io);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _HG_XSPI_H_
#define _HG_XSPI_H_
#ifdef __cplusplus
extern "C" {
#endif
enum hg_xspi_flags {
hg_xspi_flags_ready,
hg_xspi_flags_suspend,
hg_xspi_flags_suspend_ulp,
hg_xspi_flags_suspend_pd,
};
struct hg_xspi {
struct dev_obj dev;
void *hw;
uint32 irq_num;
//qspi_irq_hdl irq_hdl;
uint32 irq_data;
uint32 opened;
uint32 flags;
uint8_t rst_pin;
void *priv;
//#ifdef CONFIG_SLEEP
#if 1
uint32 sys_regs[6];
uint32 ospi_regs[256 / 4];
#endif
#if 1
int tx[2];
int rx[2][2];
#endif
};
struct hg_xspi_hw;
int32 hg_xspi_attach(uint32 dev_id, struct hg_xspi *p_spi);
void hg_xspi_sample_offset(uint32 ospi_base, int8 rx_offset, int8 tx_offset);
uint32 hg_xspi_get_div(struct hg_xspi_hw *p_qspi, uint8 cs);
int hg_xspi_set_div(struct hg_xspi_hw *p_qspi, uint32 div, uint8 cs_ex);
#ifdef __cplusplus
}
#endif
#endif

88
sdk/include/dev/xspi/hg_xspi_flash.h Normal file
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/**
******************************************************************************
* @file Libraries/Driver/include/LL/tx_peg_ll_qspi.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 01-07-2019
* @brief This file contains all the QSPI LL firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2019 HUGE-IC</center></h2>
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _HG_XSPI_PSRAM_H_
#define _HG_XSPI_PSRAM_H_
#include "dev/xspi/hg_xspi.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/** @addtogroup TX_PEG_StdPeriph_Driver CanesVenatici Driver
* @{
*/
/** @addtogroup qspi_interface_gr QSPI Driver
* @ingroup TX_PEG_StdPeriph_Driver
* @{
*/
/** @addtogroup QSPI_LL_Driver QSPI LL Driver
* @ingroup qspi_interface_gr
* @brief Mainly the driver part of the QSPI module, which includes \b QSPI \b Register
* \b Constants, \b QSPI \b Exported \b Constants, \b QSPI \b Exported \b Struct, \b QSPI
* \b Data \b transfers \b functions, \b QSPI \b Initialization \b and \b QSPI \b Configuration
* \b And \b Interrupt \b Handle \b function.
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/***** DRIVER API *****/
/***** LL API *****/
/***** LL API AND DRIVER API *****/
/*
* @usage:
clk_mhz == 0, use configuration makecode.ini
clk_mhz == other, use parameter clk_mhz
*
*/
int ll_xip_clock_init(int clk_mhz);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif
/*************************** (C) COPYRIGHT 2023 HUGE-IC ***** END OF FILE *****/

115
sdk/include/dev/xspi/hg_xspi_psram.h Normal file
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/**
******************************************************************************
* @file Libraries/Driver/include/LL/tx_peg_ll_qspi.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 01-07-2019
* @brief This file contains all the QSPI LL firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2019 HUGE-IC</center></h2>
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _HG_XSPI_PSRAM_H_
#define _HG_XSPI_PSRAM_H_
#include "dev/xspi/hg_xspi.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/** @addtogroup TX_PEG_StdPeriph_Driver CanesVenatici Driver
* @{
*/
/** @addtogroup qspi_interface_gr QSPI Driver
* @ingroup TX_PEG_StdPeriph_Driver
* @{
*/
/** @addtogroup QSPI_LL_Driver QSPI LL Driver
* @ingroup qspi_interface_gr
* @brief Mainly the driver part of the QSPI module, which includes \b QSPI \b Register
* \b Constants, \b QSPI \b Exported \b Constants, \b QSPI \b Exported \b Struct, \b QSPI
* \b Data \b transfers \b functions, \b QSPI \b Initialization \b and \b QSPI \b Configuration
* \b And \b Interrupt \b Handle \b function.
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
enum psram_type {
PSRAM_NONE,
UPSRAM_4MB,
UPSRAM_4MBx2,
UPSRAM_8MBx2,
UPSRAM_16MB,
APSRAM_4MB,
UNDEFINE,
};
enum psram_clk_alt {
PSRAM_CLK_240M,
PSRAM_CLK_320M,
PSRAM_CLK_274M,
PSRAM_CLK_160M,
PSRAM_CLK_USER = 0xf0,
PSRAM_CLK_MIN = 0xf1,
PSRAM_CLK_MAX = 0xf2,
PSRAM_CLK_END,
};
struct psram_dcfg {
struct list_head list;
uint32_t pid;
void *cfg;
};
/***** DRIVER API *****/
/***** LL API *****/
/***** LL API AND DRIVER API *****/
struct __ctl_clk;
int psram_auto_init(int extern_pt, uint32_t clk);
int32_t psram_init(struct hg_xspi *xspi, void *vcfg);
void psram_deinit(struct hg_xspi *xspi);
void register_psram_dcfg(void *cfg, uint32_t pid);
void* find_psram_dcfg(uint32_t pid);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif
/*************************** (C) COPYRIGHT 2023 HUGE-IC ***** END OF FILE *****/