Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
76
sdk/include/chip/txw82x/adc_voltage_type.h
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76
sdk/include/chip/txw82x/adc_voltage_type.h
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@@ -0,0 +1,76 @@
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/**
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******************************************************************************
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* @file sdk\include\chip\txw80x\adc_voltage_type.h
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* @author HUGE-IC Application Team
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* @version V1.0.0
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* @date 2022-03-18
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* @brief This file contains all the adc_voltage_type.
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* @copyright Copyright (c) 2016-2022 HUGE-IC
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******************************************************************************
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* @attention
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* Only used for txw80x.
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*
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*
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*
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __ADC_VOLTAGE_TYPE_H
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#define __ADC_VOLTAGE_TYPE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Docxygenid_ADC_voltage_type_enum
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* @{
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*/
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/**
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* @brief Enumeration constant for ADC voltage type.
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* @note
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* Enum number start from 0x101.
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*/
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enum adc_voltage_type {
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/*! RF temperature
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*/
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ADC_CHANNEL_RF_TEMPERATURE = 0x101,
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/*! Vtune电压
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*/
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ADC_CHANNEL_VTUNE = 0x102,
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/*!
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* VCO VDD电压
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*/
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ADC_CHANNEL_VCO_VDD = 0x103,
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/*!
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* VDD DIV电压
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*/
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ADC_CHANNEL_VDD_DIV = 0x104,
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/*!
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* VDDI电压
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*/
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ADC_CHANNEL_VDDI = 0x105,
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/*!
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* PMU temperature
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*/
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ADC_CHANNEL_PMU_TEMPERATURE = 0x106,
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/*!
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* vdd core
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*/
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ADC_CHANNEL_CORE_VDD = 0x107,
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};
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/** @} Docxygenid_ADC_voltage_type_enum_enum*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
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30
sdk/include/chip/txw82x/boot_lib.h
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30
sdk/include/chip/txw82x/boot_lib.h
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@@ -0,0 +1,30 @@
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#ifndef __BOOT_LIB_H
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#define __BOOT_LIB_H
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#include "typesdef.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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uint32 get_boot_loader_addr();
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void save_boot_loader_addr();
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uint32 get_boot_total_size();
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uint32 get_boot_version();
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void increase_boot_version();
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void set_boot_msg(uint8 *msg);
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uint32 get_boot_svn_version();
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uint8_t get_psram_status();
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void set_psram_status(uint8_t res);
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uint32 get_boot_loader_offset();
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//返回 0:是代表检查通过 -1:输入长度过短 -2:头部校验不过 -3:头部crc校验不过
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//注意:返回-2或者-3,crc都会被写入一个值(但不一定有效)
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int16 get_code_crc(uint8 *buf,uint32 len,uint16 *crc);//返回ota代码的crc(只需要前面256byte)
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uint16 get_code_crc16(); //获取当前代码的crc
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#ifdef __cplusplus
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}
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#endif
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#endif
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333
sdk/include/chip/txw82x/cld_cache.h
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333
sdk/include/chip/txw82x/cld_cache.h
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@@ -0,0 +1,333 @@
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/*
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* Copyright (C) 2024 ZHUHAI TAIXIN Co., Ltd. All rights reserved.
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*
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*/
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/******************************************************************************
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* @file cld_cahce.h
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* @brief cldache Access Layer Header File
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* @version V1.0
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* @date 2024.5.29
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******************************************************************************/
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#ifndef __CLD_CACHE_H_GENERIC
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#define __CLD_CACHE_H_GENERIC
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#include <stdint.h>
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#include <csi_gcc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*******************************************************************************
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* definitions
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******************************************************************************/
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/**
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\ingroup
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@{
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*/
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/* definitions */
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typedef struct
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{
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__I uint32_t HWPARAMS; //0x000
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__I uint32_t reserve0[3]; //0x004-0x00c
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__IO uint32_t CTRL; //0x010
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__I uint32_t NSEC_ACCESS; //0x014
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__I uint32_t reserve1[2]; //0x018-0x01c
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__O uint32_t MAINT_CTRL_ALL; //0x020
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__O uint32_t MAINT_CTRL_LINES; //0x024
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__I uint32_t MAINT_STATUS; //0x028
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__I uint32_t reserve2[53]; //0x02c-0x0fc
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__I uint32_t SECIRQSTAT; //0x100;
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__O uint32_t SECIRQSCLR; //0x104;
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__IO uint32_t SECIRQEN; //0x108;
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__I uint32_t SECIRQINFO1; //0x10C;
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__I uint32_t SECIRQINFO2; //0x110;
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__I uint32_t reserve3[11]; //0x114-0x13c
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__I uint32_t NSECIRQSTAT; //0x140;
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__O uint32_t NSECIRQSCLR; //0x144;
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__IO uint32_t NSECIRQEN; //0x148;
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__I uint32_t NSECIRQINFO1; //0x14C;
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__I uint32_t NSECIRQINFO2; //0x150;
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__I uint32_t reserve4[107]; //0x154-0x2fc
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__I uint32_t SECHIT; //0x300;
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__I uint32_t SECMISS; //0x304;
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__IO uint32_t SECSTATCTRL; //0x308;
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__I uint32_t reserve5[1]; //0x30c
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__I uint32_t NSECHIT; //0x310;
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__I uint32_t NSECMISS; //0x314;
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__IO uint32_t NSECSTATCTRL; //0x318;
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__I uint32_t reserve6[813]; //0x31c-0xFCC
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__I uint32_t PIDR4; //0xFD0;
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__I uint32_t PIDR5; //0xFD4;
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__I uint32_t PIDR6; //0xFD8;
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__I uint32_t PIDR7; //0xFDC;
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__I uint32_t PIDR0; //0xFE0;
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__I uint32_t PIDR1; //0xFE4;
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__I uint32_t PIDR2; //0xFE8;
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__I uint32_t PIDR3; //0xFEC;
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__I uint32_t CIDR0; //0xFF0;
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__I uint32_t CIDR1; //0xFF4;
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__I uint32_t CIDR2; //0xFF8;
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__I uint32_t CIDR3; //0xFFC;
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} DCACHE_CTRL_TypeDef;
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#define DCACHE_CTRL_BASE2 ((uint32_t)0x50000000)
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#define DCACHE_CTRL ((DCACHE_CTRL_TypeDef *) DCACHE_CTRL_BASE2)
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/* THE memory is forced non-sec */
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#define DCACHE_MAINT_NO_SEC ((uint32_t)0x00000004)
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#define DCACHE_STA_ENABLE ((uint32_t)0x00000001)
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#define DCACHE_STA_ONGOING_EN ((uint32_t)0x00000002)
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#define DCACHE_STA_ONGOING_MAINT ((uint32_t)0x00000004)
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#define DCACHE_STA_ONGOING_PWR_MAINT ((uint32_t)0x00000008)
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#define DCACHE_STA_IS_CLEAN ((uint32_t)0x00000010)
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static inline uint32_t cld_cache_get_status(void)
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{
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return DCACHE_CTRL->MAINT_STATUS;
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}
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static inline uint32_t cld_cache_is_maint_done(void)
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{
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return (0x4 == (DCACHE_CTRL->SECIRQSTAT & 0xC));
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}
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static inline uint32_t cld_cache_is_maint_ignore(void)
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{
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return (DCACHE_CTRL->SECIRQSTAT & 0x8);
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}
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static inline void cld_cache_clr_maint_done(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0x4;
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}
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static inline void cld_cache_clr_maint_ignore(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0x8;
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}
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static inline void cld_cache_clr_all_pending(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0xFF;
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}
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static inline uint32_t cld_cache_is_enable(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ENABLE;
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}
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static inline uint32_t cld_cache_is_clean(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_IS_CLEAN;
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}
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static inline uint32_t cld_cache_is_ongoing_enable(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_EN;
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}
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static inline uint32_t cld_cache_is_ongoing_maint(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_MAINT;
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}
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static inline uint32_t cld_cache_is_ongoing_pwr_maint(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_PWR_MAINT;
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}
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static inline uint32_t cld_cache_is_ongoing(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & (DCACHE_STA_ONGOING_PWR_MAINT | DCACHE_STA_ONGOING_MAINT | DCACHE_STA_ONGOING_EN);
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}
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static inline void cld_cache_force_write_through(void)
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{
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DCACHE_CTRL->CTRL |= 1UL << 1;
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}
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/* TXW82x S_NS ONLY */
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#define CLD_CACHE_MAINT_OPT_ATOMIC(opt)\
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do {\
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uint32 __disable_irq(void);\
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void __enable_irq(void);\
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uint32 flag = __disable_irq();\
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cld_cache_clr_all_pending();\
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opt;\
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while (!cld_cache_is_maint_done());\
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if(!flag) __enable_irq();\
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} while (0);
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#define CLD_CACHE_MAINT_OPT(opt)\
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do {\
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cld_cache_clr_all_pending();\
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opt;\
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while (!cld_cache_is_maint_done());\
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} while (0);
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#define CLD_CACHE_MAINT_OPT_WAIT() //do { while (cld_cache_is_ongoing_maint()); } while (0)
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#define CLD_CACHE_MAINT_FB_KICKOFF()\
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do {\
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extern uint32 psram_rsv_addr;\
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = (psram_rsv_addr & 0xFFFFFFE0) | 0x2 | DCACHE_MAINT_NO_SEC;);\
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*(uint32 volatile*)((uint32_t)psram_rsv_addr);\
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} while(0)
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static inline void cld_cache_clean_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 1;);
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}
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static inline void cld_cache_invalidate_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 2;);
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}
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static inline void cld_cache_clean_invalidate_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 3;);
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}
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static inline void cld_cache_disable(void)
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{
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__DSB();
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cld_cache_invalidate_all();
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DCACHE_CTRL->CTRL &= ~(1UL << 0);
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while (cld_cache_is_enable());
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while (cld_cache_is_ongoing_maint());
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}
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static inline void cld_cache_enable(void)
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{
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cld_cache_disable();
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/* deny powerdown \ enable nsec stat、 maintain lines */
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DCACHE_CTRL->CTRL |= 1UL << 0 | 0x10 | 0x70000;
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while (!cld_cache_is_enable());
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|
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}
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static inline void cld_cache_irq_enable(void)
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{
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/* ONLY ERROR : XOM_ERR(not support) & TR_ERR */
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DCACHE_CTRL->SECIRQEN = 0x90;
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||||
}
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static inline void cld_cache_clean_line(uint32_t addr)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = ((uint32_t)addr & (0xFFFFFFFF << 5)) | 0x1 | DCACHE_MAINT_NO_SEC;);
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CLD_CACHE_MAINT_OPT_WAIT();
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}
|
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|
||||
|
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/**
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\brief D-Cache Clean by address
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\details Cleans D-Cache for the given address
|
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
|
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static inline void cld_cache_clean_range (uint32_t *addr, int32_t dsize)
|
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{
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int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
|
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uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
|
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int32_t linesize = 32;
|
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|
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op_addr |= 0x1 | DCACHE_MAINT_NO_SEC;
|
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|
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while (op_size > 0) {
|
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
|
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CLD_CACHE_MAINT_OPT_WAIT();
|
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}
|
||||
__DSB();
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
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\brief D-Cache Clean and Invalidate by address
|
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\details Cleans and invalidates D_Cache for the given address
|
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\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
static inline void cld_cache_clean_invalid_range (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
|
||||
uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
|
||||
int32_t linesize = 32;
|
||||
|
||||
op_addr |= 0x3 | DCACHE_MAINT_NO_SEC;
|
||||
|
||||
while (op_size > 0) {
|
||||
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
|
||||
CLD_CACHE_MAINT_OPT_WAIT();
|
||||
}
|
||||
__DSB();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
static inline void cld_cache_invalid_range (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
|
||||
uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
|
||||
int32_t linesize = 32;
|
||||
|
||||
op_addr |= 0x2 | DCACHE_MAINT_NO_SEC;
|
||||
|
||||
CLD_CACHE_MAINT_FB_KICKOFF();
|
||||
|
||||
while (op_size > 0) {
|
||||
CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
|
||||
CLD_CACHE_MAINT_OPT_WAIT();
|
||||
}
|
||||
__DSB();
|
||||
|
||||
|
||||
}
|
||||
|
||||
static inline uint32_t cld_cache_get_nsec_hits(void)
|
||||
{
|
||||
return DCACHE_CTRL->NSECHIT;
|
||||
}
|
||||
static inline uint32_t cld_cache_get_nsec_miss(void)
|
||||
{
|
||||
return DCACHE_CTRL->NSECMISS;
|
||||
}
|
||||
static inline void cld_cache_reset_profile(void)
|
||||
{
|
||||
DCACHE_CTRL->NSECSTATCTRL |= 0x2;
|
||||
|
||||
}
|
||||
|
||||
static inline void cld_cache_enable_profile(void)
|
||||
{
|
||||
while (cld_cache_is_ongoing());
|
||||
|
||||
DCACHE_CTRL->NSECSTATCTRL |= 0x1;
|
||||
|
||||
}
|
||||
|
||||
static inline void cld_cache_disable_profile(void)
|
||||
{
|
||||
DCACHE_CTRL->NSECSTATCTRL &= ~ 0x1;
|
||||
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CLD_CACHE_H_GENERIC */
|
||||
|
||||
660
sdk/include/chip/txw82x/io_function.h
Normal file
660
sdk/include/chip/txw82x/io_function.h
Normal file
@@ -0,0 +1,660 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file sdk\include\chip\txw80x\io_function.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @version V1.0.0
|
||||
* @date 2022-01-11
|
||||
* @brief This file contains all the GPIO functions.
|
||||
* @copyright Copyright (c) 2016-2022 HUGE-IC
|
||||
******************************************************************************
|
||||
* @attention
|
||||
* Only used for txw80x.
|
||||
*
|
||||
*
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __IO_FUNCTION_H
|
||||
#define __IO_FUNCTION_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "typesdef.h"
|
||||
|
||||
|
||||
#define REG_GPIO_DIR_CLR(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x00)) &= ~(3<<((n)<<1))
|
||||
|
||||
#define REG_GPIO_DIR_INPUT(port, n) \
|
||||
do { \
|
||||
REG_GPIO_DIR_CLR(port, n); \
|
||||
(*(volatile unsigned int*)(port+0x00)) |= (0<<((n)<<1)); \
|
||||
} while(0)
|
||||
|
||||
#define REG_GPIO_DIR_OUTPUT(port, n) \
|
||||
do { \
|
||||
REG_GPIO_DIR_CLR(port, n); \
|
||||
(*(volatile unsigned int*)(port+0x00)) |= (1<<((n)<<1)); \
|
||||
} while(0)
|
||||
|
||||
#define REG_GPIO_OTYPE_CLR(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x04)) &= ~(1<<(n));
|
||||
|
||||
#define REG_GPIO_OPEN_DRAIN(port, n) \
|
||||
do { \
|
||||
REG_GPIO_OTYPE_CLR(port, n); \
|
||||
(*(volatile unsigned int*)(port+0x04)) |= (1<<(n));\
|
||||
} while(0)
|
||||
|
||||
#define REG_GPIO_PUSH_PULL(port, n) \
|
||||
do { \
|
||||
REG_GPIO_OTYPE_CLR(port, n); \
|
||||
(*(volatile unsigned int*)(port+0x04)) |= (0<<(n));\
|
||||
} while(0)
|
||||
|
||||
#define REG_GPIO_PUL_100(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x10)) |= BIT((((n)-0)<<2))
|
||||
#define REG_GPIO_PUH_100(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x14)) |= BIT((((n)-8)<<2))
|
||||
|
||||
#define REG_GPIO_PDL_100(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x18)) |= BIT((((n)-0)<<2))
|
||||
#define REG_GPIO_PDH_100(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x1C)) |= BIT((((n)-8)<<2))
|
||||
|
||||
#define REG_GPIO_SET(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x24)) = \
|
||||
((*(volatile unsigned int*)(port+0x24)) & ~BIT(n)) | BIT(n)
|
||||
|
||||
#define REG_GPIO_RESET(port, n) \
|
||||
(*(volatile unsigned int*)(port+0x24)) = \
|
||||
((*(volatile unsigned int*)(port+0x24)) & ~BIT(n))
|
||||
|
||||
/** @addtogroup Docxygenid_GPIO_enum
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for GPIO command.
|
||||
* @note
|
||||
* Enum number start from 0x101.
|
||||
*/
|
||||
enum gpio_cmd {
|
||||
/*! GPIO cmd afio set
|
||||
*/
|
||||
GPIO_CMD_AFIO_SET = 0x101,
|
||||
|
||||
/*! GPIO cmd iomap output
|
||||
*/
|
||||
GPIO_CMD_IOMAP_OUT_FUNC,
|
||||
|
||||
/*! GPIO cmd iomap input
|
||||
*/
|
||||
GPIO_CMD_IOMAP_IN_FUNC,
|
||||
|
||||
/*! GPIO cmd iomap inout
|
||||
*/
|
||||
GPIO_CMD_IOMAP_INOUT_FUNC,
|
||||
|
||||
/*! GPIO pin driver strength config
|
||||
*/
|
||||
GPIO_CMD_DRIVER_STRENGTH,
|
||||
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enumeration constant for GPIO afio set.
|
||||
*/
|
||||
enum gpio_afio_set{
|
||||
/*! gpio cmd afio 0
|
||||
*/
|
||||
GPIO_AF_0 = 0,
|
||||
|
||||
/*! gpio cmd afio 1
|
||||
*/
|
||||
GPIO_AF_1 ,
|
||||
|
||||
/*! gpio cmd afio 2
|
||||
*/
|
||||
GPIO_AF_2 ,
|
||||
|
||||
/*! gpio cmd afio 3
|
||||
*/
|
||||
GPIO_AF_3 ,
|
||||
};
|
||||
|
||||
/**
|
||||
* @breif : Enumeration constant for GPIO pull level.
|
||||
*/
|
||||
enum gpio_pull_level {
|
||||
/*! gpio pull level : NONE
|
||||
*/
|
||||
GPIO_PULL_LEVEL_NONE = 0,
|
||||
|
||||
/*! gpio pull level : 4.7K
|
||||
*/
|
||||
GPIO_PULL_LEVEL_4_7K ,
|
||||
|
||||
/*! gpio pull level : 100k
|
||||
*/
|
||||
GPIO_PULL_LEVEL_100K ,
|
||||
};
|
||||
|
||||
/**
|
||||
* @breif : Enumeration constant for GPIO driver strength
|
||||
*/
|
||||
enum pin_driver_strength {
|
||||
/**
|
||||
*对于81x, 分别对应4, 12, 20, 28mA
|
||||
*对于82x, 分别对应4, 8, 16, 20mA. 对于PB12/PD8/PD14/PE1, 则分别是8, 20, 32, 60mA
|
||||
*/
|
||||
GPIO_DS_G0,
|
||||
GPIO_DS_G1,
|
||||
GPIO_DS_G2,
|
||||
GPIO_DS_G3,
|
||||
};
|
||||
|
||||
/** @defgroup GPIO IO map output function selection
|
||||
* @{
|
||||
*/
|
||||
//除了GPIO_IOMAP_OUTPUT， 不能同时存在两个及以上 [ (枚举值+4)/5 ]相同的GPIO OUTPUT MAPPING 配置，下表已经分好类了
|
||||
enum gpio_iomap_out_func{
|
||||
GPIO_IOMAP_OUTPUT = 0,
|
||||
GPIO_IOMAP_OUT_OSPI_CS_IO = 0x1,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_8 = 0x2,
|
||||
GPIO_IOMAP_OUT_LCD_DE_OR_ERD = 0x3,
|
||||
GPIO_IOMAP_OUT_COMP_DOUT_DIG0 = 0x5,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_0 = 0x6,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_0 = 0x7,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_9 = 0x8,
|
||||
GPIO_IOMAP_OUT_COMP_DOUT_DIG1 = 0xA,
|
||||
GPIO_IOMAP_OUT_LCD_DE_OR_ERD1 = 0xB,
|
||||
GPIO_IOMAP_OUT_ANTENNA_SEL = 0xF,
|
||||
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC = 0x10,
|
||||
GPIO_IOMAP_OUT_PA_EN = 0x14,
|
||||
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS0 = 0x15,
|
||||
GPIO_IOMAP_OUT_RF_EXT_LNA_EN = 0x19,
|
||||
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR0 = 0x1A,
|
||||
GPIO_IOMAP_OUT_RF_SWITCH_EN1 = 0x1B,
|
||||
GPIO_IOMAP_OUT_RF_TX_EN_FEM = 0x1E,
|
||||
GPIO_IOMAP_OUT_RF_SWITCH_EN0 = 0x1F,
|
||||
GPIO_IOMAP_OUT_DVP_MCLK_OUT = 0x20,
|
||||
GPIO_IOMAP_OUT_RF_RX_EN_FEM = 0x23,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_1 = 0x24,
|
||||
GPIO_IOMAP_OUT_RF_TRX_SW_FEM = 0x25,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_1 = 0x28,
|
||||
GPIO_IOMAP_OUT_DAC_PDM_OUT = 0x29,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_2 = 0x2A,
|
||||
GPIO_IOMAP_OUT_RF_PA_EN_FEM = 0x2B,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_2 = 0x2D,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_3 = 0x2E,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_3 = 0x2F,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_0 = 0x30,
|
||||
GPIO_IOMAP_OUT_UART1_RTS_RE_O = 0x32,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_4 = 0x33,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_4 = 0x34,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_1 = 0x35,
|
||||
GPIO_IOMAP_OUT_UART1_CTS_DE_OUT = 0x37,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_5 = 0x38,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_5 = 0x39,
|
||||
GPIO_IOMAP_OUT_UART1_OUT = 0x3C,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_2 = 0x3D,
|
||||
GPIO_IOMAP_OUT_UART0_RTS_RE_O = 0x41,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_3 = 0x42,
|
||||
GPIO_IOMAP_OUT_UART0_CTS_DE_OUT = 0x46,
|
||||
GPIO_IOMAP_OUT_UART0_OUT = 0x4B,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_6 = 0x4C,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_6 = 0x4D,
|
||||
GPIO_IOMAP_OUT_STMR3_PWM_OUT = 0x50,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_7 = 0x51,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_7 = 0x52,
|
||||
GPIO_IOMAP_OUT_STMR2_PWM_OUT = 0x55,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_8 = 0x56,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_8 = 0x57,
|
||||
GPIO_IOMAP_OUT_STMR1_PWM_OUT = 0x5A,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_9 = 0x5B,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_9 = 0x5C,
|
||||
GPIO_IOMAP_OUT_STMR0_PWM_OUT = 0x5F,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_10 = 0x60,
|
||||
GPIO_IOMAP_OUT_VIDEO_PAR_DATA_O_10 = 0x61,
|
||||
GPIO_IOMAP_OUT_STMR4_PWM_OUT = 0x64,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_11 = 0x65,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_6 = 0x66,
|
||||
GPIO_IOMAP_OUT_STMR5_PWM_OUT = 0x69,
|
||||
GPIO_IOMAP_OUT_SPI0_IO3_OUT = 0x6A,
|
||||
GPIO_IOMAP_OUT_SDHOST_SCLK_O = 0x6E,
|
||||
GPIO_IOMAP_OUT_SPI0_IO2_OUT = 0x6F,
|
||||
GPIO_IOMAP_OUT_TMR3_PWM_OUT = 0x73,
|
||||
GPIO_IOMAP_OUT_SPI0_IO1_OUT = 0x74,
|
||||
GPIO_IOMAP_OUT_TMR2_PWM_OUT = 0x78,
|
||||
GPIO_IOMAP_OUT_SPI1_NSS_OUT = 0x79,
|
||||
GPIO_IOMAP_OUT_TMR1_PWM_OUT = 0x7D,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_12 = 0x7E,
|
||||
GPIO_IOMAP_OUT_TMR0_PWM_OUT = 0x82,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_4 = 0x83,
|
||||
GPIO_IOMAP_OUT_SDHOST1_DAT1_OUT = 0x84,
|
||||
GPIO_IOMAP_OUT_DUAL_ORG_FSYNC = 0x85,
|
||||
GPIO_IOMAP_OUT_LED_TMR0_PWM_OUT = 0x87,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_13 = 0x88,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_5 = 0x89,
|
||||
GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT = 0x8C,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_14 = 0x8D,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_6 = 0x8E,
|
||||
GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT = 0x91,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_15 = 0x92,
|
||||
GPIO_IOMAP_OUT_DBGPATH_DBGO_7 = 0x93,
|
||||
GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT = 0x96,
|
||||
GPIO_IOMAP_OUT_CAN_TXD = 0x97,
|
||||
GPIO_IOMAP_OUT_CPU1_JTG_TMS = 0x98,
|
||||
GPIO_IOMAP_OUT_PDM_MCLK = 0x9B,
|
||||
GPIO_IOMAP_OUT_OSPI_CS_IO1 = 0x9C,
|
||||
GPIO_IOMAP_OUT_QSPI_NSS1_OUT = 0xA0,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_0 = 0xA1,
|
||||
GPIO_IOMAP_OUT_GRANT_BLE = 0xA2,
|
||||
GPIO_IOMAP_OUT_SPI0_NSS_OUT = 0xA5,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_1 = 0xA6,
|
||||
GPIO_IOMAP_OUT_GRANT_BLE_SWITCH_O = 0xA7,
|
||||
GPIO_IOMAP_OUT_SPI0_SCK_OUT = 0xAA,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_2 = 0xAB,
|
||||
GPIO_IOMAP_OUT_GRANT_WIFI_SWITCH_O = 0xAC,
|
||||
GPIO_IOMAP_OUT_SPI0_IO0_OUT = 0xAF,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_3 = 0xB0,
|
||||
GPIO_IOMAP_OUT_SPARE0 = 0xB4,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_4 = 0xB5,
|
||||
GPIO_IOMAP_OUT_SPARE1 = 0xB9,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_5 = 0xBA,
|
||||
GPIO_IOMAP_OUT_SPARE2 = 0xBE,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_7 = 0xBF,
|
||||
GPIO_IOMAP_OUT_SPARE3 = 0xC3,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_8 = 0xC4,
|
||||
GPIO_IOMAP_OUT_SPI1_SCK_OUT = 0xC8,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_9 = 0xC9,
|
||||
GPIO_IOMAP_OUT_SPI1_IO0_OUT = 0xCD,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_10 = 0xCE,
|
||||
GPIO_IOMAP_OUT_SPI1_IO1_OUT = 0xD2,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_11 = 0xD3,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_16 = 0xD7,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_12 = 0xD8,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_17 = 0xDC,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_13 = 0xDD,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_18 = 0xDE,
|
||||
GPIO_IOMAP_OUT_SPI2_NSS_OUT = 0xE1,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_14 = 0xE2,
|
||||
GPIO_IOMAP_OUT_SDHOST1_SCLK_O = 0xE3,
|
||||
GPIO_IOMAP_OUT_SPI2_SCK_OUT = 0xE6,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_15 = 0xE7,
|
||||
GPIO_IOMAP_OUT_SDHOST1_DAT0_OUT = 0xE8,
|
||||
GPIO_IOMAP_OUT_SPI2_IO0_OUT = 0xEB,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_16 = 0xEC,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_19 = 0xED,
|
||||
GPIO_IOMAP_OUT_SDHOST1_CMD_OUT = 0xEE,
|
||||
GPIO_IOMAP_OUT_SPI2_IO1_OUT = 0xF0,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_17 = 0xF1,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_20 = 0xF2,
|
||||
GPIO_IOMAP_OUT_SDHOST1_DAT2_OUT = 0xF3,
|
||||
GPIO_IOMAP_OUT_SPI2_IO2_OUT = 0xF5,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_18 = 0xF6,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_21 = 0xF7,
|
||||
GPIO_IOMAP_OUT_SDHOST1_DAT3_OUT = 0xF8,
|
||||
GPIO_IOMAP_OUT_SPI2_IO3_OUT = 0xFA,
|
||||
GPIO_IOMAP_OUT_QSPI_OSPI_MNT_O_19 = 0xFB,
|
||||
GPIO_IOMAP_OUT_SDHOST_CMD_OUT = 0xFF,
|
||||
GPIO_IOMAP_OUT_UART6_TX = 0x100,
|
||||
GPIO_IOMAP_OUT_SDHOST_DAT0_OUT = 0x104,
|
||||
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR1 = 0x105,
|
||||
GPIO_IOMAP_OUT_SDHOST_DAT1_OUT = 0x109,
|
||||
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS1 = 0x10A,
|
||||
GPIO_IOMAP_OUT_SDHOST_DAT2_OUT = 0x10E,
|
||||
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC1 = 0x10F,
|
||||
GPIO_IOMAP_OUT_SDHOST_DAT3_OUT = 0x113,
|
||||
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR2 = 0x114,
|
||||
GPIO_IOMAP_OUT_IO2IO_CHANNAL3 = 0x115,
|
||||
GPIO_IOMAP_OUT_IIS0_MCLK_OUT = 0x118,
|
||||
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS2 = 0x119,
|
||||
GPIO_IOMAP_OUT_IO2IO_CHANNAL2 = 0x11A,
|
||||
GPIO_IOMAP_OUT_IIS0_WSCLK_OUT = 0x11D,
|
||||
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC2 = 0x11E,
|
||||
GPIO_IOMAP_OUT_IO2IO_CHANNAL1 = 0x11F,
|
||||
GPIO_IOMAP_OUT_IIS0_BCLK_OUT = 0x122,
|
||||
GPIO_IOMAP_OUT_LCD_DE_OR_ERD2 = 0x123,
|
||||
GPIO_IOMAP_OUT_IO2IO_CHANNAL0 = 0x124,
|
||||
GPIO_IOMAP_OUT_IIS0_DO = 0x127,
|
||||
GPIO_IOMAP_OUT_UART5_TX = 0x128,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_22 = 0x129,
|
||||
GPIO_IOMAP_OUT_IIS1_MCLK_OUT = 0x12C,
|
||||
GPIO_IOMAP_OUT_LCD_DATA_O_23 = 0x12D,
|
||||
GPIO_IOMAP_OUT_NFC_TX_GATE_N = 0x12E,
|
||||
GPIO_IOMAP_OUT_IIS1_WSCLK_OUT = 0x131,
|
||||
GPIO_IOMAP_OUT_SPI1_IO2_OUT = 0x132,
|
||||
GPIO_IOMAP_OUT_NFC_TX_N = 0x133,
|
||||
GPIO_IOMAP_OUT_IIS1_BCLK_OUT = 0x136,
|
||||
GPIO_IOMAP_OUT_SPI1_IO3_OUT = 0x137,
|
||||
GPIO_IOMAP_OUT_NFC_TX_GATE_P = 0x138,
|
||||
GPIO_IOMAP_OUT_IIS1_DO = 0x13B,
|
||||
GPIO_IOMAP_OUT_UART4_TX = 0x13C,
|
||||
GPIO_IOMAP_OUT_NFC_TX_P = 0x13D,
|
||||
GPIO_IOMAP_OUT_CLK_TO_IO = 0x140,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/** @defgroup Enumeration constant for GPIO IO map input function selection
|
||||
* @{
|
||||
*/
|
||||
enum gpio_iomap_in_func{
|
||||
GPIO_IOMAP_INPUT = 0xF000,
|
||||
GPIO_IOMAP_IN_SPARE_IO1 = 0x0000,
|
||||
GPIO_IOMAP_IN_SPARE_IO2,
|
||||
GPIO_IOMAP_IN_SPARE_IO3,
|
||||
GPIO_IOMAP_IN_TMR2_CAP_IN,
|
||||
GPIO_IOMAP_IN_TMR3_CAP_IN,
|
||||
GPIO_IOMAP_IN_PDM_DATA_IN_EPWM_TZ1_M3_2,
|
||||
GPIO_IOMAP_IN_PTA_REQ_IN_EPWM_TZ2_M3_3,
|
||||
GPIO_IOMAP_IN_PTA_PRI_IN_EPWM_TZ3_M3_4,
|
||||
GPIO_IOMAP_IN_FREQ_IND_IN_EPWM_TZ4_M3_5,
|
||||
GPIO_IOMAP_IN_STMR0_CAP_IN_LCD_D3_IN_M1_22_EPWM_SYNC_IO_M3_6,
|
||||
GPIO_IOMAP_IN_STMR1_CAP_IN_LCD_D4_IN_M1_23,
|
||||
GPIO_IOMAP_IN_STMR2_CAP_IN_LCD_D5_IN_M1_24,
|
||||
GPIO_IOMAP_IN_STMR3_CAP_IN_LCD_D6_IN_M1_25,
|
||||
GPIO_IOMAP_IN_PORT_WKUP_IN0 = 13,
|
||||
GPIO_IOMAP_IN_TMR0_CAP_IN = 13,
|
||||
GPIO_IOMAP_IN_PORT_WKUP_IN1_LCD_D7_IN_M1_26 = 14,
|
||||
GPIO_IOMAP_IN_TMR0_SYNCI = 14,
|
||||
GPIO_IOMAP_IN_EXT_RFSWITCH_EN0 = 14,
|
||||
GPIO_IOMAP_IN_PORT_WKUP_IN2_LCD_D8_IN_M1_27 = 15,
|
||||
GPIO_IOMAP_IN_TMR1_CAP_IN = 15,
|
||||
GPIO_IOMAP_IN_PORT_WKUP_IN3_LCD_TE_M0_10,
|
||||
GPIO_IOMAP_IN_UART0_IN,
|
||||
GPIO_IOMAP_IN_UART0_CTS_DE_IN,
|
||||
GPIO_IOMAP_IN_UART1_IN_LCD_D9_IN_M1_28,
|
||||
GPIO_IOMAP_IN_UART1_CTS_DE_IN_LCD_D10_IN_M1_29,
|
||||
GPIO_IOMAP_IN_FB_IN_EXT_PA_EN_SYS_NMI_CAN_RXD,
|
||||
GPIO_IOMAP_IN_UART4_IN,
|
||||
GPIO_IOMAP_IN_LCD_D0_IN_M1_19,
|
||||
GPIO_IOMAP_IN_SPI0_NSS_IN,
|
||||
GPIO_IOMAP_IN_SPI0_SCK_IN,
|
||||
GPIO_IOMAP_IN_SPI0_IO0_IN,
|
||||
GPIO_IOMAP_IN_SPI0_IO1_IN,
|
||||
GPIO_IOMAP_IN_SPI0_IO2_IN,
|
||||
GPIO_IOMAP_IN_SPI0_IO3_IN,
|
||||
GPIO_IOMAP_IN_SPI1_NSS_IN_LCD_D11_IN_M1_30,
|
||||
GPIO_IOMAP_IN_SPI1_SCK_IN,
|
||||
GPIO_IOMAP_IN_SPI1_IO0_IN,
|
||||
GPIO_IOMAP_IN_SPI1_IO1_IN_LCD_D12_IN_M1_31,
|
||||
GPIO_IOMAP_IN_LCD_D1_IN_M1_20,
|
||||
GPIO_IOMAP_IN_LCD_D2_IN_M1_21,
|
||||
GPIO_IOMAP_IN_SPI2_NSS_IN_LCD_D13_IN_M2_0,
|
||||
GPIO_IOMAP_IN_SPI2_SCK_IN,
|
||||
GPIO_IOMAP_IN_SPI2_IO0_IN,
|
||||
GPIO_IOMAP_IN_SPI2_IO1_IN_LCD_D14_IN_M2_1,
|
||||
GPIO_IOMAP_IN_SPI2_IO2_IN_LCD_D15_IN_M2_2,
|
||||
GPIO_IOMAP_IN_SPI2_IO3_IN_LCD_D16_IN_M2_3,
|
||||
GPIO_IOMAP_IN_STMR4_CAP_IN_LCD_D17_IN_M2_4,
|
||||
GPIO_IOMAP_IN_STMR5_CAP_IN_LCD_D18_IN_M2_5,
|
||||
GPIO_IOMAP_IN_SDHOST_CMD_IN,
|
||||
GPIO_IOMAP_IN_SDHOST_DAT0_IN,
|
||||
GPIO_IOMAP_IN_SDHOST_DAT1_IN,
|
||||
GPIO_IOMAP_IN_SDHOST_DAT2_IN,
|
||||
GPIO_IOMAP_IN_SDHOST_DAT3_IN,
|
||||
GPIO_IOMAP_IN_IIS0_MCLK_IN_LCD_D19_IN_M2_6,
|
||||
GPIO_IOMAP_IN_IIS0_WSCLK_IN_LCD_D20_IN_M2_7,
|
||||
GPIO_IOMAP_IN_IIS0_BCLK_IN_LCD_D21_IN_M2_8,
|
||||
GPIO_IOMAP_IN_IIS0_DAT_IN_UART6_RX_M3_9,
|
||||
GPIO_IOMAP_IN_IIS1_MCLK_IN_Uart5_IN_LCD_D22_IN_M2_9,
|
||||
GPIO_IOMAP_IN_IIS1_WSCLK_IN_LCD_D23_IN_M2_10,
|
||||
GPIO_IOMAP_IN_SPI1_IO2_IN_IIS1_BCLK_IN,
|
||||
GPIO_IOMAP_IN_SPI1_IO3_IN_IIS1_DAT_IN_UART6_RX_M3_9,
|
||||
};
|
||||
|
||||
|
||||
/** @defgroup Enumeration constant for GPIO spare iomap function
|
||||
* @{ 选择一个IO连接到备用的功能点上， 解决同组MAP无法复用的问题
|
||||
*
|
||||
*/
|
||||
enum smap_node{
|
||||
SMAP_OUT_0 = 0,
|
||||
SMAP_OUT_1,
|
||||
SMAP_OUT_2,
|
||||
SMAP_OUT_3,
|
||||
|
||||
SMAP_IN_1,
|
||||
SMAP_IN_2,
|
||||
SMAP_IN_3,
|
||||
};
|
||||
|
||||
enum smap_output{
|
||||
SMAP_OUT_RF_EXT_LNA_EN ,
|
||||
SMAP_OUT_RF_TX_EN_FEM ,
|
||||
SMAP_OUT_RF_SWITCH_EN1 ,
|
||||
SMAP_OUT_RF_RX_EN_FEM ,
|
||||
SMAP_OUT_RF_SWITCH_EN0 ,
|
||||
SMAP_OUT_RF_TRX_SW_FEM ,
|
||||
SMAP_OUT_RF_PA_EN_FEM ,
|
||||
SMAP_OUT_GRANT_BLE ,
|
||||
SMAP_OUT_GRANT_BLE_SWITCH_O ,
|
||||
SMAP_OUT_GRANT_WIFI_SWITCH_O ,
|
||||
SMAP_OUT_UART0_RTS_RE_O ,
|
||||
SMAP_OUT_UART0_CTS_DE_OUT ,
|
||||
SMAP_OUT_UART0_OUT ,
|
||||
SMAP_OUT_UART1_RTS_RE_O ,
|
||||
SMAP_OUT_UART1_CTS_DE_OUT ,
|
||||
SMAP_OUT_UART1_OUT ,
|
||||
SMAP_OUT_UART4_TX ,
|
||||
SMAP_OUT_UART5_TX ,
|
||||
SMAP_OUT_UART6_TX ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_0 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_1 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_2 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_3 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_4 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_5 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_6 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_7 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_8 ,
|
||||
SMAP_OUT_VIDEO_PAR_DATA_O_9 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_0 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_1 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_2 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_3 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_4 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_5 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_6 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_7 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_8 ,
|
||||
SMAP_OUT_DBGPATH_DBGO_9 ,
|
||||
SMAP_OUT_STMR0_PWM_OUT ,
|
||||
SMAP_OUT_STMR1_PWM_OUT ,
|
||||
SMAP_OUT_STMR2_PWM_OUT ,
|
||||
SMAP_OUT_STMR3_PWM_OUT ,
|
||||
SMAP_OUT_STMR4_PWM_OUT ,
|
||||
SMAP_OUT_STMR5_PWM_OUT ,
|
||||
SMAP_OUT_TMR3_PWM_OUT ,
|
||||
SMAP_OUT_TMR2_PWM_OUT ,
|
||||
SMAP_OUT_TMR1_PWM_OUT ,
|
||||
SMAP_OUT_TMR0_PWM_OUT ,
|
||||
SMAP_OUT_LED_TMR0_PWM_OUT ,
|
||||
SMAP_OUT_LED_TMR1_PWM_OUT ,
|
||||
SMAP_OUT_LED_TMR2_PWM_OUT ,
|
||||
SMAP_OUT_LED_TMR3_PWM_OUT ,
|
||||
SMAP_OUT_OSPI_CS_IO ,
|
||||
SMAP_OUT_QSPI_NSS1_OUT ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_0 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_1 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_2 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_3 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_4 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_5 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_6 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_7 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_8 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_9 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_10 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_11 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_12 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_13 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_14 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_15 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_16 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_17 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_18 ,
|
||||
SMAP_OUT_QSPI_OSPI_MNT_O_19 ,
|
||||
SMAP_OUT_SDHOST1_CMD_OUT ,
|
||||
SMAP_OUT_SDHOST1_SCLK_O ,
|
||||
SMAP_OUT_SDHOST1_DAT0_OUT,
|
||||
SMAP_OUT_SDHOST1_DAT1_OUT,
|
||||
SMAP_OUT_SDHOST1_DAT2_OUT,
|
||||
SMAP_OUT_SDHOST1_DAT3_OUT,
|
||||
SMAP_OUT_SDHOST_SCLK_O ,
|
||||
SMAP_OUT_SDHOST_CMD_OUT ,
|
||||
SMAP_OUT_SDHOST_DAT0_OUT ,
|
||||
SMAP_OUT_SDHOST_DAT1_OUT ,
|
||||
SMAP_OUT_SDHOST_DAT2_OUT ,
|
||||
SMAP_OUT_SDHOST_DAT3_OUT ,
|
||||
SMAP_OUT_IO2IO_CHANNAL3 ,
|
||||
SMAP_OUT_IO2IO_CHANNAL2 ,
|
||||
SMAP_OUT_IO2IO_CHANNAL1 ,
|
||||
SMAP_OUT_IO2IO_CHANNAL0 ,
|
||||
SMAP_OUT_IIS1_WSCLK_OUT ,
|
||||
SMAP_OUT_IIS1_BCLK_OUT ,
|
||||
SMAP_OUT_IIS1_DO ,
|
||||
SMAP_OUT_IIS1_MCLK_OUT ,
|
||||
SMAP_OUT_IIS0_MCLK_OUT ,
|
||||
SMAP_OUT_IIS0_WSCLK_OUT ,
|
||||
SMAP_OUT_IIS0_BCLK_OUT ,
|
||||
SMAP_OUT_IIS0_DO ,
|
||||
SMAP_OUT_LCD_DATA_O_0 ,
|
||||
SMAP_OUT_LCD_DATA_O_1 ,
|
||||
SMAP_OUT_LCD_DATA_O_2 ,
|
||||
SMAP_OUT_LCD_DATA_O_3 ,
|
||||
SMAP_OUT_LCD_DATA_O_4 ,
|
||||
SMAP_OUT_LCD_DATA_O_5 ,
|
||||
SMAP_OUT_LCD_DATA_O_6 ,
|
||||
SMAP_OUT_LCD_DATA_O_7 ,
|
||||
SMAP_OUT_LCD_DATA_O_8 ,
|
||||
SMAP_OUT_LCD_DATA_O_9 ,
|
||||
SMAP_OUT_LCD_DATA_O_10 ,
|
||||
SMAP_OUT_LCD_DATA_O_11 ,
|
||||
SMAP_OUT_LCD_DATA_O_12 ,
|
||||
SMAP_OUT_LCD_DATA_O_13 ,
|
||||
SMAP_OUT_LCD_DATA_O_14 ,
|
||||
SMAP_OUT_LCD_DATA_O_15 ,
|
||||
SMAP_OUT_LCD_DATA_O_16 ,
|
||||
SMAP_OUT_LCD_DATA_O_17 ,
|
||||
SMAP_OUT_LCD_DATA_O_18 ,
|
||||
SMAP_OUT_LCD_DATA_O_19 ,
|
||||
SMAP_OUT_LCD_DATA_O_20 ,
|
||||
SMAP_OUT_LCD_DATA_O_21 ,
|
||||
SMAP_OUT_LCD_DATA_O_22 ,
|
||||
SMAP_OUT_LCD_DATA_O_23 ,
|
||||
SMAP_OUT_LCD_DOTCLK_OR_RWR ,
|
||||
SMAP_OUT_LCD_VSYNC_OR_CS ,
|
||||
SMAP_OUT_LCD_HSYNC_OR_DC ,
|
||||
SMAP_OUT_LCD_DE_OR_ERD ,
|
||||
SMAP_OUT_SPI0_NSS_OUT ,
|
||||
SMAP_OUT_SPI0_SCK_OUT ,
|
||||
SMAP_OUT_SPI0_IO0_OUT ,
|
||||
SMAP_OUT_SPI0_IO1_OUT ,
|
||||
SMAP_OUT_SPI0_IO2_OUT ,
|
||||
SMAP_OUT_SPI0_IO3_OUT ,
|
||||
SMAP_OUT_SPI1_SCK_OUT ,
|
||||
SMAP_OUT_SPI1_NSS_OUT ,
|
||||
SMAP_OUT_SPI1_IO0_OUT ,
|
||||
SMAP_OUT_SPI1_IO1_OUT ,
|
||||
SMAP_OUT_SPI1_IO2_OUT ,
|
||||
SMAP_OUT_SPI1_IO3_OUT ,
|
||||
SMAP_OUT_SPI2_NSS_OUT ,
|
||||
SMAP_OUT_SPI2_SCK_OUT ,
|
||||
SMAP_OUT_SPI2_IO0_OUT ,
|
||||
SMAP_OUT_SPI2_IO1_OUT ,
|
||||
SMAP_OUT_SPI2_IO2_OUT ,
|
||||
SMAP_OUT_SPI2_IO3_OUT ,
|
||||
SMAP_OUT_NFC_TX_GATE_N ,
|
||||
SMAP_OUT_NFC_TX_N ,
|
||||
SMAP_OUT_NFC_TX_GATE_P ,
|
||||
SMAP_OUT_NFC_TX_P ,
|
||||
SMAP_OUT_COMP_DOUT_DIG0 ,
|
||||
SMAP_OUT_COMP_DOUT_DIG1 ,
|
||||
SMAP_OUT_ANTENNA_SEL ,
|
||||
SMAP_OUT_LIN_TX ,
|
||||
SMAP_OUT_LIN1_TX ,
|
||||
SMAP_OUT_PA_EN ,
|
||||
SMAP_OUT_DVP_MCLK_OUT ,
|
||||
SMAP_OUT_DAC_PDM_OUT ,
|
||||
SMAP_OUT_DUAL_ORG_FSYNC ,
|
||||
SMAP_OUT_PDM_MCLK ,
|
||||
SMAP_OUT_CAN_TXD ,
|
||||
SMAP_OUT_CLK_TO_IO ,
|
||||
};
|
||||
|
||||
enum smap_input{
|
||||
SMAP_IN_IO2IO_CH0 = 1,
|
||||
SMAP_IN_IO2IO_CH1,
|
||||
SMAP_IN_IO2IO_CH2,
|
||||
SMAP_IN_IO2IO_CH3,
|
||||
|
||||
SMAP_IN_LCD_DAT_3 =5,
|
||||
SMAP_IN_LCD_DAT_4,
|
||||
SMAP_IN_LCD_DAT_5,
|
||||
SMAP_IN_LCD_DAT_6,
|
||||
SMAP_IN_LCD_DAT_7,
|
||||
SMAP_IN_LCD_DAT_8 = 10,
|
||||
|
||||
SMAP_IN_EX_RFSWI_EN0 = 11,
|
||||
|
||||
SMAP_IN_LCD_DAT_9 = 12,
|
||||
SMAP_IN_LCD_DAT_10,
|
||||
|
||||
SMAP_IN_FB_IN = 14,
|
||||
SMAP_IN_EX_RF_PA_EN = 15,
|
||||
|
||||
SMAP_IN_LCD_DAT_11 = 16,
|
||||
SMAP_IN_LCD_DAT_12,
|
||||
|
||||
SMAP_IN_SDHOST1_DAT3,
|
||||
SMAP_IN_LCD_DAT_13,
|
||||
SMAP_IN_SDHOST1_DAT0,
|
||||
SMAP_IN_SDHOST1_CMD,
|
||||
|
||||
SMAP_IN_LCD_DAT_14,
|
||||
SMAP_IN_SDHOST1_DAT2,
|
||||
SMAP_IN_LCD_DAT_15,
|
||||
|
||||
SMAP_IN_SPI2_IO3,
|
||||
SMAP_IN_LCD_DAT_16,
|
||||
SMAP_IN_LCD_DAT_17,
|
||||
SMAP_IN_LCD_DAT_18,
|
||||
SMAP_IN_LCD_DAT_19,
|
||||
SMAP_IN_LCD_DAT_20,
|
||||
SMAP_IN_LCD_DAT_21,
|
||||
SMAP_IN_UART5_RX = 32,
|
||||
SMAP_IN_LCD_DAT_22,
|
||||
SMAP_IN_LCD_DAT_23,
|
||||
|
||||
SMAP_IN_SPI_IO2,
|
||||
SMAP_IN_SPI_IO3,
|
||||
|
||||
SMAP_IN_UART6_RX,
|
||||
};
|
||||
/** @} Docxygenid_IO_function_enum*/
|
||||
|
||||
int32 gpio_driver_strength(uint32 pin, enum pin_driver_strength strength);
|
||||
int32 gpio_set_altnt_func(uint32 pin, enum gpio_afio_set afio);
|
||||
int32 gpio_iomap_output(uint32 pin, enum gpio_iomap_out_func func_sel);
|
||||
int32 gpio_iomap_input(uint32 pin, enum gpio_iomap_in_func func_sel);
|
||||
int32 gpio_iomap_inout(uint32 pin, enum gpio_iomap_in_func in_func_sel, enum gpio_iomap_out_func out_func_sel);
|
||||
int lmac_fem_pin_func(int request);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
|
||||
|
||||
442
sdk/include/chip/txw82x/misc.h
Normal file
442
sdk/include/chip/txw82x/misc.h
Normal file
@@ -0,0 +1,442 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @version V1.0.0
|
||||
* @date 2021.01.14
|
||||
* @brief This file contains all the PowerDomain firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2021 HUGE-IC</center></h2>
|
||||
*
|
||||
*
|
||||
* Revision History
|
||||
* V1.0.0 2021.01.14 First Release, move from sysctrl
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __MISC_H__
|
||||
#define __MISC_H__
|
||||
|
||||
#include "typesdef.h"
|
||||
#include "cld_cache.h"
|
||||
#include "lib/common/rbuffer.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef VENUS_END
|
||||
/*******************************************************************/
|
||||
/* Venus to be continue */
|
||||
/*******************************************************************/
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
///** @defgroup SYSMONITOR MACRO-DEF & Exported_Functions
|
||||
// * @{
|
||||
// */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32 CHx_LMT_L;
|
||||
__IO uint32 CHx_LMT_H;
|
||||
__IO uint32 CHx_ERR_ADR;
|
||||
// uint32 RESERVEDx;
|
||||
} SYS_MNT_CH_TypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32 CTRL;
|
||||
__IO uint32 PND;
|
||||
__IO uint32 CLR;
|
||||
__IO uint32 RD;
|
||||
__IO uint32 WR;
|
||||
__IO uint32 rev[4];
|
||||
SYS_MNT_CH_TypeDef SYS_MNT_CH[2];
|
||||
} SYS_MNT_TypeDef;
|
||||
|
||||
#define SYSMNT ((SYS_MNT_TypeDef *) SYS_MNT_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @brief CPU1_MNT
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32 R0;
|
||||
__IO uint32 R1;
|
||||
__IO uint32 R2;
|
||||
__IO uint32 R3;
|
||||
__IO uint32 R4;
|
||||
__IO uint32 R5;
|
||||
__IO uint32 R6;
|
||||
__IO uint32 R7;
|
||||
__IO uint32 R8;
|
||||
__IO uint32 R9;
|
||||
__IO uint32 R10;
|
||||
__IO uint32 R11;
|
||||
__IO uint32 R12;
|
||||
__IO uint32 R13;
|
||||
__IO uint32 R14;
|
||||
__IO uint32 R15; //0x40
|
||||
uint32 reserved_0x44[12];
|
||||
__IO uint32 R28;
|
||||
uint32 reserved_0x70[19];
|
||||
__IO uint32 EXPC; //0xc0
|
||||
__IO uint32 PSR;
|
||||
__IO uint32 EPC;
|
||||
__IO uint32 EPSR;
|
||||
__IO uint32 FCR;
|
||||
__IO uint32 FESR;
|
||||
__IO uint32 CPU1_DBGON;
|
||||
__IO uint32 CPU0_DBGON;
|
||||
__IO uint32 CPU1_SFTPND;
|
||||
} CPU1_MNT_TypeDef;
|
||||
|
||||
#define CPU1_MNT ((CPU1_MNT_TypeDef *) 0x4000A100 )
|
||||
|
||||
|
||||
/** @addtogroup Template_Project
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSMONITOR_CHN_EN(n) (BIT(n))
|
||||
#define LL_SYSMONITOR_CHN_CAP_RANGE_INTER(n) (BIT(n+4))
|
||||
#define LL_SYSMONITOR_CHN_CAP_RANGE_OUTER(n) (0)
|
||||
#define LL_SYSMONITOR_CAP_PC_EN (1UL << 6)
|
||||
#define LL_SYSMONITOR_INT_EN (1UL << 7)
|
||||
|
||||
#define LL_SYSMONITOR_CH0_SEL(n) (((n) & 0x1F) << 8)
|
||||
#define LL_SYSMONITOR_CH0_SEL_MSK ((0x1F) << 8)
|
||||
#define LL_SYSMONITOR_CH0_CAP_READ ((1UL) << 18)
|
||||
#define LL_SYSMONITOR_CH0_CAP_WRITE ((1UL) << 19)
|
||||
#define LL_SYSMONITOR_CH0_CAP_MODE(n) ((((n) & 0x3)) << 18)
|
||||
|
||||
#define LL_SYSMONITOR_CH1_SEL(n) (((n) & 0x1F) << 13)
|
||||
#define LL_SYSMONITOR_CH1_SEL_MSK ((0x1F) << 13)
|
||||
#define LL_SYSMONITOR_CH1_CAP_READ ((1UL) << 20)
|
||||
#define LL_SYSMONITOR_CH1_CAP_WRITE ((1UL) << 21)
|
||||
#define LL_SYSMONITOR_CH1_CAP_MODE(n) ((((n) & 0x3)) << 20)
|
||||
|
||||
|
||||
#define LL_SYSMONITOR_CLEAR_REGISTER() do { SYSMNT->CLR = 1 | 2; } while(0)
|
||||
|
||||
/** @addtogroup XXX
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
//CHANNEL 1
|
||||
LL_SYSMONITOR_CHN_M2M0_RD = (0) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_M2M0_WR = (1) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_M2M1_RD = (2) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_M2M1_WR = (3) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_CPU0_ICODE = (4) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_CPU0_DCODE = (5) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_USB_20 = (6) | (1<<8),
|
||||
LL_SYSMONITOR_CHN_USB_11 = (7) | (1<<8),
|
||||
//CHANNEL 0
|
||||
LL_SYSMONITOR_CHN_CPU1_ICODE = (6) | (0<<8),
|
||||
LL_SYSMONITOR_CHN_CPU1_DCODE = (7) | (0<<8),
|
||||
LL_SYSMONITOR_CHN_OSPI = (8) | (0<<8),
|
||||
LL_SYSMONITOR_CHN_QSPI = (9) | (0<<8),
|
||||
LL_SYSMONITOR_CHN_GMAC_RX = (10) | (0<<8),
|
||||
LL_SYSMONITOR_CHN_GMAC_TX = (11) | (0<<8),
|
||||
} TYPE_ENUM_LL_SYSMONITOR_CH;
|
||||
|
||||
/** @addtogroup XXX
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LL_SYSMONITOR_CAP_RANGE_INTER = (0),
|
||||
LL_SYSMONITOR_CAP_RANGE_OUTER = (1),
|
||||
} TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE;
|
||||
|
||||
/** @addtogroup XXX
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LL_SYSMONITOR_CAP_MODE_READ = (1),
|
||||
LL_SYSMONITOR_CAP_MODE_WRITE = (2),
|
||||
LL_SYSMONITOR_CAP_MODE_READ_OR_WRITE = (3),
|
||||
} TYPE_ENUM_LL_SYSMONITOR_CAP_MODE;
|
||||
|
||||
typedef struct __ll_sysmonitor_cfg {
|
||||
/*! System monitor interrupt enable
|
||||
*/
|
||||
bool int_en;
|
||||
/*! System monitor sub channel : [0, 20]
|
||||
*/
|
||||
TYPE_ENUM_LL_SYSMONITOR_CH ch;
|
||||
/*! capture mode
|
||||
*/
|
||||
TYPE_ENUM_LL_SYSMONITOR_CAP_MODE cap_mode;
|
||||
/*! capture range
|
||||
*/
|
||||
TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE cap_range;
|
||||
/*! Chx low limited address
|
||||
*/
|
||||
uint32 chx_limit_low;
|
||||
/*! Chx high limited address
|
||||
*/
|
||||
uint32 chx_limit_high;
|
||||
/* IRQ handle
|
||||
*/
|
||||
void (*cb)(void *);
|
||||
} TYPE_SYSMONITOR_CFG;
|
||||
|
||||
void sys_monitor_config(TYPE_SYSMONITOR_CFG *p_cfg);
|
||||
void sys_monitor_reset(void);
|
||||
|
||||
/*******************************************************************/
|
||||
/* OSPI_EFF */
|
||||
/*******************************************************************/
|
||||
struct HW_EFF {
|
||||
volatile uint32_t CON;
|
||||
volatile uint32_t PERIOD;
|
||||
volatile uint32_t RD_CNT;
|
||||
volatile uint32_t WR_CNT;
|
||||
};
|
||||
|
||||
#define OSPI_EFF ((struct HW_EFF *) 0x40020214)
|
||||
#define EFF_CNT_CLEAR (1<<6)
|
||||
#define EFF_INTR_PEND (1<<5)
|
||||
#define EFF_CH_SHIFT (2)
|
||||
#define EFF_CH_MASK (7<<2)
|
||||
#define EFF_INTR_EN (1<<1)
|
||||
#define EFF_MODU_EN (1<<0)
|
||||
|
||||
#define OSPI_EFF_MSG_SIZE (5)
|
||||
|
||||
enum EFF_CH {
|
||||
EFF_CPU0_DBUS,
|
||||
EFF_CPU0_IBUS,
|
||||
EFF_CPU1_DBUS,
|
||||
EFF_CPU1_IBUS,
|
||||
EFF_H264,
|
||||
EFF_SCHED,
|
||||
EFF_CH_OTHER,
|
||||
EFF_CH_END,
|
||||
};
|
||||
|
||||
struct eff_msg {
|
||||
uint32_t rd_cnt[EFF_CH_END];
|
||||
uint32_t wr_cnt[EFF_CH_END];
|
||||
};
|
||||
|
||||
struct eff_mgr {
|
||||
RBUFFER_DEF(rb, struct eff_msg, OSPI_EFF_MSG_SIZE);
|
||||
};
|
||||
|
||||
|
||||
/*统计period_ms时间内PSRAM的请求数， MAX值是0xffffffff / CPU_CLK * 1000*/
|
||||
int eff_start(uint32_t period_ms);
|
||||
void eff_stop();
|
||||
|
||||
/*输出最近一次统计到的信息*/
|
||||
int eff_printf();
|
||||
int eff_read(struct eff_msg *msg);
|
||||
|
||||
/*******************************************************************/
|
||||
/* EFUSE */
|
||||
/*******************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define CHIP_PACKID_KL928 0x01
|
||||
#define CHIP_PACKID_TXW825_824 0x02
|
||||
|
||||
#define CHIP_PACKID_TXW826_824 0x10
|
||||
#define CHIP_PACKID_TXW826_824C 0x11
|
||||
|
||||
#define CHIP_PACKID_TXW827_C08 0x20
|
||||
|
||||
#define CHIP_PACKID_TXW828_C08FL 0x30
|
||||
#define CHIP_PACKID_TXW828_E08FL 0x31
|
||||
#define CHIP_PACKID_TXW828_E016FL 0x32
|
||||
#define CHIP_PACKID_TXW828_J016FL 0x33
|
||||
|
||||
#define CHIP_PACKID_TXM609_800 0x40
|
||||
#define CHIP_PACKID_TXM609_804 0x41
|
||||
#define CHIP_PACKID_TXM609_H016 0x42
|
||||
|
||||
|
||||
|
||||
/** @defgroup EFUSE MACRO-DEF & Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32 EFUSE_CON;
|
||||
__IO uint32 EFUSE_TIME_CON0;
|
||||
__IO uint32 EFUSE_TIME_CON1;
|
||||
__IO uint32 EFUSE_TIME_CON2;
|
||||
__IO uint32 EFUSE_STATUS;
|
||||
__IO uint32 EFUSE_ADDR_CNT;
|
||||
__IO uint32 EFUSE_DATA;
|
||||
} EFUSE_TypeDef;
|
||||
|
||||
#define EFUSE ((EFUSE_TypeDef *) EFUSE_BASE)
|
||||
/* efuse timing define */
|
||||
#define LL_EFUSE_POWER_FREQ 100000 /* 10us */
|
||||
#define LL_EFUSE_PROGRAM_FREQ 100000 /* 10us (9~11uS) */
|
||||
#define LL_EFUSE_READ_FREQ 10000000 /* 100ns ( > 36ns) */
|
||||
|
||||
uint16 sysctrl_efuse_config_and_read(uint32 addr, uint8 *p_buf, uint16 len);
|
||||
void rf_para_efuse_check_valid(void);
|
||||
void sysctrl_efuse_mac_addr_calc(uint8 *addr_buf);
|
||||
uint16 sysctrl_efuse_get_customer_id(void);
|
||||
uint8 sysctrl_efuse_get_chip_package(void);
|
||||
uint32 sysctrl_efuse_get_smt_dat(void);
|
||||
int32 tsensor_meas(uint8 sensor_idx);
|
||||
|
||||
/*******************************************************************/
|
||||
/* RFADC */
|
||||
/*******************************************************************/
|
||||
typedef struct {
|
||||
__IO uint32 RFADCDIGCON;
|
||||
} RFADCDIG_TypeDef;
|
||||
|
||||
#define RFADCDIG ((RFADCDIG_TypeDef *) RFADCDIG_BASE)
|
||||
|
||||
#define RFADCDIGCON_ACS_ON_MSK BIT(0)
|
||||
#define RFADCDIGCON_ACS_RW_MSK BIT(1)
|
||||
#define RFADCDIGCON_ACS_ADDR_SHIFT 2
|
||||
#define RFADCDIGCON_ACS_ADDR_MSK (0x1f<<RFADCDIGCON_ACS_ADDR_SHIFT)
|
||||
#define RFADCDIGCON_ACS_DATA_SHIFT 7
|
||||
#define RFADCDIGCON_ACS_DATA_MSK (0x3fffff<<RFADCDIGCON_ACS_DATA_SHIFT)
|
||||
|
||||
#define ADCOUTSEL 0 // 0: output data after calibration; 1: output data before calibration
|
||||
|
||||
/*******************************************************************/
|
||||
/* RFADC */
|
||||
/*******************************************************************/
|
||||
|
||||
enum lf_clk_src {
|
||||
FROM_HOSC = 0,
|
||||
FROM_RC32K = 2,
|
||||
FROM_PB0 = 3,
|
||||
};
|
||||
|
||||
enum lf_clk_count {
|
||||
_1024_CYCLE = 0,
|
||||
_512_CYCLE = 1,
|
||||
_256_CYCLE = 2,
|
||||
_128_CYCLE = 3,
|
||||
_64_CYCLE = 4,
|
||||
_32_CYCLE = 5,
|
||||
_16_CYCLE = 6,
|
||||
_8_CYCLE = 7,
|
||||
};
|
||||
|
||||
enum dac_default_state {
|
||||
POWER_OFF = 0,
|
||||
SLEEP = 1,
|
||||
STAND_BY = 2,
|
||||
POWER_ON = 3
|
||||
};
|
||||
|
||||
enum rf_bw {
|
||||
BW_1M = 0,
|
||||
BW_2M = 1,
|
||||
BW_4M = 2,
|
||||
BW_8M = 3
|
||||
};
|
||||
|
||||
enum rf_parameter_type {
|
||||
RF_EFUSE_ALL_SIM = 0,
|
||||
ADC_CALIB_VAL = 1,
|
||||
ADDA_TIM_OFFSET = 2,
|
||||
TXDCOC_CALIB_VAL = 3,
|
||||
TXIMB_CALIB_VAL = 4,
|
||||
RXDCOC_CALIB_VAL = 5,
|
||||
RXIMB_CALIB_VAL = 6
|
||||
};
|
||||
|
||||
int32 tx_digi_gain_store(uint16 tx_digi_gain);
|
||||
int32 sysctrl_internal_rf_sel_lo_freq(uint8 lo_freq_idx);
|
||||
int32 is_xo_cs_calibed(void);
|
||||
int32 is_xo_cto_calibed(void);
|
||||
int32 xo_cs_store(uint8 xo_cs_val);
|
||||
int32 sysctrl_get_xo_drcs(void);
|
||||
int32 sysctrl_set_xo_drcs(uint16 xo_drcs);
|
||||
void adc_cfg_reg_wr(uint8 addr, uint32 data);
|
||||
uint32 adc_cfg_reg_rd(uint8 addr);
|
||||
int32 is_adc_calibed(void);
|
||||
void adc_init(void);
|
||||
int32 adc_calib_res_store(void);
|
||||
void adc_calib_res_restore(void);
|
||||
void rfadc_calib_mode_soft_test(void);
|
||||
|
||||
int32 sysctrl_err_resp_icode_bus(uint8 enable);
|
||||
int32 sysctrl_err_resp_dcode_bus(uint8 enable);
|
||||
int32 sysctrl_err_resp_ahb2dma_bus(uint8 enable);
|
||||
int32 sysctrl_err_resp_sdiodevice_bus(uint8 enable);
|
||||
int32 sysctrl_err_resp_disable(void);
|
||||
|
||||
int32 sysctrl_get_chip_flash_size(void);
|
||||
|
||||
int32 sysctrl_is_chipdcn_compid(void);
|
||||
|
||||
|
||||
/* 速率：x Bps */
|
||||
uint32_t sys_dma2ahb_bw_static(int32 printf_en);
|
||||
|
||||
/* miss rate : 万分之x */
|
||||
uint32_t sys_csi_cache_static(int32 core_id, int32 printf_en);
|
||||
|
||||
uint32_t sys_cld_cache_static(int32 printf_en);
|
||||
uint32_t sys_psram_eff_static(int32 printf_en);
|
||||
|
||||
int32 sys_get_cpu_dcache_maint_both(void);
|
||||
int32 sys_get_cpu_dcache_enable(void);
|
||||
|
||||
/** use when DMA source is psram
|
||||
* usage( this -> DMA kick)
|
||||
*/
|
||||
void sys_dcache_clean_range (uint32_t *addr, int32_t dsize);
|
||||
|
||||
/* usefor TCPIP CHKSUM */
|
||||
void sys_dcache_clean_range_unaligned (uint32_t *addr, int32_t dsize);
|
||||
|
||||
/** use when DMA destination is PSRAM
|
||||
* usage : ( this -> DMA) ;
|
||||
*/
|
||||
void sys_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize);
|
||||
void sys_dcache_clean_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
|
||||
|
||||
/** use when DMA destination is PSRAM
|
||||
* Note：this function will auto writeback data head & tail (16/32byte unaligned)
|
||||
* 1.usage : ( DMA done-> this) ;
|
||||
* 2.Precondition: dma buffer addr & size is 16/32byte aligned
|
||||
* 3.DMA buffer size is not checked
|
||||
*/
|
||||
void sys_dcache_invalid_range (uint32_t *addr, int32_t dsize);
|
||||
|
||||
/** use when DMA destination is PSRAM
|
||||
* Note：this function will auto writeback data head & tail (16/32byte unaligned)
|
||||
*/
|
||||
void sys_dcache_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__MISC_H__
|
||||
|
||||
|
||||
|
||||
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
|
||||
|
||||
|
||||
1052
sdk/include/chip/txw82x/pin_names.h
Normal file
1052
sdk/include/chip/txw82x/pin_names.h
Normal file
File diff suppressed because it is too large
Load Diff
677
sdk/include/chip/txw82x/pmu.h
Normal file
677
sdk/include/chip/txw82x/pmu.h
Normal file
@@ -0,0 +1,677 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file pmu.h
|
||||
* @author HUGE-IC Application Team
|
||||
* @version V1.0.0
|
||||
* @date 2021.01.14
|
||||
* @brief This file contains all the PowerDomain firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2021 HUGE-IC</center></h2>
|
||||
*
|
||||
*
|
||||
* Revision History
|
||||
* V1.0.0 2021.01.14 First Release, move from sysctrl
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __PMU_H__
|
||||
#define __PMU_H__
|
||||
|
||||
#include "typesdef.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CORE_LVD_CON (0x00>>0)
|
||||
#define CORE_LVD_CON1 (0x04>>0)
|
||||
#define CORE_LVD_CON2 (0x08>>0)
|
||||
#define CORE_PMUCON0 (0x10>>0)
|
||||
#define CORE_PMUCON1 (0x14>>0)
|
||||
#define CORE_PMUCON2 (0x18>>0)
|
||||
#define CORE_PMUCON3 (0x1c>>0)
|
||||
#define CORE_PMUCON4 (0x20>>0)
|
||||
#define CORE_PMUCON5 (0x24>>0)
|
||||
#define CORE_RFCON0 (0x28>>0)
|
||||
#define CORE_RFCON1 (0x2c>>0)
|
||||
#define CORE_PMUCON6 (0x30>>0)
|
||||
#define CORE_PMUCON7 (0x34>>0)
|
||||
#define CORE_PMUCON8 (0x38>>0)
|
||||
#define CORE_PMUCON9 (0x3c>>0)
|
||||
#define CORE_PMUCON10 (0x40>>0)
|
||||
#define CORE_PMUCON11 (0x44>>0)
|
||||
#define CORE_PMUCON12 (0x48>>0)
|
||||
#define CORE_PMUCON13 (0x4c>>0)
|
||||
#define CORE_PNDCLR (0x50>>0)
|
||||
|
||||
//-------------RTC part1 start---------------
|
||||
#define CORE_RTCWPR (0x54>>0) //54
|
||||
#define CORE_RTCCTR (0x58>>0) //58
|
||||
#define CORE_RTCPDR (0x5c>>0) //5c
|
||||
#define CORE_RTCISR (0x60>>0) //60
|
||||
#define CORE_RTCSSR (0x64>>0) //64
|
||||
#define CORE_RTCTMR (0x68>>0) //68
|
||||
#define CORE_RTCDAR (0x6c>>0) //6c
|
||||
#define CORE_RTCALR0R (0x70>>0) //70
|
||||
#define CORE_RTCWUTR (0x74>>0) //74
|
||||
#define CORE_RTCTSSSR (0x78>>0) //78
|
||||
#define CORE_RTCTSTMR (0x7c>>0) //7c
|
||||
//-------------RTC part1 end---------------
|
||||
#define CORE_TMRCON (0x80>>0)
|
||||
#define CORE_TMRPR (0x84>>0)
|
||||
#define CORE_TMRRPT (0x88>>0)
|
||||
#define CORE_TMRTRIM (0x8c>>0)
|
||||
#define CORE_TMRPR2 (0x90>>0)
|
||||
//-------------RTC part2 start---------------
|
||||
//#define CORE_TMRRTCC (0x94>>0)
|
||||
#define CORE_RTCTSDAR (0x94>>0) //94
|
||||
#define CORE_RTCCALR (0x98>>0) //98
|
||||
#define CORE_RTCSSSR (0x9c>>0) //9c
|
||||
//-------------RTC part2 start---------------
|
||||
|
||||
#define CORE_WKCON (0xa0>>0)
|
||||
#define CORE_WKCON1 (0xa4>>0)
|
||||
#define CORE_WKCON2 (0xa8>>0)
|
||||
#define CORE_SECCON (0xb0>>0)
|
||||
#define CORE_SECDAT (0xb4>>0)
|
||||
#define CORE_SECADR (0xb8>>0)
|
||||
#define CORE_SECKEY (0xbc>>0)
|
||||
#define CORE_CMPCON (0xc0>>0)
|
||||
#define CORE_CMPCON1 (0xc4>>0)
|
||||
|
||||
#if 0 //vernus
|
||||
|
||||
#define CORE_TMR0CON (0xd0>>0)
|
||||
#define CORE_TMR1CON (0xd4>>0)
|
||||
#define CORE_TMR2CON (0xd8>>0)
|
||||
#define CORE_TMR3CON (0xdc>>0)
|
||||
|
||||
#else //vernus200= eagle v2
|
||||
|
||||
#define CORE_PMUCON14 (0xc8>>0)
|
||||
#define CORE_PMUCON15 (0xcc>>0)
|
||||
|
||||
#define CORE_TMR_CON (0xd0>>0)
|
||||
#define CORE_TMR0CON (0xd4>>0)
|
||||
#define CORE_TMR1CON (0xd8>>0)
|
||||
#define CORE_TMR2CON (0xdc>>0)
|
||||
#define CORE_TMR3CON (0xe0>>0)
|
||||
|
||||
#define CORE_WDTCON (0xe4>>0)
|
||||
#define CORE_WDTKEY (0xe8>>0)
|
||||
#endif
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32 LVD_CON;
|
||||
__IO uint32 LVD_CON1;
|
||||
__IO uint32 LVD_CON2;
|
||||
__IO uint32 TMRAOCNTL;
|
||||
__IO uint32 PMUCON0;
|
||||
__IO uint32 PMUCON1;
|
||||
__IO uint32 PMUCON2;
|
||||
__IO uint32 PMUCON3;
|
||||
__IO uint32 PMUCON4;
|
||||
__IO uint32 PMUCON5;
|
||||
__IO uint32 RFCON0;
|
||||
__IO uint32 RFCON1;
|
||||
__IO uint32 PMUCON6;
|
||||
__IO uint32 PMUCON7;
|
||||
__IO uint32 PMUCON8;
|
||||
__IO uint32 PMUCON9;
|
||||
__IO uint32 PMUCON10; //40
|
||||
__IO uint32 PMUCON11;
|
||||
__IO uint32 PMUCON12;
|
||||
__IO uint32 PMUCON13;
|
||||
__IO uint32 PNDCLR; //50
|
||||
__IO uint32 RTCWPR; //54
|
||||
__IO uint32 RTCCTR; //58
|
||||
__IO uint32 RTCPDR; //5c
|
||||
__IO uint32 RTCISR; //60
|
||||
__IO uint32 RTCSSR; //64
|
||||
__IO uint32 RTCTMR; //68
|
||||
__IO uint32 RTCDAR; //6c
|
||||
__IO uint32 RTCALR0R; //70
|
||||
__IO uint32 RTCWUTR; //74
|
||||
__IO uint32 RTCTSSSR; //78
|
||||
__IO uint32 RTCTSTMR; //7c
|
||||
__IO uint32 TMRCON; //80
|
||||
__IO uint32 TMRPR;
|
||||
__IO uint32 TMRRPT;
|
||||
__IO uint32 TMRTRIM;
|
||||
__IO uint32 TMRPR2; //90
|
||||
__IO uint32 RTCTSDAR; //94
|
||||
__IO uint32 RTCCALR; //98
|
||||
__IO uint32 RTCSSSR; //9c
|
||||
__IO uint32 WKCON; //a0
|
||||
__IO uint32 WKCON1;
|
||||
__IO uint32 WKCON2;
|
||||
__IO uint32 TMRAOCNTH;
|
||||
__IO uint32 SECCON; //b0
|
||||
__IO uint32 SECDAT;
|
||||
__IO uint32 SECADDR;
|
||||
__IO uint32 SECKEY;
|
||||
__IO uint32 CMPCON; //c0
|
||||
__IO uint32 CMPCON1; //c4
|
||||
__IO uint32 PMUCON14; //c8
|
||||
__IO uint32 PMUCON15; //cc
|
||||
__IO uint32 TMR_CON; //d0
|
||||
__IO uint32 TMR0CON0; //d4
|
||||
__IO uint32 TMR1CON0; //d8
|
||||
__IO uint32 TMR2CON0; //dc
|
||||
__IO uint32 TMR3CON0; //e0
|
||||
__IO uint32 WDTCON; //e4
|
||||
__IO uint32 WDTKEY; //e8
|
||||
__IO uint32 PMUCON16; //ec
|
||||
__IO uint32 RTC_VCCHVD_CON; //f0
|
||||
__IO uint32 RTC_VCCHVD_PND; //f4
|
||||
|
||||
} PMU_TypeDef;
|
||||
|
||||
#define PMU ((PMU_TypeDef *) PMU_BASE)
|
||||
|
||||
#define PMU_REG_SET_BITS(reg, bits) do { pmu_reg_write((uint32)®, (reg)|(bits)); } while(0)
|
||||
#define PMU_REG_CLR_BITS(reg, bits) do { pmu_reg_write((uint32)®, (reg) & ~(bits)); } while(0)
|
||||
#define PMU_REG_SET_VALUE(reg, bit_mask, val, bit_pos) do { pmu_reg_write((uint32)®, ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)) ); } while(0)
|
||||
#define PMU_REG_BIT_FUN(fun_name, reg, bits)\
|
||||
__STATIC_INLINE void fun_name##_en(void) { PMU_REG_SET_BITS(reg, bits); }\
|
||||
__STATIC_INLINE void fun_name##_dis(void) { PMU_REG_CLR_BITS(reg, bits); }
|
||||
|
||||
|
||||
/* lvdcon */
|
||||
#define pmu_vcam_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(31))
|
||||
#define pmu_vcam_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(31))
|
||||
#define PMU_VCAM_OC_PENDING (PMU->LVD_CON & BIT(30))
|
||||
#define PMU_V15_OC_PENDING (PMU->LVD_CON & BIT(29))
|
||||
#define PMU_VDD_OC_PENDING (PMU->LVD_CON & BIT(28))
|
||||
#define PMU_VDD_LV_PENDING (PMU->LVD_CON & BIT(27))
|
||||
#define PMU_VCC_LV_PENDING (PMU->LVD_CON & BIT(26))
|
||||
#define PMU_VCC1_LV_PENDING (PMU->LVD_CON & BIT(25)) //?
|
||||
#define PMU_VCC15_LV_PENDING (PMU->LVD_CON & BIT(24))
|
||||
#define pmu_vcc1_lv_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(23))
|
||||
#define pmu_vcc1_lv_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(23))
|
||||
#define pmu_vcc15_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(22))
|
||||
#define pmu_vcc15_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(22))
|
||||
#define pmu_lvd_oe_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(21))
|
||||
#define pmu_lvd_oe_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(21))
|
||||
#define pmu_vdd_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(20))
|
||||
#define pmu_vdd_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(20))
|
||||
#define pmu_vdd_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(19))
|
||||
#define pmu_vdd_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(19))
|
||||
#define pmu_vcc_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(18))
|
||||
#define pmu_vcc_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(18))
|
||||
#define pmu_vcc15_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(17))
|
||||
#define pmu_vcc15_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(17))
|
||||
|
||||
enum vcc15_oc_level {
|
||||
VCC15_OC_200MA = 0,
|
||||
VCC15_OC_90MA = 0x3,
|
||||
VCC15_OC_70MA,
|
||||
VCC15_OC_60MA,
|
||||
VCC15_OC_50MA,
|
||||
};
|
||||
#define pmu_vcc15_oc_level_set(vcc15_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x0001c000, vcc15_oc_level, 14)
|
||||
|
||||
enum vdd_oc_level {
|
||||
VDD_OC_50MA,
|
||||
VDD_OC_100MA,
|
||||
VDD_OC_150MA,
|
||||
VDD_OC_200MA,
|
||||
};
|
||||
#define pmu_vdd_oc_level_set(vdd_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00003000, vdd_oc_level, 12)
|
||||
|
||||
enum vcc15_lv_level {
|
||||
VCC15_LV_0V86_T_0V90,
|
||||
VCC15_LV_1V00_T_1V05,
|
||||
VCC15_LV_1V14_T_1V19,
|
||||
VCC15_LV_1V29_T_1V35,
|
||||
|
||||
};
|
||||
#define pmu_vcc15_lv_level_set(vcc15_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000c00, vcc15_lv_level, 10)
|
||||
|
||||
enum vdd_lv_level {
|
||||
VDD_LV_0V64_T_0V68,
|
||||
VDD_LV_0V74_T_0V78,
|
||||
VDD_LV_0V84_T_0V88,
|
||||
VDD_LV_0V84_T_0V98,
|
||||
};
|
||||
#define pmu_vdd_lv_level_set(vdd_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000300, vdd_lv_level, 8)
|
||||
|
||||
enum avcc_lv_level {
|
||||
AVCC_LV_1V90_T_1V99,
|
||||
AVCC_LV_2V06_T_2V16,
|
||||
AVCC_LV_2V21_T_2V31,
|
||||
AVCC_LV_2V33_T_2V44,
|
||||
AVCC_LV_2V46_T_2V58,
|
||||
AVCC_LV_2V62_T_2V74,
|
||||
AVCC_LV_2V75_T_2V87,
|
||||
AVCC_LV_2V90_T_3V04,
|
||||
};
|
||||
#define pmu_avcc_lv_level_set(avcc_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x000000e0, avcc_lv_level, 5)
|
||||
|
||||
enum vcc1_lv_level {
|
||||
VCC1_LV_2V54_T_2V66,
|
||||
VCC1_LV_1V46_T_1V53,
|
||||
};
|
||||
#define pmu_vcc1_lv_level_set(vcc1_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000010, vcc1_lv_level, 4)
|
||||
|
||||
#define pmu_vdd_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(3))
|
||||
#define pmu_vdd_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(3))
|
||||
#define pmu_avcc_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(2))
|
||||
#define pmu_avcc_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(2))
|
||||
#define pmu_vcc1_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(1))
|
||||
#define pmu_vcc1_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(1))
|
||||
#define pmu_vcc15_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(0))
|
||||
#define pmu_vcc15_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(0))
|
||||
|
||||
/* lvdcon1 */
|
||||
#define PMU_VDD18_OC_PENDING (PMU->LVD_CON1 & BIT(31))
|
||||
#define PMU_VDD12_OC_PENDING (PMU->LVD_CON1 & BIT(30))
|
||||
#define pmu_vcc_lv_detect_sync_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(30))
|
||||
#define pmu_vcc_lv_detect_sync_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(30))
|
||||
#define pmu_vdd_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(29))
|
||||
#define pmu_vdd_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(29))
|
||||
#define pmu_vcc_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(28))
|
||||
#define pmu_vcc_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(28))
|
||||
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
|
||||
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
|
||||
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
|
||||
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
|
||||
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
|
||||
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
|
||||
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
|
||||
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
|
||||
|
||||
/* lvdcon2 */
|
||||
#define pmu_vdd12_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(31))
|
||||
#define pmu_vdd12_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(31))
|
||||
#define pmu_vdd18_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(30))
|
||||
#define pmu_vdd18_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(30))
|
||||
#define pmu_vcc1_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(29))
|
||||
#define pmu_vcc1_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(29))
|
||||
#define pmu_vcc15_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(28))
|
||||
#define pmu_vcc15_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(28))
|
||||
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
|
||||
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
|
||||
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
|
||||
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
|
||||
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
|
||||
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
|
||||
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
|
||||
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
|
||||
|
||||
/* CORE_PMUCON0 */
|
||||
#define pmu_ftmclr_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(31))
|
||||
#define pmu_ftmclr_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(31))
|
||||
#define pmu_port_wk_auto_dis_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(29))
|
||||
#define pmu_port_wk_auto_dis_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(29))
|
||||
#define pmu_mclr_soft_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(28))
|
||||
#define pmu_mclr_soft_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(28))
|
||||
#define pmu_led_io_mux_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(27))
|
||||
#define pmu_led_io_mux_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(27))
|
||||
enum pd_tmr1_clk_sel {
|
||||
PD_TMR1_CLK_RC128K,
|
||||
PD_TMR1_CLK_XOSC,
|
||||
PD_TMR1_CLK_RC8M,
|
||||
PD_TMR1_CLK_LX32K,
|
||||
};
|
||||
#define pmu_pd_tmr1_clk_sel(pd_tmr1_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x06000000, pd_tmr1_clk_sel, 25)
|
||||
|
||||
#define pmu_pd_mem2_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(24))
|
||||
#define pmu_pd_mem2_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(24))
|
||||
#define pmu_fls_pg_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(23))
|
||||
#define pmu_fls_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(23))
|
||||
#define pmu_pd_mem32k_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(22))
|
||||
#define pmu_pd_mem32k_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(22))
|
||||
#define pmu_pd_ulp_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(21))
|
||||
#define pmu_pd_ulp_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(21))
|
||||
#define pmu_pd_io_latch_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(20))
|
||||
#define pmu_pd_io_latch_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(20))
|
||||
#define pmu_pd_rf_latch_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(19))
|
||||
#define pmu_pd_rf_latch_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(19))
|
||||
#define pmu_pd_osc_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(18))
|
||||
#define pmu_pd_osc_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(18))
|
||||
#define pmu_pd_osc_hw_trim_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(17))
|
||||
#define pmu_pd_osc_hw_trim_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(17))
|
||||
enum pd_tmr_clk_sel {
|
||||
PD_TMR_CLK_RC128K,
|
||||
PD_TMR_CLK_XOSC,
|
||||
PD_TMR_CLK_RC32K,
|
||||
PD_TMR_CLK_LX32K,
|
||||
};
|
||||
#define pmu_pd_tmr_clk_sel(pd_tmr_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00018000, pd_tmr_clk_sel, 15)
|
||||
#define pmu_io_clk_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(14))
|
||||
#define pmu_io_clk_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(14))
|
||||
#define pmu_pd_wdt_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(11))
|
||||
#define pmu_pd_wdt_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(11))
|
||||
|
||||
enum lpvdd_vol_level {
|
||||
LPVDD_VOL_0V74,
|
||||
LPVDD_VOL_0V81,
|
||||
LPVDD_VOL_0V88,
|
||||
LPVDD_VOL_0V95,
|
||||
LPVDD_VOL_1V02,
|
||||
LPVDD_VOL_1V09,
|
||||
LPVDD_VOL_1V16,
|
||||
LPVDD_VOL_1V23,
|
||||
};
|
||||
#define pmu_lpvdd_vol_set(lpvdd_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00000700, lpvdd_vol_level, 8)
|
||||
|
||||
|
||||
/* CORE_PMUCON1 */
|
||||
/* CORE_PMUCON2 */
|
||||
/* CORE_PMUCON3 */
|
||||
/* CORE_PMUCON4 */
|
||||
#define pmu_vdd_en() PMU_REG_SET_BITS(PMU->PMUCON4, BIT(9))
|
||||
#define pmu_vdd_dis() PMU_REG_CLR_BITS(PMU->PMUCON4, BIT(9))
|
||||
|
||||
/* CORE_PMUCON5 */
|
||||
enum vdd15_vol_level {
|
||||
VDD15_VOL_1V2,
|
||||
VDD15_VOL_1V3,
|
||||
VDD15_VOL_1V4,
|
||||
VDD15_VOL_1V5,
|
||||
VDD15_VOL_1V6,
|
||||
VDD15_VOL_1V7,
|
||||
VDD15_VOL_1V8,
|
||||
VDD15_VOL_1V9,
|
||||
VDD15_VOL_2V0,
|
||||
VDD15_VOL_2V1,
|
||||
VDD15_VOL_2V2,
|
||||
VDD15_VOL_2V3,
|
||||
VDD15_VOL_2V4,
|
||||
VDD15_VOL_2V5,
|
||||
};
|
||||
#define pmu_vdd15_vol_set(vdd15_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON5, 0xF, vdd15_vol_level, 0)
|
||||
|
||||
|
||||
#define pmu_hirc_8mhz_en() PMU_REG_SET_BITS(PMU->PMUCON5, BIT(24))
|
||||
#define pmu_hirc_8mhz_dis() PMU_REG_CLR_BITS(PMU->PMUCON5, BIT(24))
|
||||
|
||||
|
||||
/* CORE_PMUCON7 */
|
||||
enum pmu_con7_bits_funcs {
|
||||
PMU_BOOT_DIRECT_RUN, //0
|
||||
PMU_APP_DEADCODE_PENDING,
|
||||
PMU_CP_FAIL_PENDING,
|
||||
PMU_BOOT_CODE_POS,
|
||||
|
||||
PMU_DIRECT_RUN_DISABLE_SIGN, //4
|
||||
PMU_SKIP_MASTER_BOOT_SIGN,
|
||||
PMU_SKIP_TEST_MODE_SIGN,
|
||||
PMU_SKIP_PSRAM_SIGN,
|
||||
|
||||
PMU_RSV8, //8
|
||||
PMU_RSV9,
|
||||
PMU_RSV10,
|
||||
PMU_RSV11,
|
||||
PMU_RSV12,
|
||||
PMU_RSV13,
|
||||
PMU_RSV14,
|
||||
PMU_RSV15,
|
||||
|
||||
PMU_DSLEEP_INIT_SIGN, //16
|
||||
PMU_LPWDT_LOCK_SIGN,
|
||||
PMU_WDT1_LOCK_SIGN,
|
||||
PMU_WDT_LOCK_SIGN,
|
||||
|
||||
PMU_APP_SOFTRESET_SIGN, //20
|
||||
PMU_WIFI_TEST_MODE_SIGN,
|
||||
PMU_RSV22,
|
||||
PMU_BOOT_DIRECT_RUN_PENDING2,
|
||||
};
|
||||
|
||||
#define pmu_boot_direct_run_en() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(0))
|
||||
#define pmu_boot_direct_run_dis() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(0))
|
||||
#define pmu_get_boot_direct_run_pending() ((PMU->PMUCON7 & BIT(0)))
|
||||
#define pmu_get_deadcode_pending() ((PMU->PMUCON7 & BIT(1)) ? 1 : 0)
|
||||
#define pmu_clr_deadcode_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(1))
|
||||
#define pmu_get_cp_fail_pending() ((PMU->PMUCON7 & BIT(2)) ? 1 : 0)
|
||||
#define pmu_clr_cp_fail_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(2))
|
||||
#define pmu_get_boot_code_pos() ((PMU->PMUCON7 & BIT(3)) ? 1 : 0)
|
||||
|
||||
#define GET_DIRECT_RUN_DISABLE_SIGN() ((PMU->PMUCON7 & BIT(4)) ? 1 : 0)
|
||||
#define SET_DIRECT_RUN_DISABLE_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(4));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(4));\
|
||||
} while(0)
|
||||
|
||||
#define GET_SKIP_MASTER_BOOT_SIGN() ((PMU->PMUCON7 & BIT(5)) ? 1 : 0)
|
||||
#define SET_SKIP_MASTER_BOOT_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(5));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(5));\
|
||||
} while(0)
|
||||
|
||||
#define GET_SKIP_TEST_MODE_SIGN() ((PMU->PMUCON7 & BIT(6)))
|
||||
#define SET_SKIP_TEST_MODE_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(6));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(6));\
|
||||
} while(0)
|
||||
|
||||
#define GET_SKIP_PSRAM_SIGN() ((PMU->PMUCON7 & BIT(7)))
|
||||
#define SET_SKIP_PSRAM_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(7));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(7));\
|
||||
} while(0)
|
||||
|
||||
/* PMU->PMUCON7[8:19] : not used */
|
||||
|
||||
|
||||
/* PMU->PMUCON7[20] */
|
||||
#define GET_APP_SOFTRESET_SIGN() ((PMU->PMUCON7 & BIT(20)))
|
||||
#define SET_APP_SOFTRESET_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(20));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(20));\
|
||||
} while(0)
|
||||
|
||||
/* PMU->PMUCON7[22] */
|
||||
#define GET_WIFI_TEST_MODE_SIGN() ((PMU->PMUCON7 & BIT(21)))
|
||||
#define SET_WIFI_TEST_MODE_SIGN(n)\
|
||||
do {\
|
||||
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(21));\
|
||||
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(21));\
|
||||
} while(0)
|
||||
|
||||
#define pmu_get_boot_direct_run_pending2() ((PMU->PMUCON7 & BIT(23)))
|
||||
#define pmu_set_direct_run_pengding2() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(23))
|
||||
#define pmu_clr_direct_run_pengding2() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(23))
|
||||
|
||||
#define pmu_set_direct_run_addr(addr) PMU_REG_SET_VALUE(PMU->PMUCON7, 0xFF000000, ((addr >> 12) & 0xFF), 24)
|
||||
|
||||
/* CORE_PMUCON8 */
|
||||
#define pmu_jtag_io_en() PMU_REG_SET_BITS(PMU->PMUCON8, BIT(0))
|
||||
#define pmu_jtag_io_dis() PMU_REG_CLR_BITS(PMU->PMUCON8, BIT(0))
|
||||
|
||||
|
||||
/* CORE_PMUCON11 */
|
||||
#define VCCFLS_PG_DISABLE()\
|
||||
do {\
|
||||
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 & (~ BIT(23))); \
|
||||
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 | (BIT(17))); \
|
||||
} while(0)
|
||||
|
||||
#define VCCFLS_PG_ENABLE()\
|
||||
do {\
|
||||
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
|
||||
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 | BIT(23)); \
|
||||
} while(0)
|
||||
|
||||
#define pmu_efuse_program_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(31))
|
||||
#define pmu_efuse_program_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(31))
|
||||
|
||||
#define pmu_vcam_lc_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(29))
|
||||
#define pmu_vcam_lc_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(29))
|
||||
#define pmu_vcam_pg_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(16))
|
||||
#define pmu_vcam_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(16))
|
||||
#define pmu_vcam_oc_detect_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(15))
|
||||
#define pmu_vcam_oc_detect_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(15))
|
||||
#define pmu_vcam_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(14))
|
||||
#define pmu_vcam_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(14))
|
||||
#define pmu_vcam_discharge_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(13))
|
||||
#define pmu_vcam_discharge_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(13))
|
||||
|
||||
/* CORE_PNDCLR */
|
||||
#define pmu_vcam2_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(30))
|
||||
#define pmu_vcc18_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(29))
|
||||
#define pmu_vcam_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(22))
|
||||
#define pmu_vcc15_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(13))
|
||||
#define pmu_vdd_oc_pending_clr() PMU_REG_SET_BITS(PMU->PNDCLR, BIT(12))
|
||||
|
||||
enum vcam_vol_level {
|
||||
VCAM_VOL_2V50,
|
||||
VCAM_VOL_2V55,
|
||||
VCAM_VOL_2V60,
|
||||
VCAM_VOL_2V65,
|
||||
VCAM_VOL_2V70,
|
||||
VCAM_VOL_2V75,
|
||||
VCAM_VOL_2V80,
|
||||
VCAM_VOL_2V85,
|
||||
VCAM_VOL_2V90,
|
||||
VCAM_VOL_2V95,
|
||||
VCAM_VOL_3V00,
|
||||
VCAM_VOL_3V05,
|
||||
VCAM_VOL_3V10,
|
||||
VCAM_VOL_3V15,
|
||||
VCAM_VOL_3V20,
|
||||
VCAM_VOL_3V25,
|
||||
};
|
||||
#define pmu_set_vcam_vol(vcam_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON11, 0x01e00000, vcam_vol_level, 21)
|
||||
enum vcam_oc_level {
|
||||
VCAM_OC_750MA,
|
||||
VCAM_OC_300MA,
|
||||
VCAM_OC_200MA,
|
||||
VCAM_OC_100MA,
|
||||
};
|
||||
#define pmu_vcam_oc_set(vcam_oc_level) PMU_REG_SET_VALUE(PMU->PMUCON11, 0x00000600, vcam_oc_level, 9)
|
||||
|
||||
|
||||
/* CORE_RFCON0 */
|
||||
#define pmu_xo_cs_set(xo_cs_vdd) PMU_REG_SET_VALUE(PMU->RFCON0, 0x03f80000, xo_cs_vdd, 19)
|
||||
#define xo_set_cs_sec(xo_cs_vdd) pmu_xo_cs_set(xo_cs_vdd)
|
||||
|
||||
#define pmu_xosc_en() PMU_REG_SET_BITS(PMU->RFCON0, BIT(0))
|
||||
#define pmu_xosc_dis() PMU_REG_CLR_BITS(PMU->RFCON0, BIT(0))
|
||||
|
||||
enum vcc_ldo_vol_level {
|
||||
VCC_LDO_VOL_1V00,
|
||||
VCC_LDO_VOL_1V05,
|
||||
VCC_LDO_VOL_1V10,
|
||||
VCC_LDO_VOL_1V15,
|
||||
VCC_LDO_VOL_1V20,
|
||||
VCC_LDO_VOL_1V25,
|
||||
VCC_LDO_VOL_1V30,
|
||||
VCC_LDO_VOL_1V35,
|
||||
VCC_LDO_VOL_1V40,
|
||||
VCC_LDO_VOL_1V45,
|
||||
VCC_LDO_VOL_1V50,
|
||||
VCC_LDO_VOL_1V55,
|
||||
VCC_LDO_VOL_1V60,
|
||||
VCC_LDO_VOL_1V65,
|
||||
VCC_LDO_VOL_1V70,
|
||||
VCC_LDO_VOL_1V75,
|
||||
VCC_LDO_VOL_1V80,
|
||||
VCC_LDO_VOL_1V85,
|
||||
VCC_LDO_VOL_1V90,
|
||||
VCC_LDO_VOL_1V95,
|
||||
VCC_LDO_VOL_2V00,
|
||||
VCC_LDO_VOL_2V05,
|
||||
VCC_LDO_VOL_2V10,
|
||||
VCC_LDO_VOL_2V15,
|
||||
VCC_LDO_VOL_2V20,
|
||||
VCC_LDO_VOL_2V25,
|
||||
VCC_LDO_VOL_2V30,
|
||||
VCC_LDO_VOL_2V35,
|
||||
VCC_LDO_VOL_2V40,
|
||||
VCC_LDO_VOL_2V45,
|
||||
VCC_LDO_VOL_2V50,
|
||||
VCC_LDO_VOL_2V55,
|
||||
};
|
||||
|
||||
struct system_reset_pending_bits {
|
||||
uint32 srp_mclr : 1, /* mclr pin reset */
|
||||
srp_soft : 1, /* cpu0 mcu reset */
|
||||
srp_wdt : 1, /* cpu0 watchdog reset */
|
||||
srp_lp_wdt : 1, /* lowpower watchdog reset */
|
||||
srp_wdt1 : 1, /* cpu1 watchdog reset */
|
||||
srp_soft1 : 1, /* cpu1 mcu reset */
|
||||
Reserved0 : 2,
|
||||
|
||||
srp_lvd : 1, /* vcc lower voltage reset */
|
||||
srp_lvd_vcam_cur_ov : 1,/* vcam over-current */
|
||||
srp_lvd_vcc15_cur_ov : 1,/* vcc15 over-current */
|
||||
srp_lvd_vdd_cur_ov : 1, /* vdd over-current */
|
||||
srp_lvd_vdd_vol_low : 1, /* vdd voltage low */
|
||||
srp_lvd_vcc_vol_low : 1, /* vcc voltage low */
|
||||
srp_lvd_vcc1_vol_low : 1, /* vcc1 voltage low */
|
||||
srp_lvd_vcc15_vol_low : 1, /* vcc15 voltage low */
|
||||
|
||||
srp_deep_sleep : 1,
|
||||
srp_lvd_vdd18_cur_ov : 1, /* vdd18 over-current */
|
||||
srp_lvd_vcam2_cur_ov : 1, /* vcam2 over-current */
|
||||
|
||||
Reserved : 13;
|
||||
};
|
||||
|
||||
struct system_reset_info {
|
||||
union {
|
||||
uint32 system_reset_pending;
|
||||
struct system_reset_pending_bits system_reset_pending_bits_s;
|
||||
};
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
extern struct system_reset_info sri;
|
||||
|
||||
|
||||
void pmu_reg_write(uint32 reg_addr, uint32 data) ;
|
||||
|
||||
void pmu_dcdc_open(void);
|
||||
|
||||
void pmu_vccfls_power_set(uint32 power_on, uint32 suply_3p3v);
|
||||
/* PC[8:13] power domain : VCC or VCC18 */
|
||||
void pmu_vccsd_power_set(uint32 power_on, uint32 suply_3p3v);
|
||||
int32 pmu_vdd18_ldo_en(uint32 en, enum vcc_ldo_vol_level vol);
|
||||
int pmu_is_vdd18_ldo_en(void);
|
||||
int pmu_get_vdd18_ldo_vol(void);
|
||||
|
||||
/**
|
||||
* strongly recommend vol same with vcc18 when power for mipi sensor
|
||||
*/
|
||||
int32 pmu_vcam2_ldo_en(uint32 en, enum vcc_ldo_vol_level vol);
|
||||
int pmu_is_vcam2_ldo_en(void);
|
||||
int pmu_get_vcam2_ldo_vol(void);
|
||||
|
||||
|
||||
void pmu_tsensor_chan_sel_sec(uint8 chan_idx);
|
||||
void pmu_pd_set_anatop_en_sec(void);
|
||||
int jtag_map_set(uint8 val);
|
||||
|
||||
void tsensor_open(void);
|
||||
void tsensor_close(void);
|
||||
|
||||
void lvd_irq_handler(void *data);
|
||||
void sys_reset_detect(void);
|
||||
void sys_reset_pending_clr(void);
|
||||
void sys_reset_show(void);
|
||||
void pmu_vdd_core_set(uint32 vddcore);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__PMU_H__
|
||||
|
||||
|
||||
|
||||
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
|
||||
|
||||
|
||||
116
sdk/include/chip/txw82x/rpc.h
Normal file
116
sdk/include/chip/txw82x/rpc.h
Normal file
@@ -0,0 +1,116 @@
|
||||
#ifndef _TXW82X_RPC_FUNCID_H_
|
||||
#define _TXW82X_RPC_FUNCID_H_
|
||||
|
||||
#define RPC_FUNC_ID(f) RPC_FUNCID_##f
|
||||
|
||||
enum CPU0_RPC_FUNCID {
|
||||
RPC_FUNC_ID(sys_wifi_register) = 2, /*ID 1 空出来*/
|
||||
RPC_FUNC_ID(sys_wifi_recv),
|
||||
RPC_FUNC_ID(sys_event_new),
|
||||
RPC_FUNC_ID(sys_wifi_event_cb),
|
||||
RPC_FUNC_ID(atcmd_recv),
|
||||
|
||||
//BT
|
||||
RPC_FUNC_ID(hci_host_recv),
|
||||
|
||||
//lvgl
|
||||
RPC_FUNC_ID(lvgl_frame_rotate_rpc_sync),
|
||||
|
||||
/////////////////////////////////
|
||||
CPU0_RPC_FUNCID_NUM,
|
||||
};
|
||||
|
||||
enum CPU1_RPC_FUNCID {
|
||||
RPC_FUNC_ID(sys_enter_sleep), //SLEEP: 固定为 ID 1
|
||||
RPC_FUNC_ID(cpu1_run_func),
|
||||
RPC_FUNC_ID(cpu1_atcmd_recv),
|
||||
RPC_FUNC_ID(lmac_ioctl_rpc),
|
||||
RPC_FUNC_ID(skbpool_add_region),
|
||||
RPC_FUNC_ID(ieee80211_deliver_init),
|
||||
RPC_FUNC_ID(ieee80211_iface_create_ap),
|
||||
RPC_FUNC_ID(ieee80211_iface_create_sta),
|
||||
RPC_FUNC_ID(ieee80211_iface_start),
|
||||
RPC_FUNC_ID(ieee80211_iface_stop),
|
||||
RPC_FUNC_ID(ieee80211_pairing),
|
||||
RPC_FUNC_ID(ieee80211_unpair),
|
||||
RPC_FUNC_ID(ieee80211_scan),
|
||||
RPC_FUNC_ID(ieee80211_scatter_tx),
|
||||
RPC_FUNC_ID(ieee80211_tx),
|
||||
RPC_FUNC_ID(ieee80211_input),
|
||||
RPC_FUNC_ID(ieee80211_tx_mgmt),
|
||||
RPC_FUNC_ID(ieee80211_tx_custmgmt),
|
||||
RPC_FUNC_ID(ieee80211_tx_ether),
|
||||
RPC_FUNC_ID(ieee80211_disassoc),
|
||||
RPC_FUNC_ID(ieee80211_disassoc_all),
|
||||
RPC_FUNC_ID(ieee80211_hook_ext_data),
|
||||
RPC_FUNC_ID(ieee80211_cleanup_bsslist),
|
||||
RPC_FUNC_ID(ieee80211_get_bsslist),
|
||||
RPC_FUNC_ID(ieee80211_get_stalist),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_bssbw),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_bssbw),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_chanlist),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_ssid),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_ssid),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_keymgmt),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_keymgmt),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_psk),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_passwd),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_psk),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_beacon_int),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_dtim_int),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_bssid),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_bssid),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_channel),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_channel),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_mac),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_mac),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_bss_max_idle),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_connstate),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_wkreason),
|
||||
RPC_FUNC_ID(ieee80211_conf_wakeup_sta),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_txpower),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_heartbeat_int),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_aplost_time),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_acs),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_wmm_enable),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_use4addr),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_stainfo),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_stalist),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_sta_snr),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_stacnt),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_aphide),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_bgrssi),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_mcast_txrate),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_hwmode),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_psdata_cnt),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_wmm_param),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_wmm_param),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_wpa_group_rekey),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_datatag),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_ant_sel),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_reason_code),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_status_code),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_rtc),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_acs_result),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_rtc),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_radio_onoff),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_isolate),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_ft),
|
||||
RPC_FUNC_ID(ieee80211_pair_enable),
|
||||
RPC_FUNC_ID(hci_controller_recv),
|
||||
RPC_FUNC_ID(audio_coder_run),
|
||||
RPC_FUNC_ID(lvgl_frame_rotate_rpc_init),
|
||||
RPC_FUNC_ID(lvgl_frame_rotate_rpc),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_pair_ngo),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_mutl_pair),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_linkcost_param),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_pair_channel),
|
||||
RPC_FUNC_ID(ieee80211_conf_get_tx_mcs),
|
||||
RPC_FUNC_ID(ieee80211_conf_set_tx_mcs),
|
||||
RPC_FUNC_ID(cpu1_new_task),
|
||||
|
||||
/////////////////////////////////
|
||||
CPU1_RPC_FUNCID_NUM,
|
||||
};
|
||||
|
||||
#endif
|
||||
1377
sdk/include/chip/txw82x/sysctrl.h
Normal file
1377
sdk/include/chip/txw82x/sysctrl.h
Normal file
File diff suppressed because it is too large
Load Diff
56
sdk/include/chip/txw82x/test_atcmd.h
Normal file
56
sdk/include/chip/txw82x/test_atcmd.h
Normal file
@@ -0,0 +1,56 @@
|
||||
#ifndef _TXW82X_TEST_ATCMD_H_
|
||||
#define _TXW82X_TEST_ATCMD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int32 atcmd_reg_rd_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_reg_wt_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_test_start_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_test_addr_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_temp_en_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_type_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_rf_pwr_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_pha_amp_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_step_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_cont_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_start_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_trig_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_frm_type_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_mcs_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_lo_freq_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_edca_cw_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_edca_aifs_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_edca_txop_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 at_cmd_cfg_rx_agc_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_lmac_print_period_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_bss_bw_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_set_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_set_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 at_cmd_cca_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_wave_dump_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_write_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_write_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_write_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_set_cca_cert_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_set_srrc_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_dbg_level_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 sys_atcmd_reset(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_sleep_dbg_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_sleep_alg_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_sleep_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
int32 atcmd_dtim_hdl(const char *cmd, char *argv[], uint32 argc);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
503
sdk/include/chip/txw82x/txw82x.h
Normal file
503
sdk/include/chip/txw82x/txw82x.h
Normal file
@@ -0,0 +1,503 @@
|
||||
#ifndef _TXW82X_DEF_H_
|
||||
#define _TXW82X_DEF_H_
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
#define RETURN_ADDR() __builtin_return_address(0)
|
||||
#define cpu_dcache_disable() csi_dcache_clean_invalid(); csi_dcache_disable();
|
||||
#define cpu_dcache_enable() csi_dcache_enable()
|
||||
|
||||
typedef signed char int8;
|
||||
typedef signed short int16;
|
||||
typedef signed int int32;
|
||||
typedef signed long long int64;
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned long long uint64;
|
||||
typedef unsigned long ulong;
|
||||
|
||||
#ifndef _SIZE_T_DECLARED
|
||||
typedef unsigned int size_t;
|
||||
#define _SIZE_T_DECLARED
|
||||
#endif
|
||||
|
||||
#ifndef _SSIZE_T_DECLARED
|
||||
#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
|
||||
typedef int ssize_t;
|
||||
#else
|
||||
typedef long ssize_t;
|
||||
#endif
|
||||
#define _SSIZE_T_DECLARED
|
||||
#endif
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/* ------------------------- Interrupt Number Definition ------------------------ */
|
||||
|
||||
enum IRQn {
|
||||
/****** Peripheral Interrupt Numbers *********************************************************/
|
||||
USB20DMA_IRQn = 0,
|
||||
USB20MC_IRQn = 1,
|
||||
UART0_IRQn = 2,
|
||||
UART1_IRQn = 3,
|
||||
LCD_IRQn = 4,
|
||||
QSPI_IRQn = 5,
|
||||
SPI0_IRQn = 6,
|
||||
SPI1_IRQn = 7,
|
||||
SPI2_IRQn = 8,
|
||||
OSPI_IRQn = 9,
|
||||
TIM0_IRQn = 10,
|
||||
TIM1_IRQn = 11,
|
||||
TIM2_IRQn = 12,
|
||||
TIM3_IRQn = 13,
|
||||
SCALE1_IRQn = 14,
|
||||
AUDIO_SUBSYS2_IRQn = 15,//Swap the position of number 2 with number 0 ,
|
||||
AUDIO_SUBSYS1_IRQn = 16,//To keep consist with rtl design
|
||||
AUDIO_SUBSYS0_IRQn = 17,//
|
||||
SDIO_IRQn = 18,
|
||||
SDHOST1_IRQn = 19,
|
||||
SDHOST_IRQn = 20,
|
||||
LMAC_IRQn = 21,
|
||||
GMAC_IRQn = 22,
|
||||
DUAL_ORG_IRQn = 23,
|
||||
GEN422_IRQn = 24,
|
||||
CORET_IRQn = 25, //CPU TIMER
|
||||
SHA_IRQn = 26, //SHA/SYS_AES
|
||||
CRC_IRQn = 27,
|
||||
ADKEY0_IRQn = 28,
|
||||
PD_TMR_IRQn = 29,
|
||||
WKPND_IRQn = 30,
|
||||
PDWKPND_IRQn = 31,
|
||||
LVD_IRQn = 32,
|
||||
WDT_IRQn = 33,
|
||||
SYS_ERR_IRQn = 34,
|
||||
IIS0_IRQn = 35,
|
||||
IIS1_IRQn = 36,
|
||||
GPIOA_IRQn = 37,
|
||||
LO_MNT_IRQn = 38,
|
||||
DVP_IRQn = 39,
|
||||
MJPEG01_IRQn = 40,
|
||||
H264ENC_IRQn = 41,
|
||||
VPP_IRQn = 42,
|
||||
PRC_IRQn = 43,
|
||||
STMR5_IRQn = 44,
|
||||
PDM_IRQn = 45,
|
||||
LED_TMR_IRQn = 46,
|
||||
SCALE2_IRQn = 47,
|
||||
GFSK_IRQn = 48,
|
||||
CMPOUT0_IRQn = 49,
|
||||
UART6_IRQn = 50,
|
||||
SCALE3_IRQn = 51,
|
||||
IMG_ISP_IRQn = 52,
|
||||
MIPI_CSI2_IRQn = 53,
|
||||
RF_IRQn = 54,
|
||||
USB11_MC_IRQn = 55,
|
||||
USB11_DMA_IRQn = 56,
|
||||
RTC_VCCHVD_IRQn = 57,
|
||||
RTC_IRQn = 58,
|
||||
MIPI_DSI_IRQn = 59,
|
||||
PARA_OUT_IRQn = 60,
|
||||
M2M_DMA0_IRQn = 61,
|
||||
CAN_IRQn = 62,
|
||||
EXT_DCACHE_IRQn = 63,
|
||||
CPU_SPINLOCK_IRQn = 64,
|
||||
CPU_RECV_MAIL_IRQn = 65,
|
||||
CPU_SEND_MAIL_IRQn = 66,
|
||||
CPU_DBG_ON_IRQn = 67,
|
||||
OSPI_FIFO_IRQn = 68,
|
||||
OSPI_EFF_IRQn = 69,
|
||||
GEN420_IRQn = 70,
|
||||
SYS_AES_IRQn = 71,
|
||||
PKA_IRQn = 72,
|
||||
WDT1_IRQn = 73,
|
||||
GPIOB_IRQn = 74,
|
||||
GPIOC_IRQn = 75,
|
||||
GPIOD_IRQn = 76,
|
||||
GPIOE_IRQn = 77,
|
||||
GPIOF_IRQn = 78,
|
||||
DVP1_IRQn = 79,
|
||||
PNG_IRQn = 80,
|
||||
STMR4_IRQn = 81,
|
||||
STMR3_IRQn = 82,
|
||||
STMR2_IRQn = 83,
|
||||
STMR1_IRQn = 84,
|
||||
STMR0_IRQn = 85,
|
||||
CMPOUT1_IRQn = 86,
|
||||
UART5_IRQn = 87,
|
||||
UART4_IRQn = 88,
|
||||
MIPI1_CSI2_IRQn = 89,
|
||||
DMA2D_IRQn = 90,
|
||||
CSC_IRQn = 91,
|
||||
OSD_ENC_IRQn = 92,
|
||||
USB20PHY_IRQn = 93,
|
||||
PARA_IN_IRQn = 94,
|
||||
M2M_DMA1_IRQn = 95,
|
||||
WKUP_IRQn = 96,
|
||||
SAM_IRQn = 97,
|
||||
LIN_IRQn = 98,
|
||||
LIN1_IRQn = 99,
|
||||
CPU_SOFT_INT_IRQn = 100,
|
||||
M2M_DMA2_IRQn = 105,
|
||||
|
||||
IRQ_NUM,
|
||||
};
|
||||
|
||||
/* ================================================================================ */
|
||||
/* ================ Processor and Core Peripheral Section ================ */
|
||||
/* ================================================================================ */
|
||||
|
||||
/* -------- Configuration of the CK804 Processor and Core Peripherals ------- */
|
||||
#define __CK803_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __CK804_REV 0x0000U /* Core revision r0p0 */
|
||||
#define __MPU_PRESENT 0 /* MGU present or not */
|
||||
#define __VIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
|
||||
|
||||
#include "csi_core.h" /* Processor and core peripherals */
|
||||
#include "stdint.h"
|
||||
|
||||
|
||||
/** @addtogroup Peripheral_registers_structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define PSRAM_BASE_I ((uint32_t)0x08000000) /*!< SRAM base address in the alias region */
|
||||
#define PSRAM_END_ADDR_I ((uint32_t)0x10000000) /*!< SRAM end address in the alias region */
|
||||
#define FLASH_BASE ((uint32_t)0x10000000) /*!< FLASH base address in the alias region */
|
||||
#define FLASH_END_BASE ((uint32_t)0x20000000) /*!< FLASH base address in the alias region */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define DCACHE_CTRL_BASE ((uint32_t)0x50000000)
|
||||
#define PSRAM_BASE ((uint32_t)0x28000000) /*!< SRAM base address in the alias region */
|
||||
#define PSRAM_END_ADDR ((uint32_t)0x30000000) /*!< SRAM end address in the alias region */
|
||||
|
||||
/*!< Peripheral memory map */
|
||||
#define APB0_BASE PERIPH_BASE
|
||||
#define APB1_BASE (PERIPH_BASE + 0x10000)
|
||||
#define APB2_BASE (PERIPH_BASE + 0xc0000)
|
||||
#define AHB_BASE (PERIPH_BASE + 0x20000)
|
||||
#define GPIO_BASE (PERIPH_BASE + 0xe0000)
|
||||
|
||||
#define SYSCTRL_BASE (AHB_BASE + 0x0000)
|
||||
#define CPUDBG_BASE (AHB_BASE + 0x0280)
|
||||
|
||||
#define GPIOA_BASE (GPIO_BASE + 0x0000)
|
||||
#define GPIOB_BASE (GPIO_BASE + 0x0100)
|
||||
#define GPIOC_BASE (GPIO_BASE + 0x0200)
|
||||
#define GPIOD_BASE (GPIO_BASE + 0x0300)
|
||||
#define GPIOE_BASE (GPIO_BASE + 0x0400)
|
||||
#define GPIOF_BASE (GPIO_BASE + 0x0500)
|
||||
|
||||
#define SYS_MNT_BASE (AHB_BASE + 0x023c)
|
||||
#define SDHOST_BASE (0x40040048)
|
||||
#define SDHOST1_BASE (0x40040068)
|
||||
#define SDIO_HOST_BASE (AHB_BASE + 0x3000) //not used
|
||||
#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
|
||||
#define LMAC_BASE (AHB_BASE + 0x42000)
|
||||
#define USB11S_BASE (PERIPH_BASE + 0x70000)
|
||||
#define GMAC_BASE (PERIPH_BASE + 0x71000)
|
||||
#define MODEM_BASE (PERIPH_BASE + 0xd0000)
|
||||
#define USB20_BASE (PERIPH_BASE + 0xf0000)
|
||||
//#define DMAC_BASE (AHB_BASE + 0x0000)
|
||||
//#define GPIOA_BASE (AHB_BASE + 0x2000)
|
||||
//#define GPIOB_BASE (AHB_BASE + 0x5000)
|
||||
//#define SYS_MNT_BASE (AHB_BASE + 0x9000)
|
||||
|
||||
//-------------------------------------------------------
|
||||
// APB0 SYNC CLK DOMAIN PERIS
|
||||
//-------------------------------------------------------
|
||||
#define QSPI_BASE (APB0_BASE + 0x0000)
|
||||
#define OSPI_BASE (APB0_BASE + 0x1000)
|
||||
#define SCHED_BASE (APB0_BASE + 0x2000)
|
||||
#define UART0_BASE (APB2_BASE + 0x0000)
|
||||
#define UART1_BASE (APB2_BASE + 0x0100)
|
||||
#define UART2_BASE (APB2_BASE + 0x0200)
|
||||
#define UART3_BASE (APB2_BASE + 0x0300)
|
||||
#define UART4_BASE (APB2_BASE + 0x0b70)
|
||||
#define UART5_BASE (APB2_BASE + 0x0b90)
|
||||
#define UART6_BASE (APB2_BASE + 0x0bb0)
|
||||
#define SPI0_BASE (APB0_BASE + 0x7400)
|
||||
#define SPI1_BASE (APB0_BASE + 0x7500)
|
||||
#define SPI2_BASE (APB2_BASE + 0x0600)
|
||||
#define SPI3_BASE (APB2_BASE + 0x0700)
|
||||
#define SPI4_BASE (APB2_BASE + 0x0800)
|
||||
#define SPI5_BASE (APB2_BASE + 0x0b20)
|
||||
#define SPI6_BASE (APB2_BASE + 0x0b38)
|
||||
#define LED_BASE (APB0_BASE + 0x4b50)
|
||||
#define IIC0_BASE (APB0_BASE + 0x7400)
|
||||
#define IIC1_BASE (APB0_BASE + 0x7500)
|
||||
#define IIC2_BASE (APB2_BASE + 0x0600)
|
||||
#define IIC3_BASE (APB2_BASE + 0x0700)
|
||||
#define IIC4_BASE (APB2_BASE + 0x0800)
|
||||
#define IIS0_BASE (APB2_BASE + 0x3400)
|
||||
#define IIS1_BASE (APB2_BASE + 0x3440)
|
||||
#define PDM_BASE (APB2_BASE + 0x3480)
|
||||
#define PRC_BASE (APB0_BASE + 0x5000)
|
||||
#define OF_BASE (APB0_BASE + 0x5020)
|
||||
#define FT_BASE (APB0_BASE + 0x5040)
|
||||
#define PALE_BASE (APB0_BASE + 0x5060)
|
||||
#define VPP_BASE (APB0_BASE + 0x5100)
|
||||
#define MJPEG0_BASE (APB0_BASE + 0x5200)
|
||||
#define MJPEG0_DQT_BASE (APB0_BASE + 0x5280)
|
||||
#define MJPEG1_BASE (APB0_BASE + 0x5300)
|
||||
#define CSI2_HOST_BASE (APB0_BASE + 0x5700)
|
||||
#define MJPEG0_TAB_BASE (APB0_BASE + 0x5280)
|
||||
#define MJPEG1_TAB_BASE (APB0_BASE + 0x5380)
|
||||
#define MJPEG_HUFF_BASE (APB0_BASE + 0x5400)
|
||||
#define PARA_OUT_BASE (APB0_BASE + 0x6000)
|
||||
#define PARA_IN_BASE (APB0_BASE + 0x6040)
|
||||
#define DVP_BASE (APB0_BASE + 0x6070)
|
||||
#define DVP1_BASE (APB0_BASE + 0x6088)
|
||||
#define GEN422_BASE (APB0_BASE + 0x60a0)
|
||||
#define GEN420_BASE (APB0_BASE + 0x60e0)
|
||||
#define DUAL_ORG_BASE (APB0_BASE + 0x6110)
|
||||
#define MIPI_DSI_BASE (APB0_BASE + 0x6200)
|
||||
#define MIPI_CSI0_BASE (APB0_BASE + 0x6400)
|
||||
#define MIPI_CSI1_BASE (APB0_BASE + 0x6600)
|
||||
#define SCALE1_BASE (APB0_BASE + 0x7100)
|
||||
#define LCDC_BASE (APB0_BASE + 0x7000)
|
||||
#define ROT_BASE (APB1_BASE + 0xc140)
|
||||
#define FILL_BASE (APB1_BASE + 0xc180)
|
||||
#define CSC_BASE (APB1_BASE + 0xc200)
|
||||
#define OSD_ENC_BASE (APB1_BASE + 0xc240)
|
||||
#define SHADOW_BASE (APB1_BASE + 0xc280)
|
||||
#define TRANSFORM_BASE (APB1_BASE + 0xc300)
|
||||
#define SCALE2_BASE (APB0_BASE + 0x71A0)
|
||||
#define SCALE3_BASE (APB0_BASE + 0x7200)
|
||||
#define AUDIO_BASE (APB2_BASE + 0x3000)
|
||||
|
||||
|
||||
#define COMP_BASE (APB0_BASE + 0x9000)
|
||||
#define EFUSE_BASE (APB0_BASE + 0xa000)
|
||||
#define LO_MNT_BASE (APB2_BASE + 0x3740)
|
||||
#define AUDIO_DSP (APB2_BASE + 0x3600)
|
||||
#define CAN_RBUF_BASE (APB2_BASE + 0x4000)
|
||||
#define CAN_TBUF_BASE (APB2_BASE + 0x4050)
|
||||
#define CAN_CTRL_BASE (APB2_BASE + 0x4098)
|
||||
#define CAN_ACF_BASE (APB2_BASE + 0x40b8)
|
||||
|
||||
#define FPGA_DDR_BASE (APB0_BASE + 0xf000)
|
||||
#define H264_REG_BASE (APB1_BASE + 0x1000)
|
||||
#define RFADCDIG_BASE (APB1_BASE + 0x4000)
|
||||
#define WDT_BASE (APB2_BASE + 0x1000)
|
||||
#define WDT1_BASE (APB2_BASE + 0x1010)
|
||||
#define TIMER_ALL_BASE (APB2_BASE + 0x1128)
|
||||
#define TIMER0_BASE (APB2_BASE + 0x1100)
|
||||
#define TIMER1_BASE (APB2_BASE + 0x1200)
|
||||
#define TIMER2_BASE (APB2_BASE + 0x1300)
|
||||
#define TIMER3_BASE (APB2_BASE + 0x1400)
|
||||
#define TIMER4_BASE (APB2_BASE + 0x1500)
|
||||
#define SUPTMR_BASE (APB2_BASE + 0x1600)
|
||||
#define SIMPLE_TIMER0_BASE (APB2_BASE + 0x1b00)
|
||||
#define SIMPLE_TIMER1_BASE (APB2_BASE + 0x1b10)
|
||||
#define SIMPLE_TIMER2_BASE (APB2_BASE + 0x1b20)
|
||||
#define SIMPLE_TIMER3_BASE (APB2_BASE + 0x1b30)
|
||||
#define SIMPLE_TIMER4_BASE (APB2_BASE + 0x1b40)
|
||||
#define SIMPLE_TIMER5_BASE (APB2_BASE + 0x1b50)
|
||||
|
||||
#define CRC_BASE (APB1_BASE + 0x2000)
|
||||
#define SYS_AES_BASE (APB1_BASE + 0x2100)
|
||||
#define SHA_BASE (APB1_BASE + 0X2200)
|
||||
|
||||
#define IMAGE_ISP_BASE (APB1_BASE + 0x6000)
|
||||
#define ISP_LSC_BASE (APB1_BASE + 0x6300)
|
||||
#define ISP_R_GAMMA_BASE (APB1_BASE + 0x6400)
|
||||
#define ISP_G_GAMMA_BASE (APB1_BASE + 0x6500)
|
||||
#define ISP_B_GAMMA_BASE (APB1_BASE + 0x6600)
|
||||
#define ISP_Y_GAMMA_BASE (APB1_BASE + 0x6700)
|
||||
#define ISP_R_HIST_BASE (APB1_BASE + 0x6800)
|
||||
#define ISP_G_HIST_BASE (APB1_BASE + 0x6900)
|
||||
#define ISP_B_HIST_BASE (APB1_BASE + 0x6a00)
|
||||
#define ISP_Y_HIST_BASE (APB1_BASE + 0x6b00)
|
||||
|
||||
#define PMU_BASE (APB1_BASE + 0x8000)
|
||||
#define LVD_BASE (APB1_BASE + 0x8000)
|
||||
#define RTC_BASE (APB1_BASE + 0x8000)
|
||||
#define RFDIG_BASE (APB1_BASE + 0x9000)
|
||||
#define ADKEY_BASE (APB2_BASE + 0x2000)
|
||||
#define CMP_BASE (APB1_BASE + 0xa020)
|
||||
#define ADKEY1_BASE (APB1_BASE + 0xa024)
|
||||
#define USB11_BASE (APB1_BASE + 0xb000)
|
||||
#define DMA2D_BASE (APB1_BASE + 0xc000)
|
||||
#define DMA2D_FGCLUT_BASE (APB1_BASE + 0xc800)
|
||||
#define DMA2D_BGCLUT_BASE (APB1_BASE + 0xcc00)
|
||||
#define RFDIGCAL_BASE (APB1_BASE + 0xd000)
|
||||
#define NPU_BASE (APB1_BASE + 0xe000)
|
||||
|
||||
#define SYSCTRL_BASE (AHB_BASE + 0x0000)
|
||||
#define GPIOA_BASE (GPIO_BASE + 0x0000)
|
||||
#define GPIOB_BASE (GPIO_BASE + 0x0100)
|
||||
#define GPIOC_BASE (GPIO_BASE + 0x0200)
|
||||
#define GPIOD_BASE (GPIO_BASE + 0x0300)
|
||||
#define GPIOE_BASE (GPIO_BASE + 0x0400)
|
||||
#define GPIOF_BASE (GPIO_BASE + 0x0500)
|
||||
|
||||
#define AUDIO_CORDIC_BASE (AUDIO_BASE+ 0x500)
|
||||
#define AUDIO_DSP_FLT_BASE (AUDIO_BASE+ 0x600)
|
||||
#define AUDIO_EQ_BASE (AUDIO_BASE+ 0x700)
|
||||
#define AUDIO_ASRC_BASE (AUDIO_BASE+ 0x710)
|
||||
#define AUDIO_DRC_BASE (AUDIO_BASE+ 0x720)
|
||||
#define M2M_DMA_BASE (0x40040000)
|
||||
#define M2M_DMA0_BASE (M2M_DMA_BASE + 0x00)
|
||||
#define M2M_DMA1_BASE (M2M_DMA_BASE + 0x18)
|
||||
#define M2M_DMA2_BASE (M2M_DMA_BASE + 0x30)
|
||||
|
||||
#define SYS_MNT_BASE (AHB_BASE + 0x023c)
|
||||
#define SDHOST_BASE (0x40040048)
|
||||
#define SDHOST1_BASE (0x40040068)
|
||||
#define SDIO_SLAVE_BASE (AHB_BASE + 0x20000)
|
||||
#define MODEM_BASE (PERIPH_BASE + 0xd0000)
|
||||
#define LMAC_BASE (AHB_BASE + 0x42000)
|
||||
#define GMAC_BASE (PERIPH_BASE + 0x71000)
|
||||
#define USB20_BASE (PERIPH_BASE + 0xf0000)
|
||||
#define FT_USB3_BASE (APB0_BASE + 0x5040)
|
||||
#define LED_TIMER0_BASE (PMU_BASE + 0x000d0)
|
||||
#define LED_TIMER1_BASE (PMU_BASE + 0x000d4)
|
||||
#define LED_TIMER2_BASE (PMU_BASE + 0x000d8)
|
||||
#define LED_TIMER3_BASE (PMU_BASE + 0x000dc)
|
||||
#define CPU0_MSGBOX_BASE (0x80001000)
|
||||
#define CPU0_SPLCK_BASE (0x80001060)
|
||||
#define CPU1_MSGBOX_BASE (0x80000000)
|
||||
#define CPU1_SPLCK_BASE (0x80000060)
|
||||
#define CORESETTING_BASE (0x2006bf00)
|
||||
|
||||
typedef enum {
|
||||
HG_AHB_PT_ALL,
|
||||
HG_AHB_PT_GPIOA_DEBUNCE,
|
||||
HG_AHB_PT_GPIOB_DEBUNCE,
|
||||
HG_AHB_PT_GPIOC_DEBUNCE,
|
||||
HG_AHB_PT_M2M_DMA,
|
||||
HG_AHB_PT_SYS_MNT,
|
||||
HG_AHB_PT_SDMMC,
|
||||
HG_AHB_PT_SDIO,
|
||||
HG_AHB_PT_MODEM,
|
||||
HG_AHB_PT_LMAC,
|
||||
HG_AHB_PT_GMAC,
|
||||
HG_AHB0_PT_DISPLAY, //scale0/2/3,rotate,screenshot,osd0,gama,dither,lcd_if,ccm_constrast_saturation,alpha_blend,video
|
||||
HG_AHB0_PT_VEDIO_IF, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
|
||||
|
||||
HG_APB0_PT_ALL,
|
||||
HG_AHB0_PT_H264, //dual_org,dvp0/1,gen420,gen422,csi0/1,dsi,para_in.
|
||||
HG_APB0_PT_QSPI,
|
||||
HG_APB0_PT_OSPI,
|
||||
HG_APB0_PT_UART0,
|
||||
HG_APB0_PT_UART1,
|
||||
HG_APB0_PT_UART4,
|
||||
HG_APB0_PT_UART5,
|
||||
HG_APB0_PT_UART6,
|
||||
HG_APB0_PT_SPI0,
|
||||
HG_APB0_PT_SPI1,
|
||||
HG_APB0_PT_SPI2,
|
||||
HG_APB0_PT_SPI3,
|
||||
HG_APB0_PT_SPI5,
|
||||
HG_APB0_PT_SPI6,
|
||||
HG_APB0_PT_LED,
|
||||
HG_APB0_PT_IIC0,
|
||||
HG_APB0_PT_IIC1,
|
||||
HG_APB0_PT_IIC2,
|
||||
HG_APB0_PT_IIC3,
|
||||
HG_APB0_PT_IIS0,
|
||||
HG_APB0_PT_IIS1,
|
||||
HG_APB0_PT_PDM,
|
||||
HG_APB0_PT_JPEG,
|
||||
HG_APB0_PT_DVP,
|
||||
HG_APB0_PT_CMP,
|
||||
HG_APB0_PT_EFUSE,
|
||||
|
||||
HG_APB1_PT_ALL,
|
||||
HG_APB1_PT_AES,
|
||||
HG_APB1_PT_ISP,
|
||||
HG_APB1_PT_TMR0,
|
||||
HG_APB1_PT_TMR1,
|
||||
HG_APB1_PT_TMR2,
|
||||
HG_APB1_PT_TMR3,
|
||||
HG_APB1_PT_STMR,
|
||||
HG_APB1_PT_SUPTMR,
|
||||
HG_APB1_PT_CRC,
|
||||
HG_APB1_PT_PMU,
|
||||
HG_APB1_PT_LVD,
|
||||
HG_APB1_PT_ADKEY,
|
||||
HG_ASYNC_APB1_PT_AUDIO_SUB, //adc,dac,iis0/1,pdm,cordic,hs,sync,vad
|
||||
} HG_Peripheral_Type;
|
||||
|
||||
typedef enum {
|
||||
CPU_SPLOCK_ID_0,
|
||||
CPU_SPLOCK_ID_1,
|
||||
CPU_SPLOCK_ID_2,
|
||||
CPU_SPLOCK_ID_3,
|
||||
CPU_SPLOCK_ID_4,
|
||||
CPU_SPLOCK_ID_5,
|
||||
CPU_SPLOCK_ID_6,
|
||||
CPU_SPLOCK_ID_7,
|
||||
CPU_SPLOCK_ID_8,
|
||||
CPU_SPLOCK_ID_9,
|
||||
CPU_SPLOCK_ID_10,
|
||||
CPU_SPLOCK_ID_11,
|
||||
CPU_SPLOCK_ID_12,
|
||||
CPU_SPLOCK_ID_13_DMA2D,
|
||||
CPU_SPLOCK_ID_14_EFUSE,
|
||||
CPU_SPLOCK_ID_15_DCACHE,
|
||||
CPU_SPLOCK_ID_MAX,
|
||||
} CPU_SPLOCK_ID;
|
||||
|
||||
#define EFUSE_OFFSET 3
|
||||
#define JPG_NUM 2
|
||||
#define OSC_CLK 32000000UL
|
||||
|
||||
#define JPG_NUM 2
|
||||
|
||||
#define CPU_CYCLE_VALUE() csi_coret_get_value()
|
||||
#define IS_DCACHE_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
|
||||
#define IS_PSRAM_ADDR(addr) ((uint32_t)(addr) >= PSRAM_BASE && (uint32_t)(addr) < PSRAM_END_ADDR)
|
||||
#define IS_FLASH_ADDR(addr) ((uint32_t)(addr) >= FLASH_BASE && (uint32_t)(addr) < FLASH_END_BASE)
|
||||
#define IS_SRAM_ADDR(addr) ((uint32_t)(addr) >= SRAM_BASE && (uint32_t)(addr) < PSRAM_BASE)
|
||||
|
||||
typedef struct {
|
||||
uint32_t crc32;
|
||||
volatile uint8 cpu1_ready;
|
||||
volatile uint8 soft_int_pending;
|
||||
uint8_t print_level;
|
||||
uint8_t disable_print:1, dcache_maint_en:1, afh_en:1, rev:5;
|
||||
uint8_t vif_maxcnt;
|
||||
uint8_t bss_maxcnt;
|
||||
uint16_t dbg_flags;
|
||||
uint16_t sta_maxcnt;
|
||||
uint16_t bss_lifetime;
|
||||
uint32_t dbg_uart_dev;
|
||||
uint32_t m2m_dma_dev;
|
||||
uint32_t wdt1_to;
|
||||
void * wdt1_irq_hdl;
|
||||
uint32_t adc_dev;
|
||||
uint32_t cpu_clk;
|
||||
uint32_t rxbuf_addr;
|
||||
uint32_t rxbuf_size;
|
||||
uint32_t heap_addr;
|
||||
uint32_t heap_size;
|
||||
uint32_t skbpool_addr;
|
||||
uint32_t skbpool_size;
|
||||
uint32_t skbpool_flag;
|
||||
uint32_t heap_flag;
|
||||
uint32_t afh_chan_mask;
|
||||
uint32_t psram_rsv_addr_core0;
|
||||
|
||||
} txw82x_CoreSetting;
|
||||
#define CoreSetting ((txw82x_CoreSetting *) CORESETTING_BASE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user