810 lines
21 KiB
C
810 lines
21 KiB
C
//#include "fm15l0xx_ll_spi.h"
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#include "../include/READER.h"
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#include "../include/READER_REG.h"
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#include <stdio.h>
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#include "../include/rfid_main.h"
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struct picc_a_struct PICC_A;
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struct picc_b_struct PICC_B;
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struct picc_v_struct PICC_V;
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struct picc_f_struct PICC_F;
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void DelayMs( uint32_t xms );
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void DelayUs( uint32_t xus );
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void DelayUs( uint32_t xus )
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{
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int t;
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while ( xus-- )
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{
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t = 5;
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while ( t-- )
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;
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}
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}
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void DelayMs( uint32_t xms )
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{
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DelayUs( xms * 1000 );
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}
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// void Reader_GPIO_Init( void )
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// {
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/******** 重做GPIO初始化 **********/
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// // LL_GPIO_SetPinMode( PD_GPIO, PD_PIN, LL_GPIO_PINxMODE_OUTPUT );//PA7 PD
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// //LL_GPIO_EnablePinPullUp( SPI_GPIO, SCK_PIN | MOSI_PIN ); // Enable Pullup
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// //xtell注释
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// // LL_GPIO_SetPinMode( SPI_GPIO, SCK_PIN, LL_GPIO_PINxMODE_OUTPUT ); // PB1 Digital function - SPI1 SCK
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// // LL_GPIO_SetPinMode( SPI_GPIO, MISO_PIN, LL_GPIO_PINxMODE_INPUT ); // PB2 Digital function - SPI1 MISO1
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// // LL_GPIO_SetPinMode( SPI_GPIO, MOSI_PIN, LL_GPIO_PINxMODE_OUTPUT ); // PB3 Digital function - SPI1 MOSI
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// LL_GPIO_SetPinMode(); //xtell
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// SCK_0;
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// MOSI_0;
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//
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// LL_GPIO_SetPinMode(); //xtell
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// //xtell注释
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// // LL_GPIO_SetPinMode( SPI_GPIO, NSS_PIN, LL_GPIO_PINxMODE_OUTPUT ); // PB0 Digital function - SPI1 NSS1
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// PD_0;
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// NSS_1;
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// }
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// unsigned char FM176XX_HardReset(void)
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// {
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/*************NFC 硬件初始化 重做********************/
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// unsigned char reg_data;
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// NSS_1;//NSS = 1
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// PD_1;//RST = 1
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// DelayMs(1);
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// PD_0;//RST = 0
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// DelayMs(1);
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// GetReg(REG_COMMAND,®_data);
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// if (reg_data != 0x40)
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// return FAIL;
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// return SUCCESS;
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// }
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// unsigned char Reader_Set_HPD( unsigned char mode ) //mode = DISABLE <20>˳<EFBFBD>HPDģʽ <20><>mode = ENABLE <20><><EFBFBD><EFBFBD>HPDģʽ
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// {
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// if ( mode == ENABLE )
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// {
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// DelayMs( 1 ); //<2F><>ʱ1ms
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// /******设置一个GPIO输出高*******xtell******/
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// //PD_1; // PD = 1
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// P34 = 1;
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// }
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// else
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// {
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// /******设置一个GPIO输出低*************/
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// //PD_0; //PD = 0
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// P34 =0;
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// DelayMs( 1 ); //<2F><>ʱ1ms<6D><73><EFBFBD>ȴ<EFBFBD>Reader<65><72><EFBFBD><EFBFBD>
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// }
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// return (mode);
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// }
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//***********************************************
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƣ<EFBFBD>GetReg(unsigned char addr,unsigned char *regdata)
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>ֵ
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//<2F><>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>addr:Ŀ<><C4BF>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ regdata:<3A><>ȡ<EFBFBD><C8A1>ֵ
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//<2F><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>unsigned char TRUE<55><45><EFBFBD><EFBFBD>ȡ<EFBFBD>ɹ<EFBFBD> FALSE:ʧ<><CAA7>
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//***********************************************
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// 从FM17660 读取数据时，BIT7 置 1
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// unsigned char GetReg(unsigned char address,unsigned char *reg_data)
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// {
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// unsigned char spi_data,i;
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// NSS_0; //NSS = 0;
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// spi_data = (address << 1) | 0x01;
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// for(i=0;i<8;i++)
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// {
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// if(spi_data & 0x80)
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// MOSI_1;
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// else
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// MOSI_0;
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// SCK_1;
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// spi_data = spi_data<<1;
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// SCK_0;
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// }
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// MOSI_0;
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// *reg_data = 0;
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// for(i=0;i<8;i++)
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// {
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// *reg_data = *reg_data<<1;
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// SCK_1;
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// if(LL_GPIO_ReadInputPort(SPI_GPIO)& MISO_PIN)
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// *reg_data = *reg_data | 0x01;
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// SCK_0;
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// }
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// NSS_1; //NSS = 1;
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// return SUCCESS;
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// }
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//***********************************************
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƣ<EFBFBD>SetReg(unsigned char addr,unsigned char* regdata)
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD>д<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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//<2F><>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>addr:Ŀ<><C4BF>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ regdata:Ҫд<D2AA><D0B4><EFBFBD>ֵ
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//<2F><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>unsigned char TRUE<55><45>д<EFBFBD>ɹ<EFBFBD> FALSE:дʧ<D0B4><CAA7>
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//***********************************************
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// unsigned char SetReg(unsigned char address,unsigned char reg_data)
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// {
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// unsigned char spi_data,i;
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// NSS_0; //NSS = 0;
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// spi_data = (address << 1) & 0xFE;
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// for(i=0;i<8;i++)
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// {
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// if(spi_data & 0x80)
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// MOSI_1;
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// else
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// MOSI_0;
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// SCK_1;
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// spi_data = spi_data<<1;
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// SCK_0;
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// }
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// MOSI_0;
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// spi_data = reg_data;
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// for(i=0;i<8;i++)
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// {
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// if(spi_data & 0x80)
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// MOSI_1;
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// else
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// MOSI_0;
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// SCK_1;
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// spi_data = spi_data<<1;
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// SCK_0;
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// }
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// SCK_0;
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// MOSI_0;
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// NSS_1; //NSS = 1;
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// return SUCCESS;
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// }
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void ModifyReg( unsigned char reg_address, unsigned char mask, unsigned char set )
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{
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unsigned char reg_data;
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// Uart1SendString(" ModifyReg begin ");
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GetReg( reg_address, ®_data );
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if ( set )
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{
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reg_data |= mask;
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}
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else
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{
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reg_data &= ~mask;
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}
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SetReg( reg_address, reg_data );
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return;
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}
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unsigned char SetCommand(unsigned char command)
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{
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unsigned char result;
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result = SetReg(REG_COMMAND,CMD_MASK & command);
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return result;
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}
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void SetTimer(unsigned int timeout) //
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{
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unsigned long prescale = 1;
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unsigned long t,fc;
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fc = timeout*13560;
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t = fc;
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while(fc > 65535)
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{
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prescale*=2;
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fc = t/prescale;
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if(fc*prescale != t)
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fc++;
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}
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if(prescale>1)
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{
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SetReg(REG_T0CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | BIT_TAUTORESTARTED | VALUE_TCLK_1356_MHZ );
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SetReg(REG_T0RELOADHI,(u8)(fc>>8));
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SetReg(REG_T0RELOADLO,(u8)fc);
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SetReg(REG_T1CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | VALUE_TCLK_T0 );
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SetReg(REG_T1RELOADHI,(u8)(prescale>>8));
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SetReg(REG_T1RELOADLO,(u8)prescale);
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}
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else
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{
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SetReg(REG_T1CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | VALUE_TCLK_1356_MHZ );
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SetReg(REG_T1RELOADHI,(u8)(fc>>8));
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SetReg(REG_T1RELOADLO,(u8)fc);
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}
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}
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unsigned char SetCW(unsigned char mode)
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{
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unsigned char result;
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if(mode == ENABLE)
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{
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ModifyReg(REG_COMMAND,BIT_MODEMOFF,DISABLE);
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ModifyReg(REG_TXMODE,BIT0 | BIT1,ENABLE);
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}
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else
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{
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ModifyReg(REG_COMMAND,BIT_MODEMOFF,ENABLE);
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ModifyReg(REG_TXMODE,BIT0 | BIT1,DISABLE);
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}
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DelayMs(5);
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return result;
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}
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void Clear_FIFO(void)
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{
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unsigned char fifolength;
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GetReg(REG_FIFOLENGTH,&fifolength);
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if((fifolength) != 0) //FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><D5A3><EFBFBD>FLUSH FIFO
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{
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);
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}
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return ;
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}
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unsigned char LoadProtocol(unsigned char p_rx,unsigned char p_tx)
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{
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unsigned char reg_data = 0;
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// Uart1SendString(" LoadProtocol begin ");
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SetCommand(CMD_IDLE); //
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
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SetReg(REG_FIFODATA,p_rx);//Rx
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SetReg(REG_FIFODATA,p_tx);//Tx
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SetCommand(CMD_LOADPROTOCOL);
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DelayMs(2);
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GetReg(REG_COMMAND,®_data);
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if(reg_data != CMD_IDLE)
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return FAIL;
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return SUCCESS;
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}
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void SetParity(unsigned char state)
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{
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// Uart1SendString(" SetParity begin");
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ModifyReg(REG_FRAMECON,BIT_TXPARITYEN|BIT_RXPARITYEN,state);
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}
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unsigned char ReaderA_Initial(void)
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{
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// Uart1SendString(" ReaderA_Initial begin");
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LoadProtocol(RX_TYPEA_106,TX_TYPEA_106);
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ModifyReg(REG_TXMODE,BIT2,ENABLE);//FORCE 100ask ENABLE
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SetReg(REG_TXAMP,AMPLITUDE_A);
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SetReg(REG_TXCON,0x00);
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SetReg(REG_RXANA,(HPCF_A<<3)|GAIN_A);
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SetReg(0x5F,0x08);
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SetReg(REG_THNSET,0xFF);
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SetReg(REG_THNMIN,0xC0);
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SetReg(REG_RXTXCON,0x80);//
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SetParity(ENABLE);
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SetReg(REG_STATUS,0);//<2F><><EFBFBD>Cry1Onλ
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// Uart1SendString(" ReaderA_Initial end");
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return SUCCESS;
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}
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unsigned char ReaderB_Initial(void)
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{
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LoadProtocol(RX_TYPEB_106,TX_TYPEB_106);
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ModifyReg(REG_TXMODE,BIT2,DISABLE);//FORCE 100ask DISABLE
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SetReg(REG_TXAMP,AMPLITUDE_B);
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SetReg(REG_TXCON,MODULATION_B);
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SetReg(REG_RXANA,(HPCF_B<<3)|GAIN_B);
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SetReg(0x5F,0x08);
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SetReg(REG_THNSET,0xFF);
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SetReg(REG_THNMIN,0xC0);
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SetReg(REG_RXTXCON,0x80);//
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return SUCCESS;
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}
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unsigned char ReaderV_Initial(void)
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{
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LoadProtocol(RX_TYPEV_26,RX_TYPEV_26);
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ModifyReg(REG_RXANA,BIT3|BIT2|BIT1|BIT0,DISABLE);
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ModifyReg(REG_RXANA,(HPCF_V<<3)|GAIN_V,ENABLE);//39h
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SetParity(DISABLE);
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SetReg(REG_TXAMP,AMPLITUDE_V);
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SetReg(REG_TXCON,MODULATION_V);
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SetReg(REG_TXI,0x06);
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SetReg(REG_THNSET,0xFF);
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SetReg(REG_THNMIN,0x80);
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SetReg(REG_THNADJ,0x08);
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SetReg(REG_RXTXCON,0);
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return SUCCESS;
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}
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unsigned char ReaderF_Initial(void)
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{
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ModifyReg(REG_MISC, 0x04,ENABLE);
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LoadProtocol(RX_FELICA_212,TX_FELICA_212);
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SetReg(REG_TXAMP,AMPLITUDE_F); //
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SetReg(REG_TXCON,MODULATION_F);
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ModifyReg(REG_RXANA,BIT3|BIT2|BIT1|BIT0,DISABLE);
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ModifyReg(REG_RXANA,(HPCF_F<<3)|GAIN_F,ENABLE);//39h
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SetParity(DISABLE);
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SetReg(REG_THNSET,0xFF);
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SetReg(REG_THNMIN,0x80);
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SetReg(REG_THNADJ,0x08);
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ModifyReg(REG_MISC, 0x04,DISABLE);
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return SUCCESS;
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}
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unsigned char ReaderA_Wakeeup(struct picc_a_struct *picc_a)
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{
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unsigned char reg_data;
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SetCommand(CMD_IDLE);
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SetReg(REG_TXDATANUM,0x0F);
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
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SetReg(REG_FIFODATA,RF_CMD_WUPA);
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ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
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ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
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SetCommand(CMD_TRANSCEIVE);
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DelayMs(2);
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GetReg(REG_FIFOLENGTH,®_data);
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if(reg_data != 2)
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return FAIL;
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GetReg(REG_FIFODATA,&picc_a->ATQA[0]);
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GetReg(REG_FIFODATA,&picc_a->ATQA[1]);
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return SUCCESS;
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}
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unsigned char ReaderA_Request(struct picc_a_struct *picc_a)
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{
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unsigned char reg_data;
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SetCommand(CMD_IDLE);
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SetReg(REG_TXDATANUM,0x0F);
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
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SetReg(REG_FIFODATA,RF_CMD_REQA);
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ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
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ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
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SetCommand(CMD_TRANSCEIVE);
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// DelayMs(2);
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Delay1ms();
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Delay1ms();
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GetReg(REG_FIFOLENGTH,®_data);
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// Uart1SendString("REG_FIFOLENGTH data=");
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// printHex(reg_data);
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if(reg_data != 2)
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return FAIL;
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GetReg(REG_FIFODATA,&picc_a->ATQA[0]);
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GetReg(REG_FIFODATA,&picc_a->ATQA[1]);
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return SUCCESS;
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}
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unsigned char ReaderA_Anticoll(struct picc_a_struct *picc_a)
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{
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unsigned char reg_data;
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SetCommand(CMD_IDLE);
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SetReg(REG_TXDATANUM,0x08);
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
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SetReg(REG_FIFODATA,RF_CMD_ANTICOLL[picc_a->CASCADE_LEVEL]);
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SetReg(REG_FIFODATA,0x20);
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ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
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ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
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SetCommand(CMD_TRANSCEIVE);
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DelayMs(2);
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GetReg(REG_FIFOLENGTH,®_data);
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if(reg_data != 5)
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return FAIL;
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GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4]);
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GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+1]);
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GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+2]);
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GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+3]);
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GetReg(REG_FIFODATA,&picc_a->BCC[picc_a->CASCADE_LEVEL]);
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if( (picc_a->UID[picc_a->CASCADE_LEVEL*4] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+1] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+2] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+3]) == picc_a->BCC[picc_a->CASCADE_LEVEL])
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return SUCCESS;
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return FAIL;
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}
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unsigned char ReaderA_Select(struct picc_a_struct *picc_a)
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{
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unsigned char reg_data;
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SetCommand(CMD_IDLE);
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SetReg(REG_TXDATANUM,0x08);
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ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
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SetReg(REG_FIFODATA,RF_CMD_ANTICOLL[picc_a->CASCADE_LEVEL]);
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SetReg(REG_FIFODATA,0x70);
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SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4]);
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SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+1]);
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SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+2]);
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SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+3]);
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SetReg(REG_FIFODATA,picc_a->BCC[picc_a->CASCADE_LEVEL]);
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ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
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ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
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SetCommand(CMD_TRANSCEIVE);
|
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DelayMs(2);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 1)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,&picc_a->SAK [picc_a->CASCADE_LEVEL]);
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
|
||
unsigned char ReaderA_CardActivate(struct picc_a_struct *picc_a)
|
||
{
|
||
unsigned char result,cascade_level;
|
||
result = ReaderA_Request(picc_a);//
|
||
if (result != SUCCESS)
|
||
return result;
|
||
|
||
if ((picc_a->ATQA[0]&0xC0)==0x00) //1<><31>UID
|
||
{
|
||
cascade_level = 1;
|
||
picc_a->UID_Length = 4;
|
||
}
|
||
if ((picc_a->ATQA[0]&0xC0)==0x40) //2<><32>UID
|
||
{
|
||
cascade_level = 2;
|
||
picc_a->UID_Length = 8;
|
||
}
|
||
if ((picc_a->ATQA[0]&0xC0)==0x80) //3<><33>UID
|
||
{
|
||
cascade_level = 3;
|
||
picc_a->UID_Length = 12;
|
||
}
|
||
for (picc_a->CASCADE_LEVEL = 0; picc_a->CASCADE_LEVEL < cascade_level; picc_a->CASCADE_LEVEL++)
|
||
{
|
||
result = ReaderA_Anticoll(picc_a);//
|
||
if (result != SUCCESS)
|
||
return result;
|
||
|
||
result = ReaderA_Select(picc_a);//
|
||
if (result != SUCCESS)
|
||
return result;
|
||
}
|
||
picc_a->CASCADE_LEVEL--;
|
||
return result;
|
||
}
|
||
|
||
|
||
unsigned char ReaderB_Wakeup(struct picc_b_struct *picc_b)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x05); //APf
|
||
SetReg(REG_FIFODATA, 0x00); //AFI (00:for all cards)
|
||
SetReg(REG_FIFODATA, 0x08); //PARAM(REQB,Number of slots =0)
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)//<2F>жϴ<D0B6><CFB4><EFBFBD><EFBFBD>־
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 12)//<2F>жϽ<D0B6><CFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||
return FAIL;
|
||
for(i=0;i<12;i++)
|
||
GetReg(REG_FIFODATA,&picc_b->ATQB [i]);
|
||
memcpy(picc_b->PUPI,picc_b->ATQB + 1,4);
|
||
memcpy(picc_b->APPLICATION_DATA,picc_b->ATQB + 6,4);
|
||
memcpy(picc_b->PROTOCOL_INF,picc_b->ATQB + 10,3);
|
||
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
unsigned char ReaderB_Request(struct picc_b_struct *picc_b)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x05); //APf
|
||
SetReg(REG_FIFODATA, 0x00); //AFI (00:for all cards)
|
||
SetReg(REG_FIFODATA, 0x00); //PARAM(REQB,Number of slots =0)
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 12)
|
||
return FAIL;
|
||
for(i=0;i<12;i++)
|
||
GetReg(REG_FIFODATA,&picc_b->ATQB [i]);
|
||
memcpy(picc_b->PUPI,picc_b->ATQB + 1,4);
|
||
memcpy(picc_b->APPLICATION_DATA,picc_b->ATQB + 6,4);
|
||
memcpy(picc_b->PROTOCOL_INF,picc_b->ATQB + 10,3);
|
||
return SUCCESS;
|
||
}
|
||
|
||
unsigned char ReaderB_Attrib(struct picc_b_struct *picc_b)
|
||
{
|
||
unsigned char reg_data;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x1D); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[0]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[1]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[2]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[3]); //
|
||
SetReg(REG_FIFODATA, 0x00); //Param1
|
||
SetReg(REG_FIFODATA, 0x08); //Param2 BIT0~BIT3 Frame Size 0 = 16, 1 = 24, 2 = 32, 3 = 40, 4 = 48, 5 = 64, 6 = 96, 7 = 128, 8 = 256
|
||
//Param2 BIT4~BIT5 TX BaudRate BIT6~BIT7 RX BaudRate,00 = 106Kbps, 01 = 212Kbps, 10 = 424Kbps, 11 = 848Kbps
|
||
SetReg(REG_FIFODATA, 0x01); //COMPATIBLE WITH 14443-4
|
||
SetReg(REG_FIFODATA, 0x01); //CID:01
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 1)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,®_data);
|
||
picc_b->CID = reg_data & 0x0F;
|
||
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
unsigned char ReaderB_Halt(struct picc_b_struct *picc_b)
|
||
{
|
||
unsigned char reg_data;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x50); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[0]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[1]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[2]); //
|
||
SetReg(REG_FIFODATA, picc_b->PUPI[3]); //
|
||
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 1)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,®_data);
|
||
*picc_b->Answer_to_HALT = reg_data & 0x0F;
|
||
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
unsigned char ReaderB_Get_SN(struct picc_b_struct *picc_b)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x00); //
|
||
SetReg(REG_FIFODATA, 0x36); //
|
||
SetReg(REG_FIFODATA, 0x00); //
|
||
SetReg(REG_FIFODATA, 0x00); //
|
||
SetReg(REG_FIFODATA, 0x08); //
|
||
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 10)
|
||
return FAIL;
|
||
for(i=0;i<8;i++)
|
||
GetReg(REG_FIFODATA,&picc_b->SN[i]);
|
||
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
unsigned char ReaderV_Inventory(struct picc_v_struct *picc_v)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x26); //
|
||
SetReg(REG_FIFODATA, 0x01);
|
||
SetReg(REG_FIFODATA, 0x00);
|
||
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 10)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,&picc_v->RESPONSE );
|
||
GetReg(REG_FIFODATA,®_data);
|
||
for(i = 0;i < 8; i++)
|
||
{
|
||
GetReg(REG_FIFODATA,&picc_v->UID[i]);
|
||
}
|
||
return SUCCESS;
|
||
}
|
||
|
||
unsigned char ReaderV_Select(struct picc_v_struct *picc_v)
|
||
{
|
||
unsigned char reg_data;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA, 0x22);
|
||
SetReg(REG_FIFODATA, 0x25); //
|
||
SetReg(REG_FIFODATA, picc_v->UID[0]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[1]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[2]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[3]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[4]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[5]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[6]);
|
||
SetReg(REG_FIFODATA, picc_v->UID[7]);
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 1)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,&picc_v->RESPONSE );
|
||
return SUCCESS;
|
||
}
|
||
|
||
unsigned char ReaderV_ReadSingleBlock(unsigned char block_num,struct picc_v_struct *picc_v)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA,0x12);
|
||
SetReg(REG_FIFODATA, 0x20); //
|
||
SetReg(REG_FIFODATA, block_num);
|
||
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 5)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,&picc_v->RESPONSE );
|
||
for(i = 0;i < 4; i++)
|
||
{
|
||
GetReg(REG_FIFODATA,&picc_v->BLOCK_DATA[i]);
|
||
}
|
||
return SUCCESS;
|
||
}
|
||
|
||
|
||
|
||
unsigned char ReaderV_WriteSingleBlock(unsigned char block_num,struct picc_v_struct *picc_v)
|
||
{
|
||
unsigned char reg_data;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
SetReg(REG_FIFODATA,0x02);
|
||
SetReg(REG_FIFODATA, 0x21); //
|
||
SetReg(REG_FIFODATA, block_num);
|
||
SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[0]);
|
||
SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[1]);
|
||
SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[2]);
|
||
SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[3]);
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 1)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,&picc_v->RESPONSE );
|
||
|
||
return SUCCESS;
|
||
}
|
||
|
||
unsigned char ReaderF_Inventory(struct picc_f_struct *picc_f)
|
||
{
|
||
unsigned char reg_data,i;
|
||
SetCommand(CMD_IDLE);
|
||
SetReg(REG_TXDATANUM,0x08);
|
||
ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE); //Clear FIFO
|
||
|
||
SetReg(REG_FIFODATA, 0x06);
|
||
SetReg(REG_FIFODATA, 0x00); //
|
||
SetReg(REG_FIFODATA, 0xFF);
|
||
SetReg(REG_FIFODATA, 0xFF);
|
||
SetReg(REG_FIFODATA, 0x10);
|
||
SetReg(REG_FIFODATA, 0x00);
|
||
|
||
ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
|
||
ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
|
||
|
||
SetCommand(CMD_TRANSCEIVE);
|
||
DelayMs(10);
|
||
GetReg(REG_ERROR,®_data);
|
||
if((reg_data & 0x0F)!=0)
|
||
return FAIL;
|
||
GetReg(REG_FIFOLENGTH,®_data);
|
||
if(reg_data != 18)
|
||
return FAIL;
|
||
GetReg(REG_FIFODATA,®_data);
|
||
GetReg(REG_FIFODATA,®_data);
|
||
for(i = 0;i < 8; i++)
|
||
{
|
||
GetReg(REG_FIFODATA,&picc_f->UID[i]);
|
||
}
|
||
return SUCCESS;
|
||
|
||
}
|
||
|
||
|
||
|
||
|