//#include "fm15l0xx_ll_spi.h"
#include "../include/READER.h"
#include "../include/READER_REG.h"
#include <stdio.h>
#include "../include/rfid_main.h"


struct picc_a_struct PICC_A; 
struct picc_b_struct PICC_B;
struct picc_v_struct PICC_V;
struct picc_f_struct PICC_F;
void DelayMs( uint32_t xms );
void DelayUs( uint32_t xus );
void DelayUs( uint32_t xus )
{
    int t;

    while ( xus-- )
    {
        t = 5;
        while ( t-- )
            ;
    }
}


void DelayMs( uint32_t xms )
{
    DelayUs( xms * 1000 );
}


// void Reader_GPIO_Init( void )
// {
		/********  	重做GPIO初始化   **********/
	
	
//		// LL_GPIO_SetPinMode( PD_GPIO, PD_PIN, LL_GPIO_PINxMODE_OUTPUT );//PA7 PD


//    //LL_GPIO_EnablePinPullUp( SPI_GPIO, SCK_PIN | MOSI_PIN );       // Enable Pullup

//	//xtell注释
//	//   LL_GPIO_SetPinMode( SPI_GPIO, SCK_PIN, LL_GPIO_PINxMODE_OUTPUT );                // PB1 Digital function - SPI1 SCK
//    // LL_GPIO_SetPinMode( SPI_GPIO, MISO_PIN, LL_GPIO_PINxMODE_INPUT );                // PB2 Digital function - SPI1 MISO1
//    // LL_GPIO_SetPinMode( SPI_GPIO, MOSI_PIN, LL_GPIO_PINxMODE_OUTPUT );                // PB3 Digital function - SPI1 MOSI
//	LL_GPIO_SetPinMode();	//xtell 
//		SCK_0;
//		MOSI_0;
//    
//		LL_GPIO_SetPinMode();	//xtell 
//		//xtell注释
//		// LL_GPIO_SetPinMode( SPI_GPIO, NSS_PIN, LL_GPIO_PINxMODE_OUTPUT );                // PB0 Digital function - SPI1 NSS1
//		PD_0;	
//		NSS_1;
// }

// unsigned char FM176XX_HardReset(void)
// {	
	
	/*************NFC 硬件初始化 重做********************/
	
//	unsigned char reg_data;
//	NSS_1;//NSS = 1
//	PD_1;//RST = 1	
//	DelayMs(1);		
//	PD_0;//RST = 0	
//	DelayMs(1);
//	GetReg(REG_COMMAND,&reg_data);
//	if (reg_data != 0x40)
//		return FAIL;
//  	return SUCCESS;
// }

// unsigned char Reader_Set_HPD( unsigned char mode )                                            //mode = DISABLE �˳�HPDģʽ ��mode = ENABLE ����HPDģʽ
// {
//     if ( mode == ENABLE )
//     {
//         DelayMs( 1 );                                                       //��ʱ1ms
       
// 			/******设置一个GPIO输出高*******xtell******/
// 			//PD_1;      // PD = 1
// 			P34 = 1;
				
//     }
//     else
//     {
//        	/******设置一个GPIO输出低*************/
// 		//PD_0;	//PD = 0
// 		P34 =0;
//         DelayMs( 1 );                                                       //��ʱ1ms���ȴ�Reader����
//     }
//     return (mode);
// }




//***********************************************
//�������ƣ�GetReg(unsigned char addr,unsigned char *regdata)
//�������ܣ���ȡ�Ĵ���ֵ
//��ڲ�����addr:Ŀ��Ĵ�����ַ   regdata:��ȡ��ֵ
//���ڲ�����unsigned char  TRUE����ȡ�ɹ�   FALSE:ʧ��
//***********************************************

// 从FM17660 读取数据时，BIT7 置 1
// unsigned char GetReg(unsigned char address,unsigned char *reg_data)
// {	
// unsigned char spi_data,i;
// 		NSS_0;	//NSS = 0;
// 		spi_data = (address << 1) | 0x01;	  

// 		for(i=0;i<8;i++)
// 			{				
// 				if(spi_data & 0x80)
// 					MOSI_1;
// 				else
// 					MOSI_0;
// 				SCK_1;
// 				spi_data = spi_data<<1;
// 				SCK_0;
// 			}
			
// 			MOSI_0;
// 			*reg_data = 0;
// 		for(i=0;i<8;i++)
// 			{
// 				*reg_data = *reg_data<<1;
// 				SCK_1;
				
// 				if(LL_GPIO_ReadInputPort(SPI_GPIO)& MISO_PIN)
// 					*reg_data = *reg_data | 0x01;						
// 				SCK_0;		
// 			}

// 		NSS_1;	//NSS = 1;	
// 	return SUCCESS;
// }

//***********************************************
//�������ƣ�SetReg(unsigned char addr,unsigned char* regdata)
//�������ܣ�д�Ĵ���
//��ڲ�����addr:Ŀ��Ĵ�����ַ   regdata:Ҫд���ֵ
//���ڲ�����unsigned char  TRUE��д�ɹ�   FALSE:дʧ��
//***********************************************
// unsigned char SetReg(unsigned char address,unsigned char reg_data)
// {	
// 		unsigned char spi_data,i;
// 			NSS_0;	//NSS = 0;
// 			spi_data = (address << 1) & 0xFE;	 	   
	
// 			for(i=0;i<8;i++)
// 			{
				
// 				if(spi_data & 0x80)
// 					MOSI_1;
// 				else
// 					MOSI_0;
// 				SCK_1;
// 				spi_data = spi_data<<1;
// 				SCK_0;
// 			}
// 			MOSI_0;
// 			spi_data = reg_data;
// 			for(i=0;i<8;i++)
// 			{		
// 				if(spi_data & 0x80)
// 					MOSI_1;
// 				else
// 					MOSI_0;
// 				SCK_1;
// 				spi_data = spi_data<<1;
// 				SCK_0;
// 			}
// 			SCK_0;
// 			MOSI_0;
// 			NSS_1;	//NSS = 1;
	
// 	return SUCCESS;
// }

void ModifyReg( unsigned char reg_address, unsigned char mask, unsigned char set )
{
    unsigned char reg_data;
	// Uart1SendString(" ModifyReg begin ");

    GetReg( reg_address, &reg_data );

    if ( set )
    {
        reg_data |= mask;
    }
    else
    {
        reg_data &= ~mask;
    }

    SetReg( reg_address, reg_data );
    return;
}

unsigned char SetCommand(unsigned char command)
{
	unsigned char result;
	result = SetReg(REG_COMMAND,CMD_MASK & command);
	return result;
}

void SetTimer(unsigned int timeout)	//
{
    unsigned long prescale = 1;
    unsigned long t,fc;
		fc = timeout*13560;
    t = fc;

    while(fc > 65535)
    {
        prescale*=2;
        fc = t/prescale;
        if(fc*prescale != t)
            fc++;
    }
	
	if(prescale>1)
	{
		SetReg(REG_T0CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | BIT_TAUTORESTARTED | VALUE_TCLK_1356_MHZ );
		SetReg(REG_T0RELOADHI,(u8)(fc>>8));
		SetReg(REG_T0RELOADLO,(u8)fc);	

		SetReg(REG_T1CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | VALUE_TCLK_T0 );
		SetReg(REG_T1RELOADHI,(u8)(prescale>>8));
		SetReg(REG_T1RELOADLO,(u8)prescale);	
	}
	else
	{		
		SetReg(REG_T1CONTROL, BIT_TSTOP_RX | BIT_TSTART_TX | VALUE_TCLK_1356_MHZ );
		SetReg(REG_T1RELOADHI,(u8)(fc>>8));
		SetReg(REG_T1RELOADLO,(u8)fc);	
	}
	
}

unsigned char SetCW(unsigned char mode)
{
	unsigned char result;
	if(mode == ENABLE)
		{
	    ModifyReg(REG_COMMAND,BIT_MODEMOFF,DISABLE);
		ModifyReg(REG_TXMODE,BIT0 | BIT1,ENABLE);
		}
		else
		{
	    ModifyReg(REG_COMMAND,BIT_MODEMOFF,ENABLE);
		ModifyReg(REG_TXMODE,BIT0 | BIT1,DISABLE);		
		}
		DelayMs(5);
		return result;
}

void Clear_FIFO(void)
{
	unsigned char fifolength;
		
	GetReg(REG_FIFOLENGTH,&fifolength);
	if((fifolength) != 0)			//FIFO������գ���FLUSH FIFO
	{
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);
	}
	return ;
}

unsigned char LoadProtocol(unsigned char p_rx,unsigned char p_tx)
{
	unsigned char reg_data = 0;
	// Uart1SendString(" LoadProtocol begin ");
	SetCommand(CMD_IDLE);					//
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO	
	SetReg(REG_FIFODATA,p_rx);//Rx
	SetReg(REG_FIFODATA,p_tx);//Tx

	SetCommand(CMD_LOADPROTOCOL);
	DelayMs(2);	
	GetReg(REG_COMMAND,&reg_data);
	if(reg_data != CMD_IDLE)
		return FAIL;
	return SUCCESS;
}

void SetParity(unsigned char state)
{	
    // Uart1SendString(" SetParity begin");
	ModifyReg(REG_FRAMECON,BIT_TXPARITYEN|BIT_RXPARITYEN,state);
}

unsigned char ReaderA_Initial(void)
{
	
    // Uart1SendString(" ReaderA_Initial begin");
	LoadProtocol(RX_TYPEA_106,TX_TYPEA_106);
	ModifyReg(REG_TXMODE,BIT2,ENABLE);//FORCE 100ask  ENABLE
	SetReg(REG_TXAMP,AMPLITUDE_A);
	SetReg(REG_TXCON,0x00);
	SetReg(REG_RXANA,(HPCF_A<<3)|GAIN_A);
	SetReg(0x5F,0x08);
	SetReg(REG_THNSET,0xFF);
	SetReg(REG_THNMIN,0xC0);
	SetReg(REG_RXTXCON,0x80);//	
	SetParity(ENABLE);
	SetReg(REG_STATUS,0);//���Cry1Onλ
	
    // Uart1SendString(" ReaderA_Initial end");
	return SUCCESS;
}


unsigned char ReaderB_Initial(void)
{
	LoadProtocol(RX_TYPEB_106,TX_TYPEB_106);

	ModifyReg(REG_TXMODE,BIT2,DISABLE);//FORCE 100ask  DISABLE
	SetReg(REG_TXAMP,AMPLITUDE_B);
	SetReg(REG_TXCON,MODULATION_B);
	SetReg(REG_RXANA,(HPCF_B<<3)|GAIN_B);
	SetReg(0x5F,0x08);
	SetReg(REG_THNSET,0xFF);
	SetReg(REG_THNMIN,0xC0);
	SetReg(REG_RXTXCON,0x80);//
	return SUCCESS;
}


unsigned char ReaderV_Initial(void)
{
	LoadProtocol(RX_TYPEV_26,RX_TYPEV_26);
	ModifyReg(REG_RXANA,BIT3|BIT2|BIT1|BIT0,DISABLE);
	ModifyReg(REG_RXANA,(HPCF_V<<3)|GAIN_V,ENABLE);//39h
	SetParity(DISABLE);
	SetReg(REG_TXAMP,AMPLITUDE_V);	
	SetReg(REG_TXCON,MODULATION_V);
	SetReg(REG_TXI,0x06);
	SetReg(REG_THNSET,0xFF);
	SetReg(REG_THNMIN,0x80);
	SetReg(REG_THNADJ,0x08);
	SetReg(REG_RXTXCON,0);

	return SUCCESS;
}

unsigned char ReaderF_Initial(void)
{
	ModifyReg(REG_MISC, 0x04,ENABLE);
	LoadProtocol(RX_FELICA_212,TX_FELICA_212);
	SetReg(REG_TXAMP,AMPLITUDE_F);				//
  SetReg(REG_TXCON,MODULATION_F);
	ModifyReg(REG_RXANA,BIT3|BIT2|BIT1|BIT0,DISABLE);
	ModifyReg(REG_RXANA,(HPCF_F<<3)|GAIN_F,ENABLE);//39h
	SetParity(DISABLE);
	SetReg(REG_THNSET,0xFF);
	SetReg(REG_THNMIN,0x80);
	SetReg(REG_THNADJ,0x08);
	ModifyReg(REG_MISC, 0x04,DISABLE);
	return SUCCESS;
}

unsigned char ReaderA_Wakeeup(struct picc_a_struct *picc_a)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x0F);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO
	SetReg(REG_FIFODATA,RF_CMD_WUPA);
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(2);	
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 2)
		return FAIL;
	
	GetReg(REG_FIFODATA,&picc_a->ATQA[0]);
	GetReg(REG_FIFODATA,&picc_a->ATQA[1]);
	
	return SUCCESS;
}

unsigned char ReaderA_Request(struct picc_a_struct *picc_a)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x0F);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO
	SetReg(REG_FIFODATA,RF_CMD_REQA);
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
	ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
	SetCommand(CMD_TRANSCEIVE);	
	// DelayMs(2);	
	Delay1ms();	
	Delay1ms();	
	GetReg(REG_FIFOLENGTH,&reg_data);
	// Uart1SendString("REG_FIFOLENGTH data=");
	// printHex(reg_data);
	if(reg_data != 2)
		return FAIL;
	
	GetReg(REG_FIFODATA,&picc_a->ATQA[0]);
	GetReg(REG_FIFODATA,&picc_a->ATQA[1]);
	
	return SUCCESS;
}

unsigned char ReaderA_Anticoll(struct picc_a_struct *picc_a)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO
	SetReg(REG_FIFODATA,RF_CMD_ANTICOLL[picc_a->CASCADE_LEVEL]);
	SetReg(REG_FIFODATA,0x20);
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,DISABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,DISABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(2);	
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 5)
		return FAIL;
	
	GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4]);
	GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+1]);
	GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+2]);
	GetReg(REG_FIFODATA,&picc_a->UID[picc_a->CASCADE_LEVEL*4+3]);
	GetReg(REG_FIFODATA,&picc_a->BCC[picc_a->CASCADE_LEVEL]);
	if( (picc_a->UID[picc_a->CASCADE_LEVEL*4] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+1] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+2] ^ picc_a->UID[picc_a->CASCADE_LEVEL*4+3]) == picc_a->BCC[picc_a->CASCADE_LEVEL])
			return SUCCESS;
	
	return FAIL;	
}

unsigned char ReaderA_Select(struct picc_a_struct *picc_a)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA,RF_CMD_ANTICOLL[picc_a->CASCADE_LEVEL]);
	SetReg(REG_FIFODATA,0x70);
	SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4]);
	SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+1]);
	SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+2]);
	SetReg(REG_FIFODATA,picc_a->UID[picc_a->CASCADE_LEVEL*4+3]);
	SetReg(REG_FIFODATA,picc_a->BCC[picc_a->CASCADE_LEVEL]);
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(2);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 1)
		return FAIL;
  GetReg(REG_FIFODATA,&picc_a->SAK [picc_a->CASCADE_LEVEL]);		
	return SUCCESS;
	
}


unsigned char ReaderA_CardActivate(struct picc_a_struct *picc_a)
{
unsigned char  result,cascade_level;	
		result = ReaderA_Request(picc_a);//
		if (result != SUCCESS)
			return result;
				
			if 	((picc_a->ATQA[0]&0xC0)==0x00)	//1��UID
			{
					cascade_level = 1;
					picc_a->UID_Length = 4;			
			}
			if 	((picc_a->ATQA[0]&0xC0)==0x40)	//2��UID		
			{
					cascade_level = 2;
					picc_a->UID_Length = 8;				
			}
			if 	((picc_a->ATQA[0]&0xC0)==0x80)	//3��UID
			{
					cascade_level = 3;	
					picc_a->UID_Length = 12;
			}
			for (picc_a->CASCADE_LEVEL = 0; picc_a->CASCADE_LEVEL < cascade_level; picc_a->CASCADE_LEVEL++)
				{
						result = ReaderA_Anticoll(picc_a);//
						if (result != SUCCESS)
							return result;
						
						result = ReaderA_Select(picc_a);//
						if (result != SUCCESS)
							return result;
				}						
			picc_a->CASCADE_LEVEL--;
		return result;
}


unsigned char ReaderB_Wakeup(struct picc_b_struct *picc_b)
{
	unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x05);  //APf
	SetReg(REG_FIFODATA, 0x00);   //AFI (00:for all cards)
	SetReg(REG_FIFODATA, 0x08);   //PARAM(REQB,Number of slots =0)
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)//�жϴ����־
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 12)//�жϽ������ݳ���
		return FAIL;
	for(i=0;i<12;i++)
		GetReg(REG_FIFODATA,&picc_b->ATQB [i]);	
	memcpy(picc_b->PUPI,picc_b->ATQB + 1,4);
	memcpy(picc_b->APPLICATION_DATA,picc_b->ATQB + 6,4);
	memcpy(picc_b->PROTOCOL_INF,picc_b->ATQB + 10,3);
	
	return SUCCESS;

}

unsigned char ReaderB_Request(struct picc_b_struct *picc_b)
{
		unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x05);  //APf
	SetReg(REG_FIFODATA, 0x00);   //AFI (00:for all cards)
	SetReg(REG_FIFODATA, 0x00);   //PARAM(REQB,Number of slots =0)
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 12)
		return FAIL;
	for(i=0;i<12;i++)
		GetReg(REG_FIFODATA,&picc_b->ATQB [i]);	
	memcpy(picc_b->PUPI,picc_b->ATQB + 1,4);
	memcpy(picc_b->APPLICATION_DATA,picc_b->ATQB + 6,4);
	memcpy(picc_b->PROTOCOL_INF,picc_b->ATQB + 10,3);	
	return SUCCESS;
}

unsigned char ReaderB_Attrib(struct picc_b_struct *picc_b)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x1D);  //
	SetReg(REG_FIFODATA, picc_b->PUPI[0]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[1]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[2]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[3]);   //
	SetReg(REG_FIFODATA, 0x00);   //Param1
	SetReg(REG_FIFODATA, 0x08);   //Param2  BIT0~BIT3 Frame Size 0 = 16, 1 = 24, 2 = 32, 3 = 40, 4 = 48, 5 = 64, 6 = 96, 7 = 128, 8 = 256
	//Param2 BIT4~BIT5 TX BaudRate BIT6~BIT7 RX BaudRate,00 = 106Kbps, 01 = 212Kbps, 10 = 424Kbps, 11 = 848Kbps
	SetReg(REG_FIFODATA, 0x01);   //COMPATIBLE WITH 14443-4
	SetReg(REG_FIFODATA, 0x01);   //CID:01 
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 1)
		return FAIL;
	GetReg(REG_FIFODATA,&reg_data);	
	picc_b->CID = reg_data & 0x0F;
	
	return SUCCESS;
	
}

unsigned char ReaderB_Halt(struct picc_b_struct *picc_b)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x50);  //
	SetReg(REG_FIFODATA, picc_b->PUPI[0]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[1]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[2]);   //
	SetReg(REG_FIFODATA, picc_b->PUPI[3]);   //

	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 1)
		return FAIL;
	GetReg(REG_FIFODATA,&reg_data);	
	*picc_b->Answer_to_HALT = reg_data & 0x0F;
	
	return SUCCESS;

}

unsigned char ReaderB_Get_SN(struct picc_b_struct *picc_b)
{
	unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x00);  //
	SetReg(REG_FIFODATA, 0x36);   //
	SetReg(REG_FIFODATA, 0x00);   //
	SetReg(REG_FIFODATA, 0x00);   //
	SetReg(REG_FIFODATA, 0x08);   //

	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 10)
		return FAIL;
	for(i=0;i<8;i++)
		GetReg(REG_FIFODATA,&picc_b->SN[i]);	
		
	return SUCCESS;	
	
}

unsigned char ReaderV_Inventory(struct picc_v_struct *picc_v)
{
	unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x26);   //
	SetReg(REG_FIFODATA, 0x01); 
	SetReg(REG_FIFODATA, 0x00); 
	
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 10)
		return FAIL;
	GetReg(REG_FIFODATA,&picc_v->RESPONSE );
	GetReg(REG_FIFODATA,&reg_data);
	for(i = 0;i < 8; i++)
	{
		GetReg(REG_FIFODATA,&picc_v->UID[i]);
	}
	return SUCCESS;
}

unsigned char ReaderV_Select(struct picc_v_struct *picc_v)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA, 0x22);
	SetReg(REG_FIFODATA, 0x25);   //
	SetReg(REG_FIFODATA, picc_v->UID[0]); 
	SetReg(REG_FIFODATA, picc_v->UID[1]); 
	SetReg(REG_FIFODATA, picc_v->UID[2]);
	SetReg(REG_FIFODATA, picc_v->UID[3]);
	SetReg(REG_FIFODATA, picc_v->UID[4]);
	SetReg(REG_FIFODATA, picc_v->UID[5]);
	SetReg(REG_FIFODATA, picc_v->UID[6]);
	SetReg(REG_FIFODATA, picc_v->UID[7]);
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 1)
		return FAIL;
	GetReg(REG_FIFODATA,&picc_v->RESPONSE );	
	return SUCCESS;
}

unsigned char ReaderV_ReadSingleBlock(unsigned char block_num,struct picc_v_struct *picc_v)
{
	unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA,0x12);
	SetReg(REG_FIFODATA, 0x20);   //
	SetReg(REG_FIFODATA, block_num); 

	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 5)
		return FAIL;
	GetReg(REG_FIFODATA,&picc_v->RESPONSE );
	for(i = 0;i < 4; i++)
	{
		GetReg(REG_FIFODATA,&picc_v->BLOCK_DATA[i]);
	}	
	return SUCCESS;	
}



unsigned char ReaderV_WriteSingleBlock(unsigned char block_num,struct picc_v_struct *picc_v)
{
	unsigned char reg_data;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	SetReg(REG_FIFODATA,0x02);
	SetReg(REG_FIFODATA, 0x21);   //
	SetReg(REG_FIFODATA, block_num); 
	SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[0]); 
	SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[1]); 
	SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[2]); 
	SetReg(REG_FIFODATA, picc_v->BLOCK_DATA[3]); 
	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 1)
		return FAIL;
	GetReg(REG_FIFODATA,&picc_v->RESPONSE );
	
	return SUCCESS;	
}

unsigned char ReaderF_Inventory(struct picc_f_struct *picc_f)
{
	unsigned char reg_data,i;
	SetCommand(CMD_IDLE);	
	SetReg(REG_TXDATANUM,0x08);
	ModifyReg(REG_FIFOCONTROL,BIT_FIFOFLUSH,ENABLE);		//Clear FIFO 
	
	SetReg(REG_FIFODATA, 0x06);
	SetReg(REG_FIFODATA, 0x00);   //
	SetReg(REG_FIFODATA, 0xFF); 
	SetReg(REG_FIFODATA, 0xFF); 
	SetReg(REG_FIFODATA, 0x10); 
	SetReg(REG_FIFODATA, 0x00); 

	ModifyReg(REG_TXCRCCON, BIT_CRCEN,ENABLE);
  ModifyReg(REG_RXCRCCON, BIT_CRCEN,ENABLE);
	
	SetCommand(CMD_TRANSCEIVE);	
	DelayMs(10);	
	GetReg(REG_ERROR,&reg_data);
	if((reg_data & 0x0F)!=0)
		return FAIL;
	GetReg(REG_FIFOLENGTH,&reg_data);
	if(reg_data != 18)
		return FAIL;
	GetReg(REG_FIFODATA,&reg_data);
	GetReg(REG_FIFODATA,&reg_data);
	for(i = 0;i < 8; i++)
	{
		GetReg(REG_FIFODATA,&picc_f->UID[i]);
	}	
	return SUCCESS;		
	
}