727 lines
17 KiB
C
727 lines
17 KiB
C
/**
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* @file hguart_v4.c
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* @author bxd
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* @brief simple uart
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* @version
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* TXW81X
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* @date 2023-08-02
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*
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* @copyright Copyright (c) 2023
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*
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*/
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "osal/irq.h"
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#include "osal/semaphore.h"
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#include "osal/mutex.h"
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#include "osal/string.h"
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#include "hal/uart.h"
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#include "hal/gpio.h"
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#include "dev/uart/hguart_v4.h"
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#include "hguart_v4_hw.h"
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#define SIMPLE_UART_LOCK(mutex, flag)\
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do{\
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if(flag){\
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os_mutex_lock(mutex, osWaitForever);\
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}\
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}while(0);
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#define SIMPLE_UART_UNLOCK(mutex, flag)\
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do{\
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if(flag){\
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os_mutex_unlock(mutex);\
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}\
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}while(0);
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/**********************************************************************************/
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/* UART LOW LAYER FUNCTION */
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/**********************************************************************************/
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static int32 hguart_v4_set_dma(struct hguart_v4 *dev, uint32 enable)
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{
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if (enable) {
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dev->use_dma = 1;
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} else {
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dev->use_dma = 0;
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}
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return RET_OK;
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}
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static int32 hguart_v4_dma_rx_config(struct hguart_v4_hw *p_uart, uint8 status)
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{
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uint32 _dmacon = p_uart->DMACON;
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uint32 flag = 0;
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if (status) {
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_dmacon = 0x5;
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} else {
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_dmacon = 0;
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}
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/*!
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* fix: kick 2 times to counteract an unnecessary rx dma done
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*/
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if (p_uart->CON & LL_SIMPLE_UART_CON_DMA_IE) {
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p_uart->CON &=~ LL_SIMPLE_UART_CON_DMA_IE;
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flag = 1;
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//printf("<%x>", *(uint32 *)(0x40004b70));
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}
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p_uart->DMACON = _dmacon;
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__NOP();__NOP();__NOP();__NOP();
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//printf("<%x>", *(uint32 *)(0x40004b70));
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//clear rx done pending
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p_uart->CON |= LL_SIMPLE_UART_CON_CLRDMAPEND;
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//kick again
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p_uart->DMACON = _dmacon;
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__NOP();__NOP();__NOP();__NOP();
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//printf("<%x>", *(uint32 *)(0x40004b70));
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//clear rx done pending
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p_uart->CON |= LL_SIMPLE_UART_CON_CLRDMAPEND;
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//printf("<%x>", *(uint32 *)(0x40004b70));
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if (flag) {
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flag = 0;
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p_uart->CON |= LL_SIMPLE_UART_CON_DMA_IE;
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}
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return 0;
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}
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static int32 hguart_v4_dma_tx_config(struct hguart_v4_hw *p_uart, uint8 status)
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{
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uint32 _dmacon = p_uart->DMACON;
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if (status) {
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_dmacon = 0xA;
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} else {
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_dmacon = 0;
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}
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p_uart->DMACON = _dmacon;
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return 0;
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}
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static int32 hguart_v4_set_time_out(struct hguart_v4_hw *p_uart, uint32 time_bit, uint32 enable)
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{
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if (enable) {
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p_uart->CON |= LL_SIMPLE_UART_CON_TO_EN;
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p_uart->TOCON = LL_SIMPLE_UART_TOCON(time_bit);
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} else {
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p_uart->CON &=~ LL_SIMPLE_UART_CON_TO_EN;
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p_uart->TOCON = 0;
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}
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return RET_OK;
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}
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/**********************************************************************************/
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/* UART ATTCH FUNCTION */
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/**********************************************************************************/
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static int32 hguart_v4_open(struct uart_device *uart, uint32 baudrate) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if (dev->opened) {
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if (!dev->dsleep) {
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return -EBUSY;
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}
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}
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/* pin config */
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if (pin_func(dev->dev.dev.dev_id , 1) != RET_OK) {
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return RET_ERR;
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}
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/* reg config */
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hw->BAUD = (peripheral_clock_get(HG_APB0_PT_UART4) / baudrate) - 1;
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hw->CON = LL_SIMPLE_UART_CON_UARTEN;
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dev->opened = 1;
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dev->irq_dma_rx = 0;
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dev->irq_dma_tx = 0;
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dev->use_dma = 0;
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dev->dsleep = 0;
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return RET_OK;
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}
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static int32 hguart_v4_close(struct uart_device *uart) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if (!dev->opened) {
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return RET_OK;
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}
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irq_disable(dev->irq_num );
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pin_func(dev->dev.dev.dev_id, 0);
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hw->CON &= ~ LL_SIMPLE_UART_CON_UARTEN;
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dev->opened = 0;
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dev->irq_dma_rx = 0;
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dev->irq_dma_tx = 0;
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dev->use_dma = 0;
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dev->dsleep = 0;
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return RET_OK;
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}
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static int32 hguart_v4_putc(struct uart_device *uart, int8 value) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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SIMPLE_UART_LOCK(&dev->mutex_tx, dev->debug_uart);
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if (dev->opened && (hw->CON & LL_SIMPLE_UART_CON_UARTEN)) {
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while(!(hw->CON & LL_SIMPLE_UART_CON_TXBUFEMPTY));
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hw->DATA = value;
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SIMPLE_UART_UNLOCK(&dev->mutex_tx, dev->debug_uart);
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return RET_OK;
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} else {
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SIMPLE_UART_UNLOCK(&dev->mutex_tx, dev->debug_uart);
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return -EIO;
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}
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}
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static uint8 hguart_v4_getc(struct uart_device *uart) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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SIMPLE_UART_LOCK(&dev->mutex_rx, dev->debug_uart);
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while(!(hw->CON & LL_SIMPLE_UART_CON_RXBUFNOTEMPTY));
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hw->CON |= LL_SIMPLE_UART_CON_CLRRXDONE;
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SIMPLE_UART_UNLOCK(&dev->mutex_rx, dev->debug_uart);
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return hw->DATA;
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}
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static int32 hguart_v4_rs485_de_set(void)
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{
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if(PIN_UART4_DE != 255) {
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gpio_set_val(PIN_UART4_DE, 1);
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return RET_OK;
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}
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if(PIN_UART5_DE != 255) {
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gpio_set_val(PIN_UART5_DE, 1);
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return RET_OK;
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}
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return RET_ERR;
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}
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static int32 hguart_v4_rs485_de_reset(void)
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{
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if(PIN_UART4_DE != 255) {
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gpio_set_val(PIN_UART4_DE, 0);
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return RET_OK;
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}
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if(PIN_UART5_DE != 255) {
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gpio_set_val(PIN_UART5_DE, 0);
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return RET_OK;
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}
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return RET_ERR;
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}
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static int32 hguart_v4_rs485_re_set(void)
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{
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if(PIN_UART4_RE != 255) {
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gpio_set_val(PIN_UART4_RE, 1);
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return RET_OK;
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}
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if(PIN_UART5_RE != 255) {
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gpio_set_val(PIN_UART5_RE, 1);
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return RET_OK;
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}
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return RET_ERR;
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}
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static int32 hguart_v4_rs485_re_reset(void)
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{
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if(PIN_UART4_RE != 255) {
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gpio_set_val(PIN_UART4_RE, 0);
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return RET_OK;
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}
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if(PIN_UART5_RE != 255) {
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gpio_set_val(PIN_UART5_RE, 0);
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return RET_OK;
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}
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return RET_ERR;
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}
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static int32 hguart_v4_puts(struct uart_device *uart, uint8 *buf, uint32 size) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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uint32 i = 0;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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SIMPLE_UART_LOCK(&dev->mutex_tx, dev->debug_uart);
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if (dev->use_dma) {
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if (dev->debug_uart) {
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//enable uart 1Byte tx done irq
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hw->CON |= LL_SIMPLE_UART_CON_UARTTXIE;
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dev->p_tx_buf = (uint8 *)buf;
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dev->tx_total_byte = size;
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dev->tx_cur_byte = 0;
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//send 1Byte to trigger 1Byte tx done irq
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hw->DATA = buf[0];
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os_sema_down(&dev->sema_tx, osWaitForever);
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//disable uart 1Byte tx done irq
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hw->CON &=~ LL_SIMPLE_UART_CON_UARTTXIE;
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} else if (dev->rs485_set) {
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hguart_v4_dma_tx_config(hw, 0);
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hw->CON |= LL_SIMPLE_UART_CON_CLRDMAPEND;
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hguart_v4_rs485_de_set();
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hguart_v4_rs485_re_set();
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hw->DMAADR = (uint32)buf;
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hw->DMALEN = size;
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hguart_v4_dma_tx_config(hw, 1);
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/* waiting for tx done */
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while (!(hw->CON & LL_SIMPLE_UART_CON_DMAPEND));
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hguart_v4_rs485_re_reset();
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hguart_v4_rs485_de_reset();
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} else {
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for (i = 0; i < size; i++) {
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hguart_v4_putc(uart, buf[i]);
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}
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}
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} else {
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for (i = 0; i < size; i++) {
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hguart_v4_putc(uart, buf[i]);
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}
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}
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SIMPLE_UART_UNLOCK(&dev->mutex_tx, dev->debug_uart);
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return RET_OK;
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}
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static int32 hguart_v4_gets(struct uart_device *uart, uint8 *buf, uint32 size) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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uint32 i = 0;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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SIMPLE_UART_LOCK(&dev->mutex_rx, dev->debug_uart);
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if (dev->use_dma) {
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hw->DMAADR = (uint32)buf;
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hw->DMALEN = size;
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hguart_v4_dma_rx_config(hw, 1);
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} else {
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for (i = 0; i < size; i++) {
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hguart_v4_getc(uart);
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}
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}
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SIMPLE_UART_UNLOCK(&dev->mutex_rx, dev->debug_uart);
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return i;
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}
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static int32 hguart_v4_ioctl(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2) {
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int32 ret_val = RET_OK;
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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switch (ioctl_cmd) {
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case (UART_IOCTL_CMD_USE_DMA):
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ret_val = hguart_v4_set_dma(dev, param1);
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break;
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case (UART_IOCTL_CMD_SET_TIME_OUT):
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ret_val = hguart_v4_set_time_out((struct hguart_v4_hw *)dev->hw, param1, param2);
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break;
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case (UART_IOCTL_CMD_DISABLE_DEBUG_SELECTION):
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dev->debug_uart = (param1) ? (1) : (0);
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ret_val = RET_OK;
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break;
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case (UART_IOCTL_CMD_SET_RS485_EN):
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dev->rs485_set = (param1) ? (1) : (0);
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ret_val = RET_OK;
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break;
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default:
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ret_val = -ENOTSUPP;
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break;
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}
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return ret_val;
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}
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/* interrupt handler */
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static void hguart_v4_irq_handler(void *data) {
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struct hguart_v4 *dev = (struct hguart_v4 *)data;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if ((hw->CON & LL_SIMPLE_UART_CON_UARTTXIE) && (hw->CON & LL_SIMPLE_UART_CON_TXDONE)) {
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hw->CON |= LL_SIMPLE_UART_CON_CLRTXDONE;
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dev->tx_cur_byte++;
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//printf("cur len:%d\r\n", dev->tx_cur_byte);
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if (dev->tx_cur_byte == dev->tx_total_byte) {
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//printf("up\r\n");
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os_sema_up(&dev->sema_tx);
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//diable uart tx 1byte done irq
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hw->CON &=~ LL_SIMPLE_UART_CON_UARTTXIE;
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} else {
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hw->DATA = dev->p_tx_buf[dev->tx_cur_byte];
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}
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}
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if ((hw->CON & LL_SIMPLE_UART_CON_UARTRXIE) && (hw->CON & LL_SIMPLE_UART_CON_RXBUFNOTEMPTY)) {
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hw->CON |= LL_SIMPLE_UART_CON_CLRRXDONE;
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if (dev->irq_hdl) {
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dev->irq_hdl(UART_IRQ_FLAG_RX_BYTE, dev->irq_data, hw->DATA, 0);
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}
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}
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if ((hw->CON & LL_SIMPLE_UART_CON_FERRIE) && (hw->CON & LL_SIMPLE_UART_CON_FERR)) {
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hw->CON |= LL_SIMPLE_UART_CON_CLRFERR;
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if (dev->irq_hdl) {
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dev->irq_hdl(UART_IRQ_FLAG_FRAME_ERR, dev->irq_data, 0, 0);
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}
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}
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//UART4/5 TIMEOUT来了之后，DMA DONE也会起来，故DMA DONE中断之前要判断是否TIMEOUT
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if (!(hw->CON & LL_SIMPLE_UART_CON_TO_PENDING)) {
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if ((hw->CON & LL_SIMPLE_UART_CON_DMA_IE) && (hw->CON & LL_SIMPLE_UART_CON_DMAPEND)) {
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hw->CON |= LL_SIMPLE_UART_CON_CLRDMAPEND;
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if (dev->irq_hdl) {
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if (dev->irq_dma_rx) {
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dev->irq_hdl(UART_IRQ_FLAG_DMA_RX_DONE, dev->irq_data, hw->DMACNT, 0);
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} else {
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dev->irq_hdl(UART_IRQ_FLAG_DMA_TX_DONE, dev->irq_data, hw->DMACNT, 0);
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}
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}
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}
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} else {
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if ((hw->CON & LL_SIMPLE_UART_CON_TO_IE) && (hw->CON & LL_SIMPLE_UART_CON_TO_PENDING)) {
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hw->CON |= (LL_SIMPLE_UART_CON_CLRTOPEND | LL_SIMPLE_UART_CON_CLRDMAPEND);
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if (dev->irq_hdl) {
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dev->irq_hdl(UART_IRQ_FLAG_TIME_OUT, dev->irq_data, hw->DMACNT, 0);
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}
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}
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}
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}
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/* request interrupt */
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static int32 hguart_v4_request_irq(struct uart_device *uart, uart_irq_hdl irqhdl, uint32 irq_flag, uint32 data) {
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struct hguart_v4 *dev = (struct hguart_v4 *)uart;
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struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
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if ((!dev->opened) || (dev->dsleep)) {
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return RET_ERR;
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}
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dev->irq_hdl = irqhdl;
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dev->irq_data = data ;
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if (irq_flag & UART_IRQ_FLAG_RX_BYTE) {
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hw->CON |= LL_SIMPLE_UART_CON_UARTRXIE;
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}
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if (irq_flag & UART_IRQ_FLAG_FRAME_ERR) {
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hw->CON |= LL_SIMPLE_UART_CON_FERRIE;
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}
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if (irq_flag & UART_IRQ_FLAG_DMA_RX_DONE) {
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hw->CON |= LL_SIMPLE_UART_CON_DMA_IE;
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dev->irq_dma_tx = 0;
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dev->irq_dma_rx = 1;
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}
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if (irq_flag & UART_IRQ_FLAG_DMA_TX_DONE) {
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hw->CON |= LL_SIMPLE_UART_CON_DMA_IE;
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dev->irq_dma_tx = 1;
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dev->irq_dma_rx = 0;
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}
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if (irq_flag & UART_IRQ_FLAG_TIME_OUT) {
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hw->CON |= LL_SIMPLE_UART_CON_TO_IE;
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}
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#if defined(TXW81X)
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irq_enable(dev->comm_irq_num);
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#elif defined(TXW82X)
|
||
irq_enable(dev->irq_num);
|
||
#endif
|
||
|
||
return RET_OK;
|
||
}
|
||
|
||
static int32 hguart_v4_release_irq(struct uart_device *uart, uint32 irq_flag) {
|
||
|
||
struct hguart_v4 *dev = (struct hguart_v4 *)uart;
|
||
struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
|
||
|
||
if ((!dev->opened) || (dev->dsleep)) {
|
||
return RET_ERR;
|
||
}
|
||
|
||
if (irq_flag & UART_IRQ_FLAG_RX_BYTE) {
|
||
hw->CON &= ~ LL_SIMPLE_UART_CON_UARTRXIE;
|
||
}
|
||
|
||
if (irq_flag & UART_IRQ_FLAG_FRAME_ERR) {
|
||
hw->CON &= ~ LL_SIMPLE_UART_CON_FERRIE;
|
||
}
|
||
|
||
if (irq_flag & UART_IRQ_FLAG_DMA_RX_DONE) {
|
||
hw->CON &=~ LL_SIMPLE_UART_CON_DMA_IE;
|
||
}
|
||
|
||
if (irq_flag & UART_IRQ_FLAG_TIME_OUT) {
|
||
hw->CON &=~ LL_SIMPLE_UART_CON_TO_IE;
|
||
}
|
||
|
||
#if defined(TXW81X)
|
||
irq_disable(dev->comm_irq_num);
|
||
#elif defined(TXW82X)
|
||
irq_disable(dev->irq_num);
|
||
#endif
|
||
|
||
return RET_OK;
|
||
}
|
||
|
||
#ifdef CONFIG_SLEEP
|
||
int32 hguart_v4_suspend(struct dev_obj *obj)
|
||
{
|
||
struct hguart_v4 *dev = (struct hguart_v4 *)obj;
|
||
struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
|
||
|
||
if (!dev->opened) {
|
||
return RET_OK;
|
||
}
|
||
|
||
if (0 > os_mutex_lock(&dev->bp_suspend_lock, 10000)) {
|
||
return RET_ERR;
|
||
}
|
||
|
||
|
||
/*!
|
||
* Close the UART
|
||
*/
|
||
hw->CON &= ~ BIT(4);
|
||
|
||
|
||
// pin_func(dev->dev.dev.dev_id, 0);
|
||
|
||
#if defined(TXW81X)
|
||
irq_disable(dev->comm_irq_num);
|
||
#elif defined(TXW82X)
|
||
irq_disable(dev->irq_num);
|
||
#endif
|
||
/*
|
||
* clear pending
|
||
*/
|
||
hw->CON |= 0x3f000000;
|
||
|
||
|
||
os_memset((void *)&dev->bp_regs, 0, sizeof(dev->bp_regs));
|
||
|
||
/*
|
||
* save the reglist
|
||
*/
|
||
dev->bp_regs.con = hw->CON;
|
||
dev->bp_regs.baud = hw->BAUD;
|
||
dev->bp_regs.tocon = hw->TOCON;
|
||
dev->bp_regs.dmaadr = hw->DMAADR;
|
||
dev->bp_regs.dmalen = hw->DMALEN;
|
||
dev->bp_regs.dmacon = hw->DMACON;
|
||
|
||
/*
|
||
* save the irq_hdl created by user
|
||
*/
|
||
dev->bp_irq_hdl = dev->irq_hdl;
|
||
dev->bp_irq_data = dev->irq_data;
|
||
|
||
//venus v2：uart4&5 clk and uart0 clk are share the same source
|
||
if (UART4_BASE == (uint32)hw) {
|
||
// sysctrl_uart4_clk_close();
|
||
} else if (UART5_BASE == (uint32)hw) {
|
||
// sysctrl_uart5_clk_close();
|
||
}
|
||
|
||
dev->dsleep = 1;
|
||
|
||
os_mutex_unlock(&dev->bp_suspend_lock);
|
||
|
||
return RET_OK;
|
||
}
|
||
|
||
int32 hguart_v4_resume(struct dev_obj *obj)
|
||
{
|
||
struct hguart_v4 *dev = (struct hguart_v4 *)obj;
|
||
struct hguart_v4_hw *hw = (struct hguart_v4_hw *)dev->hw;
|
||
if (!dev->opened) {
|
||
return RET_OK;
|
||
}
|
||
|
||
if (0 > os_mutex_lock(&dev->bp_resume_lock, 10000)) {
|
||
return RET_ERR;
|
||
}
|
||
|
||
/* pin config */
|
||
// if (pin_func(dev->dev.dev.dev_id, 1) != RET_OK) {
|
||
// return RET_ERR;
|
||
// }
|
||
|
||
|
||
/*
|
||
* recovery the UART clk
|
||
*/
|
||
if (UART4_BASE == (uint32)hw) {
|
||
// sysctrl_uart4_clk_open();
|
||
} else if (UART5_BASE == (uint32)hw) {
|
||
// sysctrl_uart5_clk_open();
|
||
}
|
||
|
||
/*
|
||
* recovery the reglist from sram
|
||
*/
|
||
hw->CON = dev->bp_regs.con;
|
||
hw->BAUD = dev->bp_regs.baud;
|
||
hw->TOCON = dev->bp_regs.tocon;
|
||
hw->DMAADR = dev->bp_regs.dmaadr;
|
||
hw->DMALEN = dev->bp_regs.dmalen;
|
||
hw->DMACON = dev->bp_regs.dmacon;
|
||
|
||
/*
|
||
* recovery the irq handle and data
|
||
*/
|
||
dev->irq_hdl = dev->bp_irq_hdl;
|
||
dev->irq_data = dev->bp_irq_data;
|
||
|
||
os_memset((void *)&dev->bp_regs, 0, sizeof(dev->bp_regs));
|
||
|
||
/*!
|
||
* Open the UART
|
||
*/
|
||
hw->CON |= BIT(4);
|
||
if (hw->DMACON & 1) {
|
||
hguart_v4_dma_rx_config(hw, 1);
|
||
}
|
||
|
||
#if defined(TXW81X)
|
||
irq_enable(dev->comm_irq_num);
|
||
#elif defined(TXW82X)
|
||
irq_enable(dev->irq_num);
|
||
#endif
|
||
dev->dsleep = 0;
|
||
|
||
os_mutex_unlock(&dev->bp_resume_lock);
|
||
|
||
return RET_OK;
|
||
}
|
||
#endif
|
||
|
||
static const struct uart_hal_ops uart_v4_ops = {
|
||
.open = hguart_v4_open,
|
||
.close = hguart_v4_close,
|
||
.getc = hguart_v4_getc,
|
||
.putc = hguart_v4_putc,
|
||
.gets = hguart_v4_gets,
|
||
.puts = hguart_v4_puts,
|
||
.ioctl = hguart_v4_ioctl,
|
||
.request_irq = hguart_v4_request_irq,
|
||
.release_irq = hguart_v4_release_irq,
|
||
#ifdef CONFIG_SLEEP
|
||
.ops.suspend = hguart_v4_suspend,
|
||
.ops.resume = hguart_v4_resume,
|
||
#endif
|
||
};
|
||
|
||
int32 hguart_v4_attach(uint32 dev_id, struct hguart_v4 *uart) {
|
||
|
||
uart->irq_data = 0;
|
||
uart->irq_hdl = NULL;
|
||
uart->opened = 0;
|
||
uart->irq_dma_rx = 0;
|
||
uart->irq_dma_tx = 0;
|
||
uart->use_dma = 0;
|
||
uart->debug_uart = 0;
|
||
uart->rs485_set = 0;
|
||
uart->dsleep = 0;
|
||
uart->p_tx_buf = NULL;
|
||
uart->tx_cur_byte = 0;
|
||
uart->tx_total_byte = 0;
|
||
uart->dev.dev.ops = (const struct devobj_ops *)&uart_v4_ops;
|
||
|
||
os_sema_init(&uart->sema_tx, 0);
|
||
os_mutex_init(&uart->mutex_rx);
|
||
os_mutex_init(&uart->mutex_tx);
|
||
#ifdef CONFIG_SLEEP
|
||
os_mutex_init(&uart->bp_suspend_lock);
|
||
os_mutex_init(&uart->bp_resume_lock);
|
||
#endif
|
||
|
||
request_irq(uart->irq_num, hguart_v4_irq_handler, uart);
|
||
|
||
dev_register(dev_id, (struct dev_obj *)uart);
|
||
return RET_OK;
|
||
}
|
||
|