124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
#ifndef _HGI2S_V0_HW_H
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#define _HGI2S_V0_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup IIS MODULE REGISTER
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* @{
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*/
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/***** CON Register *****/
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/*! Filter the RX data from IO
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*/
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#define LL_I2S_CON_RXDBSBPS(n) (((n)&0x01) << 14)
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/*! Filter the WSCLK clock from IO
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*/
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#define LL_I2S_CON_WSCLKDBSBPS(n) (((n)&0x01) << 13)
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/*! Filter the BCLK clock from IO
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*/
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#define LL_I2S_CON_BCLKDBSBPS(n) (((n)&0x01) << 12)
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/*! I2S work mode select
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*/
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#define LL_I2S_CON_MCLK_OE(n) (((n)&0x01) << 11)
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/*! I2S channel mode select
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*/
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#define LL_I2S_CON_OV_PEND_IE(n) (((n)&0x01) << 10)
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/*! I2S BCK clock polarity
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*/
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#define LL_I2S_CON_HF_PEND_IE(n) (((n)&0x01) << 9)
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/*! I2S WS clock polarity
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*/
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#define LL_I2S_CON_WORKMODE(n) (((n)&0x01) << 8)
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/*! sign extension function
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*/
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#define LL_I2S_CON_MONO(n) (((n)&0x03) << 6)
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/*! I2S mode select
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*/
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#define LL_I2S_CON_BCKPOL(n) (((n)&0x01) << 5)
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/*! I2S serial data format
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*/
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#define LL_I2S_CON_WSPOL(n) (((n)&0x01) << 4)
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/*! Receive channel select
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*/
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#define LL_I2S_CON_MODE(n) (((n)&0x01) << 3)
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/*! Transmit channel select
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*/
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#define LL_I2S_CON_FRMT(n) (((n)&0x03) << 1)
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/*! I2S enable
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*/
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#define LL_I2S_CON_ENABLE(n) (((n)&0x01) << 0)
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/***** BIT_SET Register *****/
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/*! I2S bit set
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*/
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#define LL_I2S_BIT_SET_IISBIT(n) (((n)&0x1F) << 0)
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/***** BUAD Register *****/
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/*! I2S baud set
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*/
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#define LL_I2S_BAUD_SET_BUAD(n) (((n)&0x3F) << 0)
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/***** WSCON Register *****/
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/*! I2S wscon set
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*/
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#define LL_I2S_WSCON_SET_WSCON(n) (((n)&0x3F) << 0)
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/***** STA Register *****/
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/*! I2S DMA data over pending
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*/
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#define LL_I2S_STA_DMA_OV_PENGING(n) (((n)&0x01) << 5)
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/*! I2S DMA data half pending
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*/
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#define LL_I2S_STA_DMA_HF_PENGING(n) (((n)&0x01) << 4)
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/*! I2S transmit done pending
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*/
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#define LL_I2S_STA_DONE_PENGING(n) (((n)&0x01) << 3)
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/*! I2S work state pending
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*/
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#define LL_I2S_STA_WORK_STATE_PENGING(n) (((n)&0x01) << 2)
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/*! I2S fifo write full pending
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*/
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#define LL_I2S_STA_FIFO_WFULL_PENGING(n) (((n)&0x01) << 1)
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/*! I2S fifo read empty pending
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*/
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#define LL_I2S_STA_FIFO_REMPTY_PENGING(n) (((n)&0x01) << 0)
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/***** STADR0 Register *****/
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/*! I2S DMA address config
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*/
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#define LL_I2S_STADR_DMA_ADDR0(n) (((n)&0xFFFFFFFF) << 0)
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/***** DMALEN Register *****/
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/*! I2S DMA len config
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*/
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#define LL_I2S_DMALEN_LEN(n) (((n)&0xFFFF) << 0)
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/** @brief I2S register structure
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* @{
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*/
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struct hgi2s_v0_hw {
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__IO uint32_t CON;
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__IO uint32_t BIT_SET;
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__IO uint32_t BAUD;
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__IO uint32_t WS_CON;
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__IO uint32_t STA;
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__IO uint32_t DMA_STADR;
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__IO uint32_t RESERVE;
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__IO uint32_t DMA_LEN;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HGI2S_V0_HW_H */ |