375 lines
11 KiB
C
375 lines
11 KiB
C
#ifndef HAL_DSI_H
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#define HAL_DSI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* User interrupt handle */
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typedef int32(*dsi_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
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// Data Types for Processor-Sourced Packets
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#define DSI_SP_VSS 0x01
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#define DSI_SP_VSE 0x11
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#define DSI_SP_HSS 0x21
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#define DSI_SP_HSE 0x31
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#define DSI_SP_EOTP 0x08
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#define DSI_SP_CMOFF 0x02
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#define DSI_SP_CMON 0x12
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#define DSI_SP_SDON 0x22
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#define DSI_SP_SDOFF 0x32
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#define DSI_SP_GENW0P 0x03
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#define DSI_SP_GENW1P 0x13
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#define DSI_SP_GENW2P 0x23
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#define DSI_SP_GENR0P 0x04
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#define DSI_SP_GENR1P 0x14
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#define DSI_SP_GENR2P 0x24
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#define DSI_SP_DCSW0P 0x05
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#define DSI_SP_DCSW1P 0x15
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#define DSI_SP_DCSR0P 0x06
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#define DSI_SP_MAXRPACK 0x37
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#define DSI_LP_NULL 0x09
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#define DSI_LP_BLANK 0x19
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#define DSI_LP_GENW 0x29
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#define DSI_LP_DCSW 0x39
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#define DSI_LP_PPS16B 0x0E
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#define DSI_LP_PPS18B 0x1E
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#define DSI_LP_LPPS18B 0x2E
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#define DSI_LP_PPS24B 0x3E
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//display command set
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#define DSI_ENTER_IDLE_MODE 0x39
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#define DSI_ENTER_INVERT_MODE 0x21
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#define DSI_ENTER_NORMAL_MODE 0x13
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#define DSI_ENTER_PARTIAL_MODE 0x12
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#define DSI_ENTER_SLEEP_MODE 0x10
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#define DSI_EXIT_IDLE_MODE 0x38
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#define DSI_EXIT_INVERT_MODE 0x20
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#define DSI_EXIT_SLEEP_MODE 0x11
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#define DSI_NOP 0x00
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#define DSI_SET_DISPLAY_OFF 0x28
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#define DSI_SET_DISPLAY_ON 0x29
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#define DSI_SET_ALLP_ON 0x23
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#define DSI_SET_ALLP_OFF 0x22
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#define DSI_SET_TEAR_OFF 0x34
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#define DSI_SOFT_RESET 0x01
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#define DSI_SET_ADDRESS_MODE 0x36
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#define DSI_SET_GAMMA_CURVE 0x26
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#define DSI_SET_PIXEL_FORMAT 0x3A
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#define DSI_SET_TEAR_ON 0x35
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#define DSI_SET_SCROLL_START 0x37
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#define DSI_SET_TEAR_SCAN_LINE 0x44
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#define DSI_SET_COLUMN_ADDRESS 0x2A
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#define DSI_SET_PAGE_ADDRESS 0x2B
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#define DSI_SET_PARTIAL_COLUMNS 0x31
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#define DSI_SET_PARTIAL_ROWS 0x30
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#define DSI_SET_SCROLL_AREA 0x33
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#define DSI_WRITE_LUT 0x2D
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#define DSI_WRITE_MEMORY_CONTINUE 0x3C
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#define DSI_WRITE_MEMORY_START 0x2C
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#define DSI_GET_ADDRESS_MODE 0x0B
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#define DSI_GET_BLUE_CHANNEL 0x08
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#define DSI_GET_COMPRESSION_MODE 0x03
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#define DSI_GET_DIAGNOSTIC_RESULT 0x0F
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#define DSI_GET_DISPLAY_MODE 0x0D
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#define DSI_GET_GREEN_CHANNEL 0x07
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#define DSI_GET_PIXEL_FORMAT 0x0C
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#define DSI_GET_POWER_MODE 0x0A
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#define DSI_GET_RED_CHANNEL 0x06
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#define DSI_GET_SCAN_LINE 0x45
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#define DSI_GET_SIGNAL_MODE 0x0E
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#define DSI_READ_DDB_CONTINUE 0xA8
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#define DSI_READ_DDB_START 0xA1
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#define DSI_READ_MEMORY_CONTINUE 0x3E
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#define DSI_READ_MEMORY_START 0x2E
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/**
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* @brief UART ioctl_cmd type
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*/
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enum dsi_ioctl_cmd {
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_LANE_NUM,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_MAX_CLK_TIM,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_REMAIN_STOP_STATE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CFG_ENABLE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_ULPS_CTRL,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_ULPS_MIN_TIME,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_ULPS_ENTRY_DELAY_TIME,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_ULPS_WAKEUP_TIME,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_ULPS_MODE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CMD_VIDEO_SELECT_MODE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GEN_VCID_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CMD_MODE_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_DPI_VCID,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_COLOR_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CFG_POL,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_VID_MODE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_VID_PKT_SIZE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_VID_CHUNK_NUM,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_VID_NULL_SIZE,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_VID_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_LPCMD_TMR,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_EDPI_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_DPHY_RST,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_PIXEL_GENERIC_SRAM_FIFO,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_FIFO_DEPTH,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CMD_PKT_FIFO_EMPTY,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_WAIT_PKT_FIFO_FULL,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GEN_PLD_WRITE_FULL,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GEN_PLD_READ_EMPTY,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_CMD_CFG,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_SET_GEN_PLD_DATA,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GET_GEN_PLD_DATA,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GET_STA0,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_GET_STA1,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_SET_IO_REMAP,
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/*! Compatible version: V2;
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*@ Describe:
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*
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*/
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DSI_IOCTL_RESET_MODULE,
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};
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struct dsi_device {
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struct dev_obj dev;
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};
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struct dsi_hal_ops{
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struct devobj_ops ops;
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int32(*init)(struct dsi_device *dsi_dev,uint8 clk_div,uint8_t tx_esc_clk_div,uint8_t auto_clklane,uint8_t lane_num,uint8_t clkselect,uint8_t div_strong);
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int32(*deinit)(struct dsi_device *dsi_dev);
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int32(*open)(struct dsi_device *dsi_dev);
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int32(*close)(struct dsi_device *dsi_dev);
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int32(*ioctl)(struct dsi_device *dsi_dev, enum dsi_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
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int32(*request_irq)(struct dsi_device *dsi_dev, uint32 irq_flag, dsi_irq_hdl irq_hdl, uint32 irq_data);
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int32(*release_irq)(struct dsi_device *dsi_dev, uint32 irq_flag);
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};
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enum dsi_module_clk {
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DSI_MODULE_CLK_480M = 0,
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DSI_MODULE_CLK_960M,
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DSI_MODULE_CLK_240M,
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};
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int32 dsi_init(struct dsi_device *p_dsi,uint8 clk_div,uint8_t tx_esc_clk_div,uint8_t auto_clklane,uint8_t lane_num,uint8_t clkselect,uint8_t div_strong);
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int32 dsi_deinit(struct dsi_device *p_dsi);
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int32 dsi_open(struct dsi_device *p_dsi);
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int32 dsi_close(struct dsi_device *p_dsi);
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int32 mipi_dsi_set_lane_num(struct dsi_device *p_dsi,uint8 lane_num);
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int32 mipi_dsi_max_clk_time(struct dsi_device *p_dsi,uint32 max_clk);
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int32 mipi_dsi_remain_stop_state(struct dsi_device *p_dsi,uint8 state);
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int32 mipi_dsi_cfg_enable(struct dsi_device *p_dsi,uint8_t htxeotp_en,uint8_t rxeotp_en,uint8_t bta_en,uint8_t ecc_en,uint8_t crc_en,uint8_t ltxeotp_en);
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int32 mipi_dsi_ulps_ctrl(struct dsi_device *p_dsi,uint8_t indatulps,uint8_t outdatulps,uint8_t inclkulps,uint8_t outclkulps);
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int32 mipi_dsi_ulps_min_time(struct dsi_device *p_dsi,uint8 time);
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int32 mipi_dsi_ulps_entry_delay_time(struct dsi_device *p_dsi,uint32 time);
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int32 mipi_dsi_ulps_wakeup_time(struct dsi_device *p_dsi,uint16 twakeup_clk,uint16 twakeup_cnt);
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int32 mipi_dsi_ulps_mode(struct dsi_device *p_dsi,uint8_t pll_off,uint8_t auto_ulps,uint8_t pre_pll_off_req);
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int32 mipi_dsi_select_mode(struct dsi_device *p_dsi,uint8 cmd);
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int32 mipi_dsi_gen_vcid_cfg(struct dsi_device *p_dsi,uint8_t vcid,uint8_t vcid_tear_auto,uint8_t vcid_tx_auto);
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int32 mipi_dsi_cmd_mode_cfg(struct dsi_device *p_dsi,uint8_t te_ack,uint8_t ack,uint8_t sw0p_tx,uint8_t sw1p_tx,uint8_t sw2p_tx,uint8_t sr0p_tx,uint8_t sr1p_tx,uint8_t sr2p_tx, uint8_t gen_lw_tx,uint8_t dcs_sw0p_tx,uint8_t dcs_sw1p_tx,uint8_t dcs_sr0p_tx,uint8_t dcs_lw_tx,uint8_t max_rd_pkt_size);
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int32 mipi_dsi_dpi_vcid(struct dsi_device *p_dsi,uint8 vcid);
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int32 mipi_dsi_color_cfg(struct dsi_device *p_dsi,uint8_t color_mode,uint8_t loosely18_en);
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int32 mipi_dsi_cfg_pol(struct dsi_device *p_dsi,uint8_t dataen_active,uint8_t vsync_active,uint8_t hsync_active,uint8_t shutd_active,uint8_t colorm_active);
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int32 mipi_dsi_vid_mode(struct dsi_device *p_dsi,uint8_t vsa_en,uint8_t vbp_en,uint8_t vfp_en,uint8_t vact_en,uint8_t hbp_en,uint8_t hfp_en,uint8_t frame_bta_ack_en,uint8_t cmd_en,uint8_t vid_mode_type);
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int32 mipi_dsi_vid_pkt_size(struct dsi_device *p_dsi,uint32 size);
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int32 mipi_dsi_vid_chunk_num(struct dsi_device *p_dsi,uint32 chunk_num);
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int32 mipi_dsi_vid_null_size(struct dsi_device *p_dsi,uint32 null_num);
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int32 mipi_dsi_vid_cfg(struct dsi_device *p_dsi,uint32 dpi2laneclkratio,uint32_t vid_vsa,uint32_t vid_vbp,uint32_t vid_vactive,uint32_t w,uint32_t vid_vfp,uint8_t hsa,uint8_t hbp,uint8_t hfp);
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int32 mipi_dsi_lpcmd_tmr(struct dsi_device *p_dsi,uint16_t invact_lptime,uint16_t outvact_lptime);
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int32 mipi_dsi_edpi_cfg(struct dsi_device *p_dsi,uint16_t edpi_maxpkt,uint8_t hw_te_on,uint8_t hw_te_gen,uint8_t hw_scan_line,uint16_t line_parameter);
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int32 mipi_dsi_phy_rst(struct dsi_device *p_dsi);
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int32 mipi_dsi_set_pixel_sram_fifo(struct dsi_device *p_dsi,uint32 gen_addr);
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int32 mipi_dsi_set_fifo_depth(struct dsi_device *p_dsi,uint32 depth);
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int32 mipi_dsi_cmd_pkt_fifo_empty(struct dsi_device *p_dsi);
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int32 mipi_dsi_wait_pkt_fifo_full(struct dsi_device *p_dsi);
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int32 mipi_dsi_gen_pld_write_full(struct dsi_device *p_dsi);
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int32 mipi_dsi_gen_pld_read_empty(struct dsi_device *p_dsi);
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int32 mipi_dsi_cmd_cfg(struct dsi_device *p_dsi,uint8_t cmdid,uint8_t cmd,uint8_t vcid,uint8_t dat);
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int32 mipi_dsi_set_gen_pld_data(struct dsi_device *p_dsi,uint8_t param0,uint8_t param1,uint8_t param2,uint8_t param3);
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int32 mipi_dsi_get_gen_pld_data(struct dsi_device *p_dsi);
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int32 mipi_dsi_set_lane_remap(struct dsi_device *p_dsi,uint8_t clklane,uint8_t lane0,uint8_t lane1,uint8_t lane2,uint8_t lane3,uint8_t clk_pol,uint8_t lane0_pol,uint8_t lane1_pol,uint8_t lane2_pol,uint8_t lane3_pol);
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int32 mipi_dsi_get_sta0(struct dsi_device *p_dsi);
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int32 mipi_dsi_get_sta1(struct dsi_device *p_dsi);
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int32 mipi_dsi_reset_module(struct dsi_device *p_dsi);
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#ifdef __cplusplus
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}
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#endif
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#endif
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