152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
#ifndef _HAL_DMA_H_
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#define _HAL_DMA_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* enum dma_status - DMA transaction status
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* @DMA_SUCCESS: transaction completed successfully
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* @DMA_IN_PROGRESS: transaction not yet processed
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* @DMA_PAUSED: transaction is paused
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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DMA_SUCCESS,
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DMA_IN_PROGRESS,
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DMA_PAUSED,
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DMA_ERROR,
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};
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enum dma_xfer_direct {
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/*! xfer directiont: NONE
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*/
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DMA_XFER_DIR_NONE,
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/*! xfer directiont: memory to memory
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*/
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DMA_XFER_DIR_M2M,
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/*! xfer directiont: memory to device
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*/
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DMA_XFER_DIR_M2D,
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/*! xfer directiont: device to memory
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*/
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DMA_XFER_DIR_D2M,
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/*! xfer directiont: device to device
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*/
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DMA_XFER_DIR_D2D,
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};
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enum dma_xfer_mode {
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/*! xfer mode: source address increase
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*/
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DMA_XFER_MODE_INCREASE,
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/*! xfer mode: source address recycling
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*/
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DMA_XFER_MODE_RECYCLE,
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/*! xfer mode: source address block copy
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*/
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DMA_XFER_MODE_BLKCPY,
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};
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/**
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* enum dma_slave_buswidth - defines bus with of the DMA slave
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* device, source or target buses
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*/
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enum dma_slave_buswidth {
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DMA_SLAVE_BUSWIDTH_1_BYTE = 0,
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DMA_SLAVE_BUSWIDTH_2_BYTES = 1,
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DMA_SLAVE_BUSWIDTH_4_BYTES = 2,
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DMA_SLAVE_BUSWIDTH_8_BYTES = 3,
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DMA_SLAVE_BUSWIDTH_UNDEFINED = 4,
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};
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enum dma_irq_type {
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DMA_IRQ_TYPE_DONE,
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DMA_IRQ_TYPE_ERROR,
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};
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enum dma_endian_type{
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DMA_ENDIAN_TYPE_NO_OVERTURN,
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DMA_ENDIAN_TYPE_16BIT_OVERTURN,
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DMA_ENDIAN_TYPE_32BIT_OVERTURN,
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};
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enum dma_ioctl_cmd{
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DMA_IOCTL_CMD_ENDIAN,
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DMA_IOCTL_CMD_CHECK_DMA1_STATUS,
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DMA_IOCTL_CMD_DMA1_LOCK,
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DMA_IOCTL_CMD_DMA1_UNLOCK,
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};
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struct dma_device;
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typedef void (*dma_irq_hdl)(struct dma_device *p_dma, uint32 ch, enum dma_irq_type irq, uint32 data);
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struct dma_xfer_data {
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uint32 dest;
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uint32 src;
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uint32 dir : 3, //enum dma_xfer_direct
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endian : 2,
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dst_id : 8,
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src_id : 8,
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src_addr_mode : 2,
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dst_addr_mode : 2,
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reserved : 7;
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uint32 element_per_width;
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uint32 element_num;
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uint32 irq_data;
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dma_irq_hdl irq_hdl;
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};
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struct dma_device {
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struct dev_obj dev;
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};
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struct dma_hal_ops{
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struct devobj_ops ops;
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int32(*pause)(struct dma_device *dma, uint32 ch);
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int32(*resume)(struct dma_device *dma, uint32 ch);
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int32(*xfer)(struct dma_device *dma, struct dma_xfer_data *data);
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int32(*only_hw_xfer)(struct dma_device *dma, struct dma_xfer_data *data);
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int32(*get_status)(struct dma_device *dma, uint32 ch);
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int32(*stop)(struct dma_device *dma, uint32 ch);
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int32(*ioctl)(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
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};
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int32 dma_pause(struct dma_device *dma, uint32 ch);
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int32 dma_resume(struct dma_device *dma, uint32 ch);
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void dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n);
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void dma_memcpy_no_cache(struct dma_device *dma, void *dst, const void *src, uint32 n);
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void dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n);
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void dma_memset_word(struct dma_device *dma, void *dst, uint32 c, uint32 n);
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void dma_memcpy_endian(struct dma_device *dma, void *dst, const void *src, uint32 n, enum dma_endian_type type);
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int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
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int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data);
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int32 dma_status(struct dma_device *dma, uint32 ch);
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int32 dma_stop(struct dma_device *dma, uint32 ch);
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#ifdef __cplusplus
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}
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#endif
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#endif
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