443 lines
12 KiB
C
443 lines
12 KiB
C
/**
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******************************************************************************
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* @file misc.h
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* @author HUGE-IC Application Team
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* @version V1.0.0
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* @date 2021.01.14
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* @brief This file contains all the PowerDomain firmware functions.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2021 HUGE-IC</center></h2>
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*
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*
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* Revision History
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* V1.0.0 2021.01.14 First Release, move from sysctrl
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*
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******************************************************************************
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*/
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#ifndef __MISC_H__
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#define __MISC_H__
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#include "typesdef.h"
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#include "cld_cache.h"
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#include "lib/common/rbuffer.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef VENUS_END
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/*******************************************************************/
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/* Venus to be continue */
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/*******************************************************************/
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#endif
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/**
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* @}
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*/
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///** @defgroup SYSMONITOR MACRO-DEF & Exported_Functions
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// * @{
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// */
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typedef struct
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{
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__IO uint32 CHx_LMT_L;
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__IO uint32 CHx_LMT_H;
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__IO uint32 CHx_ERR_ADR;
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// uint32 RESERVEDx;
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} SYS_MNT_CH_TypeDef;
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typedef struct
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{
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__IO uint32 CTRL;
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__IO uint32 PND;
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__IO uint32 CLR;
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__IO uint32 RD;
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__IO uint32 WR;
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__IO uint32 rev[4];
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SYS_MNT_CH_TypeDef SYS_MNT_CH[2];
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} SYS_MNT_TypeDef;
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#define SYSMNT ((SYS_MNT_TypeDef *) SYS_MNT_BASE)
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/**
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* @}
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*/
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/**
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* @brief CPU1_MNT
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*/
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typedef struct
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{
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__IO uint32 R0;
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__IO uint32 R1;
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__IO uint32 R2;
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__IO uint32 R3;
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__IO uint32 R4;
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__IO uint32 R5;
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__IO uint32 R6;
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__IO uint32 R7;
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__IO uint32 R8;
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__IO uint32 R9;
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__IO uint32 R10;
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__IO uint32 R11;
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__IO uint32 R12;
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__IO uint32 R13;
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__IO uint32 R14;
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__IO uint32 R15; //0x40
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uint32 reserved_0x44[12];
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__IO uint32 R28;
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uint32 reserved_0x70[19];
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__IO uint32 EXPC; //0xc0
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__IO uint32 PSR;
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__IO uint32 EPC;
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__IO uint32 EPSR;
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__IO uint32 FCR;
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__IO uint32 FESR;
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__IO uint32 CPU1_DBGON;
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__IO uint32 CPU0_DBGON;
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__IO uint32 CPU1_SFTPND;
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} CPU1_MNT_TypeDef;
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#define CPU1_MNT ((CPU1_MNT_TypeDef *) 0x4000A100 )
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/** @addtogroup Template_Project
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* @{
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*/
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#define LL_SYSMONITOR_CHN_EN(n) (BIT(n))
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#define LL_SYSMONITOR_CHN_CAP_RANGE_INTER(n) (BIT(n+4))
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#define LL_SYSMONITOR_CHN_CAP_RANGE_OUTER(n) (0)
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#define LL_SYSMONITOR_CAP_PC_EN (1UL << 6)
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#define LL_SYSMONITOR_INT_EN (1UL << 7)
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#define LL_SYSMONITOR_CH0_SEL(n) (((n) & 0x1F) << 8)
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#define LL_SYSMONITOR_CH0_SEL_MSK ((0x1F) << 8)
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#define LL_SYSMONITOR_CH0_CAP_READ ((1UL) << 18)
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#define LL_SYSMONITOR_CH0_CAP_WRITE ((1UL) << 19)
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#define LL_SYSMONITOR_CH0_CAP_MODE(n) ((((n) & 0x3)) << 18)
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#define LL_SYSMONITOR_CH1_SEL(n) (((n) & 0x1F) << 13)
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#define LL_SYSMONITOR_CH1_SEL_MSK ((0x1F) << 13)
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#define LL_SYSMONITOR_CH1_CAP_READ ((1UL) << 20)
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#define LL_SYSMONITOR_CH1_CAP_WRITE ((1UL) << 21)
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#define LL_SYSMONITOR_CH1_CAP_MODE(n) ((((n) & 0x3)) << 20)
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#define LL_SYSMONITOR_CLEAR_REGISTER() do { SYSMNT->CLR = 1 | 2; } while(0)
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/** @addtogroup XXX
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* @{
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*/
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typedef enum {
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//CHANNEL 1
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LL_SYSMONITOR_CHN_M2M0_RD = (0) | (1<<8),
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LL_SYSMONITOR_CHN_M2M0_WR = (1) | (1<<8),
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LL_SYSMONITOR_CHN_M2M1_RD = (2) | (1<<8),
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LL_SYSMONITOR_CHN_M2M1_WR = (3) | (1<<8),
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LL_SYSMONITOR_CHN_CPU0_ICODE = (4) | (1<<8),
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LL_SYSMONITOR_CHN_CPU0_DCODE = (5) | (1<<8),
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LL_SYSMONITOR_CHN_USB_20 = (6) | (1<<8),
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LL_SYSMONITOR_CHN_USB_11 = (7) | (1<<8),
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//CHANNEL 0
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LL_SYSMONITOR_CHN_CPU1_ICODE = (6) | (0<<8),
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LL_SYSMONITOR_CHN_CPU1_DCODE = (7) | (0<<8),
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LL_SYSMONITOR_CHN_OSPI = (8) | (0<<8),
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LL_SYSMONITOR_CHN_QSPI = (9) | (0<<8),
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LL_SYSMONITOR_CHN_GMAC_RX = (10) | (0<<8),
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LL_SYSMONITOR_CHN_GMAC_TX = (11) | (0<<8),
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} TYPE_ENUM_LL_SYSMONITOR_CH;
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/** @addtogroup XXX
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* @{
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*/
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typedef enum {
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LL_SYSMONITOR_CAP_RANGE_INTER = (0),
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LL_SYSMONITOR_CAP_RANGE_OUTER = (1),
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} TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE;
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/** @addtogroup XXX
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* @{
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*/
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typedef enum {
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LL_SYSMONITOR_CAP_MODE_READ = (1),
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LL_SYSMONITOR_CAP_MODE_WRITE = (2),
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LL_SYSMONITOR_CAP_MODE_READ_OR_WRITE = (3),
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} TYPE_ENUM_LL_SYSMONITOR_CAP_MODE;
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typedef struct __ll_sysmonitor_cfg {
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/*! System monitor interrupt enable
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*/
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bool int_en;
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/*! System monitor sub channel : [0, 20]
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*/
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TYPE_ENUM_LL_SYSMONITOR_CH ch;
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/*! capture mode
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*/
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TYPE_ENUM_LL_SYSMONITOR_CAP_MODE cap_mode;
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/*! capture range
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*/
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TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE cap_range;
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/*! Chx low limited address
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*/
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uint32 chx_limit_low;
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/*! Chx high limited address
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*/
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uint32 chx_limit_high;
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/* IRQ handle
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*/
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void (*cb)(void *);
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} TYPE_SYSMONITOR_CFG;
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void sys_monitor_config(TYPE_SYSMONITOR_CFG *p_cfg);
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void sys_monitor_reset(void);
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/*******************************************************************/
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/* OSPI_EFF */
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/*******************************************************************/
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struct HW_EFF {
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volatile uint32_t CON;
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volatile uint32_t PERIOD;
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volatile uint32_t RD_CNT;
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volatile uint32_t WR_CNT;
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};
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#define OSPI_EFF ((struct HW_EFF *) 0x40020214)
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#define EFF_CNT_CLEAR (1<<6)
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#define EFF_INTR_PEND (1<<5)
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#define EFF_CH_SHIFT (2)
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#define EFF_CH_MASK (7<<2)
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#define EFF_INTR_EN (1<<1)
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#define EFF_MODU_EN (1<<0)
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#define OSPI_EFF_MSG_SIZE (5)
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enum EFF_CH {
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EFF_CPU0_DBUS,
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EFF_CPU0_IBUS,
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EFF_CPU1_DBUS,
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EFF_CPU1_IBUS,
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EFF_H264,
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EFF_SCHED,
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EFF_CH_OTHER,
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EFF_CH_END,
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};
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struct eff_msg {
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uint32_t rd_cnt[EFF_CH_END];
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uint32_t wr_cnt[EFF_CH_END];
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};
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struct eff_mgr {
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RBUFFER_DEF(rb, struct eff_msg, OSPI_EFF_MSG_SIZE);
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};
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/*统计period_ms时间内PSRAM的请求数， MAX值是0xffffffff / CPU_CLK * 1000*/
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int eff_start(uint32_t period_ms);
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void eff_stop();
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/*输出最近一次统计到的信息*/
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int eff_printf();
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int eff_read(struct eff_msg *msg);
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/*******************************************************************/
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/* EFUSE */
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/*******************************************************************/
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/**
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* @}
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*/
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#define CHIP_PACKID_KL928 0x01
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#define CHIP_PACKID_TXW825_824 0x02
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#define CHIP_PACKID_TXW826_824 0x10
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#define CHIP_PACKID_TXW826_824C 0x11
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#define CHIP_PACKID_TXW827_C08 0x20
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#define CHIP_PACKID_TXW828_C08FL 0x30
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#define CHIP_PACKID_TXW828_E08FL 0x31
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#define CHIP_PACKID_TXW828_E016FL 0x32
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#define CHIP_PACKID_TXW828_J016FL 0x33
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#define CHIP_PACKID_TXM609_800 0x40
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#define CHIP_PACKID_TXM609_804 0x41
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#define CHIP_PACKID_TXM609_H016 0x42
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/** @defgroup EFUSE MACRO-DEF & Exported_Functions
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* @{
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*/
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typedef struct
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{
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__IO uint32 EFUSE_CON;
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__IO uint32 EFUSE_TIME_CON0;
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__IO uint32 EFUSE_TIME_CON1;
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__IO uint32 EFUSE_TIME_CON2;
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__IO uint32 EFUSE_STATUS;
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__IO uint32 EFUSE_ADDR_CNT;
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__IO uint32 EFUSE_DATA;
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} EFUSE_TypeDef;
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#define EFUSE ((EFUSE_TypeDef *) EFUSE_BASE)
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/* efuse timing define */
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#define LL_EFUSE_POWER_FREQ 100000 /* 10us */
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#define LL_EFUSE_PROGRAM_FREQ 100000 /* 10us (9~11uS) */
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#define LL_EFUSE_READ_FREQ 10000000 /* 100ns ( > 36ns) */
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uint16 sysctrl_efuse_config_and_read(uint32 addr, uint8 *p_buf, uint16 len);
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void rf_para_efuse_check_valid(void);
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void sysctrl_efuse_mac_addr_calc(uint8 *addr_buf);
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uint16 sysctrl_efuse_get_customer_id(void);
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uint8 sysctrl_efuse_get_chip_package(void);
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uint32 sysctrl_efuse_get_smt_dat(void);
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int32 tsensor_meas(uint8 sensor_idx);
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/*******************************************************************/
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/* RFADC */
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/*******************************************************************/
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typedef struct {
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__IO uint32 RFADCDIGCON;
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} RFADCDIG_TypeDef;
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#define RFADCDIG ((RFADCDIG_TypeDef *) RFADCDIG_BASE)
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#define RFADCDIGCON_ACS_ON_MSK BIT(0)
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#define RFADCDIGCON_ACS_RW_MSK BIT(1)
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#define RFADCDIGCON_ACS_ADDR_SHIFT 2
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#define RFADCDIGCON_ACS_ADDR_MSK (0x1f<<RFADCDIGCON_ACS_ADDR_SHIFT)
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#define RFADCDIGCON_ACS_DATA_SHIFT 7
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#define RFADCDIGCON_ACS_DATA_MSK (0x3fffff<<RFADCDIGCON_ACS_DATA_SHIFT)
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#define ADCOUTSEL 0 // 0: output data after calibration; 1: output data before calibration
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/*******************************************************************/
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/* RFADC */
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/*******************************************************************/
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enum lf_clk_src {
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FROM_HOSC = 0,
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FROM_RC32K = 2,
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FROM_PB0 = 3,
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};
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enum lf_clk_count {
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_1024_CYCLE = 0,
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_512_CYCLE = 1,
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_256_CYCLE = 2,
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_128_CYCLE = 3,
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_64_CYCLE = 4,
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_32_CYCLE = 5,
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_16_CYCLE = 6,
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_8_CYCLE = 7,
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};
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enum dac_default_state {
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POWER_OFF = 0,
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SLEEP = 1,
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STAND_BY = 2,
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POWER_ON = 3
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};
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enum rf_bw {
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BW_1M = 0,
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BW_2M = 1,
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BW_4M = 2,
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BW_8M = 3
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};
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enum rf_parameter_type {
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RF_EFUSE_ALL_SIM = 0,
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ADC_CALIB_VAL = 1,
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ADDA_TIM_OFFSET = 2,
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TXDCOC_CALIB_VAL = 3,
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TXIMB_CALIB_VAL = 4,
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RXDCOC_CALIB_VAL = 5,
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RXIMB_CALIB_VAL = 6
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};
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int32 tx_digi_gain_store(uint16 tx_digi_gain);
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int32 sysctrl_internal_rf_sel_lo_freq(uint8 lo_freq_idx);
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int32 is_xo_cs_calibed(void);
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int32 is_xo_cto_calibed(void);
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int32 xo_cs_store(uint8 xo_cs_val);
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int32 sysctrl_get_xo_drcs(void);
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int32 sysctrl_set_xo_drcs(uint16 xo_drcs);
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void adc_cfg_reg_wr(uint8 addr, uint32 data);
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uint32 adc_cfg_reg_rd(uint8 addr);
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int32 is_adc_calibed(void);
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void adc_init(void);
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int32 adc_calib_res_store(void);
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void adc_calib_res_restore(void);
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void rfadc_calib_mode_soft_test(void);
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int32 sysctrl_err_resp_icode_bus(uint8 enable);
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int32 sysctrl_err_resp_dcode_bus(uint8 enable);
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int32 sysctrl_err_resp_ahb2dma_bus(uint8 enable);
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int32 sysctrl_err_resp_sdiodevice_bus(uint8 enable);
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int32 sysctrl_err_resp_disable(void);
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int32 sysctrl_get_chip_flash_size(void);
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int32 sysctrl_is_chipdcn_compid(void);
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/* 速率：x Bps */
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uint32_t sys_dma2ahb_bw_static(int32 printf_en);
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/* miss rate : 万分之x */
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uint32_t sys_csi_cache_static(int32 core_id, int32 printf_en);
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uint32_t sys_cld_cache_static(int32 printf_en);
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uint32_t sys_psram_eff_static(int32 printf_en);
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int32 sys_get_cpu_dcache_maint_both(void);
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int32 sys_get_cpu_dcache_enable(void);
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/** use when DMA source is psram
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* usage( this -> DMA kick)
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*/
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void sys_dcache_clean_range (uint32_t *addr, int32_t dsize);
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/* usefor TCPIP CHKSUM */
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void sys_dcache_clean_range_unaligned (uint32_t *addr, int32_t dsize);
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/** use when DMA destination is PSRAM
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* usage : ( this -> DMA) ;
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*/
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void sys_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize);
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void sys_dcache_clean_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
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/** use when DMA destination is PSRAM
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* Note：this function will auto writeback data head & tail (16/32byte unaligned)
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* 1.usage : ( DMA done-> this) ;
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* 2.Precondition: dma buffer addr & size is 16/32byte aligned
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* 3.DMA buffer size is not checked
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*/
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void sys_dcache_invalid_range (uint32_t *addr, int32_t dsize);
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/** use when DMA destination is PSRAM
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* Note：this function will auto writeback data head & tail (16/32byte unaligned)
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*/
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void sys_dcache_invalid_range_unaligned (uint32_t *addr, int32_t dsize);
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#ifdef __cplusplus
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}
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#endif
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#endif //__MISC_H__
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/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
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