119 lines
4.1 KiB
C
119 lines
4.1 KiB
C
/*
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* Copyright (C) 2018 Alibaba Group Holding Limited
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*/
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/*
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modification history
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--------------------
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14jan2018, init vesion
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*/
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#ifndef __cpu_pwr_hal_lib_h__
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#define __cpu_pwr_hal_lib_h__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "k_cpuset.h"
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#include "pwr_state.h"
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#include "dl_list.h"
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#include "k_err.h"
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/* defines */
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#define CPU_PWR_TOPO_LEVEL_ROOT 0
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#define CPU_PWR_TOPO_LEVEL_1 1
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#define CPU_PWR_TOPO_LEVEL_2 2
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#define CPU_PWR_TOPO_LEVEL_3 3
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#define CPU_PWR_TOPO_LEVEL_4 4
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#define CPU_PWR_TOPO_LEVEL_5 5
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#define CPU_PWR_NODE_NAME_LEN 64
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#define CPU_PWR_ROOT_NODE_NAME "cpu_pwr_root"
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#define CPU_STATE_BIT(n) (1 << (n))
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#define CPU_FREQ_UNKNOW (-1)
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#define CPU_VOLT_UNKNOW (-1)
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#define CPU_LATENCY_UNKNOW (-1)
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typedef struct
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{
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uint32_t state;
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uint32_t value;
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} state_val_pair_t;
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struct cpu_pwr;
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typedef kstat_t (*FUNC_CPU_PSTATE_SET) (struct cpu_pwr * p_cpu_node, uint32_t cpu_state);
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typedef kstat_t (*FUNC_CPU_CSTATE_SET) (uint32_t cpu_state, int master);
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typedef kstat_t (*FUNC_CPU_STATE_GET) (struct cpu_pwr * p_cpu_node, uint32_t * pCpuState);
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typedef struct cpu_pwr
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{
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uint32_t supportBitsetC;
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int stateNumC;
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state_val_pair_t * pPairLatency;
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atomic_val_t stateUpdatingC;
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cpu_cstate_t currentCState;
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cpu_cstate_t desireCState;
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FUNC_CPU_CSTATE_SET cpuCStateSetFunc;
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#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
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uint32_t supportBitsetP;
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int stateNumP;
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state_val_pair_t * pPairFreq;
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state_val_pair_t * pPairVolt;
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atomic_val_t stateUpdatingP;
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cpu_pstate_t currentPState;
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cpu_pstate_t desirePState;
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FUNC_CPU_PSTATE_SET cpuPStateSetFunc;
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#endif /* RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT */
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#ifdef RHINO_CONFIG_SMP
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cpuset_t childLiveCpuSet;
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uint32_t childIndexMask;
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#endif /* RHINO_CONFIG_SMP */
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char * name;
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uint32_t unit;
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uint32_t level;
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DL_NODE node;
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DL_LIST childList;
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struct cpu_pwr * pParent;
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} cpu_pwr_t;
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extern void cpu_pwr_hal_lib_init (void);
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extern void cpu_pwr_child_add (cpu_pwr_t * p_cpu_parent, cpu_pwr_t * pCpuChild);
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extern kstat_t cpu_pwr_node_init_static (uint32_t,char *,uint32_t,cpu_pwr_t *);
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extern kstat_t cpu_pwr_node_init_dyn (uint32_t,char*,uint32_t,cpu_pwr_t **);
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extern cpu_pwr_t * cpu_pwr_node_find_by_name (char * pName,uint32_t index);
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extern kstat_t cpu_pwr_leaf_node_record (cpu_pwr_t * p_cpu_node, uint32_t cpuIndex);
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extern kstat_t cpu_pwr_c_method_set_by_level (uint32_t level, FUNC_CPU_CSTATE_SET cpuCStateSetFunc);
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extern kstat_t cpu_pwr_c_state_capability_set (uint32_t cpuIndex, uint32_t supportBitsetC);
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extern kstat_t cpu_pwr_c_state_capability_set_by_level (uint32_t level, uint32_t supportBitsetC);
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extern kstat_t cpu_pwr_c_state_latency_save (uint32_t cpuIndex, cpu_cstate_t cpu_state, uint32_t latency);
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extern uint32_t cpu_pwr_c_state_latency_get (uint32_t cpuIndex, cpu_cstate_t CState);
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extern void cpu_pwr_child_index_mask_set (uint32_t, uint32_t);
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#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
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extern kstat_t cpu_pwr_p_method_set_by_level (uint32_t level, FUNC_CPU_PSTATE_SET cpuPStateSetFunc);
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extern kstat_t cpu_pwr_cur_p_state_update_directly (uint32_t cpuIndex, cpu_pstate_t cpuPState);
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extern kstat_t cpu_pwr_p_state_capability_set (uint32_t cpuIndex, uint32_t supportBitsetP);
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extern kstat_t cpu_pwr_p_state_capability_set_by_level (uint32_t level, uint32_t supportBitsetP);
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extern kstat_t cpu_pwr_freq_save (uint32_t cpuIndex, cpu_pstate_t cpu_state, uint32_t cpuFreq);
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extern kstat_t cpu_pwr_volt_save (uint32_t cpuIndex, cpu_pstate_t cpu_state, uint32_t cpuVolt);
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extern uint32_t cpu_pwr_freq_get_by_p_state (cpu_pwr_t * p_cpu_node, cpu_pstate_t PState);
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extern uint32_t cpu_pwr_volt_get_by_p_state (cpu_pwr_t * p_cpu_node, cpu_pstate_t PState);
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#endif /*RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __cpu_pwr_hal_lib_h__ */
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