Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
517
sdk/lib/sdhost/mmc_ops.c
Normal file
517
sdk/lib/sdhost/mmc_ops.c
Normal file
@@ -0,0 +1,517 @@
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#include "sys_config.h"
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#include "typesdef.h"
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#include "devid.h"
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#include "list.h"
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#include "dev.h"
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#include "osal/task.h"
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#include "osal/semaphore.h"
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#include "osal/mutex.h"
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#include "lib/sdhost/sdhost.h"
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#include "lib/sdhost/mmc.h"
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#include "hal/gpio.h"
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#include "osal/irq.h"
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#include "osal/string.h"
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#include "osal/mutex.h"
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#include "osal/irq.h"
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#include "osal/task.h"
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#include "osal/sleep.h"
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#include "osal/timer.h"
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#include "osal/work.h"
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#if 1
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#define EMMC_PRINTF(fmt, arg...) printf(fmt, ##arg)
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#else
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#define EMMC_PRINTF(fmt, arg...)
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#endif
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/*
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* Read extended CSD.
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*/
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int mmc_get_ext_csd(struct sdh_device *host, uint8_t *ext_csd)
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{
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int ret;
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struct rt_mmcsd_cmd cmd;
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struct rt_mmcsd_data data;
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if (GET_BITS(host->resp_csd, 122, 4) < 4) {
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EMMC_PRINTF("can't get ext csd\r\n");
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return 0;
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}
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/*
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* As the ext_csd is so large and mostly unused, we don't store the
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* raw block in mmc_card.
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*/
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memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
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memset(&data, 0, sizeof(struct rt_mmcsd_data));
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cmd.cmd_code = SEND_EXT_CSD;
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cmd.arg = 0;
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/* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
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* rely on callers to never use this with "native" calls for reading
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* CSD or CID. Native versions of those commands use the R2 type,
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* not R1 plus a data block.
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*/
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cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
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host->data.blksize = 512;
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host->data.blks = 1;
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host->data.flags = DATA_DIR_READ;
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host->data.buf = ext_csd;
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/*
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* Some cards require longer data read timeout than indicated in CSD.
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* Address this by setting the read timeout to a "reasonably high"
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* value. For the cards tested, 300ms has proven enough. If necessary,
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* this value can be increased if other problematic cards require this.
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*/
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host->data.timeout_ns = 300000000;
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host->data.timeout_clks = 0;
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ret = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd);
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if(ret) {
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EMMC_PRINTF("%s cmd error\r\n", __FUNCTION__);
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return 1;
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}
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ret = ((const struct sdhc_hal_ops *)host->dev.ops)->read(host, ext_csd);
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if (((const struct sdhc_hal_ops *)host->dev.ops)->complete)
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ret |= ((const struct sdhc_hal_ops *)host->dev.ops)->complete(host);
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if(ret) {
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return RET_ERR;
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}
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return 0;
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}
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int mmc_parse_ext_csd(struct sdh_device *host, uint8_t *ext_csd)
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{
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uint32_t card_capacity = 0;
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if (ext_csd == NULL)
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{
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EMMC_PRINTF("emmc parse ext csd fail, invaild args");
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return RET_ERR;
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}
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// uint8_t device_type = ext_csd[EXT_CSD_CARD_TYPE];
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// if ((host->flags & MMCSD_SUP_HS400) && (device_type & EXT_CSD_CARD_TYPE_HS400))
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// {
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// card->flags |= CARD_FLAG_HS400;
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// card->max_data_rate = 200000000;
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// }
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// else if ((host->flags & MMCSD_SUP_HS200) && (device_type & EXT_CSD_CARD_TYPE_HS200))
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// {
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// card->flags |= CARD_FLAG_HS200;
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// card->max_data_rate = 200000000;
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// }
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// else if ((host->flags & MMCSD_SUP_HIGHSPEED_DDR) && (device_type & EXT_CSD_CARD_TYPE_DDR_52))
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// {
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// card->flags |= CARD_FLAG_HIGHSPEED_DDR;
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// card->hs_max_data_rate = 52000000;
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// }
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// else
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// {
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// card->flags |= CARD_FLAG_HIGHSPEED;
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// card->hs_max_data_rate = 52000000;
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// }
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// host->flags |= CARD_FLAG_HIGHSPEED;
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// card->hs_max_data_rate = 52000000;
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// if (ext_csd[EXT_CSD_STROBE_SUPPORT] != 0)
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// {
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// card->ext_csd.enhanced_data_strobe = 1;
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// }
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// host->ext_csd.cache_size =
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// ext_csd[EXT_CSD_CACHE_SIZE + 0] << 0 |
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// ext_csd[EXT_CSD_CACHE_SIZE + 1] << 8 |
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// ext_csd[EXT_CSD_CACHE_SIZE + 2] << 16 |
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// ext_csd[EXT_CSD_CACHE_SIZE + 3] << 24;
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card_capacity = *((uint32_t*)&ext_csd[EXT_CSD_SEC_CNT]);
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card_capacity /= 2; //unit: KB
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host->card_capacity = card_capacity;
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EMMC_PRINTF("emmc card capacity %d KB, card sec count:0x%x \r\n", card_capacity, card_capacity*2);
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EMMC_PRINTF("bus mode: %d\r\n", ext_csd[EXT_CSD_BUS_WIDTH]);
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// switch (ext_csd[EXT_CSD_PART_CONFIG] & 7)
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// {
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// case 0:
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// EMMC_PRINTF("access default partition\r\n");
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// break;
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// case 1:
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// case 2:
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// EMMC_PRINTF("access boot partition-%d\r\n", (ext_csd[EXT_CSD_PART_CONFIG]&7));
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// break;
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// case 3:
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// EMMC_PRINTF("access RPMB partition\r\n");
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// break;
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// case 4:
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// case 5:
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// case 6:
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// case 7:
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// EMMC_PRINTF("access to gp partition-%d\r\n", (ext_csd[EXT_CSD_PART_CONFIG]&7) - 3);
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// break;
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// default:
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// EMMC_PRINTF("access to ?\r\n");
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// }
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return 0;
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}
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int mmc_switch(struct sdh_device *host, uint8_t set, uint8_t index, uint8_t value)
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{
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int err;
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struct rt_mmcsd_cmd cmd = {0};
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cmd.cmd_code = SWITCH;
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cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
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(index << 16) | (value << 8) | set;
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cmd.flags = RESP_R1B | CMD_AC;
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err = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd);
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if (err)
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return err;
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return 0;
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}
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int mmc_compare_ext_csds(struct sdh_device *host, uint8_t *ext_csd, uint32_t bus_width)
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{
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uint8_t *bw_ext_csd = NULL;
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int err = 0;
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if (bus_width == MMCSD_BUS_WIDTH_1)
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return 0;
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bw_ext_csd = os_malloc(512);
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if(!bw_ext_csd) {
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EMMC_PRINTF("%s malloc fail\r\n", __FUNCTION__);
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return RET_ERR;
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}
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err = mmc_get_ext_csd(host, bw_ext_csd);
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/* only compare read only fields */
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err = !((ext_csd[EXT_CSD_PARTITION_SUPPORT] == bw_ext_csd[EXT_CSD_PARTITION_SUPPORT]) &&
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(ext_csd[EXT_CSD_ERASED_MEM_CONT] == bw_ext_csd[EXT_CSD_ERASED_MEM_CONT]) &&
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(ext_csd[EXT_CSD_REV] == bw_ext_csd[EXT_CSD_REV]) &&
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(ext_csd[EXT_CSD_STRUCTURE] == bw_ext_csd[EXT_CSD_STRUCTURE]) &&
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(ext_csd[EXT_CSD_CARD_TYPE] == bw_ext_csd[EXT_CSD_CARD_TYPE]) &&
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(ext_csd[EXT_CSD_S_A_TIMEOUT] == bw_ext_csd[EXT_CSD_S_A_TIMEOUT]) &&
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(ext_csd[EXT_CSD_HC_WP_GRP_SIZE] == bw_ext_csd[EXT_CSD_HC_WP_GRP_SIZE]) &&
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(ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT] == bw_ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT]) &&
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(ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] == bw_ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) &&
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(ext_csd[EXT_CSD_SEC_TRIM_MULT] == bw_ext_csd[EXT_CSD_SEC_TRIM_MULT]) &&
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(ext_csd[EXT_CSD_SEC_ERASE_MULT] == bw_ext_csd[EXT_CSD_SEC_ERASE_MULT]) &&
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(ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT] == bw_ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT]) &&
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(ext_csd[EXT_CSD_TRIM_MULT] == bw_ext_csd[EXT_CSD_TRIM_MULT]) &&
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(ext_csd[EXT_CSD_SEC_CNT + 0] == bw_ext_csd[EXT_CSD_SEC_CNT + 0]) &&
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(ext_csd[EXT_CSD_SEC_CNT + 1] == bw_ext_csd[EXT_CSD_SEC_CNT + 1]) &&
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(ext_csd[EXT_CSD_SEC_CNT + 2] == bw_ext_csd[EXT_CSD_SEC_CNT + 2]) &&
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(ext_csd[EXT_CSD_SEC_CNT + 3] == bw_ext_csd[EXT_CSD_SEC_CNT + 3]) &&
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(ext_csd[EXT_CSD_PWR_CL_52_195] == bw_ext_csd[EXT_CSD_PWR_CL_52_195]) &&
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(ext_csd[EXT_CSD_PWR_CL_26_195] == bw_ext_csd[EXT_CSD_PWR_CL_26_195]) &&
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(ext_csd[EXT_CSD_PWR_CL_52_360] == bw_ext_csd[EXT_CSD_PWR_CL_52_360]) &&
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(ext_csd[EXT_CSD_PWR_CL_26_360] == bw_ext_csd[EXT_CSD_PWR_CL_26_360]) &&
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(ext_csd[EXT_CSD_PWR_CL_200_195] == bw_ext_csd[EXT_CSD_PWR_CL_200_195]) &&
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(ext_csd[EXT_CSD_PWR_CL_200_360] == bw_ext_csd[EXT_CSD_PWR_CL_200_360]) &&
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(ext_csd[EXT_CSD_PWR_CL_DDR_52_195] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_195]) &&
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(ext_csd[EXT_CSD_PWR_CL_DDR_52_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_52_360]) &&
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(ext_csd[EXT_CSD_PWR_CL_DDR_200_360] == bw_ext_csd[EXT_CSD_PWR_CL_DDR_200_360]));
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if (err)
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err = -RET_ERR;
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os_free(bw_ext_csd);
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return err;
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}
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int mmc_select_bus_width(struct sdh_device *host, uint8_t *ext_csd)
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{
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unsigned bus_width = 0;
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int err = 0;
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if (GET_BITS(host->resp_csd, 122, 4) < 4)
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return 0;
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/*
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* Unlike SD, MMC cards don't have a configuration register to notify
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* supported bus width. So bus test command should be run to identify
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* the supported bus width or compare the EXT_CSD values of current
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* bus width and EXT_CSD values of 1 bit mode read earlier.
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*/
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err = mmc_switch(host, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_BUS_WIDTH,
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EXT_CSD_BUS_WIDTH_4);
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//2就是EXT_CSD_BUS_WIDTH_4
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sd_set_bus_width(host, 2);
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err = mmc_compare_ext_csds(host, ext_csd, bus_width);
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if(err) {
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mmc_switch(host, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_BUS_WIDTH,
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EXT_CSD_BUS_WIDTH_1);
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//0就是EXT_CSD_BUS_WIDTH_1
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sd_set_bus_width(host, 0);
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err = mmc_compare_ext_csds(host, ext_csd, bus_width);
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if(err) {
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EMMC_PRINTF("%s dangenrous error ocurr\r\n", __FUNCTION__);
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}
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}
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EMMC_PRINTF("bus width: %d\r\n", 1 << host->io_cfg.bus_width);
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return err;
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}
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int mmc_set_card_addr(struct sdh_device *host, uint32_t rca)
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{
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int err;
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struct rt_mmcsd_cmd cmd;
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memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
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cmd.cmd_code = SET_RELATIVE_ADDR;
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cmd.arg = rca << 16;
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cmd.flags = RESP_R1 | CMD_AC;
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err = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd);
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if (err)
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return err;
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return 0;
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}
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int __send_status(struct sdh_device *host, uint32_t *status, unsigned retries)
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{
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int err;
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struct rt_mmcsd_cmd cmd;
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cmd.cmd_code = SEND_STATUS;
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cmd.arg = host->rca << 16;
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cmd.flags = RESP_R1 | CMD_AC;
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err = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd);
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if (err)
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return err;
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if (status)
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*status = cmd.resp[0];
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return 0;
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}
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int card_busy_detect(struct sdh_device *host, unsigned int timeout_ms,
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uint32_t *resp_errs)
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{
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int err = 0;
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uint32_t status;
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uint32_t start;
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uint32_t is_to;
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start = os_jiffies();
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do
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{
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is_to = (int)(os_jiffies() - start) > timeout_ms;
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err = __send_status(host, &status, 5);
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if (err)
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{
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EMMC_PRINTF("error %d requesting status", err);
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return err;
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}
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/* Accumulate any response error bits seen */
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if (resp_errs)
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*resp_errs |= status;
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if (is_to)
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{
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EMMC_PRINTF("wait card busy timeout");
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return -RET_ERR;
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}
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/*
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* Some cards mishandle the status bits,
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* so make sure to check both the busy
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* indication and the card state.
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*/
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}
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while (!(status & (1 << 8)) ||
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(((status & 0x00001E00) >> 9) == 7));
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return err;
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}
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int mmcsd_req_blk1(struct sdh_device *host,
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uint32_t sector,
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void *buf,
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uint32_t blks,
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uint8_t dir)
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{
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struct rt_mmcsd_cmd cmd, stop;
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uint32_t r_cmd, w_cmd;
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int err;
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memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
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memset(&stop, 0, sizeof(struct rt_mmcsd_cmd));
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cmd.arg = sector;
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if (!(host->flags & CARD_FLAG_SDHC))
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{
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cmd.arg <<= 9;
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}
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cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
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host->data.blksize = SECTOR_SIZE;
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host->data.blks = blks;
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stop.cmd_code = STOP_TRANSMISSION;
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stop.arg = 0;
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stop.flags = RESP_SPI_R1B | RESP_R1B | CMD_AC;
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r_cmd = READ_MULTIPLE_BLOCK;
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w_cmd = WRITE_MULTIPLE_BLOCK;
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if (host->flags & 0x8000)
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{
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/* last request is WRITE,need check busy */
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card_busy_detect(host, 10000, NULL);
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}
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if (!dir) {
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cmd.cmd_code = r_cmd;
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host->data.flags |= DATA_DIR_READ;
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host->flags &= 0x7fff;
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} else {
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cmd.cmd_code = w_cmd;
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host->data.flags |= DATA_DIR_WRITE;
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host->flags |= 0x8000;
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}
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host->data.buf = buf;
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host->data.blks = blks;
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err = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd);
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if(err) {
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EMMC_PRINTF("%s start err", __FUNCTION__);
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}
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if(!dir) {
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((const struct sdhc_hal_ops *)host->dev.ops)->read(host, buf);
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} else {
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((const struct sdhc_hal_ops *)host->dev.ops)->write(host, buf);
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}
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if(((const struct sdhc_hal_ops *)host->dev.ops)->complete) {
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((const struct sdhc_hal_ops *)host->dev.ops)->complete(host);
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}
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os_sleep_ms(1);
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err = ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &stop);
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||||
if(err) {
|
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EMMC_PRINTF("%s stop err", __FUNCTION__);
|
||||
}
|
||||
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return RET_OK;
|
||||
}
|
||||
|
||||
|
||||
int mmcsd_req_blk(struct sdh_device *host,
|
||||
uint32_t sector,
|
||||
void *buf,
|
||||
uint32_t blks,
|
||||
uint8_t dir)
|
||||
{
|
||||
struct rt_mmcsd_cmd cmd1, cmd2;
|
||||
uint32_t r_cmd, w_cmd;
|
||||
int err = 0;
|
||||
|
||||
memset(&cmd1, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
memset(&cmd2, 0, sizeof(struct rt_mmcsd_cmd));
|
||||
|
||||
cmd1.arg = sector;
|
||||
if (!(host->flags & CARD_FLAG_SDHC))
|
||||
{
|
||||
cmd1.arg <<= 9;
|
||||
}
|
||||
cmd1.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
|
||||
|
||||
r_cmd = READ_MULTIPLE_BLOCK;
|
||||
w_cmd = WRITE_MULTIPLE_BLOCK;
|
||||
|
||||
if (host->flags & 0x8000)
|
||||
{
|
||||
/* last request is WRITE,need check busy */
|
||||
card_busy_detect(host, 10000, NULL);
|
||||
}
|
||||
|
||||
if (!dir) {
|
||||
cmd1.cmd_code = r_cmd;
|
||||
host->sd_opt = SD_M_R;
|
||||
host->data.flags |= DATA_DIR_READ;
|
||||
host->flags &= 0x7fff;
|
||||
} else {
|
||||
cmd1.cmd_code = w_cmd;
|
||||
host->sd_opt = SD_M_W;
|
||||
host->data.flags |= DATA_DIR_WRITE;
|
||||
host->flags |= 0x8000;
|
||||
}
|
||||
|
||||
cmd2.cmd_code = SET_BLOCK_COUNT;
|
||||
cmd2.arg = blks;
|
||||
cmd2.flags = RESP_SPI_R1 | RESP_R1 | CMD_AC;
|
||||
|
||||
if(((const struct sdhc_hal_ops *)host->dev.ops)->cmd) {
|
||||
err |= ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd2);
|
||||
err |= ((const struct sdhc_hal_ops *)host->dev.ops)->cmd(host, &cmd1);
|
||||
}
|
||||
|
||||
|
||||
if(err) {
|
||||
EMMC_PRINTF("%s start err", __FUNCTION__);
|
||||
}
|
||||
|
||||
host->data.blksize = SECTOR_SIZE;
|
||||
host->data.buf = buf;
|
||||
host->data.blks = blks;
|
||||
|
||||
if(!dir) {
|
||||
((const struct sdhc_hal_ops *)host->dev.ops)->read(host, buf);
|
||||
} else {
|
||||
((const struct sdhc_hal_ops *)host->dev.ops)->write(host, buf);
|
||||
}
|
||||
|
||||
if(((const struct sdhc_hal_ops *)host->dev.ops)->complete) {
|
||||
((const struct sdhc_hal_ops *)host->dev.ops)->complete(host);
|
||||
}
|
||||
|
||||
return RET_OK;
|
||||
}
|
||||
|
||||
int mmc_cmdq_switch(struct sdh_device *host, bool enable)
|
||||
{
|
||||
uint8_t val = enable ? 1 : 0;
|
||||
int err;
|
||||
|
||||
#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
|
||||
|
||||
err = mmc_switch(host, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_CMDQ_MODE_EN, val);
|
||||
if (err)
|
||||
printf("cmdq switch fail %d\r\n", enable);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user