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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
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584
sdk/include/lib/lmac/hgic.h Normal file
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#ifndef _HUGE_IC_H_
#define _HUGE_IC_H_
#define HGIC_WDEV_ID_AP 0
#define HGIC_WDEV_ID_STA 1
#define HGIC_SCAN_MAX_NUM 32
#define HGIC_HDR_TX_MAGIC 0x1A2B
#define HGIC_HDR_RX_MAGIC 0x2B1A
#define HGIC_VENDOR_ID (0xA012)
#define HGIC_WLAN_AH_6001 (0x6001)
#define HGIC_WLAN_AH_4001 (0x4001)
#define HGIC_WLAN_AH_4002 (0x4002)
#define HGIC_WLAN_BGN_4102 (0x4102)
#define HGIC_WLAN_BGN_4103 (0x4103)
#define HGIC_WLAN_BGN_4104 (0x4104)
#define HGIC_WLAN_BGN_8400 (0x8400)
#define HGIC_CTRL_TIMEOUT 100
#define HGIC_CMD_PRIORITY 0
#define HGIC_TX_WINDOW 20
#define HGIC_TX_COOKIE_MASK 0x7FFF
#define HGIC_BLOCK_ACK_CNT 256
#define HGIC_BOOTDL_CMD_ENTER (0x00)
#define HGIC_BOOTDL_CMD_WRITE_MEM (0x02)
#define HGIC_BOOTDL_CMD_RUN (0x04)
#define HGIC_BOOTDL_RSP_ERR_IN_FW (0xFF)
#define hgic_dbg(fmt, ...) //os_printf("%s:%d::"fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__)
#define hgic_err(fmt, ...) os_printf(fmt, ##__VA_ARGS__)
#define hgic_enter() os_printf("enter %s\n", __FUNCTION__)
#define hgic_leave() os_printf("leave %s\n", __FUNCTION__)
#define HGIC_CMD_TIMEOUT 100
#define HGIC_TX_TIMEOUT 10
enum hgic_dev_flags {
HGIC_DEV_FLAGS_STOP = BIT(0),
HGIC_DEV_FLAGS_RUNNING = BIT(1),
};
enum hgic_bus_type {
HGIC_BUS_SDIO = 0x1,
HGIC_BUS_USB,
HGIC_BUS_HWSIM,
HGIC_BUS_WFOE,
};
enum hgic_cmd {
HGIC_CMD_DEV_OPEN = 1,
HGIC_CMD_DEV_CLOSE = 2,
HGIC_CMD_SET_MAC = 3,
HGIC_CMD_SET_SSID = 4,
HGIC_CMD_SET_BSSID = 5,
HGIC_CMD_SET_COUNTRY = 6,
HGIC_CMD_SET_CHANNEL = 7,
HGIC_CMD_SET_CENTER_FREQ = 8,
HGIC_CMD_SET_RTS_THRESHOLD = 9,
HGIC_CMD_SET_FRG_THRESHOLD = 10,
HGIC_CMD_SET_KEY_MGMT = 11,
HGIC_CMD_SET_WPA_PSK = 12,
HGIC_CMD_SET_KEY = 13,
HGIC_CMD_SCAN = 14,
HGIC_CMD_GET_SCAN_LIST = 15,
HGIC_CMD_SET_BSSID_FILTER = 16,
HGIC_CMD_DISCONNECT = 17,
HGIC_CMD_GET_BSSID = 18,
HGIC_CMD_SET_WBNAT = 19,
HGIC_CMD_GET_STATUS = 20,
HGIC_CMD_SET_LISTEN_INTERVAL = 21,
HGIC_CMD_SET_TX_POWER = 22,
HGIC_CMD_GET_TX_POWER = 23,
HGIC_CMD_SET_TX_LCOUNT = 24,
HGIC_CMD_SET_TX_SCOUNT = 25,
HGIC_CMD_ADD_STA = 26,
HGIC_CMD_REMOVE_STA = 27,
HGIC_CMD_SET_TX_BW = 28,
HGIC_CMD_SET_TX_MCS = 29,
HGIC_CMD_SET_FREQ_RANGE = 30,
HGIC_CMD_ACS_ENABLE = 31,
HGIC_CMD_SET_PRIMARY_CHAN = 32,
HGIC_CMD_SET_BG_RSSI = 33,
HGIC_CMD_SET_BSS_BW = 34,
HGIC_CMD_TESTMODE_CMD = 35,
HGIC_CMD_SET_AID = 36,
HGIC_CMD_GET_FW_STATE = 37,
HGIC_CMD_SET_TXQ_PARAM = 38,
HGIC_CMD_SET_CHAN_LIST = 39,
HGIC_CMD_GET_CONN_STATE = 40,
HGIC_CMD_SET_WORK_MODE = 41,
HGIC_CMD_SET_PAIRED_STATIONS = 42,
HGIC_CMD_GET_FW_INFO = 43,
HGIC_CMD_PAIRING = 44,
HGIC_CMD_GET_TEMPERATURE = 45,
HGIC_CMD_ENTER_SLEEP = 46,
HGIC_CMD_OTA = 47,
HGIC_CMD_GET_SSID = 48,
HGIC_CMD_GET_WPA_PSK = 49,
HGIC_CMD_GET_SIGNAL = 50,
HGIC_CMD_GET_TX_BITRATE = 51,
HGIC_CMD_SET_BEACON_INT = 52,
HGIC_CMD_GET_STA_LIST = 53,
HGIC_CMD_SAVE_CFG = 54,
HGIC_CMD_JOIN_GROUP = 55,
HGIC_CMD_SET_ETHER_TYPE = 56,
HGIC_CMD_GET_STA_COUNT = 57,
HGIC_CMD_SET_HEARTBEAT_INT = 58,
HGIC_CMD_SET_MCAST_KEY = 59,
HGIC_CMD_SET_AGG_CNT = 60,
HGIC_CMD_GET_AGG_CNT = 61,
HGIC_CMD_GET_BSS_BW = 62,
HGIC_CMD_GET_FREQ_RANGE = 63,
HGIC_CMD_GET_CHAN_LIST = 64,
HGIC_CMD_RADIO_ONOFF = 65,
HGIC_CMD_SET_PS_HEARTBEAT = 66,
HGIC_CMD_SET_WAKEUP_STA = 67,
HGIC_CMD_SET_PS_HEARTBEAT_RESP = 68,
HGIC_CMD_SET_PS_WAKEUP_DATA = 69,
HGIC_CMD_SET_PS_CONNECT = 70,
HGIC_CMD_SET_BSS_MAX_IDLE = 71,
HGIC_CMD_SET_WKIO_MODE = 72,
HGIC_CMD_SET_DTIM_PERIOD = 73,
HGIC_CMD_SET_PS_MODE = 74,
HGIC_CMD_LOAD_DEF = 75,
HGIC_CMD_DISASSOC_STA = 76,
HGIC_CMD_SET_APLOST_TIME = 77,
HGIC_CMD_GET_WAKEUP_REASON = 78,
HGIC_CMD_UNPAIR = 79,
HGIC_CMD_SET_AUTO_CHAN_SWITCH = 80,
HGIC_CMD_SET_REASSOC_WKHOST = 81,
HGIC_CMD_SET_WAKEUP_IO = 82,
HGIC_CMD_DBGINFO_OUTPUT = 83,
HGIC_CMD_SET_SYSDBG = 84,
HGIC_CMD_SET_AUTO_SLEEP_TIME = 85,
HGIC_CMD_GET_KEY_MGMT = 86,
HGIC_CMD_SET_PAIR_AUTOSTOP = 87,
HGIC_CMD_SET_SUPER_PWR = 88,
HGIC_CMD_SET_REPEATER_SSID = 89,
HGIC_CMD_SET_REPEATER_PSK = 90,
HGIC_CMD_CFG_AUTO_SAVE = 91,
HGIC_CMD_SEND_CUST_MGMT = 92,
HGIC_CMD_GET_BATTERY_LEVEL = 93,
HGIC_CMD_SET_DCDC13 = 94,
HGIC_CMD_SET_ACKTMO = 95,
HGIC_CMD_GET_MODULETYPE = 96,
HGIC_CMD_PA_PWRCTRL_DIS = 97,
HGIC_CMD_SET_DHCPC = 98,
HGIC_CMD_GET_DHCPC_RESULT = 99,
HGIC_CMD_SET_WKUPDATA_MASK = 100,
HGIC_CMD_GET_WKDATA_BUFF = 101,
HGIC_CMD_GET_DISASSOC_REASON = 102,
HGIC_CMD_SET_WKUPDATA_SAVEEN = 103,
HGIC_CMD_SET_CUST_DRIVER_DATA = 104,
HGIC_CMD_SET_MCAST_TXPARAM = 105,
HGIC_CMD_SET_STA_FREQINFO = 106,
HGIC_CMD_SET_RESET_STA = 107,
HGIC_CMD_SET_UART_FIXLEN = 108,
HGIC_CMD_GET_UART_FIXLEN = 109,
HGIC_CMD_SET_ANT_AUTO = 110,
HGIC_CMD_SET_ANT_SEL = 111,
HGIC_CMD_GET_ANT_SEL = 112,
HGIC_CMD_SET_WKUP_HOST_REASON = 113,
HGIC_CMD_SET_MAC_FILTER_EN = 114,
HGIC_CMD_SET_ATCMD = 115,
HGIC_CMD_SET_ROAMING = 116,
HGIC_CMD_SET_AP_HIDE = 117,
HGIC_CMD_SET_DUAL_ANT = 118,
HGIC_CMD_SET_MAX_TCNT = 119,
HGIC_CMD_SET_ASSERT_HOLDUP = 120,
HGIC_CMD_SET_AP_PSMODE_EN = 121,
HGIC_CMD_SET_DUPFILTER_EN = 122,
HGIC_CMD_SET_DIS_1V1_M2U = 123,
HGIC_CMD_SET_DIS_PSCONNECT = 124,
HGIC_CMD_SET_RTC = 125,
HGIC_CMD_GET_RTC = 126,
HGIC_CMD_SET_KICK_ASSOC = 127,
HGIC_CMD_START_ASSOC = 128,
HGIC_CMD_SET_AUTOSLEEP = 129,
HGIC_CMD_SET_BLENC_DATA = 130,
HGIC_CMD_SET_BLENC_EN = 131,
HGIC_CMD_RESET = 132,
HGIC_CMD_SET_HWSCAN = 133,
HGIC_CMD_GET_TXQ_PARAM = 134,
HGIC_CMD_SET_PROMISC = 135,
HGIC_CMD_SET_USER_EDCA = 136,
HGIC_CMD_SET_FIX_TXRATE = 137,
HGIC_CMD_SET_NAV_MAX = 138,
HGIC_CMD_CLEAR_NAV = 139,
HGIC_CMD_SET_CCA_PARAM = 140,
HGIC_CMD_SET_TX_MODGAIN = 141,
HGIC_CMD_GET_NAV = 142,
HGIC_CMD_SET_BEACON_START = 143,
HGIC_CMD_SET_BLE_OPEN = 144,
HGIC_CMD_GET_MODE = 145,
HGIC_CMD_GET_BGRSSI = 146,
HGIC_CMD_SET_BLENC_ADVDATA = 147,
HGIC_CMD_SET_BLENC_SCANRESP = 148,
HGIC_CMD_SET_BLENC_DEVADDR = 149,
HGIC_CMD_SET_BLENC_ADVINTERVAL = 150,
HGIC_CMD_SET_BLENC_STARTADV = 151,
HGIC_CMD_SET_RTS_DURATION = 152,
HGIC_CMD_STANDBY_CFG = 153,
HGIC_CMD_SET_CONNECT_PAIRONLY = 154,
HGIC_CMD_SET_DIFFCUST_CONN = 155,
HGIC_CMD_GET_CENTER_FREQ = 156,
HGIC_CMD_SET_WAIT_PSMODE = 157,
HGIC_CMD_SET_AP_CHAN_SWITCH = 158,
HGIC_CMD_SET_CCA_FOR_CE = 159,
HGIC_CMD_SET_DISABLE_PRINT = 160,
HGIC_CMD_SET_APEP_PADDING = 161,
HGIC_CMD_GET_ACS_RESULT = 162,
HGIC_CMD_GET_WIFI_STATUS_CODE = 163,
HGIC_CMD_GET_WIFI_REASON_CODE = 164,
HGIC_CMD_SET_WATCHDOG = 165,
HGIC_CMD_SET_RETRY_FALLBACK_CNT = 166,
HGIC_CMD_SET_FALLBACK_MCS = 167,
HGIC_CMD_GET_XOSC_VALUE = 168,
HGIC_CMD_SET_XOSC_VALUE = 169,
HGIC_CMD_GET_FREQ_OFFSET = 170,
HGIC_CMD_SET_CALI_PERIOD = 171,
HGIC_CMD_SET_BLENC_ADVFILTER = 172,
HGIC_CMD_SET_MAX_TX_DELAY = 173,
HGIC_CMD_GET_STA_INFO = 174,
HGIC_CMD_SEND_MGMTFRAME = 175,
HGIC_CMD_SET_POOL_MAXUSAGE = 176,
HGIC_CMD_SET_ICMP_MNTR = 177,
HGIC_CMD_SET_WIFI_PASSWD = 178,
HGIC_CMD_SET_WIFI_RPASSWD = 179,
HGIC_CMD_GET_CHIP_UUID = 180,
HGIC_CMD_SET_COEXIST_EN = 181,
HGIC_CMD_SET_THROUGHPUT_EN = 182,
HGIC_CMD_SET_PS_HBDATA_MASK = 183,
HGIC_CMD_SET_MEM_RECYCLE = 184,
HGIC_CMD_SET_HOST_MONITOR = 185,
HGIC_CMD_SET_DMA_SCATTER = 186,
HGIC_CMD_SET_BLE_LL_LENGTH = 187,
HGIC_CMD_SET_SLEEP_ROAMING = 188,
HGIC_CMD_SET_EDCA_LIMIT_MAX = 189,
HGIC_CMD_SET_EDCA_SLOT_TIME = 190,
HGIC_CMD_SET_EDCA_LIMIT_MIN = 191,
HGIC_CMD_SET_SIGNAL_THRESHOLD = 192,
HGIC_CMD_SET_ROAMING_BSSID = 193,
HGIC_CMD_GET_LINK_QUALITY = 194,
HGIC_CMD_SET_NAV_LIMIT_MAX = 195,
HGIC_CMD_SET_TXPOWER_MODE = 196,
HGIC_CMD_SET_DISABLE_BSS = 197,
HGIC_CMD_SET_RESP_IND = 198,
HGIC_CMD_SET_SHORT_GI = 199,
HGIC_CMD_SET_NDP_PROBE = 200,
HGIC_CMD_SET_CTRL_RESP_1M = 201,
HGIC_CMD_SET_AMPDU_EN = 202,
HGIC_CMD_SET_DUP_1M = 203,
};
enum hgic_event {
HGIC_EVENT_STATE_CHG = 1,
HGIC_EVENT_CH_SWICH = 2,
HGIC_EVENT_DISCONNECT_REASON = 3,
HGIC_EVENT_ASSOC_STATUS = 4,
HGIC_EVENT_SCANNING = 5,
HGIC_EVENT_SCAN_DONE = 6,
HGIC_EVENT_TX_BITRATE = 7,
HGIC_EVENT_PAIR_START = 8,
HGIC_EVENT_PAIR_SUCCESS = 9,
HGIC_EVENT_PAIR_DONE = 10,
HGIC_EVENT_CONECT_START = 11,
HGIC_EVENT_CONECTED = 12,
HGIC_EVENT_DISCONECTED = 13,
HGIC_EVENT_SIGNAL = 14,
HGIC_EVENT_DISCONNET_LOG = 15,
HGIC_EVENT_REQUEST_PARAM = 16,
HGIC_EVENT_TESTMODE_STATE = 17,
HGIC_EVENT_FWDBG_INFO = 18,
HGIC_EVENT_CUSTOMER_MGMT = 19,
HGIC_EVENT_SLEEP_FAIL = 20,
HGIC_EVENT_DHCPC_DONE = 21,
HGIC_EVENT_CONNECT_FAIL = 22,
HGIC_EVENT_CUST_DRIVER_DATA = 23,
HGIC_EVENT_UNPAIR_STA = 24,
HGIC_EVENT_BLENC_DATA = 25,
HGIC_EVENT_HWSCAN_RESULT = 26,
HGIC_EVENT_EXCEPTION_INFO = 27,
HGIC_EVENT_DSLEEP_WAKEUP = 28,
HGIC_EVENT_STA_MIC_ERROR = 29,
HGIC_EVENT_ACS_DONE = 30,
HGIC_EVENT_FW_INIT_DONE = 31,
HGIC_EVENT_ROAM_CONECTED = 32,
HGIC_EVENT_MGMT_FRAME = 33,
HGIC_EVENT_UNKNOWN_STA = 34,
HGIC_EVENT_ROAM_FAIL = 35,
HGIC_EVENT_BEACON_TX_DONE = 36,
HGIC_EVENT_WIFI_FATAL_ERR = 37,
};
enum HGIC_EXCEPTION_NUM {
HGIC_EXCEPTION_CPU_USED_OVERTOP = 1,
HGIC_EXCEPTION_HEAP_USED_OVERTOP = 2,
HGIC_EXCEPTION_WIFI_BUFFER_USED_OVERTOP = 3,
HGIC_EXCEPTION_TX_BLOCKED = 4,
HGIC_EXCEPTION_TXDELAY_TOOLONG = 5,
HGIC_EXCEPTION_STRONG_BGRSSI = 6,
HGIC_EXCEPTION_TEMPERATURE_OVERTOP = 7,
HGIC_EXCEPTION_WRONG_PASSWORD = 8,
};
struct hgic_exception_info {
int32 num;
union {
struct {
int32 max, avg, min;
} txdelay;
struct {
int32 max, avg, min;
} bgrssi;
struct {
int32 total, used;
} buffer_usage;
struct {
int32 total, used;
} heap_usage;
struct {
int32 temp;
} temperature;
} info;
};
enum hgic_testbox_cmd {
HGIC_TESTBOX_CMD_DEV_INIT = 1,
HGIC_TESTBOX_CMD_GD_TEST_START = 2,
HGIC_TESTBOX_CMD_GD_TX_FRM_TYPE = 3,
HGIC_TESTBOX_CMD_GD_TX_MCS = 4,
HGIC_TESTBOX_CMD_GD_TX_DELAY = 5,
HGIC_TESTBOX_CMD_GD_TX_START = 6,
HGIC_TESTBOX_CMD_GET_RSSI = 7,
HGIC_TESTBOX_CMD_GET_EVM = 8,
HGIC_TESTBOX_CMD_GET_BGRSSI = 9,
HGIC_TESTBOX_CMD_GET_FREQ_OFFSET = 10,
HGIC_TESTBOX_CMD_GET_DUT_MAC = 11,
HGIC_TESTBOX_CMD_SET_RSSI_RANGE = 12,
HGIC_TESTBOX_CMD_SET_FREQ_OFFSET_TH = 13,
HGIC_TESTBOX_CMD_SET_FREQ_CALI_EN = 14,
HGIC_TESTBOX_CMD_SET_WRITE_EFUSE_EN = 15,
HGIC_TESTBOX_CMD_DEV_OPEN = 16,
};
enum hgic_hdr_type {
HGIC_HDR_TYPE_ACK = 1,
HGIC_HDR_TYPE_FRM = 2,
HGIC_HDR_TYPE_CMD = 3,
HGIC_HDR_TYPE_EVENT = 4,
HGIC_HDR_TYPE_FIRMWARE = 5,
HGIC_HDR_TYPE_NLMSG = 6,
HGIC_HDR_TYPE_BOOTDL = 7,
HGIC_HDR_TYPE_TEST = 8,
HGIC_HDR_TYPE_FRM2 = 9,
HGIC_HDR_TYPE_TEST2 = 10,
HGIC_HDR_TYPE_SOFTFC = 11,
HGIC_HDR_TYPE_OTA = 12,
HGIC_HDR_TYPE_CMD2 = 13,
HGIC_HDR_TYPE_EVENT2 = 14,
HGIC_HDR_TYPE_BOOTDL_DATA = 15,
HGIC_HDR_TYPE_IFBR = 16,
HGIC_HDR_TYPE_BEACON = 17,
HGIC_HDR_TYPE_AGGFRM = 18,
HGIC_HDR_TYPE_BLUETOOTH = 19,
HGIC_HDR_TYPE_TESTBOX = 20,
HGIC_HDR_TYPE_MAX,
};
enum hgic_hdr_flags2 {
HGIC_HDR_FLAGS2_AFT_BEACON = BIT(0),
HGIC_HDR_FLAGS2_MGMT_ACK = BIT(1),
};
/*data packet header*/
struct hgic_hdr {
unsigned short magic;
unsigned char type;
unsigned char ifidx: 4, flags: 4;
unsigned short length;
unsigned short cookie;
} __packed;
struct hgic_rx_info {
uint8 band;
uint8 mcs: 4, bw: 4;
int8 evm;
int8 signal;
uint16 freq;
int16 freq_off;
uint8 rx_flags;
uint8 antenna: 4, moredata: 1, rev: 3;
uint8 vht_nss : 4, s1g_nss : 4;
uint8 vht_flag : 3, s1g_flag : 5;
};
struct hgic_tx_info {
uint8 band;
uint8 tx_bw;
uint8 tx_mcs;
uint8 freq_idx: 5, antenna: 3;
uint32 tx_flags;
uint16 tx_flags2;
uint8 priority;
uint8 tx_power;
};
#ifndef CONFIG_UMAC
enum ieee80211_key_flags {
IEEE80211_KEY_FLAG_GENERATE_IV_MGMT = BIT(0),
IEEE80211_KEY_FLAG_GENERATE_IV = 1 << 1,
IEEE80211_KEY_FLAG_GENERATE_MMIC = 1 << 2,
IEEE80211_KEY_FLAG_PAIRWISE = 1 << 3,
IEEE80211_KEY_FLAG_SW_MGMT_TX = 1 << 4,
IEEE80211_KEY_FLAG_PUT_IV_SPACE = 1 << 5,
IEEE80211_KEY_FLAG_RX_MGMT = 1 << 6,
IEEE80211_KEY_FLAG_GROUP_TX = BIT(7),
IEEE80211_KEY_FLAG_GROUP_RX = BIT(8),
};
#endif
struct hgic_key_conf {
unsigned int cipher;
unsigned int flags;
unsigned char keyidx;
unsigned char keylen;
unsigned char key[0];
};
struct hgic_sta_info {
unsigned char aid;
unsigned char ps: 1, rev: 7;
unsigned char addr[6];
signed char rssi;
signed char evm;
signed char tx_snr;
signed char rx_snr;
};
//当前链路质量
struct hgic_link_quality {
char bgrssi;
char rssi;
char evm;
char per;
int obss_stas;
int cca_busy[8]; // 1M,2M,4M,8M
};
struct hgic_frm_hdr {
struct hgic_hdr hdr;
union {
struct hgic_rx_info rx_info;
struct hgic_tx_info tx_info;
uint8 rev[24];
};
} __packed;
struct hgic_frm_hdr2 {
struct hgic_hdr hdr;
} __packed;
struct hgic_acs_ctl {
uint32 enable: 1, scan_ms: 8, chn_bitmap: 23;
};
struct hgic_acs_result{
uint32 freq;//KHz
uint8 sync_cnt;
int8 min;
int8 max;
int8 avg;
};
#define HDR_CMDID(ctl) ((ctl)->hdr.type==HGIC_HDR_TYPE_CMD2?(ctl)->cmd2.cmd_id:(ctl)->cmd.cmd_id)
#define HDR_CMDRESP(ctl) ((ctl)->hdr.type==HGIC_HDR_TYPE_CMD2?(ctl)->cmd2.status:(ctl)->cmd.status)
#define HDR_EVTID(ctl) ((ctl)->hdr.type==HGIC_HDR_TYPE_EVENT2?(ctl)->event2.event_id:(ctl)->event.event_id)
#define HDR_CMDID_SET(ctl, id) if(id>255){\
(ctl)->hdr.type =HGIC_HDR_TYPE_CMD2;\
(ctl)->cmd2.cmd_id = id;\
}else{\
(ctl)->hdr.type =HGIC_HDR_TYPE_CMD;\
(ctl)->cmd.cmd_id = id;\
}
#define HDR_EVTID_SET(ctl, id) if(id>255){\
(ctl)->hdr.type =HGIC_HDR_TYPE_EVENT2;\
(ctl)->event2.event_id = id;\
}else{\
(ctl)->hdr.type =HGIC_HDR_TYPE_EVENT;\
(ctl)->event.event_id = id;\
}
/*contro pakcet header*/
struct hgic_ctrl_hdr {
struct hgic_hdr hdr;
union {
struct {
unsigned char cmd_id;
short status;
} cmd;
struct {
unsigned short cmd_id;
short status;
} cmd2;
struct {
unsigned char event_id;
} event;
struct {
unsigned short event_id;
} event2;
struct {
unsigned char type;
} hci;
unsigned char info[4];
};
} __packed;
#define HGIC_CTRL_HDR_LEN (sizeof(struct hgic_ctrl_hdr))
//ack packet
struct hgic_dack_hdr {
struct hgic_hdr hdr;
uint16_t cookies[0];
} __packed;
struct hgic_bootdl_cmd_hdr {
struct hgic_hdr hdr;
unsigned char cmd;
unsigned char cmd_len;
unsigned char cmd_flag;
unsigned char addr[4];
unsigned char len[4];
unsigned char check;
} __packed;
struct hgic_bootdl_resp_hdr {
struct hgic_hdr hdr;
unsigned char cmd;
unsigned char rsp;
unsigned char rsp_data[4];
unsigned char reserved;
unsigned char check;
} __packed;
struct hgic_fw_info {
uint32 version;
uint32 svn_version;
uint16 chip_id;
uint16 cpuid;
uint8 mac[6];
uint8 resv[2]; //align 4 for app_version
uint32 app_version;
uint32 smt_dat;
} __packed;
struct hgic_bss_info {
uint8 bssid[6];
uint8 ssid[32];
uint8 encrypt;
int8 signal;
uint16 freq;
};
struct hgic_freqinfo {
uint8 bss_bw, chan_cnt;
uint16 freq_start, freq_end;
uint16 chan_list[16];
};
struct hgic_module_hwinfo {
union {
struct {
uint8 type;
uint8 saw: 1, rev: 7;
};
unsigned short v;
};
};
#endif

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sdk/include/lib/lmac/ieee802_11_ah_defs.h Normal file
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#ifndef IEEE802_11_AH_DEFS_H
#define IEEE802_11_AH_DEFS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <typesdef.h>
#include "ieee802_11_defs.h"
#define GET_FC(addr) get_unaligned_le16(addr)
#define GET_PV(addr) ((*(uint8 *)addr) & 0x03)
static const uint8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
//#define GET_TYPE_SUBTYPE(fc) (((fc) & 0x00fc) >> 2)
/* control */
#define WLAN_FC_STYPE_CTRL_WRAP 7
#define WLAN_FC_STYPE_BA_REQ 8
#define WLAN_FC_STYPE_BA 9
#define ACK_RXED_FLAG -1
#define BA_RXED_FLAG -2
#define WLAN_INVALID_SEQ_NUM 0xFFFF
#define WLAN_EID_EXT_QA_OPERATION (128)
#define MAC_ADDR_SIZE 6
#define COMPRESSED_S1G_SSID_MAX_LEN 4
#define SHORT_ID_MASK 0x00001fff
#define IEEE80211_QOS_CTL_TID_MASK 0x000f
#define IEEE80211_MORE_DATA_MASK 0x2000
enum _NDP_BW {
NDP_NONE = 0,
NDP_1MHZ = 1,
NDP_2MHZ = 2,
};
enum _DUP_EN {
DUP_DISABLE = 0,
DUP_ENABLE = 1,
};
/*
* same as struct ieee80211_rts, to be delete
*/
struct pv0_ctrl_rts {
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration;
uint8 ra[MAC_ADDR_SIZE];
uint8 ta[MAC_ADDR_SIZE];
};
struct short_id {
uint16 aid : 13,
a3p : 1,
a4p : 1,
amsdu : 1;
};
struct sid_mac {
struct short_id sid;
uint8 mac[MAC_ADDR_SIZE];
};
struct fromds0_addr {
uint8 a1[MAC_ADDR_SIZE];
struct short_id a2;
};
struct fromds1_addr {
struct short_id a1;
uint8 a2[MAC_ADDR_SIZE];
};
struct ieee80211_pv1_qos_data1 {
union {
uint16 frame_control;
IEEE80211_FRAME_CONTROL frm_ctrl;
} fc;
union {
struct fromds0_addr sta2ap;
struct fromds1_addr ap2sta;
} addr;
uint16 seq_ctrl;
};
struct ieee80211_pv1_ctrl_action {
union {
uint16 frame_control;
IEEE80211_FRAME_CONTROL frm_ctrl;
} fc;
union {
struct fromds0_addr sta2ap;
struct fromds1_addr ap2sta;
} addr;
uint16 seq_ctrl;
};
struct ieee80211_pv1_qos_data2 {
union {
uint16 val;
IEEE80211_FRAME_CONTROL frm_ctrl;
};
uint8 a1[MAC_ADDR_SIZE];
uint8 a2[MAC_ADDR_SIZE];
uint16 seq_ctrl;
};
// =====================================================================================
// NDP, D8, p.223, to be handled by PHY
//0 NDP CTS (control frame) 9.9.2.1 (NDP CTS)
//0 NDP CF-End (control frame) 9.9.2.2 (NDP CF-End)
//1 NDP PS-Poll (control frame) 9.9.2.3 (NDP PS-Poll)
//2 NDP Ack (control frame) 9.9.2.4 (NDP Ack)
//3 NDP PS-Poll-Ack (control frame) 9.9.2.5 (NDP PS-Poll-Ack)
//4 NDP BlockAck (control frame) 9.9.2.6 (NDP BlockAck)
//5 NDP Beamforming Report Poll (control frame)9.9.2.7 (NDP Beamforming Report Poll)
//6 NDP Paging (control frame) 9.9.2.8 (NDP Paging)
//7 NDP Probe Request (management frame)9.9.3.1 (NDP Probe Request)
//D8, p.276, p.278
// BSSID[39:47]mod(2^9-1) + 1
//(AID[0:8] + 2^5 * BSSID[44:47] (+) BSSID[40:43])mod 2^9
// D8, p.223
struct ndp_cmac_cts1m {
uint32 ndp_type : 3, // B0
cts_cfend_ind : 1, // B3, 0 = CTS, 1 = CF-END or RTS
addr_ind : 1, // B4, 0 = CTS resp to RTS, 1 = AP broadcast
ra_bssid : 9, // B5
duration : 10, //B14 in units of OFDM symbol duration (40 us)
early_sec_ind : 1, //B24, No BF = 0
unused : 7; // make it 32 bit;
};
struct ndp_cmac_cts2m {
uint64 ndp_type : 3, // B0
cts_cfend_ind : 1, // B3, 0 = CTS, 1 = CF-END or RTS
addr_ind : 1, // B4, 0 = CTS resp to RTS, 1 = AP broadcast
ra_bssid : 9, // B5, partial AID for receiving non-ap sta, partial
//bssid for receiving ap
duration : 15, //B14 microseconds nc ? 15 bits?
early_sec_ind : 1, //B29, No BF = 0
bw_ind : 3, //B30, 0=1MHz, 1=2MHz, 2=4MHz, 3=8MHz, 4=16MHz
rsvd : 4, //B33
unused : 27; // make it 64 bit
};
struct ndp_cmac_ack1m { // 2
uint32 ndp_type : 3, // B0
ack_id : 9, // B3
more_data : 1, //B12
idle_ind : 1, //B13
duration : 10, //B14 //idle_ind = 0: in units of 40us, =1:in milliseconds
relay_frame : 1, //B24
unused : 7; // make it 32 bit;
};
struct ndp_cmac_ack2m { // 2
uint64 ndp_type : 3, // B0
ack_id : 16, // B3
more_data : 1, //B19
idle_ind : 1, //B20
duration : 14, //B21
relay_frame : 1, //B35
reserved : 1, //B36
unused : 27; // make it 64 bit;
};
//D8, p.232
struct ndp_cmac_ba1m { // 4
uint32 ndp_type : 3, // B0
id : 2, // B3
start_sn : 12, // B5
bitmap : 8, //B17
unused : 7; // make it 32 bit;
};
struct ndp_cmac_ba2m { // 4
uint64 type : 3, // B0
id : 6, // B3
start_sn : 12, // B9
bitmap : 16, //B21
unused : 27; // make it 64 bit;
};
struct ndp_cmac_psp2m {
uint64 type : 3, // B0
ra : 9, // B3
ta : 9, // B12
preferred_mcs : 4, // B21
udi : 12;// B25, duration in units of 40us
};
struct ndp_cmac_pspack2m {
uint64 type : 3, // B0
ack_id : 16,// B3
more_data : 1, // B19
idle_ind : 1, // B20
duration : 16;// B21, duration in units of us
};
//D8, p.232
struct ndp_probe_req_1m { // 4
uint32 type : 3, // B0
cssid_ano_present : 1, // B3
cssid_ano : 16, // B4
probe_resp_type : 1, // B20
reserved : 4, // B24
unused : 7; // make it 32 bit;
};
struct ndp_probe_req_2m { // 4
uint64 type : 3, // B0
cssid_ano_present : 1, // B3
cssid_ano : 32, // B9
probe_resp_type : 1, //B21
unused : 27; // make it 64 bit;
};
struct ndp_cmac {
union {
struct ndp_cmac_cts1m cts1m;
struct ndp_cmac_cts2m cts2m;
struct ndp_cmac_ack1m ack1m;
struct ndp_cmac_ack2m ack2m;
struct ndp_cmac_ba1m ba1m;
struct ndp_cmac_ba2m ba2m;
struct ndp_cmac_psp2m psp2m;
struct ndp_cmac_pspack2m pspack2m;
//mgmt
struct ndp_probe_req_1m prob_req1m;
struct ndp_probe_req_2m prob_req2m;
uint64 frm_body; // NDP_1M = 25 bits, NDP_2M = 37 bits
};
} ;
enum _ndp_type {
NDP_CTS_CFEND = 0,
NDP_PS_POLL = 1,
NDP_ACK = 2,
NDP_PS_POLL_ACK = 3,
NDP_BA = 4,
NDP_BRP = 5,
NDP_PAGING = 6,
NDP_PROBE_REQ = 7,
};
struct key_iv {
uint8 rsvd : 5, // b0-4
ext_iv: 1, // b5 always 1 for ccmp
key_id: 2; // b6-8, key index, default = 0;
};
struct pv0_ccmp_hdr {
uint8 pn0;
uint8 pn1;
uint8 rsvd;
struct key_iv key_iv;
uint8 pn2;
uint8 pn3;
uint8 pn4;
uint8 pn5;
};
struct ccmp_aad_pv0 {
IEEE80211_FRAME_CONTROL fc;
uint8 a1[MAC_ADDR_SIZE];
uint8 a2[MAC_ADDR_SIZE];
uint8 a3[MAC_ADDR_SIZE];
int16 seq_ctrl;
uint8 options[8]; // a4 qos Optional
};
struct ccmp_aad_pv1 {
IEEE80211_FRAME_CONTROL fc;
uint8 a1[MAC_ADDR_SIZE];
uint8 a2[MAC_ADDR_SIZE];
int16 seq_ctrl;
uint8 options[12]; // a3 a4 Optional
};
struct nonce_flags {
uint8 priority : 4,
mgmt : 1,
pv1 : 1, //pv1 flag
zeros : 2;
};
struct ccmp_nonce {
struct nonce_flags flags; // b0-b3, b4-b7=0;
uint8 a2[MAC_ADDR_SIZE];
uint8 pn[6]; //pn0..5
};
static inline uint8 ieee80211_is_pv0(uint16 fc)
{
return ((fc & WLAN_FC_PVER) == 0x00);
}
/**
* 9.2.4.6.2 HT variant
**/
struct ht_control{
uint32 vht : 1,//b0
trq : 1,//b1 transmit a sounding PPDU
mai : 4,//b2~b5
mfsi : 3,//b6~b8
mfb_aselc : 7,//b9~b15
cali_pos : 2,//b16~b17
cali_seq : 2,//b18~b19
reserved1 : 2,//b20~b21
csi_steering : 2,//b22~b23
ndp_announce : 1,//b24
reserved2 : 4,//b25~b28
dei : 1,//b29
ac_constrain : 1,//b30
rdg : 1;//b31
};
/**
* reference 2016 9.2.4.6.3 VHT variant
* Figure 9-14a—MFB subfield in the VHT variant HT Control field when carried in S1G PPDU
* bw: Set to 0 for 1 MHz, 1 for 2 MHz, 2 for 4 MHz, 3 for 8 MHz
**/
struct vht_control{
uint32 vht : 1,//b0 VHT
reserved : 1,//b1 fix 0
mrq : 1,//b2 mcs req
msi_stbc : 3,//b3~b5
mfsi_gidl : 3,//b6~b8
num_sts : 2,//b9~b10
vht_mcs : 4,//b11~b14
bw : 3,//b15~b17
snr : 6,//b18~b23
gid_h : 3,//b24~b26
coding_type : 1,//b27
fb_tx_type : 1,//b28
unsolicited_mfb : 1,//b29
ac_constraint : 1,//b30
rdg_more_ppdu : 1;//b31
};
struct vs_qa_resp{
int8 rssi;
int8 evm;
int8 freq_dev;//KHz
uint8 agc; //last two
int8 bgrssi;
uint16 svn_version;
uint8 uni_test : 1,
sdk_bver : 4,
sdk_pver : 3;
}STRUCT_PACKED;
struct vs_qa_resp2{
int8 temperature;
uint8 vcc_meas : 6,
resv : 2;
};
struct pv0_ctrl_ba {
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration; //in microseconds(us)
uint8 ra[MAC_ADDR_SIZE];
uint8 ta[MAC_ADDR_SIZE];
uint16 ba_ack_policy : 1,
multi_tid : 1,
compressed_bitmap : 1,
gcr : 1,
reserved : 8,
tid_info : 4;
uint16 frag_num : 4,
start_seq : 12;
union{
uint64 bitmap;
struct vs_qa_resp qa_resp;
};
}STRUCT_PACKED;
struct pv0_wrapper_ctrl {
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration;
uint8 ra[MAC_ADDR_SIZE];
union {
uint16 cfc_val;
IEEE80211_FRAME_CONTROL carried_fc;
};
struct vht_control vht_ctrl;
}STRUCT_PACKED;
struct pv0_wrapper_ba {
struct pv0_wrapper_ctrl wp;
uint8 ta[MAC_ADDR_SIZE];
uint16 ba_ack_policy : 1,
multi_tid : 1,
compressed_bitmap : 1,
gcr : 1,
reserved : 8,
tid_info : 4;
uint16 frag_num : 4,
start_seq : 12;
union{
uint64 bitmap;
struct vs_qa_resp qa_resp;
};
}STRUCT_PACKED;
struct pv0_ctrl_wrapper_ba {
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration;
uint8 ra[MAC_ADDR_SIZE];
union {
uint16 cfc_val;
IEEE80211_FRAME_CONTROL carried_fc;
};
struct vht_control vht_ctrl;
uint8 ta[MAC_ADDR_SIZE];
uint16 ba_ack_policy : 1,
multi_tid : 1,
compressed_bitmap : 1,
gcr : 1,
reserved : 8,
tid_info : 4;
uint16 frag_num : 4,
start_seq : 12;
uint64 bitmap;
}STRUCT_PACKED;
//WLAN_FC_STYPE_QOS_DATA_CFPOLL
struct pv0_data_cf_poll{
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration; //in microseconds(us)
uint8 ra[MAC_ADDR_SIZE];
uint8 ta[MAC_ADDR_SIZE];
uint8 a3[MAC_ADDR_SIZE];
uint16 seq_ctrl;
uint16 tid:4, //qos control
eosp:1,
ack_policy:2,
reserved:1,
txop_limit:8;
struct vht_control vht_ctrl;
};
struct pv0_ctrl_cf_end{
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration; //in microseconds(us)
uint8 ra[MAC_ADDR_SIZE];//broad-cast
uint8 ta[MAC_ADDR_SIZE];//bssid
};
//qos null
struct pv0_data_qos_null{
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 duration; //in microseconds(us)
uint8 ra[MAC_ADDR_SIZE];//broad-cast
uint8 ta[MAC_ADDR_SIZE];//bssid
uint8 bssid[MAC_ADDR_SIZE];//bssid
uint16 seq_ctrl;
uint16 tid:4, //qos control
eosp:1,
ack_policy:2,
reserved:1,
txop_limit:8;
}STRUCT_PACKED;
//ps-poll
struct pv0_ctrl_pspoll{
union {
uint16 val;
IEEE80211_FRAME_CONTROL fc;
};
uint16 id; //associate ID
uint8 ra[MAC_ADDR_SIZE];//broad-cast
uint8 ta[MAC_ADDR_SIZE];//bssid
}STRUCT_PACKED;
struct pv0_ctrl_ack {
uint16 fc;
uint16 duration;
uint8 ra[MAC_ADDR_SIZE];
}__attribute__ ((__packed__));
/**
* struct ieee80211_channel_sw_ie
* This structure refers to "Channel Switch Announcement information element"
*/
struct ieee80211_channel_sw_ie {
uint8 eid;
uint8 len;
uint8 mode;
uint8 new_ch_num;
uint8 count;
} STRUCT_PACKED;
/**
* This structure refers to 9.4.2.5 CF Parameter Set element
*/
struct ieee80211_cf_parameter_set_ie {
uint8 eid;
uint8 len;
uint8 cfp_count;
uint8 cfp_period;
uint8 cfp_maxdur[2];//TU
uint8 cfp_durremain[2];
} STRUCT_PACKED;
/**
* This structure refers to 9.4.2.6 TIM element
*/
struct ieee80211_tim_ie {
uint8 dtim_count;
uint8 dtim_period;
uint8 bitmap_control;
uint8 partial_virtual_bitmap[1];
} STRUCT_PACKED;
struct ieee80211_s1g_tim_ie{
uint8 dtim_count;
uint8 dtim_period;
uint8 group_traffic_ind : 1,
page_slice_num : 5,
page_idx : 2;
uint8 block_control : 3,
block_offset : 5;
uint8 buff[0];
} STRUCT_PACKED;
struct noise_hist_req{
union{
uint16 freq; //hgic private
uint16 operating_class : 8,
channel_number : 8;
};
uint16 rand_interval;
uint16 meas_duration;
}STRUCT_PACKED;
/**
* reference: Figure 9-147--Measurement Request element format
**/
struct ieee80211_measure_req_ie {
uint8 eid;
uint8 len;
uint8 token;
uint8 parallel : 1,
enable : 1,
request : 1,
report : 1,
dur_mandatory : 1,
reserved : 3;
uint8 type;
} STRUCT_PACKED;
struct bgrssi_report_info {
uint8 freq[4];
int8 bgrssi_avg;
};
struct noise_hist_report{
union{
uint16 freq; //hgic private
uint8 operating_class : 8,
channel_number : 8;
};
uint8 actual_meas_start_time[8];
uint16 meas_dur;
uint8 antenna_id;
uint8 anpi;
uint8 ipi_density[11];
}STRUCT_PACKED;
/**
* reference: Figure 9-191--Measurement Report element format
**/
struct ieee80211_measure_report_ie {
uint8 eid;
uint8 len;
uint8 token;
uint8 late : 1,
incapable : 1,
refused : 1,
reserved : 3;
uint8 type;
//uint8 report[0];//variable
} STRUCT_PACKED;
/**
* struct ieee80211_ext_chansw_ie
*
* This structure represents the "Extended Channel Switch Announcement element"
*/
struct ieee80211_ext_chansw_ie {
uint8 eid;
uint8 len;
uint8 mode;
uint8 new_operating_class;
uint8 new_ch_num;
uint8 count;
} STRUCT_PACKED;
/**
* struct ieee80211_wide_bw_chansw_ie - wide bandwidth channel switch IE
*/
struct ieee80211_wide_bw_chansw_ie {
uint8 new_channel_width;
uint8 new_center_freq_seg0;
uint8 new_center_freq_seg1;
} STRUCT_PACKED;
struct pv0_mgmt_s1g_beacon{
struct {
uint16 protol_version : 2,
type : 2,
subtype : 4,
next_tbtt : 1,
comp_ssid : 1,
ano : 1,
bss_bw : 3,
security : 1,
ap_pm : 1;
};//oct 0~1
uint16 duration;//oct 2~3
uint8 sa[MAC_ADDR_SIZE];////oct 4~9
uint8 timestamp[4];//oct 10~13
uint8 change_sequence; //oct 14
uint8 next_target_beacon_trans_time[3]; //0ct 15~17
uint8 compressed_ssid[4];//0ct 18~21
uint8 access_network_opt;//0ct 22
}STRUCT_PACKED;
struct s1g_beacon_compatibility{
union {
uint16 compat_info;
uint16 ess : 1,
ibss : 1,
cf_pollable : 1,
cf_poll_req : 1,
privacy : 1,
short_preamble:1,
rsvd1 : 1,
rsvd2 : 1,
spectrum_mgmt:1,
qos : 1,
short_slot_time:1,
apsd : 1,
radio_measure:1,
rsvd3 : 1,
delay_ba : 1,
immediate_ba: 1;
};
uint16 interval; //TU= 1024us
uint32 tsf_completion;
}STRUCT_PACKED;
struct vs_bss_announcement_ie{
int32 bss_freq;
int8 pri_chan;
int8 bss_bw;
int8 bg_rssi;//reserved: TODO: add bgrssi
int8 sta_num;
//uint8 ssid[32 + 4];
}STRUCT_PACKED;
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/lib/lmac/ieee802_11_defs.h Normal file
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#ifndef _HGIC_LMAC_H_
#define _HGIC_LMAC_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************************ for lmac rate ************************************/
#define LMAC_RATE_MCS_MASK 0xFF
#define LMAC_RATE_MCS_SHIFT 0
#define LMAC_RATE_NSS_MASK 0x0F
#define LMAC_RATE_NSS_SHIFT 8
#define LMAC_RATE_PHY_TYPE_MASK 0x3F
#define LMAC_RATE_PHY_TYPE_SHIFT 12
//PHY TYPE
#define LMAC_PHY_S1G 0
#define LMAC_PHY_DSSS_CCK 1
#define LMAC_PHY_NON_HT 2
#define LMAC_PHY_HT 3
//flags
#define LMAC_RATE_SHORT_PREAMBLE (1 << 24)
#define LMAC_RATE_SHORT_GI (1 << 24)
#define LMAC_RATE_GREEN_FILED (1 << 25)
//lmac rate define
#define LMAC_RATE_DEF(phy_type, nss, mcs, flags) ((((phy_type) & LMAC_RATE_PHY_TYPE_MASK) << LMAC_RATE_PHY_TYPE_SHIFT) | \
(((nss) & LMAC_RATE_NSS_MASK) << LMAC_RATE_NSS_SHIFT) | \
(((mcs) & LMAC_RATE_MCS_MASK) << LMAC_RATE_MCS_SHIFT) | (flags))
/***************************************************************************************/
//FEM chip support
#define LMAC_FEM_POWER_5V BIT(16) //FEM uses 5V power supply
#define LMAC_FEM_NONE 0
#define LMAC_FEM_GSR2401C 1
#define LMAC_FEM_GSR2701 2
#define LMAC_FEM_GSR2701_3_3V LMAC_FEM_GSR2701
#define LMAC_FEM_GSR2701_5V (LMAC_FEM_GSR2701_3_3V | LMAC_FEM_POWER_5V)
#define LMAC_FEM_KCT8227D_1_SWITCH 3
#define LMAC_FEM_KCT8227D_1_SWITCH_3_3V LMAC_FEM_KCT8227D_1_SWITCH
#define LMAC_FEM_KCT8227D_1_SWITCH_5V (LMAC_FEM_KCT8227D_1_SWITCH | LMAC_FEM_POWER_5V)
#define LMAC_FEM_KCT8227D_NON_SWITCH 4
#define LMAC_FEM_KCT8227D_NON_SWITCH_3_3V LMAC_FEM_KCT8227D_NON_SWITCH
#define LMAC_FEM_KCT8227D_NON_SWITCH_5V (LMAC_FEM_KCT8227D_NON_SWITCH | LMAC_FEM_POWER_5V)
#define LMAC_FEM_KCT8227D_ADD_SWITCH 5
#define LMAC_FEM_KCT8227D_ADD_SWITCH_3_3V LMAC_FEM_KCT8227D_ADD_SWITCH
#define LMAC_FEM_KCT8227D_ADD_SWITCH_5V (LMAC_FEM_KCT8227D_ADD_SWITCH | LMAC_FEM_POWER_5V)
//FREQ offset tracking mode
#define LMAC_FREQ_OFFSET_TRACK_ALWAYS_ON 0
#define LMAC_FREQ_OFFSET_TRACK_ALWAYS_OFF 1
#define LMAC_FREQ_OFFSET_TRACK_ONLY_STA_ON 2
struct lmac_txq_param {
uint16 txop;
uint16 cw_min;
uint16 cw_max;
uint8 aifs;
uint8 acm;
};
struct lmac_init_param {
uint32 rxbuf, rxbuf_size;
uint32 tdma_buff, tdma_buff_size;
uint32 uart0_sel : 1;
};
struct lmac_acs_ctl {
uint32 enable: 1, scan_ms: 8, chn_bitmap: 23;
};
struct lmac_csa_scan_ctl {
uint32 chn_bitmap;
uint8 mode;
uint8 rounds; //The number of rounds to scan before switching channels.
uint8 scan_time; //Scan time per channel, in ms. Allowed range: 10~32.
uint8 period; //The number of beacons to pass before performing a channel scan.
uint8 csa_cnt; //CSA element count
uint8 debug_en; //enable debug print
};
struct lmac_cca_ctl {
int8 start_th;
int8 mid_th;
int8 ed_th;
/* CCA auto adjustment.
* When the cca automatic adjustment takes effect, the
* above three parameters are invalid.
*/
uint8 auto_en : 1;
};
struct lmac_wifi_ble_switch_ctl {
struct {
uint8 chan; //for ble
uint32 type; //for ble
} ble_priv;
/* only work for ap */
struct {
uint8 switch_time; //Switch time per beacon, in ms. Allowed range: 0~32.
uint8 period; //The number of beacons to pass before switching. 0 means no switching will take place.
/* User-defined content that will be passed as a parameter to the hdl function pointer. */
void *arg;
void (*hdl)(void *lmac_ops, void *arg);
} ap_ctl;
};
struct lmac_fallback_type {
uint8 type;
uint8 mcs;
uint8 gi; //for HT: 0 for LGI, 1 for SGI
uint8 bw; //0 for 20M, 1 for 40M
};
struct lmac_fallback_ctl {
struct lmac_fallback_type original;
struct lmac_fallback_type fallback;
};
enum LMAC_IOCTL_CMD {
/*Set CMDs*/
LMAC_IOCTL_SET_AGGCNT = 0x1,
LMAC_IOCTL_SET_BSS_BW,
LMAC_IOCTL_SET_TX_BW,
LMAC_IOCTL_SET_TX_MCS,
LMAC_IOCTL_SET_RTS_TH,
LMAC_IOCTL_SET_TXPOWER,
LMAC_IOCTL_SET_BSS_MAX_IDLE,
LMAC_IOCTL_SET_TX_ORDERED,
LMAC_IOCTL_SET_AUTO_CHAN_SWITCH,
LMAC_IOCTL_SET_PRI_CHAN,
LMAC_IOCTL_SET_RADIO_ONOFF,
LMAC_IOCTL_SET_PS_HEARBEAT,
LMAC_IOCTL_SET_PS_HEARBEAT_RESP,
LMAC_IOCTL_SET_PS_WAKEUP_DATA,
LMAC_IOCTL_SET_PS_HEARBEAT_PERIOD,
LMAC_IOCTL_SET_SSID,
LMAC_IOCTL_SET_WAKEUPIO_MODE,
LMAC_IOCTL_SET_PS_MODE,
LMAC_IOCTL_SET_SLEEP_APLOST_TIME,
LMAC_IOCTL_SET_SLEEP_WAKEIUP_IO,
LMAC_IOCTL_SET_SUPER_PWR,
LMAC_IOCTL_SET_PA_PWR_CTRL,
LMAC_IOCTL_SET_STA_ROAMING,
LMAC_IOCTL_SET_HW_SCAN,
LMAC_IOCTL_SET_COMPRESSED_SSID,
LMAC_IOCTL_SET_VDD13,
LMAC_IOCTL_SET_ACK_TIMEOUT_EXTRA,
LMAC_IOCTL_SET_TX_CNT_MAX,
LMAC_IOCTL_SET_SLEEP_GPIOA_RESV,
LMAC_IOCTL_SET_SLEEP_GPIOB_RESV,
LMAC_IOCTL_SET_SLEEP_GPIOC_RESV,
LMAC_IOCTL_SET_ENTER_SLEEP_CB,
LMAC_IOCTL_SET_KEEP_ALIVE_CB,
LMAC_IOCTL_SET_WAKE_UP_CB,
LMAC_IOCTL_SET_PSCONNECT_PERIOD,
LMAC_IOCTL_SET_MCAST_TX_RATE,
LMAC_IOCTL_SET_MCAST_TXBW,
LMAC_IOCTL_SET_MCAST_TXPOWER,
LMAC_IOCTL_SET_MCAST_DUP_TXCNT,
LMAC_IOCTL_SET_MCAST_CLEAR_CHN,
LMAC_IOCTL_SET_ANT_CTRL_PIN,
LMAC_IOCTL_SET_ANT_DUAL_EN,
LMAC_IOCTL_SET_ANT_AUTO_EN,
LMAC_IOCTL_SET_ANT_SEL,
LMAC_IOCTL_SET_REASSOCIATION,
LMAC_IOCTL_SET_APSLEEP_RC,
LMAC_IOCTL_SET_BSSID,
LMAC_IOCTL_SET_AP_PSMODE_EN,
LMAC_IOCTL_SET_WKSRC_DETECT,
LMAC_IOCTL_SET_RTC,
LMAC_IOCTL_SET_STANDBY,
LMAC_IOCTL_SET_WAIT_PSMODE,
LMAC_IOCTL_SET_CCA_FOR_CE,
LMAC_IOCTL_SET_RXG_OFFEST,
LMAC_IOCTL_SET_OBSS_EN,
LMAC_IOCTL_SET_OBSS_TH,
LMAC_IOCTL_SET_OBSS_PER,
LMAC_IOCTL_SET_BKN_TMO,
LMAC_IOCTL_SET_AID,
LMAC_IOCTL_SET_TXQ_PARAM,
LMAC_IOCTL_SET_MAC_ADDR,
LMAC_IOCTL_SET_MCAST_KEY,
LMAC_IOCTL_DEL_MCAST_KEY,
LMAC_IOCTL_SET_PROMISC_MODE,
LMAC_IOCTL_SET_STA_SUPP_RATE,
LMAC_IOCTL_SET_SUPP_RATE,
LMAC_IOCTL_SET_MAX_STA_CNT,
LMAC_IOCTL_SET_MAX_PS_FRAME,
LMAC_IOCTL_SET_TX_DUTY_CYCLE,
LMAC_IOCTL_SET_SSID_FILTER,
LMAC_IOCTL_SET_WPHY_DPD,
LMAC_IOCTL_SET_PREVENT_PS_MODE,
LMAC_IOCTL_SET_CSA_SCAN_CFG,
LMAC_IOCTL_SET_CSA_SCAN_START,
LMAC_IOCTL_SET_CSA_CHN_SWITCH_NOW,
LMAC_IOCTL_SET_TX_MODULATION_GAIN,
LMAC_IOCTL_SET_TX_EDCA_SLOT_TIME,
LMAC_IOCTL_SET_DBG_LEVEL,
LMAC_IOCTL_SET_FIX_TX_RATE,
LMAC_IOCTL_SET_NAV_MAX,
LMAC_IOCTL_CLR_NAV,
LMAC_IOCTL_SET_CCA,
LMAC_IOCTL_SET_FRAG_TH,
LMAC_IOCTL_SET_BEACON,
LMAC_IOCTL_SET_RTS_FIX_DURATION,
LMAC_IOCTL_SET_DSLEEP_BSS_MAX_IDLE,
LMAC_IOCTL_SET_DSLEEP_WKIO_PIN,
LMAC_IOCTL_SET_DSLEEP_WKIO_EDGE,
LMAC_IOCTL_SET_DSLEEP_APLOST_TIME,
LMAC_IOCTL_SET_DSLEEP_SENS_LEVEL,
LMAC_IOCTL_SET_DSLEEP_PWM_SEL,
LMAC_IOCTL_SET_DSLEEP_PWM_MODE,
LMAC_IOCTL_SET_WIFI_BLE_SWITCH_CFG,
LMAC_IOCTL_SET_WIFI_SWITCH_BLE,
LMAC_IOCTL_SET_BLE_SWITCH_WIFI,
LMAC_IOCTL_SET_RX_AGGCNT,
LMAC_IOCTL_SET_APEP_PADDING,
LMAC_IOCTL_SET_RETRY_FALLBACK_CNT,
LMAC_IOCTL_SET_FALLBACK_MCS,
LMAC_IOCTL_SET_XOSC,
LMAC_IOCTL_SET_FREQ_CALI_PERIOD,
LMAC_IOCTL_SET_MAX_TX_DELAY,
LMAC_IOCTL_SET_RX_DUP_FILTER,
LMAC_IOCTL_SET_RX_REORDER,
LMAC_IOCTL_SET_RF_PWR_LEVEL,
LMAC_IOCTL_SET_RC_MCS_MASK,
LMAC_IOCTL_SET_RC_TYPE,
LMAC_IOCTL_SET_PSRAM_USED,
LMAC_IOCTL_SET_HW_HT_CAP,
LMAC_IOCTL_SET_FEM,
LMAC_SETCFG_SET_SLEEP_ROAMING,
LMAC_IOCTL_SET_TX_DMA_WAIT_EMPTY,
LMAC_IOCTL_SET_PWRLIMIT_MAX_LIMIT,
LMAC_IOCTL_SET_PWRLIMIT_EN,
LMAC_IOCTL_SET_PWRLIMIT_ACTUAL_PWR,
LMAC_IOCTL_SET_PWRLIMIT_GAIN,
LMAC_IOCTL_SET_PWRLIMIT_GAIN_TABLE,
LMAC_IOCTL_SET_EDCA_MAX,
LMAC_IOCTL_SET_TEMPERATURE_COMPESATE_TYPE,
LMAC_IOCTL_SET_RX_DMA_KICK_THRESHOLD,
LMAC_IOCTL_SET_RF_TX_DIGITAL_GAIN,
LMAC_IOCTL_SET_STA_CONNECTED,
LMAC_IOCTL_SET_FREQ_OFFSET_TRACK_MODE,
LMAC_IOCTL_SET_TEMPERATURE_COMPESATE_EN,
LMAC_IOCTL_SET_EDCA_MIN,
LMAC_IOCTL_SET_HEARTBEAT_DATA,
LMAC_IOCTL_SET_START_ASYNC_ACS,
LMAC_IOCTL_SET_TEMP_COMPENSATION_TABLE,
LMAC_IOCTL_SET_PS_NO_FRM_LOSS_EN,
LMAC_IOCTL_SET_STA_CAPABILITES,
LMAC_IOCTL_SET_UPDATE_FEM_VOLTAGE,
LMAC_IOCTL_SET_TX_AGG_TID_BITMAP,
LMAC_IOCTL_SET_BEACON_MODULATION,
LMAC_IOCTL_SET_AFH_PERIOD,
/*Get CMDs*/
LMAC_IOCTL_GET_AGGCNT = 0x20000000,
LMAC_IOCTL_GET_BSS_BW,
LMAC_IOCTL_GET_TX_BW,
LMAC_IOCTL_GET_TX_MCS,
LMAC_IOCTL_GET_RTS_TH,
LMAC_IOCTL_GET_TXPOWER,
LMAC_IOCTL_GET_BSS_MAX_IDLE,
LMAC_IOCTL_GET_TX_ORDERED,
LMAC_IOCTL_GET_LO_FREQ,
LMAC_IOCTL_GET_QA_BW,
LMAC_IOCTL_GET_QA_MCS,
LMAC_IOCTL_GET_QA_PER,
LMAC_IOCTL_GET_AID,
LMAC_IOCTL_GET_PRI_CHAN,
LMAC_IOCTL_GET_MAC_ADDR,
LMAC_IOCTL_GET_BSS_ID,
LMAC_IOCTL_GET_BKN_INTERVAL,
LMAC_IOCTL_GET_DTIM_PERIOD,
LMAC_IOCTL_GET_SLEEP_USER_DATA_ADDR,
LMAC_IOCTL_GET_SLEEP_USER_DATA_LEN,
LMAC_IOCTL_GET_ANT_SEL,
LMAC_IOCTL_GET_BSS_LOAD,
LMAC_IOCTL_GET_RTC,
LMAC_IOCTL_GET_BKN_TMO,
LMAC_IOCTL_GET_SNR,
LMAC_IOCTL_GET_BGR,
LMAC_IOCTL_GET_PROMISC_MODE,
LMAC_IOCTL_GET_STA_SUPP_RATE,
LMAC_IOCTL_GET_SUPP_RATE,
LMAC_IOCTL_GET_MAX_STA_CNT,
LMAC_IOCTL_GET_BG_RSSI,
LMAC_IOCTL_GET_TXQ_PARAM,
LMAC_IOCTL_GET_STA_TX_MCS,
LMAC_IOCTL_GET_NAV,
LMAC_IOCTL_GET_STALIST,
LMAC_IOCTL_GET_RTCC,
LMAC_IOCTL_GET_RX_AGGCNT,
LMAC_IOCTL_GET_ACS_RESULT,
LMAC_IOCTL_GET_XOSC,
LMAC_IOCTL_GET_FREQ_OFFSET,
LMAC_IOCTL_GET_RF_DRV_CHECK,
LMAC_IOCTL_GET_RC_MCS_MASK,
LMAC_IOCTL_GET_RC_TYPE,
LMAC_IOCTL_GET_MODULE_TYPE,
LMAC_IOCTL_GET_ASYNC_ACS_RET,
LMAC_IOCTL_GET_STA_PER,
LMAC_IOCTL_GET_STA_TX_DELAY,
LMAC_IOCTL_GET_STA_TX_DATARATE,
};
enum LMAC_RATE {
/*** for AH ***/
LMAC_RATE_S1G_1_NSS_MCS0 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 0, 0),
LMAC_RATE_S1G_1_NSS_MCS1 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 1, 0),
LMAC_RATE_S1G_1_NSS_MCS2 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 2, 0),
LMAC_RATE_S1G_1_NSS_MCS3 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 3, 0),
LMAC_RATE_S1G_1_NSS_MCS4 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 4, 0),
LMAC_RATE_S1G_1_NSS_MCS5 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 5, 0),
LMAC_RATE_S1G_1_NSS_MCS6 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 6, 0),
LMAC_RATE_S1G_1_NSS_MCS7 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 7, 0),
LMAC_RATE_S1G_1_NSS_MCS10 = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 10, 0),
LMAC_RATE_S1G_1_NSS_MCS0_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 0, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS1_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 1, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS2_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 2, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS3_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 3, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS4_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 4, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS5_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 5, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS6_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 6, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS7_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 7, LMAC_RATE_SHORT_GI),
LMAC_RATE_S1G_1_NSS_MCS10_SGI = LMAC_RATE_DEF(LMAC_PHY_S1G, 1, 10, LMAC_RATE_SHORT_GI),
/*** for BGN ***/
//DSSS/CCK long preamble
LMAC_RATE_DSSS_CCK_RATE0 = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 0, 0), //RATE=1Mbps
LMAC_RATE_DSSS_CCK_RATE1 = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 1, 0), //RATE=2Mbps
LMAC_RATE_DSSS_CCK_RATE2 = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 2, 0), //RATE=5.5Mbps
LMAC_RATE_DSSS_CCK_RATE3 = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 3, 0), //RATE=11Mbps
//DSSS/CCK short preamble
LMAC_RATE_DSSS_CCK_RATE0_SHORT = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 1, LMAC_RATE_SHORT_PREAMBLE), //RATE=2Mbps
LMAC_RATE_DSSS_CCK_RATE1_SHORT = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 2, LMAC_RATE_SHORT_PREAMBLE), //RATE=5.5Mbps
LMAC_RATE_DSSS_CCK_RATE2_SHORT = LMAC_RATE_DEF(LMAC_PHY_DSSS_CCK, 1, 3, LMAC_RATE_SHORT_PREAMBLE), //RATE=11Mbps
//NON HT
LMAC_RATE_NON_HT_RATE0 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 0, 0),
LMAC_RATE_NON_HT_RATE1 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 1, 0),
LMAC_RATE_NON_HT_RATE2 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 2, 0),
LMAC_RATE_NON_HT_RATE3 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 3, 0),
LMAC_RATE_NON_HT_RATE4 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 4, 0),
LMAC_RATE_NON_HT_RATE5 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 5, 0),
LMAC_RATE_NON_HT_RATE6 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 6, 0),
LMAC_RATE_NON_HT_RATE7 = LMAC_RATE_DEF(LMAC_PHY_NON_HT, 1, 7, 0),
//HT MF long GI
LMAC_RATE_HT_MF_1_NSS_MCS0 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 0, 0),
LMAC_RATE_HT_MF_1_NSS_MCS1 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 1, 0),
LMAC_RATE_HT_MF_1_NSS_MCS2 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 2, 0),
LMAC_RATE_HT_MF_1_NSS_MCS3 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 3, 0),
LMAC_RATE_HT_MF_1_NSS_MCS4 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 4, 0),
LMAC_RATE_HT_MF_1_NSS_MCS5 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 5, 0),
LMAC_RATE_HT_MF_1_NSS_MCS6 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 6, 0),
LMAC_RATE_HT_MF_1_NSS_MCS7 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 7, 0),
//HT MF short GI
LMAC_RATE_HT_MF_1_NSS_MCS0_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 0, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS1_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 1, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS2_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 2, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS3_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 3, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS4_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 4, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS5_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 5, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS6_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 6, LMAC_RATE_SHORT_GI),
LMAC_RATE_HT_MF_1_NSS_MCS7_SGI = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 7, LMAC_RATE_SHORT_GI),
//HT GF
LMAC_RATE_HT_GF_1_NSS_MCS0 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 0, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS1 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 1, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS2 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 2, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS3 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 3, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS4 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 4, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS5 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 5, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS6 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 6, LMAC_RATE_GREEN_FILED),
LMAC_RATE_HT_GF_1_NSS_MCS7 = LMAC_RATE_DEF(LMAC_PHY_HT, 1, 7, LMAC_RATE_GREEN_FILED),
};
enum {
LMAC_CSA_MODE_MANUAL = 0, //Active scanning with automatic frequency switching.
LMAC_CSA_MODE_SEMI_AUTO = 1, //Active scanning, but no automatic frequency switching.
LMAC_CSA_MODE_AUTO = 2, //Neither active scanning nor automatic frequency switching.
};
#define lmac_set_aggcnt(ops, aggcnt) lmac_ioctl(ops, LMAC_IOCTL_SET_AGGCNT, (uint32)(aggcnt), 0)
#define lmac_get_aggcnt(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_AGGCNT, 0, 0)
#define lmac_set_rx_aggcnt(ops, aggcnt) lmac_ioctl(ops, LMAC_IOCTL_SET_RX_AGGCNT, (uint32)(aggcnt), 0)
#define lmac_get_rx_aggcnt(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_RX_AGGCNT, 0, 0)
#define lmac_set_bss_bw(ops, bss_bw) lmac_ioctl(ops, LMAC_IOCTL_SET_BSS_BW, (uint32)(bss_bw), 0)
#define lmac_get_bss_bw(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_BSS_BW, 0, 0)
#define lmac_set_tx_bw(ops, tx_bw) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_BW, (uint32)(tx_bw), 0)
#define lmac_get_tx_bw(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_TX_BW, 0, 0)
#define lmac_set_tx_mcs(ops, tx_mcs, type) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_MCS, (uint32)(tx_mcs), type)
#define lmac_get_tx_mcs(ops, addr, aid) lmac_ioctl(ops, LMAC_IOCTL_GET_TX_MCS, addr, aid)
#define lmac_set_rts(ops, rts_th) lmac_ioctl(ops, LMAC_IOCTL_SET_RTS_TH, (uint32)(rts_th), 0)
#define lmac_get_rts(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_RTS_TH, 0, 0)
#define lmac_set_txpower(ops, txpower) lmac_ioctl(ops, LMAC_IOCTL_SET_TXPOWER, (uint32)(txpower), 0)
#define lmac_get_txpower(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_TXPOWER, 0, 0)
#define lmac_set_bss_max_idle(ops, max_idle_tu) lmac_ioctl(ops, LMAC_IOCTL_SET_BSS_MAX_IDLE, (uint32)(max_idle_tu), 0)
#define lmac_get_bss_max_idle(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_BSS_MAX_IDLE, 0, 0)
#define lmac_set_strictly_ordered(ops, enable) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_ORDERED, (uint32)(enable), 0)
#define lmac_get_strictly_ordered(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_TX_ORDERED, 0, 0)
#define lmac_get_lo_freq(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_LO_FREQ, 0, 0)
#define lmac_set_pri_chan(ops, prichan) lmac_ioctl(ops, LMAC_IOCTL_SET_PRI_CHAN, (uint32)(prichan), 0)
#define lmac_get_pri_chan(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_PRI_CHAN, 0, 0)
#define lmac_set_aid(ops, ifidx, aid) lmac_ioctl(ops, LMAC_IOCTL_SET_AID, (uint32)(ifidx), (uint32)(aid))
#define lmac_get_aid(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_AID, 0, 0)
#define lmac_set_ssid(ops, ssid) lmac_ioctl(ops, LMAC_IOCTL_SET_SSID, (uint32)(ssid), 32)
#define lmac_set_wkio_mode(ops, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_WAKEUPIO_MODE, (uint32)(mode), 0)
#define lmac_set_ps_mode(ops, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_MODE, (uint32)(mode), 0)
#define lmac_set_sleep_aplost_time(ops, time) lmac_ioctl(ops, LMAC_IOCTL_SET_SLEEP_APLOST_TIME, (uint32)(time), 0)
#define lmac_set_auto_chan_switch(ops, disable) lmac_ioctl(ops, LMAC_IOCTL_SET_AUTO_CHAN_SWITCH, (uint32)(disable), 0)
#define lmac_set_wakeup_io(ops, io, edge) lmac_ioctl(ops, LMAC_IOCTL_SET_SLEEP_WAKEIUP_IO, (uint32)(io), (uint32)(edge))
#define lmac_set_super_pwr(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_SUPER_PWR, (uint32)(en), 0)
#define lmac_set_pa_pwr_ctrl(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_PA_PWR_CTRL, (uint32)(en), 0)
#define lmac_set_sta_roaming(ops, addr, en) lmac_ioctl(ops, LMAC_IOCTL_SET_STA_ROAMING, (uint32)(addr), (en))
#define lmac_set_hw_scan(ops, period, chan) lmac_ioctl(ops, LMAC_IOCTL_SET_HW_SCAN, (uint32)(period), (chan))
#define lmac_set_vdd13(ops, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_VDD13, (uint32)(mode), 0)
#define lmac_set_ack_timeout_extra(ops, val) lmac_ioctl(ops, LMAC_IOCTL_SET_ACK_TIMEOUT_EXTRA, (uint32)(val), 0)
#define lmac_set_retry_cnt(ops, frm_max, rts_max) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_CNT_MAX, (uint32)(frm_max), (uint32)(rts_max))
#define lmac_set_psconnect_period(ops, period) lmac_ioctl(ops, LMAC_IOCTL_SET_PSCONNECT_PERIOD, (uint32)(period), 0)
#define lmac_set_mcast_txmcs(ops, rate) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_TX_RATE, (uint32)(rate), 0)
#define lmac_set_mcast_txbw(ops, txbw) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_TXBW, (uint32)(txbw), 0)
#define lmac_set_mcast_txpower(ops, txpwr) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_TXPOWER, (uint32)(txpwr), 0)
#define lmac_set_mcast_dup_txcnt(ops, dupcnt) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_DUP_TXCNT, (uint32)(dupcnt), 0)
#define lmac_set_mcast_clear_chn(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_CLEAR_CHN, (uint32)(en), 0)
#define lmac_set_ant_dual_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_ANT_DUAL_EN, (uint32)(en), 0)
#define lmac_set_ant_ctrl_pin(ops, pin) lmac_ioctl(ops, LMAC_IOCTL_SET_ANT_CTRL_PIN, (uint32)(pin),0)
#define lmac_set_ant_auto_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_ANT_AUTO_EN, (uint32)(en), 0)
#define lmac_set_ant_sel(ops, sel) lmac_ioctl(ops, LMAC_IOCTL_SET_ANT_SEL, (uint32)(sel), 0)
#define lmac_get_ant_sel(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_ANT_SEL, 0, 0)
#define lmac_set_bssid(ops, bssid) lmac_ioctl(ops, LMAC_IOCTL_SET_BSSID, (uint32)(bssid), 0)
#define lmac_set_ap_psmode_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_AP_PSMODE_EN, (uint32)(en), 0)
#define lmac_set_wksrc_detect(ops, io, level) lmac_ioctl(ops, LMAC_IOCTL_SET_WKSRC_DETECT, (uint32)(io), (uint32)(level))
#define lmac_set_rtc(ops, rtc) lmac_ioctl(ops, LMAC_IOCTL_SET_RTC, (uint32)(rtc), 0)
#define lmac_get_rtc(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_RTC, 0, 0)
#define lmac_set_bkn_tmo(ops, val) lmac_ioctl(ops, LMAC_IOCTL_SET_BKN_TMO, (val), 0)
#define lmac_get_bkn_tmo(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_BKN_TMO, 0, 0)
#define lmac_get_sta_snr(ops, aid, snr) lmac_ioctl(ops, LMAC_IOCTL_GET_SNR, (aid), (snr))
#define lmac_set_reassociation(ops, aid, addr) lmac_ioctl(ops, LMAC_IOCTL_SET_REASSOCIATION, (uint32)(aid), (uint32)(addr))
#define lmac_get_bss_load(ops, bss_load) lmac_ioctl(ops, LMAC_IOCTL_GET_BSS_LOAD, (uint32)(bss_load), 0)
#define lmac_set_sleep_gpioa_resv(ops, resv) lmac_ioctl(ops, LMAC_IOCTL_SET_SLEEP_GPIOA_RESV, (uint32)(resv), 0)
#define lmac_set_sleep_gpiob_resv(ops, resv) lmac_ioctl(ops, LMAC_IOCTL_SET_SLEEP_GPIOB_RESV, (uint32)(resv), 0)
#define lmac_set_sleep_gpioc_resv(ops, resv) lmac_ioctl(ops, LMAC_IOCTL_SET_SLEEP_GPIOC_RESV, (uint32)(resv), 0)
#define lmac_get_sleep_user_data_addr(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_SLEEP_USER_DATA_ADDR, 0, 0)
#define lmac_get_sleep_user_data_len(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_SLEEP_USER_DATA_LEN, 0, 0)
#define lmac_set_enter_sleep_cb(ops, func) lmac_ioctl(ops, LMAC_IOCTL_SET_ENTER_SLEEP_CB, (uint32)(func), 0)
#define lmac_set_keep_alive_cb(ops, func) lmac_ioctl(ops, LMAC_IOCTL_SET_KEEP_ALIVE_CB, (uint32)(func), 0)
#define lmac_set_wake_up_cb(ops, func) lmac_ioctl(ops, LMAC_IOCTL_SET_WAKE_UP_CB, (uint32)(func), 0)
#define lmac_radio_onoff(ops, onoff) lmac_ioctl(ops, LMAC_IOCTL_SET_RADIO_ONOFF, (uint32)(onoff), 0)
#define lmac_get_qa_bw(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_QA_BW, 0, 0)
#define lmac_get_qa_mcs(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_QA_MCS, 0, 0)
#define lmac_get_qa_per(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_QA_PER, 0, 0)
#define lmac_set_ps_heartbeat(ops, ip, port) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_HEARBEAT, (uint32)(ip), (uint32)(port))
#define lmac_set_ps_heartbeat_resp(ops, data, size) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_HEARBEAT_RESP, (uint32)(data), (size))
#define lmac_set_ps_wakeup_data(ops, data, size) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_WAKEUP_DATA, (uint32)(data), (size))
#define lmac_set_ps_heartbeat_period(ops, period) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_HEARBEAT_PERIOD, (uint32)(period), 0)
#define lmac_set_mcast_key(ops, key, key_len) lmac_ioctl(ops, LMAC_IOCTL_SET_MCAST_KEY, (uint32)(key), (key_len))
#define lmac_set_txq_param(ops, ifidx, txq, param) lmac_ioctl(ops, LMAC_IOCTL_SET_TXQ_PARAM, (uint32)((ifidx)<<16|(txq)), (uint32)(param))
#define lmac_get_txq_param(ops, ifidx, txq, param) lmac_ioctl(ops, LMAC_IOCTL_GET_TXQ_PARAM, (uint32)((ifidx)<<16|(txq)), (uint32)(param))
#define lmac_set_mac_addr(ops, ifidx, addr) lmac_ioctl(ops, LMAC_IOCTL_SET_MAC_ADDR, (uint32)(ifidx), (uint32)(addr))
#define lmac_set_promisc_mode(ops, enable) lmac_ioctl(ops, LMAC_IOCTL_SET_PROMISC_MODE, (enable), 0)
#define lmac_get_promisc_mode(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_PROMISC_MODE, 0, 0)
#define lmac_set_sta_supp_rate(ops, addr, supp_rate) lmac_ioctl(ops, LMAC_IOCTL_SET_STA_SUPP_RATE, (uint32)(addr), (supp_rate))
#define lmac_get_sta_supp_rate(ops, addr) lmac_ioctl(ops, LMAC_IOCTL_GET_STA_SUPP_RATE, (uint32 *)(addr), 0)
#define lmac_set_supp_rate(ops, supp_rate) lmac_ioctl(ops, LMAC_IOCTL_SET_SUPP_RATE, (supp_rate), 0)
#define lmac_get_supp_rate(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_SUPP_RATE, 0, 0)
#define lmac_set_max_sta_cnt(ops, cnt) lmac_ioctl(ops, LMAC_IOCTL_SET_MAX_STA_CNT, (cnt), 0)
#define lmac_get_max_sta_cnt(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_MAX_STA_CNT, 0, 0)
#define lmac_set_max_ps_frame(ops, cnt) lmac_ioctl(ops, LMAC_IOCTL_SET_MAX_PS_FRAME, (cnt), 0)
#define lmac_set_tx_duty_cycle(ops, duty) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_DUTY_CYCLE, (duty), 0)
#define lmac_set_ssid_filter(ops, ssid, len) lmac_ioctl(ops, LMAC_IOCTL_SET_SSID_FILTER, (ssid), (len))
#define lmac_get_bg_rssi(ops, chn, bgr) lmac_ioctl(ops, LMAC_IOCTL_GET_BG_RSSI, (chn), (uint32)(bgr))
#define lmac_set_wphy_dpd(ops, param1) lmac_ioctl(ops, LMAC_IOCTL_SET_WPHY_DPD, (param1), 0)
#define lmac_set_prevent_ps_mode(ops, enable) lmac_ioctl(ops, LMAC_IOCTL_SET_PREVENT_PS_MODE, (enable), 0)
#define lmac_set_csa_scan_cfg(ops, cfg) lmac_ioctl(ops, LMAC_IOCTL_SET_CSA_SCAN_CFG, (uint32)(cfg), 0)
#define lmac_set_csa_chn_switch_now(ops) lmac_ioctl(ops, LMAC_IOCTL_SET_CSA_CHN_SWITCH_NOW, 0, 0)
#define lmac_set_csa_scan_start(ops) lmac_ioctl(ops, LMAC_IOCTL_SET_CSA_SCAN_START, 1, 0)
#define lmac_set_csa_scan_stop(ops) lmac_ioctl(ops, LMAC_IOCTL_SET_CSA_SCAN_START, 0, 0)
#define lmac_set_tx_modulation_gain(ops, table, size) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_MODULATION_GAIN, (uint32)(table), (size))
#define lmac_set_tx_edca_slot_time(ops, slot_us) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_EDCA_SLOT_TIME, (uint32)(slot_us), 0)
#define lmac_get_sta_txmcs(ops, addr) lmac_ioctl(ops, LMAC_IOCTL_GET_STA_TX_MCS, (uint32)(addr), 0)
#define lmac_set_dbg_levle(ops, level) lmac_ioctl(ops, LMAC_IOCTL_SET_DBG_LEVEL, (uint32)(level), 0)
#define lmac_set_fix_tx_rate(ops, rate) lmac_ioctl(ops, LMAC_IOCTL_SET_FIX_TX_RATE, (uint32)(rate), 0)
#define lmac_set_nav_max(ops, max) lmac_ioctl(ops, LMAC_IOCTL_SET_NAV_MAX, (uint32)(max), 0)
#define lmac_clr_nav(ops) lmac_ioctl(ops, LMAC_IOCTL_CLR_NAV, 0, 0)
#define lmac_get_nav(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_NAV, 0, 0)
#define lmac_set_cca(ops, p_cca_ctl) lmac_ioctl(ops, LMAC_IOCTL_SET_CCA, (uint32)(p_cca_ctl), 0)
#define lmac_set_frag_threshold(ops, frag) lmac_ioctl(ops, LMAC_IOCTL_SET_FRAG_TH, (uint32)(frag), 0)
#define lmac_set_beacon_start(ops, start) lmac_ioctl(ops, LMAC_IOCTL_SET_BEACON, (uint32)(start), 0)
#define lmac_get_sta_list(ops, stas, count) lmac_ioctl(ops, LMAC_IOCTL_GET_STALIST, (uint32)(stas), (count))
#define lmac_set_rts_fix_duration(ops, duration_us) lmac_ioctl(ops, LMAC_IOCTL_SET_RTS_FIX_DURATION, (int32)(duration_us), 0)
#define lmac_set_dsleep_max_idle(ops, max_idle_sec) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_BSS_MAX_IDLE, (uint32)(max_idle_sec), 0)
#define lmac_set_dsleep_wkio_pin(ops, pin_idx, pin_num) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_WKIO_PIN, (uint32)(pin_idx), (uint32)(pin_num))
#define lmac_set_dsleep_wkio_edge(ops, pin_idx, neg_edge) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_WKIO_EDGE, (uint32)(pin_idx), (uint32)(neg_edge))
#define lmac_set_dsleep_aplost_time(ops, t_sec) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_APLOST_TIME, (uint32)(t_sec), 0)
#define lmac_set_dsleep_sens_level(ops, sens_level) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_SENS_LEVEL, (uint32)(sens_level), 0)
#define lmac_set_dsleep_pwm_sel(ops, pwm_idx, pin_num) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_PWM_SEL, (uint32)(pwm_idx), (pin_num))
#define lmac_set_dsleep_pwm_mode(ops, pwm_idx, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_DSLEEP_PWM_MODE, (uint32)(pwm_idx), (mode))
#define lmac_set_wifi_ble_switch_cfg(ops, cfg) lmac_ioctl(ops, LMAC_IOCTL_SET_WIFI_BLE_SWITCH_CFG, (uint32)(cfg), 0)
#define lmac_wifi_switch_ble(ops) lmac_ioctl(ops, LMAC_IOCTL_SET_WIFI_SWITCH_BLE, 0, 0)
#define lmac_ble_switch_wifi(ops) lmac_ioctl(ops, LMAC_IOCTL_SET_BLE_SWITCH_WIFI, 0, 0)
#define lmac_get_rtcc(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_RTCC, 0, 0)
#define lmac_set_apep_padding(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_APEP_PADDING, (int32)(en), 0)
#define lmac_set_standby(ops, chn, time) lmac_ioctl(ops, LMAC_IOCTL_SET_STANDBY, (chn), (time))
#define lmac_set_wait_psmode(ops, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_WAIT_PSMODE, (mode), 0)
#define lmac_set_cca_for_ce(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_CCA_FOR_CE, (en), 0)
#define lmac_set_rxg_offest(ops, offset) lmac_ioctl(ops, LMAC_IOCTL_SET_RXG_OFFEST, (offset), 0)
#define lmac_set_obss_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_OBSS_EN, (en), 0)
#define lmac_set_obss_th(ops, th) lmac_ioctl(ops, LMAC_IOCTL_SET_OBSS_TH, (th), 0)
#define lmac_set_obss_per(ops, per) lmac_ioctl(ops, LMAC_IOCTL_SET_OBSS_PER, (per), 0)
#define lmac_get_acs_result(ops, result) lmac_ioctl(ops, LMAC_IOCTL_GET_ACS_RESULT, (uint32)(result), 0)
#define lmac_set_retry_fallback_cnt(ops, cnt) lmac_ioctl(ops, LMAC_IOCTL_SET_RETRY_FALLBACK_CNT, (uint32)(cnt), 0)
#define lmac_set_fallback_mcs(ops, p_fb_ctl) lmac_ioctl(ops, LMAC_IOCTL_SET_FALLBACK_MCS, (uint32)(p_fb_ctl), 0)
#define lmac_get_xosc(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_XOSC, 0, 0)
#define lmac_get_freq_offset(ops, addr) lmac_ioctl(ops, LMAC_IOCTL_GET_FREQ_OFFSET, (uint32)(addr), 0)
#define lmac_set_xosc(ops, xosc) lmac_ioctl(ops, LMAC_IOCTL_SET_XOSC, (uint32)(xosc), 0)
#define lmac_set_freq_cali_period(ops, period) lmac_ioctl(ops, LMAC_IOCTL_SET_FREQ_CALI_PERIOD, (uint32)(period), 0)
#define lmac_set_max_tx_delay(ops, time_ms) lmac_ioctl(ops, LMAC_IOCTL_SET_MAX_TX_DELAY, (uint32)(time_ms), 0)
#define lmac_set_rx_dup_filter(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_RX_DUP_FILTER, (uint32)(en), 0)
#define lmac_set_rx_reorder(ops, en, tmo_ms) lmac_ioctl(ops, LMAC_IOCTL_SET_RX_REORDER, (uint32)(en), (uint32)(tmo_ms))
#define lmac_set_rf_pwr_level(ops, level) lmac_ioctl(ops, LMAC_IOCTL_SET_RF_PWR_LEVEL, (uint32)(level), 0)
#define lmac_rf_drv_check(ops, id_ptr) lmac_ioctl(ops, LMAC_IOCTL_GET_RF_DRV_CHECK, (uint32)(id_ptr), 0)
#define lmac_rate_ctrl_mcs_mask(ops, mcs_mask) lmac_ioctl(ops, LMAC_IOCTL_SET_RC_MCS_MASK, (uint32)(mcs_mask), 0)
#define lmac_rate_ctrl_type(ops, type) lmac_ioctl(ops, LMAC_IOCTL_SET_RC_TYPE, (uint32)(type), 0)
#define lmac_set_psram_used(ops, tx_used, rx_used) lmac_ioctl(ops, LMAC_IOCTL_SET_PSRAM_USED, (uint32)((tx_used) | ((rx_used) << 16)), 0)
#define lmac_set_hw_ht_cap(ops, ht_cap) lmac_ioctl(ops, LMAC_IOCTL_SET_HW_HT_CAP, (uint32)(ht_cap), 0)
#define lmac_set_fem(ops, fem_chip) lmac_ioctl(ops, LMAC_IOCTL_SET_FEM, (uint32)(fem_chip), 0)
#define lmac_get_module_type(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_MODULE_TYPE, 0, 0)
#define lmac_set_sleep_roaming(ops, en, rssi) lmac_ioctl(ops, LMAC_SETCFG_SET_SLEEP_ROAMING, en, rssi)
#define lmac_set_tx_dma_wait_empty(ops, wait_empty) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_DMA_WAIT_EMPTY, (uint32)(wait_empty), 0)
#define lmac_set_pwrlimit_max_limit(ops, max_mdbm) lmac_ioctl(ops, LMAC_IOCTL_SET_PWRLIMIT_MAX_LIMIT, (uint32)(max_mdbm), 0)
#define lmac_set_pwrlimit_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_PWRLIMIT_EN, (uint32)(en), 0)
#define lmac_set_pwrlimit_actual_pwr(ops, type, mcs, mdbm) lmac_ioctl(ops, LMAC_IOCTL_SET_PWRLIMIT_ACTUAL_PWR, (uint32)(((type)<<16)|(mcs)), (uint32)(mdbm))
#define lmac_set_pwrlimit_gain(ops, type, mcs, gain) lmac_ioctl(ops, LMAC_IOCTL_SET_PWRLIMIT_GAIN, (uint32)(((type)<<16)|(mcs)), (uint32)(gain))
#define lmac_set_pwrlimit_gain_table(ops, gain_table, size) lmac_ioctl(ops, LMAC_IOCTL_SET_PWRLIMIT_GAIN_TABLE, (uint32)(gain_table), (uint32)(size))
#define lmac_set_edca_max(ops, p_txq_param) lmac_ioctl(ops, LMAC_IOCTL_SET_EDCA_MAX, (uint32)(p_txq_param), 0)
#define lmac_set_temperature_compesate_type(ops, type) lmac_ioctl(ops, LMAC_IOCTL_SET_TEMPERATURE_COMPESATE_TYPE, (uint32)(type), 0)
#define lmac_set_rx_dma_kick_threshold(ops, size_th) lmac_ioctl(ops, LMAC_IOCTL_SET_RX_DMA_KICK_THRESHOLD, (uint32)(size_th), 0)
#define lmac_set_rf_tx_digital_gain(ops, gain) lmac_ioctl(ops, LMAC_IOCTL_SET_RF_TX_DIGITAL_GAIN, (uint32)(gain), 0)
#define lmac_set_sta_connected(ops, addr, connected) lmac_ioctl(ops, LMAC_IOCTL_SET_STA_CONNECTED, (uint32)(addr), connected)
#define lmac_set_freq_offset_track_mode(ops, mode) lmac_ioctl(ops, LMAC_IOCTL_SET_FREQ_OFFSET_TRACK_MODE, (uint32)(mode), 0)
#define lmac_set_temperature_compesate_en(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_TEMPERATURE_COMPESATE_EN, (uint32)(en), 0)
#define lmac_set_edca_min(ops, p_txq_param) lmac_ioctl(ops, LMAC_IOCTL_SET_EDCA_MIN, (uint32)(p_txq_param), 0)
#define lmac_set_heartbeat_data(ops, addr, retry) lmac_ioctl(ops, LMAC_IOCTL_SET_HEARTBEAT_DATA, (uint32)(addr), retry)
#define lmac_start_async_acs(ops, p_ctl) lmac_ioctl(ops, LMAC_IOCTL_SET_START_ASYNC_ACS, (uint32)(p_ctl), 0)
#define lmac_get_async_acs_ret(ops) lmac_ioctl(ops, LMAC_IOCTL_GET_ASYNC_ACS_RET, 0, 0)
#define lmac_set_temp_compensation_table(ops, table, size) lmac_ioctl(ops, LMAC_IOCTL_SET_TEMP_COMPENSATION_TABLE, (uint32)(table), size)
#define lmac_set_ps_no_frm_loss(ops, en) lmac_ioctl(ops, LMAC_IOCTL_SET_PS_NO_FRM_LOSS_EN, (uint32)(en), 0)
#define lmac_get_per(ops, mac) lmac_ioctl(ops, LMAC_IOCTL_GET_STA_PER, (uint32)mac, 0)
#define lmac_get_tx_delay(ops, mac) lmac_ioctl(ops, LMAC_IOCTL_GET_STA_TX_DELAY, (uint32)mac, 0)
#define lmac_get_tx_datarate(ops, mac) lmac_ioctl(ops, LMAC_IOCTL_GET_STA_TX_DATARATE, (uint32)mac, 0)
#define lmac_set_sta_capabilites(ops, cap, len) lmac_ioctl(ops, LMAC_IOCTL_SET_STA_CAPABILITES, (uint32)cap, len)
#define lmac_update_fem_voltage(ops, voltage) lmac_ioctl(ops, LMAC_IOCTL_SET_UPDATE_FEM_VOLTAGE, (uint32)(voltage), 0)
#define lmac_set_tx_agg_tid_bitmap(ops, bitmap) lmac_ioctl(ops, LMAC_IOCTL_SET_TX_AGG_TID_BITMAP, (uint32)bitmap, 0)
#define lmac_set_beacon_modulation(ops, rate) lmac_ioctl(ops, LMAC_IOCTL_SET_BEACON_MODULATION, (uint32)rate, 0)
int32 lmac_ioctl(void *ops, uint32 cmd, uint32 param1, uint32 param2);
int32 lmac_start_acs(void *lops, struct lmac_acs_ctl *p_ctl, uint32 sync);
int32 lmac_set_chan_list(void *lops, uint16 *chan_list, uint16 count);
void *lmac_ah_init(struct lmac_init_param *param);
void *lmac_bgn_init(struct lmac_init_param *param);
//bgn module
int32 lmac_bgn_module_80211w_init(void *ops);
int32 lmac_bgn_module_csa_init(void *ops);
int32 lmac_bgn_module_multi_mac_init(void *ops);
int32 lmac_bgn_module_pwr_limit_init(void *ops);
int32 lmac_bgn_module_rx_reorder_init(void *ops);
void *dsleep_lmac_bgn_init(void);
void lmac_afh_init(void *ops);
#ifdef __cplusplus
}
#endif
#endif

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sdk/include/lib/lmac/lmac_def.h Normal file
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#ifndef _HGIC_LMAC_DEF_H_
#define _HGIC_LMAC_DEF_H_
#include "typesdef.h"
#include "list.h"
#include "lmac.h"
#include "lib/skb/skb.h"
#include "lib/lmac/hgic.h"
#ifdef __cplusplus
extern "C" {
#endif
struct lmac_acs_ctl;
struct lmac_ops {
void *priv;
void *btops;
uint8 headroom, tailroom;
uint16 radio_on : 1,
bbm_mode : 1,
dsleep_init : 1; //flags
int32(*open)(struct lmac_ops *ops);
int32(*close)(struct lmac_ops *ops);
int32(*tx)(struct lmac_ops *ops, struct sk_buff *skb);
int32(*test_tx)(struct lmac_ops *ops, struct sk_buff *skb);
int32(*tx_status)(struct lmac_ops *ops, struct sk_buff *skb);
int32(*rx)(struct lmac_ops *ops, struct hgic_rx_info *info, uint8 *data, uint32 len);
int32(*notify)(struct lmac_ops *ops, uint8 evt_id, uint8 *data, uint32 len);
int32(*set_chan_list)(struct lmac_ops *ops, uint16 *chan_list, uint16 count);
int32(*set_freq_range)(struct lmac_ops *ops, uint16 freq_start, uint16 freq_end, uint8 chan_bw);
int32(*set_freq)(struct lmac_ops *ops, uint32 center_freq);
int32(*start_acs)(struct lmac_ops *ops, struct lmac_acs_ctl *p_ctl, uint32 sync);
int32(*add_sta)(struct lmac_ops *ops, uint8 ifidx, uint16 aid, uint8 *addr);
int32(*del_sta)(struct lmac_ops *ops, uint8 ifidx, uint8 *addr);
int32(*set_key)(struct lmac_ops *ops, uint8 cmd, uint8 *addr, uint8 *key, uint32 len);
int32(*sleep)(struct lmac_ops *ops, uint32 sleep_en, uint32 sleep_tm, uint32 flags);
int32(*ioctl)(struct lmac_ops *ops, uint32 cmd, uint32 param1, uint32 param2);
struct sk_buff *(*test_cmd)(struct lmac_ops *ops, struct sk_buff *skb);
};
//////////////////////////////////////////////////////////////////////////////////
static inline int32 lmac_open(struct lmac_ops *ops)
{
return ops->open(ops);
}
static inline int32 lmac_close(struct lmac_ops *ops)
{
return ops->close(ops);
}
static inline struct sk_buff *lmac_do_test_cmd(struct lmac_ops *ops, struct sk_buff *skb)
{
return ops->test_cmd(ops, skb);
}
static inline int32 lmac_tx(struct lmac_ops *ops, struct sk_buff *skb)
{
return ops->tx(ops, skb);
}
static inline int32 lmac_test_tx(struct lmac_ops *ops, struct sk_buff *skb)
{
return ops->test_tx(ops, skb);
}
//static inline int32 lmac_set_chan_list(struct lmac_ops *ops, uint16 *chan_list, uint32 chan_cnt)
//{
// if(ops->set_chan_list)
// return ops->set_chan_list(ops, chan_list, chan_cnt);
// return RET_ERR;
//}
static inline int32 lmac_set_freq_range(struct lmac_ops *ops, uint32 freq_start, uint32 freq_end, uint8 chan_bw)
{
if(ops->set_freq_range)
return ops->set_freq_range(ops, freq_start, freq_end, chan_bw);
return RET_ERR;
}
static inline int32 lmac_add_sta(struct lmac_ops *ops, uint8 ifidx, uint16 aid, uint8 *addr)
{
return ops->add_sta(ops, ifidx, aid, addr);
}
static inline int32 lmac_del_sta(struct lmac_ops *ops, uint8 ifidx, uint8 *addr)
{
return ops->del_sta(ops, ifidx, addr);
}
static inline int32 lmac_set_key(struct lmac_ops *ops, uint8 cmd, uint8 *addr, uint8 *key, uint32 len)
{
return ops->set_key(ops, cmd, addr, key, len);
}
static inline int32 lmac_sleep(struct lmac_ops *ops, uint32 sleep_en, uint32 sleep_tm, uint32 flags)
{
return ops->sleep(ops, sleep_en, sleep_tm, flags);
}
static inline int32 lmac_set_freq(struct lmac_ops *ops, uint32 center_freq)
{
return ops->set_freq(ops, center_freq);
}
#ifdef __cplusplus
}
#endif
#endif

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// * @file dsleep.h
// * @author hushifei
// * @version V1.0.0
// * @date 08/25/2020
// * @brief This file contains all the dsleep defines.
// Revision History
// (1) V1.0.0 05/16/2022 First Release
#ifndef __BGN_DSLEEP_H__
#define __BGN_DSLEEP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "osal/sleep.h"
#include "osal/timer.h"
#include "osal/msgqueue.h"
/*****************************************************
* SDK相关宏定义设置
******************************************************/
#define CONFIG_SYSTICK_HZ_DSLEEP 1000
#define OS_SYSTICK_HZ_DSLEEP 1000
#define SYS_CACHE_ENABLE_DSLEEP 1
//----------------------------------------------------
#ifndef BIT
#define BIT(nr) (1UL << (nr))
#endif
#define SBIT(n) (1UL<<(n))
#define CBIT(n) ~(1UL<<(n))
#define TS_WIN_MAX 8000//us
#define RX_IDLE_TMO 10//ms
#define WKDATA_TMO 20//ms
#define BKN_TIMEOUT 6
#define BKN_TIMEOUT_ADD 2
#define BKN_TIMEOUT_MAX 20//(2*BKN_TIMEOUT)
#define BEACON_LOST_LIMIT 3
#define DSLEEP_VAR_WIN 10
#define TS_VEC_MAX 20
#define RC_WK_INIT_DEFAULT 1200 //measured val
#define RC_RF_INIT_DEFAULT 331 //measured each time
#define LOST_VAR_MS 2
#define DSLEEP_MAGIC_NUM 0x12344321
#define DEBUG_IO_ENABLE 0
#define LMAC_DBG0 PA_9
#define LMAC_DBG1 PA_8
#define DSLEEP_DBG_EN_PRINT BIT(0)
#define DSLEEP_DBG_NO_WAKEUP BIT(1)
#define DSLEEP_DBG_AUTO_SLEEP BIT(2)
#define DSLEEP_DBG_IO_MASK (0xff<<8)
#define DSLEEP_core_pd_pnd BIT(0)
#define DSLEEP_TrimPend BIT(1)
#define DSLEEP_wk_mclr_rst_pnd BIT(2)
#define DSLEEP_lp_wkup_pnd BIT(3)
#define DSLEEP_ALR0F BIT(4)
#define DSLEEP_CoreTmrPnd BIT(5)
#define DSLEEP_CoreTmrPnd2 BIT(6)
#define DSLEEP_second_pnding BIT(7)
#define DSLEEP_LVD_PND BIT(8)
#define DSLEEP_WATCHDOG_PND BIT(9)
#ifndef LMAC_WKDATA_SIZE
#define LMAC_WKDATA_SIZE (64)
#endif
#ifndef LMAC_WKDATA_COUNT
#define LMAC_WKDATA_COUNT (1)
#endif
struct lmac_wkdata_param {
uint8 count; //must equal to LMAC_WKDATA_COUNT
uint8 wkdata_size; //must equal to LMAC_WKDATA_SIZE
uint8 r1, r2;
struct {
uint32 sip; //source IP address. can be set 0.
uint8 offset; //wkdata's offset start from ether hdr.
uint8 wkdata_len; //wkdata's length
uint8 r1, r2;
uint8 mask[LMAC_WKDATA_SIZE / 8]; //match mask.
uint8 wkdata[LMAC_WKDATA_SIZE]; //wkdata used to match.
} data[LMAC_WKDATA_COUNT];
};
static inline uint32 LMAC_WKDATA_SIP(struct lmac_wkdata_param *wkdata, uint8 idx)
{
uint8 *ptr = (uint8 *)wkdata + 4 + idx * (8 + wkdata->wkdata_size + wkdata->wkdata_size / 8);
return (idx < wkdata->count) ? *(uint32 *)ptr : 0;
}
static inline uint8 LMAC_WKDATA_OFFSET(struct lmac_wkdata_param *wkdata, uint8 idx)
{
uint8 *ptr = (uint8 *)wkdata + 4 + idx * (8 + wkdata->wkdata_size + wkdata->wkdata_size / 8) + 4;
return (idx < wkdata->count) ? *ptr : 0;
}
static inline uint8 LMAC_WKDATA_LEN(struct lmac_wkdata_param *wkdata, uint8 idx)
{
uint8 *ptr = (uint8 *)wkdata + 4 + idx * (8 + wkdata->wkdata_size + wkdata->wkdata_size / 8) + 5;
return (idx < wkdata->count) ? *ptr : 0;
}
static inline uint8 *LMAC_WKDATA_MASK(struct lmac_wkdata_param *wkdata, uint8 idx)
{
uint8 *ptr = (uint8 *)wkdata + 4 + idx * (8 + wkdata->wkdata_size + wkdata->wkdata_size / 8) + 8;
return (idx < wkdata->count) ? ptr : NULL;
}
static inline uint8 *LMAC_WKDATA_DATA(struct lmac_wkdata_param *wkdata, uint8 idx)
{
uint8 *ptr = (uint8 *)wkdata + 4 + idx * (8 + wkdata->wkdata_size + wkdata->wkdata_size / 8) + 8 + wkdata->wkdata_size / 8;
return (idx < wkdata->count) ? ptr : NULL;
}
#define PSALIVE_HEARTBEAT_SIZE 256
#define PSALIVE_HEARTBEAT_RESP_SIZE 128
#define PSALIVE_WAKEUP_DATA_SIZE 128
#define SLEEP_USER_DATA_LEN 512
struct dsleep_psdata {
uint32 ip;
uint16 port, period, hb_tmo, aplost_time, wkdata_off;
uint8 hbdata_len, hbresp_len, wkdata_len;
uint8 psmode: 3, ap_err: 1, wkio_mode: 1, paired: 1;
uint8 conn_try;
uint8 hb_data[PSALIVE_HEARTBEAT_SIZE];
uint8 hb_resp[PSALIVE_HEARTBEAT_RESP_SIZE];
uint8 wk_data[PSALIVE_WAKEUP_DATA_SIZE];
uint8 arp_reply[64];
uint8 wk_reason;
uint8 wk_io: 7, wkio_edge: 1;
uint8 detect_io: 7, detect_level: 1;
uint8 pa_ctrl: 1, pa_ctrl_io: 7; //todo
uint8 vdd13_ctrl: 2, ssid_set: 1, gpiob_en: 1, wkdata_save: 1, io_level_wk: 1, wait_psmode: 2;
uint8 ssid[32], psk[32], bssid[6];
uint8 wkdata_mask[16];
//system_sleep_config parameter
uint32 user_gpioa_resv;
uint32 user_gpiob_resv;
uint32 sleep_us;
uint32 boot_mode : 4, dsleep_en : 1;
uint32 dhcpc_ip;
uint64 rtc_local;
uint64 last_timestamp_local;
uint64 rtc_remote;
uint64 last_timestamp_remote;
};
#define GPIOA_REG_LEN (0x0080/4 + 1)
#define GPIOB_REG_LEN (0x0080/4 + 1)
#define GPIOC_REG_LEN (0x0080/4 + 1)
struct dsleep_cfg{
uint32 magic;
uint8 aplost_time;
uint8 wk_reason;
uint8 encrypt : 1;
uint8 ap_err : 1,
alg_sel : 2,
txic_en : 1,
txic_wakeup : 1,
wdt_close : 1,
clk_switch_dis : 1,
use_old_libflash: 1;
uint8 fake_tim_fadeout;
uint8 usr_fadeout_en : 1,
usr_fadeout_val : 7;
uint8 dtim_cnt;
uint8 dtim_period;
uint8 dtim_test; //used for at+ test
uint8 debounce;
uint32 bkn_int_tu;
uint32 dtim_period_us;
uint8 tim_valid : 1,//1
bc_valid : 1,//2
psm_enter : 1,//3
auto_dsleep : 1,//4
buck_mode : 1,//5
gpiob_hold : 1,//6
dbg_en : 1,//7
fem_used : 1;//8
uint8 ext_dcdc : 1,
assert_hold : 1;
uint8 auto_dsleep_tmo;
uint8 pwm_pin[4]; //[0-3 valid]
uint8 pwm_mode;//2bit
uint8 wkio_pin[6];//[0-5 vaild]
uint8 wkio_edge;
int8 sen_level;//0-2 valid
uint16 listen_interval;
uint16 max_idle_period;//sec
uint16 ap_lost_cnt;
uint16 margin_ms;
uint32 default_sys_clk;
uint32 sleep_type;
struct system_sleep_param sleep_args;
uint32 sleep_dbg_cfg;
int16 rx_lead_margin;
int16 rx_tmo_margin;
//---------user define functions--------------
int32(*usr_kalive_cb)(void *usr_kalive_priv);
void * usr_kalive_priv;
int32(*usr_wkdet_cb)(void *usr_wkdet_priv, uint8 *data, uint32 len);
void * usr_wkdet_priv;
struct lmac_wkdata_param *wkdata;
uint16 aid;
uint8 mac_addr[6];
uint8 bssid[6];
uint32 ip_addr;
uint32 user_gpioa_resv;
uint32 user_gpiob_resv;
uint32 user_gpioc_resv;
uint32 gpioa_regs[GPIOA_REG_LEN];
uint32 gpiob_regs[GPIOB_REG_LEN];
uint32 gpioc_regs[GPIOC_REG_LEN];
uint32 pmu_regs[0x100/4];
uint32 sys_wdt_ms;
uint32 lp_wdt_ms;
uint32 rtc_wkio;
};
enum DSLEEP_MODE {
DSLEEP_MODE_NONE,
DSLEEP_MODE_STA_ALIVE,
DSLEEP_MODE_AP_ALIVE,
DSLEEP_MODE_UCASTWK,
DSLEEP_MODE_APWK,
DSLEEP_MODE_IOWK_ONLY = 6, //之前用了6，后续如果有新增先添加一个5
DSLEEP_MODE_NUM,
};
enum DSLEEP_WAIT_MODE {
DSLEEP_WAIT_MODE_PS_CONNECT,
DSLEEP_WAIT_MODE_STANDBY,
DSLEEP_WAIT_MODE_NUM,
};
#if 0
enum DSLEEP_IOCTL_CMD {
/*Set CMDs*/
DSLEEP_IOCTL_SET_ENTER_SLEEP_CB = 0x1,
DSLEEP_IOCTL_SET_KEEP_ALIVE_CB,
DSLEEP_IOCTL_SET_USR_WKDET_CB,
DSLEEP_IOCTL_SET_DSLEEP_BSS_MAX_IDLE,
DSLEEP_IOCTL_SET_DSLEEP_WKIO_PIN,
DSLEEP_IOCTL_SET_DSLEEP_WKIO_EDGE,
DSLEEP_IOCTL_SET_DSLEEP_APLOST_TIME,
DSLEEP_IOCTL_SET_DSLEEP_SENS_LEVEL,
DSLEEP_IOCTL_SET_DSLEEP_PWM_SEL,
DSLEEP_IOCTL_SET_DSLEEP_PWM_MODE,
DSLEEP_IOCTL_SET_IP_ADDR,
DSLEEP_IOCTL_SET_GPIOA_RESV,
DSLEEP_IOCTL_SET_GPIOB_RESV,
DSLEEP_IOCTL_SET_GPIOC_RESV,
/*Get CMDs*/
DSLEEP_IOCTL_GET_IP_ADDR = 0x20000000,
};
//ioctrl: set_cfg
#define dsleep_set_enter_sleep_cb(func) dsleep_ioctl(DSLEEP_IOCTL_SET_ENTER_SLEEP_CB, (uint32)(func), 0)
#define dsleep_set_keep_alive_cb(func) dsleep_ioctl(DSLEEP_IOCTL_SET_KEEP_ALIVE_CB, (uint32)(func), 0)
#define dsleep_set_usr_wkdet_cb(priv, func) dsleep_ioctl(DSLEEP_IOCTL_SET_USR_WKDET_CB, (uint32)priv, (uint32)(func))
#define dsleep_set_max_idle(max_idle_sec) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_BSS_MAX_IDLE, (uint32)(max_idle_sec), 0)
#define dsleep_set_wkio_pin(pin_idx, pin_num) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_WKIO_PIN, (uint32)(pin_idx), (uint32)(pin_num))
#define dsleep_set_wkio_edge(pin_idx, neg_edge) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_WKIO_EDGE, (uint32)(pin_idx), (uint32)(neg_edge))
#define dsleep_set_aplost_time(t_sec) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_APLOST_TIME, (uint32)(t_sec), 0)
#define dsleep_set_sens_level(sens_level) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_SENS_LEVEL, (uint32)(sens_level), 0)
#define dsleep_set_pwm_sel(pwm_idx, pin_num) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_PWM_SEL, (uint32)(pwm_idx), (pin_num))
#define dsleep_set_pwm_mode(pwm_idx, mode) dsleep_ioctl(DSLEEP_IOCTL_SET_DSLEEP_PWM_MODE, (uint32)(pwm_idx), (mode))
#define dsleep_set_ip_addr(ip_addr) dsleep_ioctl(DSLEEP_IOCTL_SET_IP_ADDR, (uint32)ip_addr, 0)
#define dsleep_set_user_gioa(user_gioa) dsleep_ioctl(DSLEEP_IOCTL_SET_GPIOA_RESV, (uint32)user_gioa, 0)
#define dsleep_set_user_giob(user_giob) dsleep_ioctl(DSLEEP_IOCTL_SET_GPIOB_RESV, (uint32)user_giob, 0)
#define dsleep_set_user_gioc(user_gioc) dsleep_ioctl(DSLEEP_IOCTL_SET_GPIOC_RESV, (uint32)user_gioc, 0)
//ioctrl: get_cfg
#define dsleep_get_ip_addr() dsleep_ioctl(DSLEEP_IOCTL_GET_IP_ADDR, 0, 0)
#endif
union DSLEEP_LO_CFG
{
struct {
uint16 freq; // unit: MHz
uint8 vco_band;
uint8 int_part;
uint32 fract_part;
}lo_cfg;
uint32 word_buf[2];
};
typedef struct {
uint8 hour ;
uint8 minute;
uint8 second;
uint16 tsssv;
float ssv;
uint8 year ;
uint8 month ;
uint8 day ;
uint8 week ;
} RTC_TIMER_TYPEDEF;
struct dsleep_priv {
uint32 flags;
uint32 dsleep_mode : 1,
beacon_rxed : 1,
no_rf_tx_cali : 1,
dsleep_wakeup_flag : 1,//use to indicate dsleep wakeup to inite driver
no_sleep_wakeup : 1;
uint32 wkup_cnt;
uint32 bkn_lost;
uint32 bkn_lost_cont: 8,
stat_wkup_cnt : 8,
stat_lost_cnt :8;
int8 rx_rssi;
int8 rsvd[3];
struct lmac_bgn_priv *lmac_bgn;
struct hggpio_v4_hw *gpioa;
struct hggpio_v4_hw *gpiob;
struct hggpio_v4_hw *gpioc;
struct hggpio_v4_hw *gpiod;
struct hggpio_v4_hw *gpioe;
struct hggpio_v4_hw *gpiof;
struct hguart_v2_hw *p_uart;
struct hguart_v2 *dev_uart;
struct dev_obj *dev_xip;
struct dev_obj *dev_xspi;
uint32 sys_con14_bak;//vdd18
uint32 clk_con1_bak;//clk_div
PMU_TypeDef pmu_bak;
union DSLEEP_LO_CFG freq_table;
uint32 dsleep_rst;
uint32 pmu_con;
//uint32 magic_num;
uint32 sleep_cnt;
uint32 rx_cnt_tmp;
uint32 tmrpr_err;
uint32 reg_tmrpr;
uint32 reg_tmrtrim;
uint32 rc_period_us;
uint32 t_rx_start;
uint32 rc_ms;
uint32 rc_cycle_sleep;
uint32 rc_elapse;
uint16 bkn_len_us;
uint8 bkn_timestamp;
uint32 tbtt_pre;
int32 drift_acc;
//add from other .h
struct sk_buff *null_psm;
struct sk_buff *ps_poll;//todo: del
struct sk_buff *ps_arp;
uint8 null_fail_cnt;
uint16 null_sn;
//pending should be clear
uint16 skb_null_psm_used : 1,
skb_null_psm_acked : 1,
skb_ps_poll_used : 1,
dsleep_loop_test : 1,
wkdata_waiting : 1,
ts_idx : 8,
ts_valid : 1,
dsleep_rdy : 1;
union{
uint32 val; //todo move all clear pending here
}todo_rsvd;
uint64 last_rx;
uint64 last_rx_init;
uint32 key_updata_tmo;
uint32 dsleep_tmr_cnt;
struct os_timer dsleep_tmr;
struct os_semaphore dsleep_sem;
//move from dcfg
uint32 bkn_trim_rc;
uint32 bkn_dtim_rc;//updata if hw trum
uint32 bkn_intv_rc : 30,
rc_init : 1;
uint32 bkn_intv_rc_pre;
uint32 rc_pr_delt;
uint8 rc_var;
int32 bkn_dly;
uint32 bkto;
uint16 bkn_dur;
uint32 rc_wk_init;//如果初始化需要设置
uint32 rc_rf_init;
int32 ts_op_avg;
int32 ts_op_min;
int32 ts_op_max;
int32 ts_op_bkn;
int32 ts_win;
uint64 timestamp_pre;
uint32 ts_vec[TS_VEC_MAX];
int32 ts_rem[TS_VEC_MAX]; //must int32
uint8 rx_buff[512];
uint32 ap_lost_det : 1,
wkdata_det : 1,
txnull_fail : 1,
wkio_pending: 6;
//no clear area
struct dsleep_cfg dcfg;
RTC_TIMER_TYPEDEF rtc_timer;
struct os_task dsleep_task;
struct os_mutex null_tx_mutex;
uint32 wkcon_bak[3];
};
//#define ETH_P_ARP 0x0806 /* Address Resolution packet */
//#define ETH_P_IP 0x0800 /* Internet Protocol packet */
struct dsleep_eth_hdr{
uint8 dsap;
uint8 ssap;
uint8 control_field;
uint8 oui[3];
uint8 type[2];//ARP= 0x0806 //IP= 0x0800
};
struct dsleep_arp_hdr{
uint8 hw_type[2];// Ethernet 0x0001
uint8 proto_type[2];//IPv4= 0x0800
uint8 hw_size;// MAC_addr: 6
uint8 porto_size;//IP_size: 4
uint8 op_code[2];//1: ARP request; 2: ARP Reply; 3: RRAP Request; 4: RRAP Reply
uint8 sender_mac[6];
uint8 sender_ip[4];
uint8 target_mac[6];
uint8 target_ip[4];
uint8 resv[18];//dump 18B tenda->Tp yes, TP->tenda no,
};
//IP header: 20Bytes
struct dsleep_ip_hdr{
uint8 version_hdr_len;//version; header length//0x45:ver4 20B
uint8 service_filed;//Differentiated Services Filed//0x00
uint16 total_len;//total length
uint16 id;//identification
uint16 flags;//Flags: 3bits, Fragment Offset:13 bits
uint8 ttl;//Time To Live
uint8 protocol;//0x01=ICMP 0x02=IGMP 0x06=TCP6 0x11=UDP //42B
uint16 hdr_check_sum;//44B
uint32 src_ip;
uint32 dst_ip; //52B
};
//tcp header: 20Bytes
struct dsleep_tcp_hdr{
uint16 src_port;
uint16 dst_port;//56B
uint32 seq_num;
uint32 ack_num;
uint16 hdr_len : 4,
rsvd : 6,
urg : 1,
ack : 1,
psh : 1,
rst : 1,
syn : 1,
fin : 1;
uint16 win_size;
uint16 checksum;
uint16 urgentpointer;
};
//tcp header: 20Bytes
struct dsleep_udp_hdr{
uint16 src_port;
uint16 dst_port;//56B
uint16 length;
uint16 checksum;
};
extern struct dsleep_priv *bgn_dsleep;
void *bgn_dsleep_init(void *ops);
void dsleep_wakeup(void);
void debug_config(void);
int32 dsleep_bgn_resume_hdl(void *ops, uint32 wake_reason, uint32 param2);
int32 dsleep_cfg_init(uint16 sleep_type);
int32 dsleep_wkdata_check(uint8* data, uint32 len);
int32 dsleep_arp_req_check(uint8 *data, int32 len);
int32 dsleep_arp_data_send(uint8 *target_mac, uint8 *target_ip, uint8 pm, uint16 seq_num);
//void lmac_bgn_send_ps_poll(struct lmac_ops *ops, uint8 pm, uint16 sn);
int32 lmac_bgn_send_null_psm(void *ops, uint8 pm);
/*---------------------------- RTC Private define --------------------------------*/
/***** RTC_WPR(for RTC) Register *****/
#define RTC_WPR_KEY(n) ((n) & 0xFF) // 写保护,依次写入0x15和0x5c, 0x0：未解除, 0x1：已解除
/***** RTC_CTR(for RTC) Register *****/
#define RTC_CTR_ALR0WKE(n) (((n) & 0x00000001) << 31) //
#define RTC_CTR_WUTWKE(n) (((n) & 0x00000001) << 30) //
#define RTC_CTR_TAMPM(n) (((n) & 0x00000001) << 29) // 入侵检测引脚复用,0x0：PE12,0x1：TMR1_INC_PIN
#define RTC_CTR_CALOE(n) (((n) & 0x00000001) << 28) // 校准输出使能 0x0：禁止，0x1：使能 Note：输出校准脉冲和1Hz
#define RTC_CTR_BPSR(n) (((n) & 0x00000001) << 27) // Bypass影子寄存器，0x0：日历值取自影子寄存器，0x1：日历值取自日历计数器
#define RTC_CTR_SUB1H_EN (0x00000001 << 26) // 减少1小时 0x0：无作用, 0x1：减少1小时
#define RTC_CTR_ADD1H_EN (0x00000001 << 25) // 增加1小时 0x0：无作用, 0x1：减少1小时
#define RTC_CTR_HF(n) (((n) & 0x00000001) << 24) // 小时格式，0x0:24小时制, 0x1:12小时制
#define RTC_CTR_TAMPPUEN(n) (((n) & 0x00000001) << 23) // 入侵检测上拉电阻使能 0x0：禁止，0x1：使能
#define RTC_CTR_TAMPPCH(n) (((n) & 0x00000003) << 21) // 入侵检测预充电时间,0x0：1个RCLK周期,0x1：2个RCLK周期,0x2：4个RCLK周期,0x3：8个RCLK周期,Note：每次采样之前激活上拉电阻的时间
#define RTC_CTR_TAMPFLT(n) (((n) & 0x00000003) << 19) // 入侵检测滤波 0x0：检测到有效边沿后激活入侵，0x1：连续检测到2次有效电平激活入侵，0x2：连续检测到4次有效电平激活入侵，0x3：连续检测到8次有效电平激活入侵
#define RTC_CTR_TAMPSF(n) (((n) & 0x00000007) << 16) // 入侵检测采样频率 RCLK/(256*(2^ TAMPSF))
#define RTC_CTR_TAMPTRG(n) (((n) & 0x00000001) << 15) // 入侵检测触发；当TAMPFLT = 0时：0x0：下降沿, 0x1：上升沿。当TAMPFLT ！= 0时：0x0：低电平, 0x1：高电平
#define RTC_CTR_TAMPTS(n) (((n) & 0x00000001) << 14) // 入侵检测激活时间戳0x0：禁止, 0x1：使能
#define RTC_CTR_TSTRG(n) (((n) & 0x00000001) << 13) // 时间戳触发0x0：上升沿, 0x1：下降沿
#define RTC_CTR_TAMPIE(n) (((n) & 0x00000001) << 12) // 入侵检测中断使能 0x0：禁止, 0x1：使能
#define RTC_CTR_TSIE(n) (((n) & 0x00000001) << 11) // 时间戳中断使能 0x0：禁止, 0x1：使能
#define RTC_CTR_ALR0IE(n) (((n) & 0x00000001) << 9) // 闹钟0中断使能 0x0：禁止, 0x1：使能
#define RTC_CTR_WUTIE(n) (((n) & 0x00000001) << 8) // 唤醒定时器中断使能 0x0：禁止, 0x1：使能
#define RTC_CTR_TAMPE(n) (((n) & 0x00000001) << 7) // 入侵检测使能 0x0：禁止, 0x1：使能
#define RTC_CTR_TSE(n) (((n) & 0x00000001) << 6) // 时间戳使能 0x0：禁止, 0x1：使能
#define RTC_CTR_ALR0E(n) (((n) & 0x00000001) << 4) // 闹钟0使能 0x0：禁止, 0x1：使能
#define RTC_CTR_WUTE(n) (((n) & 0x00000001) << 3) // 唤醒定时器使能 0x0：禁止,0x1：使能
#define RTC_CTR_WUCKSEL(n) (((n) & 0x00000007) << 0) // 唤醒定时器时钟选择,0x0：RCLK/2,0x1：RCLK/4,0x2：RCLK/8,0x3：RCLK/16,0x4，0x5：ck_spre，定时器为16位,0x6，0x7：ck_spre，定时器为17位
/***** RTC_PDR(for RTC) Register *****/
#define RTC_PDR_PREDIV_A(n) (((n) & 0x0000007F) << 16) // 异步分频系数F（ck_apre=F(RCLK)/(PREDIV_A+1)
#define RTC_PDR_PREDIV_S(n) (((n) & 0x00007FFF) << 0) // 同步分频系数F（ck_spre=F( ck_apre )/(PREDIV_S+1)
/***** RTC_ISR(for RTC) Register *****/
#define RTC_ISR_SSSPF(n) (((n) & 0x0001) << 15) // 亚秒平移挂起标志 0：亚秒平移寄存器可写， 1：亚秒平移寄存器不可写（硬件校准中）
#define RTC_ISR_RECALPF(n) (((n) & 0x0001) << 14) // 重新校准挂起标志 0：校准寄存器可写，1：校准寄存器不可写（硬件校准中）
#define RTC_ISR_TAMPF(n) (((n) & 0x0001) << 13) // 入侵检测标志 0x0：未触发，0x1：已触发
#define RTC_ISR_TSOVF(n) (((n) & 0x0001) << 12) // 时间戳溢出标志 0x0：未溢出，0x1：已溢出
#define RTC_ISR_TSF(n) (((n) & 0x0001) << 11) // 时间戳标志 0x0：未触发，0x1：已触发
#define RTC_ISR_ALR0F(n) (((n) & 0x0001) << 9) // 闹钟0标志 0x0：未触发，0x1：已触发
#define RTC_ISR_WUTF(n) (((n) & 0x0001) << 8) // 唤醒定时器标志 0x0：未触发，0x1：已触发
#define RTC_ISR_TAMPWF(n) (((n) & 0x0001) << 7) // 入侵检测写标志 0x0：不允许更新入侵检测，0x1：允许更新入侵检测
#define RTC_ISR_ALR0WF(n) (((n) & 0x0001) << 5) // 闹钟0写标志 0x0：不允许更新闹钟0，0x1：允许更新闹钟0
#define RTC_ISR_WUTWF(n) (((n) & 0x0001) << 4) // 唤醒定时器写标志 0x0：不允许更新唤醒定时器，0x1：允许更新唤醒定时器
#define RTC_ISR_INITM(n) (((n) & 0x0001) << 3) // 初始化模式 0x0：自由运行模式，该位由1->0时，计数器重新开始计数，0x1：初始化模式，用于编程RTC_TMR，RTC_DAR和RTC_PDR。当该位置1，计数器停止计数
#define RTC_ISR_INITMF(n) (((n) & 0x0001) << 2) // 初始化模式标志 0x0：不允许更新日历寄存器，0x1：允许更新日历寄存器
#define RTC_ISR_INITS(n) (((n) & 0x0001) << 1) // 初始化状态，当日历年份字段不为0时由硬件置1 0x0：未初始化，0x1：已初始化
#define RTC_ISR_RSF(n) (((n) & 0x0001) << 0) // 影子寄存器同步标志 0x0：未同步，0x1：已同步
/***** RTC_SSR(for RTC) Register *****/
#define RTC_SSR_SSV(n) (((n) & 0xFF) << 0)
/***** RTC_TMR(for RTC) Register *****/
#define RTC_TMR_PM(n) (((n) & 0x00000001) << 24)
#define RTC_TMR_HT(n) (((n) & 0x00000003) << 20) // 小时的十位（BCD格式）
#define RTC_TMR_HU(n) (((n) & 0x0000000F) << 16) // 小时的个位（BCD格式）
#define RTC_TMR_MNT(n) (((n) & 0x00000007) << 12) // 分钟的十位（BCD格式）
#define RTC_TMR_MNU(n) (((n) & 0x0000000F) << 8)
#define RTC_TMR_ST(n) (((n) & 0x00000007) << 4) // 秒的十位（BCD格式）
#define RTC_TMR_SU(n) (((n) & 0x0000000F) << 0)
/***** RTC_DAR(for RTC) Register *****/
#define RTC_DAR_YT(n) (((n) & 0x0000000F) << 28) // 年份的十位（BCD格式）
#define RTC_DAR_YU(n) (((n) & 0x0000000F) << 24) // 年份的个位（BCD格式）
#define RTC_DAR_MT(n) (((n) & 0x00000001) << 20) // 月份的十位（BCD格式）
#define RTC_DAR_MU(n) (((n) & 0x0000000F) << 16) // 月份的个位（BCD格式）
#define RTC_DAR_DT(n) (((n) & 0x00000003) << 12) // 日的十位（BCD格式）
#define RTC_DAR_DU(n) (((n) & 0x0000000F) << 8) // 日的个位（BCD格式）
#define RTC_DAR_WU(n) (((n) & 0x00000007) << 0) // 星期的个位（BCD格式）
/***** RTC_ALR0R(for RTC) Register *****/
#define RTC_ALR0R_MSK4(n) (((n) & 0xFFFFFFFF) << 31) // 星期或日期屏蔽 0x0：不屏蔽，0x1：屏蔽
#define RTC_ALR0R_WDSEL(n) (((n) & 0x00000001) << 30) // 星期或日期选择 0x0：DU[3:0]代表日期，0x1：DU[2:0]代表星期。DT[1:0]和DU[3]忽略
#define RTC_ALR0R_DT(n) (((n) & 0x00000003) << 28) // 日期的十位（BCD格式）
#define RTC_ALR0R_DU(n) (((n) & 0x0000000F) << 24) // 星期或日期的个位（BCD格式）
#define RTC_ALR0R_MSK3(n) (((n) & 0xFFFFFFFF) << 23) // 小时屏蔽 0x0：不屏蔽，0x1：屏蔽
#define RTC_ALR0R_PM(n) (((n) & 0x00000001) << 22) // AM/PM符号 0x0：AM或24小时制，0x1：PM
#define RTC_ALR0R_HT(n) (((n) & 0x00000003) << 20) // 小时的十位（BCD格式）
#define RTC_ALR0R_HU(n) (((n) & 0x0000000F) << 16) // 小时的个位（BCD格式）
#define RTC_ALR0R_MSK2(n) (((n) & 0xFFFFFFFF) << 15) // 分钟屏蔽 0x0：不屏蔽，0x1：屏蔽
#define RTC_ALR0R_MNT(n) (((n) & 0x00000007) << 12) // 分钟的十位（BCD格式）
#define RTC_ALR0R_MNU(n) (((n) & 0x0000000F) << 8) // 分钟的个位（BCD格式）
#define RTC_ALR0R_MSK1(n) (((n) & 0xFFFFFFFF) << 7) // 秒钟屏蔽 0x0：不屏蔽，0x1：屏蔽
#define RTC_ALR0R_ST(n) (((n) & 0x00000007) << 4) // 秒钟的十位（BCD格式）
#define RTC_ALR0R_SU(n) (((n) & 0x0000000F) << 0) // 秒钟的个位（BCD格式）
/***** RTC_WUTR(for RTC) Register *****/
#define RTC_WUTR_ARV(n) ((n) & 0xFFFF) // 自动重载值
/***** RTC_TSSSR(for RTC) Register *****/
#define RTC_TSSSR_SSV(n) ((n) & 0xFF) // 亚秒值
/***** RTC_TSTMR(for RTC) Register *****/
#define RTC_TSTMR_PM(n) (((n) & 0x00000001) << 31) // AM/PM符号 0x0：AM或24小时制，0x1：PM
#define RTC_TSTMR_HT(n) (((n) & 0x00000003) << 20) // 小时的十位（BCD格式）
#define RTC_TSTMR_HU(n) (((n) & 0x0000000F) << 16) // 小时的个位（BCD格式）
#define RTC_TSTMR_MNT(n) (((n) & 0x00000007) << 12) // 分钟的十位（BCD格式）
#define RTC_TSTMR_MNU(n) (((n) & 0x0000000F) << 8) // 分钟的个位（BCD格式）
#define RTC_TSTMR_ST(n) (((n) & 0x00000001) << 4) // 秒钟的十位（BCD格式）
#define RTC_TSTMR_SU(n) (((n) & 0x00000001) << 0) // 秒钟的个位（BCD格式）
/***** RTC_TSDAR(for RTC) Register *****/
#define RTC_TSDAR_YT(n) (((n) & 0x0000000F) << 28) // 年份的十位（BCD格式）
#define RTC_TSDAR_YU(n) (((n) & 0x0000000F) << 24) // 年份的个位（BCD格式）
#define RTC_TSDAR_MT(n) (((n) & 0x00000001) << 20) // 月份的十位（BCD格式）
#define RTC_TSDAR_MU(n) (((n) & 0x0000000F) << 16) // 月份的个位（BCD格式）
#define RTC_TSDAR_DT(n) (((n) & 0x00000003) << 12) // 日的十位（BCD格式）
#define RTC_TSDAR_DU(n) (((n) & 0x0000000F) << 8) // 日的个位（BCD格式）
#define RTC_TSDAR_WU(n) (((n) & 0x00000007) << 0) // 星期的个位（BCD格式）
/***** RTC_CALR(for RTC) Register *****/
#define RTC_CALR_CALP(n) (((n) & 0x0001) << 14) // 正/负校准（校准周期为32秒） 0x0：负校准，0x1：正校准
#define RTC_CALR_CALP16(n) (((n) & 0x0001) << 13) // 每2^11个RCLK屏蔽/增加1个RCLK，校准周期为16s
#define RTC_CALR_CALP8(n) (((n) & 0x0001) << 12) // 每2^10个RCLK屏蔽/增加1个RCLK，校准周期为8s
#define RTC_CALR_CEV(n) (((n) & 0x01FF) << 0) // 每2^9个RCLK屏蔽 /增加1个RCLK，校准期望值
/***** RTC_SSSR(for RTC) Register *****/
#define RTC_SSSR_ASS(n) (((n) & 0x0001) << 16) // 提前/延迟亚秒 0x0：延迟亚秒 0x1：提前亚秒
#define RTC_SSSR_SSEV(n) (((n) & 0x00003FFF) << 0) // 亚秒期望值
/* Private typedef -----------------------------------------------------------*/
// 设置时间格式：12小时制、24小时制
typedef enum
{
SET_12_HOURS = 0x1,
SET_24_HOURS = 0x0,
SET_AM = 0x0,
SET_PM = 0x1
}TYPE_ENUM_TIMER_FORMAT;
/* 夏令时操作 */
typedef enum
{
DST_SUB1H = 0x0,
DST_ADD1H = 0x1
}TYPE_ENUM_DST;
/* 时间戳触发 */
typedef enum
{
TSE_FALL_EDGE_TRIG = 0x0,
TSE_RISING_EDGE_TRIG = 0x1
}TYPE_ENUM_TIME_STAMP_TRIG;
/* 入侵检测引脚复用 */
typedef enum
{
PIN_PA8 = 0x0,
LP_WKUP_PIN = 0x1
}TYPE_ENUM_TAMPM;
/* 入侵检测触发 */
typedef enum
{
FALLING_EDGE_TRIG = 0x0,
RISING_EDGE_TRIG = 0x1,
LOW_LEV = 0x0,
HIGH_LEV = 0x1
}TYPE_ENUM_INTR_DET_TRIG;
/* Intrusion detection filtering */
typedef enum
{
EDGE_EFFE = 0x0,
TWICE_EFFE_LEV = 0x1,
FOUR_EFFE_LEV = 0x2,
EIGHT_EFFE_LEV = 0x3
}TYPE_ENUM_EFFE_LEV;
/* Intrusion detection precharge time */
typedef enum
{
// 入侵检测预充电时间
RCLK1_PRE_TIME = 0x0,
RCLK2_PRE_TIME = 0x1,
RCLK4_PRE_TIME = 0x2,
RCLK8_PRE_TIME = 0x3
}TYPE_ENUM_PRECHARGE_TIME;
/* 唤醒定时器时钟选择 */
typedef enum
{
RCLK_2PRES = 0x0, // 0x0：RCLK/2
RCLK_4PRES = 0x1, // 0x1：RCLK/4
RCLK_8PRES = 0x2, // 0x2：RCLK/8
RCLK_16PRES = 0x3, // 0x3：RCLK/16
CK_SPRE_16BIT = 0x4, // 0x4，0x5：ck_spre，定时器为16位
CK_SPRE_17BIT = 0x7 // 0x6，0x7：ck_spre，定时器为17位
}TYPE_ENUM_RCLK_PRES;
#define RTC_FLAG_USE_EXTERN_LXOSC32K BIT(0)
void dsleep_rtc_calendar_init(uint32 time, uint32 date, uint32 flags);
void dsleep_rtc_alarm_cfg(uint32 time, uint8 msk);
void dsleep_rtc_calendar_read(RTC_TIMER_TYPEDEF *rtc_time);
void dsleep_bssid_set(void *ops, uint8 *bssid);
void dsleep_tim_tx_hdl(uint8 *element);
int32 dsleep_crc_valid(void);
//----------------------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif //__IRTCC_H__
/******************* (C) COPYRIGHT 2017 HUGE-IC *****END OF FILE****/

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#ifndef _HGIC_LMAC_HOST_H_
#define _HGIC_LMAC_HOST_H_
#ifdef __cplusplus
extern "C" {
#endif
struct lmachost_param {
uint8 bus_type;
uint8 task_priority;
uint16 stack_size;
struct lmac_ops *lops;
struct bt_ops *btops;
uint32 rxwrite: 1, rev: 31;
uint32 dma_scatter;
};
struct lmac_host {
uint16 stop: 1, req_txwnd: 1, bleraw: 1, user_edca: 1, init_report: 1,
icmp_mntr: 1, rxwrite: 1, throughput_en: 3,
dup_filter:1, sta_mode:1;
uint16 cookie, last_cookie;
uint16 aggbuff_len, agg_len;
uint8 if_monitor; //interface monitor.
atomic8_t if_alive; //interface alive.
uint32 dma_scatter;
struct mac_bus *bus;
struct lmac_ops *ops;
struct bt_ops *btops;
struct skb_list iftest_list;
struct skb_list cmd_list;
struct skb_list up2host;
//struct skb_list txstatus_list;
struct skb_list rx_list;
os_semaphore_t sema;
os_task_t task;
uint8 *agg_buff;
struct sk_buff *cmdskb;
uint16 sn_head[9];
uint64 sn_bitmap[9];
uint16 stats_invalid_frm, stats_cookie_err;
uint16 stats_unsupport_frm, stats_rx_loop;
uint32 stats_recv_nomem;
uint32 rx_bytes, tx_bytes;
uint64 throughput_jiff;
};
void lmac_host_report_init_done(struct lmac_host *lmachost);
int32 lmac_host_init(struct lmachost_param *l_param, struct macbus_param *m_param);
int32 host_event_new(uint32 evt_id, uint8 *data, uint32 data_len);
int32 host_data_send(uint8 *data, uint32 data_len);
void lmac_host_status(void);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _LMAC_RXQ_H_
#define _LMAC_RXQ_H_
#include <typesdef.h>
#ifdef __cplusplus
extern "C" {
#endif
struct lmac_frm_info {
uint8 *addr;
uint32 len;
};
struct lmac_rxq {
os_semaphore_t sem;
struct lmac_frm_info *rxq;
uint16 wpos;
uint16 rpos;
uint32 size;
};
int32 lmac_rxq_init(struct lmac_rxq *rxq, uint8 *qbuf, int32 qsize);
int32 lmac_rxq_put(struct lmac_rxq *rxq, struct lmac_frm_info *frm_info, int32 count);
int32 lmac_rxq_get(struct lmac_rxq *rxq, struct lmac_frm_info *frm_info, int32 count, int32 tmo);
int32 lmac_rxq_free(struct lmac_rxq *rxq);
int32 lmac_rxq_count(struct lmac_rxq *rxq);
#ifdef __cplusplus
}
#endif
#endif