Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

sdk/hal/adc.c

@@ -0,0 +1,86 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/adc.h"
+
+int32 adc_open(struct adc_device *adc)
+{
+    if (adc) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->open(adc);
+    }
+    return RET_ERR;
+}
+
+int32 adc_close(struct adc_device *adc)
+{
+    if (adc) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->close(adc);
+    }
+    return RET_ERR;
+}
+
+int32 adc_add_channel(struct adc_device *adc, uint32 channel)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->add_channel) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->add_channel(adc, channel);
+    }
+    return RET_ERR;
+}
+
+int32 adc_delete_channel(struct adc_device *adc, uint32 channel)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->delete_channel) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->delete_channel(adc, channel);
+    }
+    return RET_ERR;
+}
+
+int32 adc_get_value(struct adc_device *adc, uint32 channel, uint32 *raw_data)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->get_value) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->get_value(adc, channel, raw_data);
+    }
+    return RET_ERR;
+}
+
+int32 adc_ioctl(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->ioctl) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->ioctl(adc, ioctl_cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 adc_request_irq(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->request_irq) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->request_irq(adc, irq_flag, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 adc_release_irq(struct adc_device *adc, enum adc_irq_flag irq_flag)
+{
+    if (adc && ((const struct adc_hal_ops *)adc->dev.ops)->release_irq) {
+        return ((const struct adc_hal_ops *)adc->dev.ops)->release_irq(adc, irq_flag);
+    }
+    return RET_ERR;
+}
+
+int32 adc_get_vref(struct adc_device *adc, float *vref)
+{
+    uint32 __vref = 0;
+
+    if (!vref || !adc) {
+        return RET_ERR;
+    }
+
+    adc_ioctl(adc, ADC_IOCTL_GET_VREF, (uint32)&__vref, 0);
+
+    *vref = (float)(__vref>>8);
+
+    return RET_OK;
+}
+
+

sdk/hal/capture.c

@@ -0,0 +1,79 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/capture.h"
+
+
+int32 capture_init(struct capture_device *capture, enum capture_channel channel, enum capture_mode mode)
+{
+    if (capture) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->init(capture, channel, mode);
+    }
+    return RET_ERR;
+}
+
+int32 capture_deinit(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->deinit(capture, channel);
+    }
+    return RET_ERR;
+}
+
+int32 capture_start(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->start(capture, channel);
+    }
+    return RET_ERR;
+}
+
+int32 capture_stop(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->stop(capture, channel);
+    }
+    return RET_ERR;
+}
+
+int32 capture_suspend(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture && ((const struct capture_hal_ops *)capture->dev.ops)->suspend) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->suspend(capture, channel);
+    }
+    return RET_ERR;
+}
+
+int32 capture_resume(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture && ((const struct capture_hal_ops *)capture->dev.ops)->resume) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->resume(capture, channel);
+    }
+    return RET_ERR;
+}
+
+int32 capture_ioctl(struct capture_device *capture, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2)
+{
+    if (capture && ((const struct capture_hal_ops *)capture->dev.ops)->ioctl) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->ioctl(capture, channel, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 capture_request_irq(struct capture_device *capture, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data)
+{
+    if (capture && ((const struct capture_hal_ops *)capture->dev.ops)->request_irq) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->request_irq(capture, channel, irq_flag, irq_hdl, data);
+    }
+    return RET_ERR;
+}
+
+int32 capture_release_irq(struct capture_device *capture, enum capture_channel channel)
+{
+    if (capture && ((const struct capture_hal_ops *)capture->dev.ops)->release_irq) {
+        return ((const struct capture_hal_ops *)capture->dev.ops)->release_irq(capture, channel);
+    }
+    return RET_ERR;
+}
+

sdk/hal/csc.c

@@ -0,0 +1,104 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/csc.h"
+
+int32 csc_init(struct csc_device *p_csc)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->init) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->init(p_csc);
+    }
+    return RET_ERR;
+}
+
+int32 csc_suspend(struct csc_device *p_csc)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->suspend) {
+		return ((const struct csc_hal_ops *)p_csc->dev.ops)->suspend(p_csc);
+    }
+    return RET_ERR;
+}
+
+int32 csc_resume(struct csc_device *p_csc)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->resume) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->resume(p_csc);
+    }
+    return RET_ERR;
+}
+
+
+int32 csc_request_irq(struct csc_device *p_csc, uint32 irq_flags, csc_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->request_irq) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->request_irq(p_csc, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 csc_release_irq(struct csc_device *p_csc, uint32 irq_flags)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->release_irq) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->release_irq(p_csc, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 csc_set_format(struct csc_device *p_csc, uint8_t input_format,uint8_t output_format)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_FORMAT_TRAN, input_format, output_format);
+    }
+    return RET_ERR;
+}
+
+int32 csc_set_photo_size(struct csc_device *p_csc, uint32_t w,uint32_t h)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_PHOTO_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 csc_set_type(struct csc_device *p_csc, uint8_t type)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_COEF_TYPE, type, 0);
+    }
+    return RET_ERR;
+}
+
+int32 csc_set_input_addr(struct csc_device *p_csc, uint32_t in0,uint32_t in1,uint32_t in2)
+{
+	uint32 input_tbl[3];
+	input_tbl[0] = in0;
+	input_tbl[1] = in1;
+	input_tbl[2] = in2;
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_INPUT_ADDR, (uint32_t)input_tbl, 0);
+    }
+    return RET_ERR;
+}
+
+int32 csc_set_output_addr(struct csc_device *p_csc, uint32_t out0,uint32_t out1,uint32_t out2)
+{
+	uint32 output_tbl[3];
+	output_tbl[0] = out0;
+	output_tbl[1] = out1;
+	output_tbl[2] = out2;
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_OUTPUT_ADDR, (uint32_t)output_tbl, 0);
+    }
+    return RET_ERR;
+}
+
+int32 csc_start_run(struct csc_device *p_csc)
+{
+    if (p_csc && ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl) {
+        return ((const struct csc_hal_ops *)p_csc->dev.ops)->ioctl(p_csc, CSC_IOCTL_KICK_RUN, 0, 0);
+    }
+    return RET_ERR;
+}
+

sdk/hal/csi2.c

@@ -0,0 +1,251 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/csi2.h"
+
+
+int32 mipi_csi_open(struct mipi_csi_device *p_mipi_csi){
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->open) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->open(p_mipi_csi);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_close(struct mipi_csi_device *p_mipi_csi){
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->close) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->close(p_mipi_csi);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_init(struct mipi_csi_device *p_mipi_csi,uint8_t lane_num){
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->init) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->init(p_mipi_csi,lane_num);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_deinit(struct mipi_csi_device *p_mipi_csi){
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->deinit) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->deinit(p_mipi_csi);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_set_baudrate(struct mipi_csi_device *p_mipi_csi, uint32 mclk)
+{
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->baudrate) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->baudrate(p_mipi_csi, mclk);
+    }
+    return RET_ERR;
+
+}
+
+int32 mipi_csi_request_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags, mipi_csi_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->request_irq) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->request_irq(p_mipi_csi, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_release_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags)
+{
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->release_irq) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->release_irq(p_mipi_csi, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi1_request_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags, mipi_csi_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->request_irq1) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->request_irq1(p_mipi_csi, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi1_release_irq(struct mipi_csi_device *p_mipi_csi, uint32 irq_flags)
+{
+    if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->release_irq1) {
+        return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->release_irq1(p_mipi_csi, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_csi_set_lane_num(struct mipi_csi_device *p_mipi_csi,uint32 lane_num){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_LANE_NUM, lane_num, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_open_virtual_channel(struct mipi_csi_device *p_mipi_csi,uint8 open){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_OPEN_VIRTUAL_CHANNEL, open, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_img_size(struct mipi_csi_device *p_mipi_csi,uint32 w,uint32 h){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_IMG_SIZE, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_hsync_rec_time(struct mipi_csi_device *p_mipi_csi,uint8 time){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_HSYNC_REC_TIME, time, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_hsync_rec_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_HSYNC_REC_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_crop_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_CROP_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_crop_img_start(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_CROP_COORD_START, x, y);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_crop_img_end(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_CROP_COORD_END, x-1, y);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_input_format(struct mipi_csi_device *p_mipi_csi,uint8 format){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_FORMAT_INPUT, format, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 mipi_csi1_img_size(struct mipi_csi_device *p_mipi_csi,uint32 w,uint32 h){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_IMG_SIZE, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_hsync_rec_time(struct mipi_csi_device *p_mipi_csi,uint8 time){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_HSYNC_REC_TIME, time, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_hsync_rec_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_HSYNC_REC_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_crop_enable(struct mipi_csi_device *p_mipi_csi,uint8 enable){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_CROP_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_crop_img_start(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_CROP_COORD_START, x, y);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_crop_img_end(struct mipi_csi_device *p_mipi_csi,uint32 x,uint32 y){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_CROP_COORD_END, x, y);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi1_input_format(struct mipi_csi_device *p_mipi_csi,uint8 format){
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI1_FORMAT_INPUT, format, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 mipi_csi_dphy_cfg(struct mipi_csi_device *p_mipi_csi,uint32 c0,uint32 c1,uint32 c2,uint32 c3,uint32 c4,uint32 c5,uint32 c6,uint32 c7){
+	uint32_t cfgbuf[8];
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		cfgbuf[0] = c0;
+		cfgbuf[1] = c1;
+		cfgbuf[2] = c2;
+		cfgbuf[3] = c3;
+		cfgbuf[4] = c4;
+		cfgbuf[5] = c5;
+		cfgbuf[6] = c6;
+		cfgbuf[7] = c7;
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_DPHY_CFG, (uint32)cfgbuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 mipi_csi_dphy_dbg(struct mipi_csi_device *p_mipi_csi,uint32 d0,uint32 d1,uint32 d2,uint32 d3){
+	uint32_t cfgdbg[8];
+	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		cfgdbg[0] = d0;
+		cfgdbg[1] = d1;
+		cfgdbg[2] = d2;
+		cfgdbg[3] = d3;
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_DPHY_DBG, (uint32)cfgdbg, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 mipi_csi_ftusb3_open(struct mipi_csi_device *p_mipi_csi, uint8 enable)
+{
+   	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_FTUSB3_OPEN, enable, 0);
+	} 
+	return RET_ERR;
+}
+
+int32 mipi_csi_hs_rx_zero_cnt_set(struct mipi_csi_device *p_mipi_csi, uint32 value)
+{
+   	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_HS_RX_ZERO_CNT, value, 0);
+	} 
+	return RET_ERR;
+}
+
+int32 mipi_csi_get_match_value(struct mipi_csi_device *p_mipi_csi, uint32 *value)
+{
+   	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_GET_MATCH_VALUE, (uint32)value, 0);
+	} 
+	return RET_ERR;
+}
+
+int32 mipi_csi_get_stop_state(struct mipi_csi_device *p_mipi_csi, uint32 *value)
+{
+   	if (p_mipi_csi && ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl) {
+		return ((const struct mipi_csi_hal_ops *)p_mipi_csi->dev.ops)->ioctl(p_mipi_csi, MIPI_CSI_STOP_STATE, (uint32)value, 0);
+	} 
+	return RET_ERR;
+}

sdk/hal/dev.c

@@ -0,0 +1,296 @@
+#include "basic_include.h"
+
+struct dev_mgr {
+    struct dev_obj  *devs;
+    struct dev_hotplug_obj  *hotplug;
+    os_mutex_t       mutex;
+};
+
+__bobj static struct dev_mgr s_dev_mgr;
+
+__init int32 dev_init()
+{
+    os_mutex_init(&s_dev_mgr.mutex);
+    s_dev_mgr.devs = NULL;
+    s_dev_mgr.hotplug = NULL;
+    return RET_OK;
+}
+
+void dev_put(struct dev_obj *dev)
+{
+    if (dev && dev->hotplug) {
+        if(atomic_dec_and_test(&dev->ref)){
+            os_free(dev);
+        }
+    }
+}
+
+struct dev_obj *dev_get(uint16 dev_id)
+{
+    struct dev_obj *dev = NULL;
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.devs;
+    while (dev) {
+        if (dev->dev_id == dev_id) {
+            break;
+        }
+        dev = dev->next;
+    }
+
+    if (dev && dev->hotplug) {
+        atomic_inc(&dev->ref);
+        if (atomic_read(&dev->ref) > 32) {
+            //os_printf(KERN_WARNING"Device %d Ref is %d, Maybe device reference exception!!!(%08x)\r\n", dev_id, atomic_read(&dev->ref),__builtin_return_address(0));
+        }
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return dev;
+}
+
+void dev_busy(struct dev_obj *dev, uint8 busy, uint8 set)
+{
+    uint32 flag = disable_irq();
+    if (set) {
+        dev->busy |= busy;
+    } else {
+        dev->busy &= ~busy;
+    }
+    enable_irq(flag);
+}
+
+__init int32 dev_register(uint16 dev_id, struct dev_obj *device)
+{
+    struct dev_obj *dev;
+
+    if (dev_id == 0 || device == NULL) {
+        return -EINVAL;
+    }
+
+    if (atomic_read(&device->ref) == 0) {
+        atomic_set(&device->ref, 1); //未初始化
+    }
+
+    dev = dev_get(dev_id);
+    if (dev) {
+        dev_put(dev);
+        os_printf(KERN_WARNING"Device id %d already exists!!\r\n", dev_id);
+        return -EEXIST;
+    }
+
+#ifdef CONFIG_SLEEP
+    os_blklist_init(&device->blklist);
+#endif
+    device->dev_id = dev_id;
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    device->next = s_dev_mgr.devs;
+    s_dev_mgr.devs = device;
+    atomic_inc(&device->ref);
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+
+int32 dev_unregister(struct dev_obj *device)
+{
+    struct dev_obj *dev = NULL;
+    struct dev_obj *last = NULL;
+
+    if (device == NULL) {
+        return RET_OK;
+    }
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.devs;
+    while (dev) {
+        if (dev == device) {
+            if (device == s_dev_mgr.devs) {
+                s_dev_mgr.devs = device->next;
+            } else {
+                last->next = device->next;
+            }
+#ifdef CONFIG_SLEEP
+            os_blklist_del(&device->blklist);
+#endif
+            break;
+        }
+        last = dev;
+        dev  = dev->next;
+    }
+
+    dev_put(device);
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+
+#ifdef CONFIG_SLEEP
+int32 dev_suspended(struct dev_obj *dev, uint8 suspend)
+{
+    if (dev->suspend && suspend && !__in_interrupt()) { /* 非中断上下文，直接挂起当前task */
+        os_printf(KERN_WARNING"device %d has been suspended!\r\n", dev->dev_id);
+        os_blklist_suspend(&dev->blklist, NULL);
+    }
+    return dev->suspend;
+}
+
+__weak int32 dev_suspend_hook(struct dev_obj *dev, uint16 type)
+{
+    return 1;
+}
+int32 dev_suspend(uint16 type)
+{
+    int32 loop;
+    struct dev_obj *dev = NULL;
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.devs;
+    while (dev) {
+        if (dev->ops && dev->ops->suspend && !dev->suspend) {
+            os_printf("%s: func= %x\r\n", __func__, dev->ops->suspend);
+            if (dev_suspend_hook(dev, type)) {
+                loop = 0;
+                dev->suspend = 1;
+                while (dev->busy) {
+                    os_sleep_ms(1);
+                    if (loop++ > 100) {
+                        loop = 0;
+                        os_printf(KERN_WARNING"device %d busy !!!!\r\n", dev->dev_id);
+                    }
+                }
+                dev->ops->suspend(dev);
+            }
+        }
+        dev = dev->next;
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+
+__weak int32 dev_resume_hook(struct dev_obj *dev, uint16 type, uint32 wkreason)
+{
+    return 1;
+}
+int32 dev_resume(uint16 type, uint32 wkreason)
+{
+    struct dev_obj *dev = NULL;
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.devs;
+    while (dev) {
+        if (dev->ops && dev->ops->resume && dev->suspend) {
+            os_printf("%s: func= %x\r\n", __func__, dev->ops->resume);
+            if (dev_resume_hook(dev, type, wkreason)) {
+                dev->ops->resume(dev);
+                dev->suspend = 0;
+                os_blklist_resume(&dev->blklist);//唤醒所有被挂起的task
+            }
+        }
+        dev = dev->next;
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+#else
+int32 dev_suspended(struct dev_obj *dev, uint8 suspend)
+{
+    return 0;
+}
+
+__weak int32 dev_suspend_hook(struct dev_obj *dev, uint16 type)
+{
+    return 1;
+}
+int32 dev_suspend(uint16 type)
+{
+    return RET_ERR;
+}
+
+__weak int32 dev_resume_hook(struct dev_obj *dev, uint16 type, uint32 wkreason)
+{
+    return 1;
+}
+int32 dev_resume(uint16 type, uint32 wkreason)
+{
+    return RET_ERR;
+}
+
+#endif
+
+int32 dev_hotplug_in(void *hdl, uint16 dev_id, uint16 dev_type, void *info)
+{
+    struct dev_hotplug_obj *dev;
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.hotplug;
+    while (dev) {
+        if (dev->hdl == hdl) {
+            break;
+        }
+        dev = dev->next;
+    }
+
+    if (dev) {
+        dev->dev_id   = dev_id;
+        dev->dev_type = dev_type;
+        dev->info     = info;
+    } else {
+        dev = os_zalloc(sizeof(struct dev_hotplug_obj));
+        if (dev) {
+            dev->hdl      = hdl;
+            dev->dev_id   = dev_id;
+            dev->dev_type = dev_type;
+            dev->info     = info;
+            dev->next = s_dev_mgr.hotplug;
+            s_dev_mgr.hotplug = dev;
+        }
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return dev ? RET_OK : -ENOMEM;
+}
+
+int32 dev_hotplug_out(void *hdl)
+{
+    struct dev_hotplug_obj *dev  = NULL;
+    struct dev_hotplug_obj *prev = NULL;
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.hotplug;
+    while (dev) {
+        if (dev->hdl == hdl) {
+            if (prev == NULL) {
+                s_dev_mgr.hotplug = dev->next;
+            } else {
+                prev->next = dev->next;
+            }
+            os_free(dev);
+            break;
+        } else {
+            prev = dev;
+            dev  = dev->next;
+        }
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+
+int32 dev_hotplug_walk(uint16 type, dev_hotplug_walkcb cb)
+{
+    struct dev_hotplug_obj *dev;
+
+    if (cb == NULL) {
+        return -EINVAL;
+    }
+
+    os_mutex_lock(&s_dev_mgr.mutex, osWaitForever);
+    dev = s_dev_mgr.hotplug;
+    while (dev) {
+        if (type == 0 || dev->dev_type == type) {
+            if (cb((const struct dev_hotplug_obj *)dev)) {
+                break;
+            }
+        }
+        dev = dev->next;
+    }
+    os_mutex_unlock(&s_dev_mgr.mutex);
+    return RET_OK;
+}
+

sdk/hal/dma.c

@@ -0,0 +1,385 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/dma.h"
+#include "osal/string.h"
+
+int32 dma_pause(struct dma_device *dma, uint32 ch)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->pause) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->pause(dma, ch);
+    }
+    return RET_ERR;
+}
+
+int32 dma_resume(struct dma_device *dma, uint32 ch)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->resume) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->resume(dma, ch);
+    }
+    return RET_ERR;
+}
+
+#pragma GCC push_options
+#pragma GCC optimize ("O3")
+void cache_deal_invalid(void *dst,uint32 n){
+	uint8 *d1;
+	uint8 *d2;
+	uint8 st_head,end_head;
+	d1 = (uint8 *)dst;
+	st_head = (uint32)d1%32;
+	end_head = 32 - ((uint32)d1+n)%32;
+	n = n+st_head+end_head;
+	d1 = d1 - st_head;
+	d2 = (uint8 *)((uint32)d1&0x0fffffff);
+	memcpy(d2,d1,32);
+	memcpy(d2+n-32,d1+n-32,32);
+	
+	sys_dcache_invalid_range((void *)d1, n);
+}
+
+void cache_deal_writeback(void *dst,uint32 n){
+	uint8 *d1;
+	uint8 *d2;
+	uint8 st_head,end_head;
+	d1 = (uint8 *)dst;
+	st_head = ((uint32)d1 % 32);
+	end_head = 32 - ((uint32)d1+n)%32;
+	n = n+st_head+end_head;
+	d1 = d1 - st_head;
+	d2 = (uint8 *)((uint32)d1&0x0fffffff);
+	memcpy(d2,d1,32);
+	memcpy(d2+n-32,d1+n-32,32);
+	
+	sys_dcache_clean_range((void *)d1, n);
+
+}
+void dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n)
+{
+	uint8  dma_buf[64];
+	uint8  *s,*d;
+	uint8  *s1,*d1,*s2,*d2;
+	uint32 i = 0;
+	uint32 addr;
+    ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
+	
+    struct dma_xfer_data xfer_data;
+	if(n <= 64){
+		s1 = (uint8 *)src;
+		d1 = (uint8 *)dst;
+		for(i = 0;i < n;i++){
+			d1[i] = s1[i];
+		}
+		return;
+	}
+
+	s1 = (uint8 *)src;
+	d1 = (uint8 *)dst;
+
+//	for(i = 0;i < 16;i++){        //处理头
+//		dma_buf[i] = s1[i];
+//	}
+    memcpy(dma_buf, s1, 32);
+
+	s2 = (uint8 *)src+n-32;
+	d2 = (uint8 *)dst+n-32;
+//	for(i = 0;i < 16;i++){        //处理头
+//		dma_buf[i+16] = s2[i];
+//	}
+	memcpy(dma_buf+32, s2, 32);
+	
+	n = n - 64;
+	s = (uint8 *)src+32;
+	d = (uint8 *)dst+32;
+
+
+    xfer_data.dest              = (uint32)d;
+    xfer_data.src               = (uint32)s;
+    xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+    xfer_data.element_num       = n;
+    xfer_data.dir               = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
+    xfer_data.src_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_id            = 0;
+    xfer_data.src_id            = 0;
+    xfer_data.irq_hdl           = NULL;
+    xfer_data.endian            = 0;
+	addr = (uint32)s;
+
+	
+	addr = addr&((0x7FFFFFFUL << 5));
+	s = (uint8*)addr;
+	addr = (uint32)d;
+	addr = addr&((0x7FFFFFFUL << 5));
+	d = (uint8*)addr;//&CACHE_CIR_INV_ADDR_Msk;
+    sys_dcache_clean_range((void *)s, (int32_t)s2-(int32_t)s);          //cache->psram
+	sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);	//psram cache invalid  //最后一行可能没有无效化	
+//	printf("===============s:%08x  d:%08x\r\n\r\n",s,d);
+//    xfer_data.irq_data          = 0;
+    ((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
+
+//    sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);
+
+//	for(i = 0;i < 16;i++){        //处理头
+//		d1[i] = dma_buf[i];
+//	}
+    memcpy(d1, dma_buf, 32);
+//	for(i = 0;i < 16;i++){        //处理尾
+//		d2[i] = dma_buf[i+16];
+//	}
+    memcpy(d2, dma_buf+32, 32);
+}
+
+void dma_memcpy_no_cache(struct dma_device *dma, void *dst, const void *src, uint32 n)
+{
+	//uint8  dma_buf[64];
+	uint8  *s,*d;
+	//uint8  *s1,*d1,*s2,*d2;
+	//uint32 i = 0;
+	uint32 addr;
+    ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
+	
+    struct dma_xfer_data xfer_data;
+
+	s = (uint8 *)src;
+	d = (uint8 *)dst;
+
+
+    xfer_data.dest              = (uint32)d;
+    xfer_data.src               = (uint32)s;
+    xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+    xfer_data.element_num       = n;
+    xfer_data.dir               = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
+    xfer_data.src_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_id            = 0;
+    xfer_data.src_id            = 0;
+    xfer_data.irq_hdl           = NULL;
+    xfer_data.endian            = 0;
+	addr = (uint32)s;
+
+    ((const struct dma_hal_ops *)dma->dev.ops)->only_hw_xfer(dma, &xfer_data);
+}
+
+void dma_memset_word(struct dma_device *dma, void *dst, uint32 c, uint32 n)
+{
+    uint32 val = c;
+	uint8 *d, *d1, *d2;
+	uint32 i = 0;
+    uint32 size  = 0;
+	uint32 addr;
+
+	if(n <= 64){
+        d1   = (uint8 *)dst;
+        i    = (uint32)dst % 4;
+        size = i + n;
+        for(;i < (size);i++){
+            *d1++ = (val >> ((i % 4)<<3));
+        }
+		return;
+	}	
+	
+	d1 = (uint8 *)(dst);
+	d2 = (uint8 *)(dst+n-32);
+	n  = n - 64;
+	d  = (uint8 *)(dst+32);
+
+	ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
+	struct dma_xfer_data xfer_data;
+	xfer_data.dest				= (uint32)d;
+	xfer_data.src				= (uint32)&val;
+	xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	xfer_data.element_num		= n;
+	xfer_data.dir				= (((uint32)dst) < SRAM_BASE) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
+	xfer_data.src_addr_mode 	= DMA_XFER_MODE_RECYCLE;
+	xfer_data.dst_addr_mode 	= DMA_XFER_MODE_INCREASE;
+	xfer_data.dst_id			= 0;
+	xfer_data.src_id			= 0;
+	xfer_data.irq_hdl			= NULL;
+	xfer_data.irq_data		    = 0;
+    xfer_data.endian            = 0;
+
+	addr = (uint32)d;
+	addr = addr&((0x7FFFFFFUL << 5));
+	d    = (uint8 *)addr;//&CACHE_CIR_INV_ADDR_Msk;		
+	sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);
+
+    ((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
+
+    i    = (uint32)dst % 4;
+    size = i + 32;
+	for(;i < (size);i++){        //处理头
+		*d1++ = (val >> ((i % 4)<<3));
+	}
+    i    = (uint32)d2 % 4;
+    size = i + 32;
+    for(;i < (size);i++){            //处理尾
+        *d2++ = (val >> ((i % 4)<<3));
+    }
+}
+
+void dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n)
+{
+    uint32 val = c | (c<<8) | (c<<16) | (c<<24);
+    dma_memset_word(dma, dst, val, n);
+}
+
+#pragma GCC pop_options
+void dma_memcpy_endian(struct dma_device *dma, void *dst, const void *src, uint32 n, enum dma_endian_type type)
+{
+	uint32 dma_buf[16];
+	uint8  *s,*d;
+	uint8  *s1, *d1, *s2, *d2;
+    uint16 *s3, *d3, *s4;
+    uint32 *s5, *d5, *s6;
+	uint32 i = 0;
+	uint32 addr;
+	uint32 ret = RET_OK;
+    ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
+	
+    struct dma_xfer_data xfer_data;
+    switch (type)
+    {
+        case DMA_ENDIAN_TYPE_NO_OVERTURN:
+            s1 = (uint8 *)src;
+            d1 = (uint8 *)dst;
+            s2 = (uint8 *)dma_buf;
+            if (n <= 64)
+            {
+                for(i = 0; i < (n >> type); i++){
+                    *d1++ = *s1++;
+                }
+            } else {
+                for(i = 0; i < (32 >> type); i++){  // 处理头
+                    *s2++ = *s1++;
+                }
+                s1 = (uint8 *)((uint32)src+n-32);
+                for(i = 0; i < (32 >> type); i++){  // 处理尾
+                    *s2++ = *s1++;
+                }
+            }
+            break;
+        
+        case DMA_ENDIAN_TYPE_16BIT_OVERTURN:
+            s3 = (uint16 *)src;
+            d3 = (uint16 *)dst;
+            s4 = (uint16 *)dma_buf;
+            ret = (n % 2 != 0);  
+            if (!ret)
+            {
+                if (n <= 64)
+                {
+                    for(i = 0; i < (n >> type); i++){
+                        *d3++ = __REVSH(*s3++);
+                    }
+                } else {
+                    for(i = 0; i < (32 >> type); i++){  // 处理头
+                        *s4++ = __REVSH(*s3++);
+                    }
+                    s3 = (uint16 *)((uint32)src+n-32);
+                    for(i = 0; i < (32 >> type); i++){  // 处理尾
+                        *s4++ = __REVSH(*s3++);
+                    }
+                }
+            } else {
+                os_printf("dma memcpy size : %d endian: %d err\r\n", n, type);
+            }
+            break;
+
+        case DMA_ENDIAN_TYPE_32BIT_OVERTURN:
+            s5 = (uint32 *)src;
+            d5 = (uint32 *)dst;
+            s6 = (uint32 *)dma_buf;
+            ret = (n % 4 != 0);
+            if (!ret)
+            {
+                if (n <= 64)
+                {
+                    for(i = 0; i < (n >> type); i++){
+                        *d5++ = __REV(*s5++);
+                    }
+                } else {
+                    for(i = 0; i < (32 >> type); i++){  // 处理头
+                        *s6++ = __REV(*s5++);
+                    }
+                    s5 = (uint32 *)((uint32)src+n-32);
+                    for(i = 0; i < (32 >> type); i++){  // 处理尾
+                        *s6++ = __REV(*s5++);
+                    }
+                }
+            } else {
+                os_printf("dma memcpy size : %d endian: %d err\r\n", n, type);
+            }
+            break;
+        
+        default:
+            os_printf("dma memcpy endian type err!");
+            ret = RET_ERR;
+            break;
+    }
+    if (ret || (n <= 64))   return;
+
+    s1 = (uint8 *)src;
+	d1 = (uint8 *)dst;
+    s2 = (uint8 *)(src+n-32);
+    d2 = (uint8 *)(dst+n-32);
+    n  = n - 64;
+    s  = (uint8 *)(src+32);
+	d  = (uint8 *)(dst+32);
+    xfer_data.dest              = (uint32)d;
+    xfer_data.src               = (uint32)s;
+    xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+    xfer_data.element_num       = n;
+    xfer_data.dir               = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
+    xfer_data.src_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_addr_mode     = DMA_XFER_MODE_INCREASE;
+    xfer_data.dst_id            = 0;
+    xfer_data.src_id            = 0;
+    xfer_data.irq_hdl           = NULL;
+    xfer_data.endian            = type;
+    addr = (uint32)s;
+	addr = addr&((0x7FFFFFFUL << 5));
+	s = (uint8*)addr;
+	addr = (uint32)d;
+	addr = addr&((0x7FFFFFFUL << 5));
+	d = (uint8*)addr;//&CACHE_CIR_INV_ADDR_Msk;
+    sys_dcache_clean_range((void *)s, (int32_t)s2-(int32_t)s);          //cache->psram
+	sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);	//psram cache invalid  //最后一行可能没有无效化	
+
+    ((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
+    memcpy(d1, dma_buf, 32);
+    memcpy(d2, (void *)((uint32)dma_buf+32), 32);
+}
+
+int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, data);
+    }
+    return RET_ERR;
+}
+
+int32 dma_status(struct dma_device *dma, uint32 ch)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->get_status) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->get_status(dma, ch);
+    }
+    return RET_ERR;
+}
+
+int32 dma_stop(struct dma_device *dma, uint32 ch)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->stop) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->stop(dma, ch);
+    }
+    return RET_ERR;
+}
+
+int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2)
+{
+    if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->ioctl) {
+        return ((const struct dma_hal_ops *)dma->dev.ops)->ioctl(dma, cmd, param1, param2);
+    }
+    return RET_ERR;
+}

sdk/hal/dma2d.c

@@ -0,0 +1,110 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/dma2d.h"
+#include "string.h"
+
+int32 dma2d_blkcpy(struct dma2d_device *dma2d, struct dma2d_blkcpy_param *p_blkcpy)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->blkcpy) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->blkcpy(dma2d, p_blkcpy);
+    }
+    return RET_ERR;
+}
+
+int32 dma2d_memcpy(struct dma2d_device *dma2d, struct dma2d_memcpy_param *p_memcpy)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->memcpy) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->memcpy(dma2d, p_memcpy);
+    }
+    return RET_ERR;
+}
+
+int32 dma2d_memset(struct dma2d_device *dma2d, struct dma2d_memset_param *p_memset)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->memset) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->memset(dma2d, p_memset);
+    }
+    return RET_ERR;
+}
+
+int32 dma2d_convert(struct dma2d_device *dma2d, struct dma2d_convert_param *p_convert)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->convert) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->convert(dma2d, p_convert);
+    }
+    return RET_ERR;   
+}
+
+int32 dma2d_mixture(struct dma2d_device *dma2d, struct dma2d_mixture_param *p_mixture)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->mixture) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->mixture(dma2d, p_mixture);
+    }
+    return RET_ERR;   
+}
+
+int32 dma2d_check_status(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_CHECK_RESULT, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dma2d_abort_trans(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_ABORT, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dma2d_suspend_trans(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_SUSPEND, 0, 0);
+    }
+    return RET_ERR; 
+}
+
+int32 dma2d_suspend_status(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_SUSPEND_CHECK, 0, 0);
+    }
+    return RET_ERR; 
+}
+
+int32 dma2d_resume_trans(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_RESUME, 0, 0);
+    }
+    return RET_ERR; 
+}
+
+int32 dma2d_resume_status(struct dma2d_device *dma2d)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_RESUME_CHECK, 0, 0);
+    }
+    return RET_ERR; 
+}
+
+int32 dma2d_foreground_clut_init(struct dma2d_device *dma2d, struct dma2d_clut_param *p_clut)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_CONFIG_FG, (uint32)p_clut, 0);
+    }
+    return RET_ERR; 
+}
+
+int32 dma2d_background_clut_init(struct dma2d_device *dma2d, struct dma2d_clut_param *p_clut)
+{
+    if (dma2d && ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl) {
+        return ((const struct dma2d_hal_ops *)dma2d->dev.ops)->ioctl(dma2d, DMA2D_IOCTL_CONFIG_BG, (uint32)p_clut, 0);
+    }
+    return RET_ERR; 
+}

sdk/hal/dsi.c

@@ -0,0 +1,408 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/dsi.h"
+
+
+int32 dsi_init(struct dsi_device *p_dsi,uint8 clk_div,uint8_t tx_esc_clk_div,uint8_t auto_clklane,uint8_t lane_num,uint8_t clkselect,uint8_t div_strong)
+{
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->init) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->init(p_dsi,clk_div,tx_esc_clk_div,auto_clklane,lane_num,clkselect,div_strong);
+    }
+    return RET_ERR;
+}
+
+int32 dsi_deinit(struct dsi_device *p_dsi)
+{
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->deinit) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->deinit(p_dsi);
+    }
+    return RET_ERR;
+}
+
+int32 dsi_open(struct dsi_device *p_dsi)
+{
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->open) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->open(p_dsi);
+    }
+    return RET_ERR;
+}
+
+int32 dsi_close(struct dsi_device *p_dsi)
+{
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->close) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->close(p_dsi);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_set_lane_num(struct dsi_device *p_dsi,uint8 lane_num){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_LANE_NUM, lane_num,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_max_clk_time(struct dsi_device *p_dsi,uint32 max_clk){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_MAX_CLK_TIM, max_clk,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_remain_stop_state(struct dsi_device *p_dsi,uint8 state){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_REMAIN_STOP_STATE, state,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_cfg_enable(struct dsi_device *p_dsi,uint8_t htxeotp_en,uint8_t rxeotp_en,uint8_t bta_en,uint8_t ecc_en,uint8_t crc_en,uint8_t ltxeotp_en){
+	uint32_t enablebuf[2];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)enablebuf;
+		p8[0] = htxeotp_en;
+		p8[1] = rxeotp_en;
+		p8[2] = bta_en;
+		p8[3] = ecc_en;
+		p8[4] = crc_en;
+		p8[5] = ltxeotp_en;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CFG_ENABLE, (uint32)enablebuf,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_ulps_ctrl(struct dsi_device *p_dsi,uint8_t indatulps,uint8_t outdatulps,uint8_t inclkulps,uint8_t outclkulps){
+	uint32_t ulpsbuf[1];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)ulpsbuf;
+		p8[0] = indatulps;
+		p8[1] = outdatulps;
+		p8[2] = inclkulps;
+		p8[3] = outclkulps;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_ULPS_CTRL, (uint32)ulpsbuf,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_ulps_min_time(struct dsi_device *p_dsi,uint8 time){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_ULPS_MIN_TIME, time,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_ulps_entry_delay_time(struct dsi_device *p_dsi,uint32 time){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_ULPS_ENTRY_DELAY_TIME, time,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_ulps_wakeup_time(struct dsi_device *p_dsi,uint16 twakeup_clk,uint16 twakeup_cnt){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_ULPS_WAKEUP_TIME, twakeup_clk,twakeup_cnt);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_ulps_mode(struct dsi_device *p_dsi,uint8_t pll_off,uint8_t auto_ulps,uint8_t pre_pll_off_req){
+	uint32_t ulpsbuf[1];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)ulpsbuf;
+		p8[0] = pll_off;
+		p8[1] = auto_ulps;
+		p8[2] = pre_pll_off_req;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_ULPS_MODE, (uint32)ulpsbuf,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_select_mode(struct dsi_device *p_dsi,uint8 cmd){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CMD_VIDEO_SELECT_MODE, cmd,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_gen_vcid_cfg(struct dsi_device *p_dsi,uint8_t vcid,uint8_t vcid_tear_auto,uint8_t vcid_tx_auto){
+	uint8_t ulpsbuf[3];
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		ulpsbuf[0] = vcid;
+		ulpsbuf[1] = vcid_tear_auto;
+		ulpsbuf[2] = vcid_tx_auto;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GEN_VCID_CFG, (uint32)ulpsbuf,0);
+    }
+    return RET_ERR;
+}
+
+int32 mipi_dsi_cmd_mode_cfg(struct dsi_device *p_dsi,uint8_t te_ack,uint8_t ack,uint8_t sw0p_tx,uint8_t sw1p_tx,uint8_t sw2p_tx,uint8_t sr0p_tx,uint8_t sr1p_tx,uint8_t sr2p_tx,
+							uint8_t gen_lw_tx,uint8_t dcs_sw0p_tx,uint8_t dcs_sw1p_tx,uint8_t dcs_sr0p_tx,uint8_t dcs_lw_tx,uint8_t max_rd_pkt_size){
+	uint32_t cmdbuf[4];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)cmdbuf;
+		p8[0] = te_ack;
+		p8[1] = ack;
+		p8[2] = sw0p_tx;
+		p8[3] = sw1p_tx;
+		p8[4] = sw2p_tx;
+		p8[5] = sr0p_tx;
+		p8[6] = sr1p_tx;
+		p8[7] = sr2p_tx;
+		p8[8] = gen_lw_tx;
+		p8[9] = dcs_sw0p_tx;
+		p8[10] = dcs_sw1p_tx;
+		p8[11] = dcs_sr0p_tx;
+		p8[12] = dcs_lw_tx;
+		p8[13] = max_rd_pkt_size;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CMD_MODE_CFG, (uint32)cmdbuf,0);
+    }
+    return RET_ERR;
+}
+							
+
+int32 mipi_dsi_dpi_vcid(struct dsi_device *p_dsi,uint8 vcid){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_DPI_VCID, vcid,0);
+    }
+    return RET_ERR;	
+}							
+
+int32 mipi_dsi_color_cfg(struct dsi_device *p_dsi,uint8_t color_mode,uint8_t loosely18_en){
+	uint32_t colorbuf[1];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)colorbuf;
+		p8[0] = color_mode;
+		p8[1] = loosely18_en;		
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_COLOR_CFG, (uint32)colorbuf,0);
+    }
+    return RET_ERR;	
+}							
+
+int32 mipi_dsi_cfg_pol(struct dsi_device *p_dsi,uint8_t dataen_active,uint8_t vsync_active,uint8_t hsync_active,uint8_t shutd_active,uint8_t colorm_active){
+	uint32_t polbuf[2];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)polbuf;
+		p8[0] = dataen_active;
+		p8[1] = vsync_active;
+		p8[2] = hsync_active;
+		p8[3] = shutd_active;
+		p8[4] = colorm_active;		
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CFG_POL, (uint32)polbuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_vid_mode(struct dsi_device *p_dsi,uint8_t vsa_en,uint8_t vbp_en,uint8_t vfp_en,uint8_t vact_en,uint8_t hbp_en,uint8_t hfp_en,uint8_t frame_bta_ack_en,uint8_t cmd_en,uint8_t vid_mode_type){
+	uint32_t vidbuf[3];
+	uint8_t *p8;
+	if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)vidbuf;
+		p8[0] = vsa_en;
+		p8[1] = vbp_en;
+		p8[2] = vfp_en;
+		p8[3] = vact_en;
+		p8[4] = hbp_en;		
+		p8[5] = hfp_en;
+		p8[6] = frame_bta_ack_en;
+		p8[7] = cmd_en;
+		p8[8] = vid_mode_type;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_VID_MODE, (uint32)vidbuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_vid_pkt_size(struct dsi_device *p_dsi,uint32 size){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_VID_PKT_SIZE, size,0);
+    }
+    return RET_ERR;	
+}	
+
+int32 mipi_dsi_vid_chunk_num(struct dsi_device *p_dsi,uint32 chunk_num){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_VID_CHUNK_NUM, chunk_num,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_vid_null_size(struct dsi_device *p_dsi,uint32 null_num){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_VID_NULL_SIZE, null_num,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_vid_cfg(struct dsi_device *p_dsi,uint32 dpi2laneclkratio,uint32_t vid_vsa,uint32_t vid_vbp,uint32_t vid_vactive,uint32_t w,uint32_t vid_vfp,uint8_t hsa,uint8_t hbp,uint8_t hfp){
+	uint32_t vidbuf[9];
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		vidbuf[0] = dpi2laneclkratio;
+		vidbuf[1] = vid_vsa;
+		vidbuf[2] = vid_vbp;
+		vidbuf[3] = vid_vactive;
+		vidbuf[4] = w;		
+		vidbuf[5] = vid_vfp;
+		vidbuf[6] = hsa;
+		vidbuf[7] = hbp;
+		vidbuf[8] = hfp;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_VID_CFG, (uint32)vidbuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_lpcmd_tmr(struct dsi_device *p_dsi,uint16_t invact_lptime,uint16_t outvact_lptime){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_LPCMD_TMR, invact_lptime,outvact_lptime);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_edpi_cfg(struct dsi_device *p_dsi,uint16_t edpi_maxpkt,uint8_t hw_te_on,uint8_t hw_te_gen,uint8_t hw_scan_line,uint16_t line_parameter){
+	uint32_t edpibuf[5];
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		edpibuf[0] = edpi_maxpkt;
+		edpibuf[1] = hw_te_on;
+		edpibuf[2] = hw_te_gen;
+		edpibuf[3] = hw_scan_line;
+		edpibuf[4] = line_parameter;		
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_EDPI_CFG, (uint32)edpibuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_phy_rst(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_DPHY_RST, 0,0);
+    }
+    return RET_ERR;	
+}
+
+
+int32 mipi_dsi_set_pixel_sram_fifo(struct dsi_device *p_dsi,uint32 gen_addr){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_PIXEL_GENERIC_SRAM_FIFO,gen_addr,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_set_fifo_depth(struct dsi_device *p_dsi,uint32 depth){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_FIFO_DEPTH, depth,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_cmd_pkt_fifo_empty(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CMD_PKT_FIFO_EMPTY, 0,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_wait_pkt_fifo_full(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_WAIT_PKT_FIFO_FULL, 0,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_gen_pld_write_full(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GEN_PLD_WRITE_FULL, 0,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_gen_pld_read_empty(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GEN_PLD_READ_EMPTY, 0,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_cmd_cfg(struct dsi_device *p_dsi,uint8_t cmdid,uint8_t cmd,uint8_t vcid,uint8_t dat){
+	uint32_t cmdbuf[1];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)cmdbuf;
+		p8[0] = dat;
+		p8[1] = cmd;
+		p8[2] = vcid;
+		p8[3] = cmdid;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_CMD_CFG, (uint32)cmdbuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_set_gen_pld_data(struct dsi_device *p_dsi,uint8_t param0,uint8_t param1,uint8_t param2,uint8_t param3){
+	uint32_t databuf[1];
+	uint8_t *p8;
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)databuf;
+		p8[0] = param0;
+		p8[1] = param1;
+		p8[2] = param2;
+		p8[3] = param3;
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_SET_GEN_PLD_DATA, (uint32)databuf,0);
+    }
+    return RET_ERR;	
+}
+
+int32 mipi_dsi_get_gen_pld_data(struct dsi_device *p_dsi){
+    if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+        return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GET_GEN_PLD_DATA, 0,0);
+    }
+    return RET_ERR;	
+}
+
+
+int32 mipi_dsi_get_sta0(struct dsi_device *p_dsi){
+	if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GET_STA0, 0,0);
+	}
+	return RET_ERR; 
+}
+
+int32 mipi_dsi_get_sta1(struct dsi_device *p_dsi){
+	if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_GET_STA1, 0,0);
+	}
+	return RET_ERR; 
+}
+
+//2 1 2 3 4 1 1 0 0 0
+
+int32 mipi_dsi_set_lane_remap(struct dsi_device *p_dsi,uint8_t clklane,uint8_t lane0,uint8_t lane1,uint8_t lane2,uint8_t lane3,uint8_t clk_pol,uint8_t lane0_pol,uint8_t lane1_pol,uint8_t lane2_pol,uint8_t lane3_pol){
+	uint32_t databuf[3];
+	uint8_t *p8;
+	if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		p8 = (uint8_t *)databuf;
+		p8[0] = clklane;
+		p8[1] = lane0;
+		p8[2] = lane1;
+		p8[3] = lane2;
+		p8[4] = lane3;
+		p8[5] = clk_pol;
+		p8[6] = lane0_pol;
+		p8[7] = lane1_pol;
+		p8[8] = lane2_pol;
+		p8[9] = lane3_pol;
+		return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_SET_IO_REMAP, (uint32)databuf,0);
+	}
+	return RET_ERR; 
+}
+
+int32 mipi_dsi_reset_module(struct dsi_device *p_dsi){	
+	if (p_dsi && ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl) {
+		return ((const struct dsi_hal_ops *)p_dsi->dev.ops)->ioctl(p_dsi, DSI_IOCTL_RESET_MODULE, 0,0);
+	}
+	return RET_ERR;
+}

sdk/hal/dual_org.c

@@ -0,0 +1,189 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/dual_org.h"
+
+int32 dual_init(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->init) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->init(p_dual);
+    }
+    return RET_ERR;
+}
+
+int32 dual_deinit(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->deinit) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->deinit(p_dual);
+    }
+    return RET_ERR;
+}
+
+int32 dual_open(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->open) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->open(p_dual);
+    }
+    return RET_ERR;
+}
+
+int32 dual_close(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->close) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->close(p_dual);
+    }
+    return RET_ERR;
+}
+
+int32 dual_request_irq(struct dual_device *p_dual, uint32 irq_flags, dual_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->request_irq) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->request_irq(p_dual, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 dual_release_irq(struct dual_device *p_dual, uint32 irq_flags)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->release_irq) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->release_irq(p_dual, irq_flags);
+    }
+    return RET_ERR;
+}
+
+
+int32 dual_input_type(struct dual_device *p_dual,uint8 src,uint8 type){
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_INPUT_TYPE, src, type);
+    }
+    return RET_ERR;
+}
+
+//0:WR0/1 + RD0/1
+//1:WR0
+//2:WR1
+//3:RD0
+//4:RD1
+int32 dual_work_mode(struct dual_device *p_dual,uint8 mode){
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_WORK_MODE, mode, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 dual_input_src_num(struct dual_device *p_dual,uint8 num){
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_INPUT_NUM, num, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dual_open_hdr(struct dual_device *p_dual,uint8 en){
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_OPEN_HDR, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dual_timer_cfg(struct dual_device *p_dual,uint32_t fs_clk_num,uint32_t hs_timer,uint32_t vs_timer){
+	uint32_t  time_buf[3];
+	if(hs_timer == 1){
+		time_buf[0] = fs_clk_num/4;
+		time_buf[1] = 15; //sys_240MHz, 1us/per_15
+		time_buf[2] = 256;
+	}else{
+		time_buf[0] = fs_clk_num/4;
+		time_buf[1] = hs_timer*(DEFAULT_SYS_CLK/1000000)/16;
+		time_buf[2] = vs_timer*(DEFAULT_SYS_CLK/1000000)/256;
+	}
+
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_TIMER_CFG, (uint32)time_buf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dual_size_cfg(struct dual_device *p_dual,uint32_t src0_w,uint32_t src1_w,uint32_t src0_raw_num,uint32_t src1_raw_num){
+	uint32_t  cfgbuf[4];
+	cfgbuf[0] = src0_w;
+	cfgbuf[1] = src1_w;
+	cfgbuf[2] = src0_raw_num;
+	cfgbuf[3] = src1_raw_num;
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+        return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_SIZE_CFG, (uint32)cfgbuf, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 dual_fs_trig(struct dual_device *p_dual,uint32 fs_trig_num){
+	if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_FS_TRIG, fs_trig_num, 0);
+	}
+	return RET_ERR;
+}
+
+int32 dual_rd_trig(struct dual_device *p_dual,uint32 rd0_trig,uint32 rd1_trig){
+	if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_RD_TRIG, rd0_trig, rd1_trig);
+	}
+	return RET_ERR;
+}
+
+int32 dual_wr_cnt_cfg(struct dual_device *p_dual,uint32 src0_w,uint32 src0_h,uint32 src1_w,uint32 src1_h,uint32 src0_raw_num,uint32 src1_raw_num){
+	uint32_t  cfgbuf[6];
+	cfgbuf[0] = src0_w;
+	cfgbuf[1] = src0_h;
+	cfgbuf[2] = src1_w;
+	cfgbuf[3] = src1_h;
+	cfgbuf[4] = src0_raw_num;
+	cfgbuf[5] = src1_raw_num;
+
+	if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_WR_CNT_CFG, (uint32)cfgbuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 dual_set_addr(struct dual_device *p_dual,uint32 psram_Src0,uint32 psram_Src1){
+	if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SET_PSRAM_ADDR, psram_Src0, psram_Src1);
+	}
+	return RET_ERR;
+}
+
+int32 dual_save_cfg(struct dual_device *p_dual, uint32 channel, uint32 img_size)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SAVE_CFG, channel, img_size);
+	}
+	return RET_ERR; 
+}
+
+int32 dual_recover_cfg(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_RECOVER_CFG, 0, 0);
+	}
+	return RET_ERR; 
+}
+
+int32 dual_save_status(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_SAVE_STA, 0, 0);
+	}
+	return RET_ERR; 
+}
+
+int32 dual_kick_read(struct dual_device *p_dual)
+{
+    if (p_dual && ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl) {
+		return ((const struct dual_hal_ops *)p_dual->dev.ops)->ioctl(p_dual, DUAL_IOCTL_KICK_READ, 0, 0);
+	}
+	return RET_ERR; 
+}
+

sdk/hal/dvp.c

@@ -0,0 +1,242 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/dvp.h"
+
+int32 dvp_open(struct dvp_device *p_dvp)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->open) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->open(p_dvp);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_close(struct dvp_device *p_dvp)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->close) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->close(p_dvp);
+    }
+    return RET_ERR;
+}
+
+
+int32 dvp_init(struct dvp_device *p_dvp)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->init) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->init(p_dvp);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_deinit(struct dvp_device *p_dvp)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->deinit) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->deinit(p_dvp);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_baudrate(struct dvp_device *p_dvp, uint32 mclk)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->baudrate) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->baudrate(p_dvp, mclk);
+    }
+    return RET_ERR;
+
+}
+
+int32 dvp_set_size(struct dvp_device *p_dvp, uint32 x_s, uint32 y_s, uint32 x_e, uint32 y_e)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        uint32 size_array[4] = {x_s, y_s, x_e, y_e};
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_SIZE, (uint32)size_array, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_addr1(struct dvp_device *p_dvp, uint32 yuv_addr)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_ADR_1, yuv_addr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_addr2(struct dvp_device *p_dvp, uint32 yuv_addr)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_ADR_2, yuv_addr, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 dvp_set_rgb2yuv(struct dvp_device *p_dvp, uint8 en)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_RGB_2_YUV, en, 0);
+    }
+    return RET_ERR;
+
+}
+
+int32 dvp_set_exchange_d5_d6(struct dvp_device *p_dvp, uint8 en)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_EX_D5_D6, en, 0);
+    }
+    return RET_ERR;
+
+}
+
+int32 dvp_set_vsync_rst_offline(struct dvp_device *p_dvp,uint8 enable,uint32 timeout)
+{
+	if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+		return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_VSYNC_RST_TM, timeout, enable);
+	}
+	return RET_ERR;
+
+}
+
+
+int32 dvp_set_format(struct dvp_device *p_dvp, uint8 format)      ///*
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_FORMAT, format, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_half_size(struct dvp_device *p_dvp, uint8 en)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_SCEN, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_vsync_polarity(struct dvp_device *p_dvp, uint8 high_valid)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_VSYNC_VAILD, high_valid, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_hsync_polarity(struct dvp_device *p_dvp, uint8 high_valid)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_HSYNC_VAILD, high_valid, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_once_sampling(struct dvp_device *p_dvp, uint8 en)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_ONE_SAMPLE, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_debounce_enable(struct dvp_device *p_dvp, uint8 en, uint8 pixel)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_DEBOUNCE, en, pixel);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_set_ycbcr(struct dvp_device *p_dvp, uint8 mode)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_YCBCR_MODE, mode, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_unload_uv(struct dvp_device *p_dvp, uint8 en)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_DIS_UV_MODE, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_frame_load_precent(struct dvp_device *p_dvp, uint8 precent)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_FRAME_RATE, precent, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_get_status(struct dvp_device *p_dvp)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_GET_STA, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_low_high_threshold(struct dvp_device *p_dvp, bool low_high)
+{
+    uint32 dlt, dht;
+    if (low_high == 0) {
+        dlt = 0x00000030;
+        dht = 0x00ffffA0;
+    } else {
+        dht = 0x00ffffff;
+        dlt = 0;
+    }
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_THRESHOLD, dlt, dht);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_jpeg_mode_set_len(struct dvp_device *p_dvp, uint32 len)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_SET_JPEG_LEN, len, 0);
+    }
+    return RET_ERR;
+
+}
+
+
+int32 dvp_10BITS_map(struct dvp_device *p_dvp, uint8 mode)
+{
+	if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+		return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_10BITS_MAP, mode, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 dvp_8BITS_map(struct dvp_device *p_dvp, uint8 mode)
+{
+	if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl) {
+		return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->ioctl(p_dvp, DVP_IOCTL_CMD_8BITS_MAP, mode, 0);
+	}
+	return RET_ERR;
+}
+
+int32 dvp_request_irq(struct dvp_device *p_dvp, uint32 irq_flags, dvp_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->request_irq) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->request_irq(p_dvp, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 dvp_release_irq(struct dvp_device *p_dvp, uint32 irq_flags)
+{
+    if (p_dvp && ((const struct dvp_hal_ops *)p_dvp->dev.ops)->release_irq) {
+        return ((const struct dvp_hal_ops *)p_dvp->dev.ops)->release_irq(p_dvp, irq_flags);
+    }
+    return RET_ERR;
+}
+

sdk/hal/gen420.c

@@ -0,0 +1,98 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/gen420.h"
+
+int32 gen420_suspend(struct gen420_device *p_gen)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->suspend) {
+		return ((const struct gen420_hal_ops *)p_gen->dev.ops)->suspend(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_resume(struct gen420_device *p_gen)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->resume) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->resume(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_open(struct gen420_device *p_gen)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->open) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->open(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_close(struct gen420_device *p_gen)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->close) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->close(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_request_irq(struct gen420_device *p_gen, uint32 irq_flags, gen420_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->request_irq) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->request_irq(p_gen, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_release_irq(struct gen420_device *p_gen, uint32 irq_flags)
+{
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->release_irq) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->release_irq(p_gen, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_sram_linebuf_adr(struct gen420_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr){
+	uint32 yuv_linebuf[3];
+	yuv_linebuf[0] = yadr;
+	yuv_linebuf[1] = uadr;
+	yuv_linebuf[2] = vadr;
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN420_IOCTL_CMD_SET_SRAM_ADR, (uint32)yuv_linebuf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_psram_adr(struct gen420_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr){
+	uint32 yuv_linebuf[3];
+	yuv_linebuf[0] = yadr;
+	yuv_linebuf[1] = uadr;
+	yuv_linebuf[2] = vadr;
+	if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN420_IOCTL_CMD_SET_PSRAM_ADR, (uint32)yuv_linebuf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_frame_size(struct gen420_device *p_gen,uint16 w,uint16 h){
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN420_IOCTL_CMD_SET_FRAME_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_dst_h264_and_jpg(struct gen420_device *p_gen,uint8 both){
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN420_IOCTL_CMD_DST_MODE, both,0);
+    }
+    return RET_ERR;
+}
+
+int32 gen420_dma_run(struct gen420_device *p_gen){
+    if (p_gen && ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen420_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN420_IOCTL_CMD_DMA_RUN,0,0);
+    }
+    return RET_ERR;
+}
+

sdk/hal/gen422.c

@@ -0,0 +1,140 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/gen422.h"
+
+int32 gen422_suspend(struct gen422_device *p_gen)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->suspend) {
+		return ((const struct gen422_hal_ops *)p_gen->dev.ops)->suspend(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_resume(struct gen422_device *p_gen)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->resume) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->resume(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_open(struct gen422_device *p_gen)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->open) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->open(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_close(struct gen422_device *p_gen)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->close) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->close(p_gen);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_request_irq(struct gen422_device *p_gen, uint32 irq_flags, gen422_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->request_irq) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->request_irq(p_gen, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_release_irq(struct gen422_device *p_gen, uint32 irq_flags)
+{
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->release_irq) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->release_irq(p_gen, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_sw_enable(struct gen422_device *p_gen,uint8 enable){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SW_ENABLE, enable, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_output_enable(struct gen422_device *p_gen,uint8 vpp_en,uint8 bt_en){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_OUTPUT_SELECT, vpp_en, bt_en);
+    }
+    return RET_ERR;
+}
+
+//0 :yuyv  1 :yvyu  2 :uyvy  3 :vyuy
+int32 gen422_yuv_mode(struct gen422_device *p_gen,uint8 yuv_mode){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_YUV_MODE, yuv_mode, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_input_from_sram_or_psram(struct gen422_device *p_gen,uint8 is_sram){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_INPUT_SRC, is_sram, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_output_single_mode(struct gen422_device *p_gen,uint8 single){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SINGLE_MODE, single, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_frame_size(struct gen422_device *p_gen,uint16 w,uint16 h){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SET_FRAME_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_frame_time(struct gen422_device *p_gen,uint32 vsync,uint32 hsync,uint32 pclk){
+	uint32 time[3];
+	time[0] = vsync;
+	time[1] = hsync;
+	time[2] = pclk;	
+	if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+		return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SET_FRAME_TIMING, (uint32)time, 0);
+	}
+	return RET_ERR;
+}
+
+int32 gen422_sram_linebuf_adr(struct gen422_device *p_gen,uint32 yadr,uint32 uadr,uint32 vadr){
+	uint32 yuv_linebuf[3];
+	yuv_linebuf[0] = yadr;
+	yuv_linebuf[1] = uadr;
+	yuv_linebuf[2] = vadr;
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SET_SRAM_ADDR, (uint32)yuv_linebuf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_psram_adr(struct gen422_device *p_gen,uint32 frame0,uint32 frame1,uint32 w,uint32 h){
+	uint32 framebuf[2];
+	framebuf[0] = frame0;
+	framebuf[1] = frame1;
+	
+
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_SET_PSRAM_ADDR, (uint32)framebuf, (w<<16)|h);
+    }
+    return RET_ERR;
+}
+
+int32 gen422_dma_run(struct gen422_device *p_gen){
+    if (p_gen && ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl) {
+        return ((const struct gen422_hal_ops *)p_gen->dev.ops)->ioctl(p_gen, GEN422_IOCTL_CMD_DMA_RUN,0,0);
+    }
+    return RET_ERR;
+}
+
+

sdk/hal/gpio.c

@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file       sdk/hal/gpio.h
+  * @author     HUGE-IC Application Team
+  * @version    V1.0.0
+  * @date       2022-01-11
+  * @brief      This file contains all the GPIO HAL functions.
+  * @copyright  Copyright (c) 2016-2022 HUGE-IC
+  ******************************************************************************
+  * @attention
+  * None
+  *
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "typesdef.h"
+#include "errno.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/gpio.h"
+
+/** @defgroup Docxygenid_GPIO_Driver GPIO Driver
+  * @brief    Mainly the driver part of the GPIO module
+  * @{
+  */
+
+
+/** @defgroup Docxygenid_GPIO_function GPIO function
+  * @ingroup  Docxygenid_GPIO_Driver
+  * @brief    GPIO Initialization And Configuration function
+  * @{
+  */
+
+
+/**
+  * @brief  Set the gpio pin mode.
+  * @param  pin   : which pin to set.\n
+  *                 This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                 But the value of the y only be (0..5) when x is C.
+  * @param  mode  : Configure gpio_pin_mode, reference @ref gpio_pin_mode.
+  * @param  level : Configure gpio_pull_level, reference @ref gpio_private_pull_level.
+  * @return
+  *         - RET_OK  : GPIO set mode successfully.
+  *         - RET_ERR : GPIO set mode unsuccessfully.
+  */
+int32 gpio_set_mode(uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->mode) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->mode(gpio, pin, mode, level);
+    }
+
+    return RET_ERR;
+}
+
+/**
+  * @brief  Set the gpio pin direction.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @param  direction : Configure gpio pin direction, reference @ref gpio_pin_direction.
+  * @return
+  *         - RET_OK  : GPIO set direction successfully.
+  *         - RET_ERR : GPIO set direction unsuccessfully.
+  */
+int32 gpio_set_dir(uint32 pin, enum gpio_pin_direction direction)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->dir) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->dir(gpio, pin, direction);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @brief  Set the gpio pin value.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @param  direction : Configure gpio pin value, it can be 0 / 1.
+  * @return
+  *         - RET_OK  : GPIO pin set value successfully.
+  *         - RET_ERR : GPIO pin set value unsuccessfully.
+  */
+int32 gpio_set_val(uint32 pin, uint32 value)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->set) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->set(gpio, pin, value);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @brief  Get the gpio pin value.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @return
+  *         - value   : GPIO pin value, it can be 0 / 1.
+  *         - RET_ERR : Get gpio pin value unsuccessfully.
+  */
+int32 gpio_get_val(uint32 pin)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->get) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->get(gpio, pin);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @brief  Request the gpio pin interrupt.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @handler          : Interrupt handle, executed after the interrupt is generated.
+  * @data             : Parameters for interrupt handler.
+  * @evt              : Interrupt type, reference @ref gpio_irq_event.
+  * @return
+  *         - RET_OK  : GPIO request pin interrupt successfully.
+  *         - RET_ERR : GPIO request pin interrupt unsuccessfully.
+  */
+int32 gpio_request_pin_irq(uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->request_pin_irq) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->request_pin_irq(gpio, pin, handler, data, evt);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @brief  Release the gpio pin interrupt.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @evt              : Interrupt type, reference @ref gpio_irq_event.
+  * @return
+  *         - RET_OK  : GPIO release pin interrupt successfully.
+  *         - RET_ERR : GPIO release pin interrupt unsuccessfully.
+  */
+int32 gpio_release_pin_irq(uint32 pin, enum gpio_irq_event evt)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->release_pin_irq) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->release_pin_irq(gpio, pin, evt);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @brief  Configure the GPIO module by ioctl_cmd.
+  * @param  pin       : which pin to set.\n
+  *                     This parameter can be Px_y where x can be (A..C) and y can be (0..15)\n
+  *                     But the value of the y only be (0..5) when x is C.
+  * @cmd              : Commands to configure the GPIO module, reference @ref gpio_ioctl_cmd.
+  * @param1           : Parameter 1, according to the command.
+  * @param2           : Parameter 2, according to the command.
+  * @return
+  *         - RET_OK  : GPIO module configure successfully.
+  *         - RET_ERR : GPIO module configure unsuccessfully.
+  */
+int32 gpio_ioctl(uint32 pin, uint32 cmd, uint32 param1, uint32 param2)
+{
+    struct gpio_device *gpio = gpio_get(pin);
+    if (gpio && ((const struct gpio_hal_ops *)gpio->dev.ops)->ioctl) {
+        return ((const struct gpio_hal_ops *)gpio->dev.ops)->ioctl(gpio, pin, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+
+/** @} Docxygenid_GPIO_functions*/
+/** @} Docxygenid_GPIO_Driver*/
+
+
+
+/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/

sdk/hal/h264.c

@@ -0,0 +1,511 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/h264.h"
+
+int32 h264_suspend(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->suspend) {
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->suspend(p_h264);
+    }
+    return RET_ERR;
+}
+
+int32 h264_resume(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->resume) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->resume(p_h264);
+    }
+    return RET_ERR;
+}
+
+
+int32 h264_init(struct h264_device *p_h264,enum h264_module_clk clk_type)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->init) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->init(p_h264,clk_type);
+    }
+    return RET_ERR;
+}
+
+int32 h264_deinit(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->deinit) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->deinit(p_h264);
+    }
+    return RET_ERR;
+}
+
+int32 h264_open(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->open) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->open(p_h264);
+    }
+    return RET_ERR;
+}
+
+int32 h264_close(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->close) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->close(p_h264);
+    }
+    return RET_ERR;
+}
+
+int32 h264_is_running(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_IS_RUNNING, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_decode_start(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->decode) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->decode(p_h264);
+    }
+    return RET_ERR;
+}
+
+int32 h264_request_irq(struct h264_device *p_h264, uint32 irq_flags, h264_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->request_irq) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->request_irq(p_h264, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 h264_release_irq(struct h264_device *p_h264, uint32 irq_flags)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->release_irq) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->release_irq(p_h264, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_src_from(struct h264_device *p_h264, uint8_t src_from)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SRC_FROM, src_from, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_hw_open(struct h264_device *p_h264, uint8_t enable)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_HW_OPEN, enable, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_sw_buf_ready(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SW_BUF_READY, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_sw_frame_ready(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SW_FRAME_START, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_sw_ready(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SW_READY, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_vpp_vsync_delay(struct h264_device *p_h264, uint8_t enable)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_VPP_VSYNC_DEALY_EN, enable, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_wrap_img_size(struct h264_device *p_h264, uint16_t w,uint16_t h)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_WRAP_IMG_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_phy_img_size(struct h264_device *p_h264, uint16_t w,uint16_t h)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_PHY_IMG_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_frame_base_cfg(struct h264_device *p_h264, uint8_t frm_type,uint16_t enc_mode,uint32_t enc_bs_buf_size,uint32_t timeout_en)
+{
+	uint32_t basebuf[4];
+	uint32_t *p32;
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		p32 = basebuf;
+		p32[0] = frm_type;
+		p32[1] = enc_mode;
+		p32[2] = enc_bs_buf_size;
+		p32[3] = timeout_en;
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FRAME_BASE_CFG, (uint32)basebuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 h264_set_frame_qp(struct h264_device *p_h264, uint32_t frame_qp)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FRAME_QP, frame_qp, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_timeout_limit(struct h264_device *p_h264, uint32_t time)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_TIMEOUT_LIMIT, time, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_len_limit(struct h264_device *p_h264, uint32_t len)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_LEN_LIMIT, len, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_ref_lu_addr(struct h264_device *p_h264, uint32_t saddr, uint32_t eaddr)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_REF_LU_ADDR, saddr, eaddr);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_ref_chro_addr(struct h264_device *p_h264, uint32_t saddr, uint32_t eaddr)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_REF_CHRO_ADDR, saddr, eaddr);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_frame_num(struct h264_device *p_h264, uint32_t num)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_FRM_NUM, num, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_enc_cnt(struct h264_device *p_h264, uint32_t cnt)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_ENC_CNT, cnt, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_enc_frame_id(struct h264_device *p_h264, uint32_t id)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_ENC_FRAME_ID, id, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_buf_addr(struct h264_device *p_h264, uint32_t addr)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_DMA_BS_ADDR, addr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_frame_mb_num(struct h264_device *p_h264, uint32_t num)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FRAME_MB_NUM, num, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_ref_wb_addr(struct h264_device *p_h264, uint32_t lpf_lu_base, uint32_t lpf_ch_base)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_REF_WB_ADDR, lpf_lu_base, lpf_ch_base);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_ref_rb_addr(struct h264_device *p_h264, uint32_t last_lpf_lu_base, uint32_t last_lpf_ch_base)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_REF_RB_ADDR, last_lpf_lu_base, last_lpf_ch_base);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_frame_rate_ctl(struct h264_device *p_h264, uint32_t rc_grp,uint32_t rc_effort,uint32_t rc_en)
+{
+	uint32_t basebuf[3];
+	uint32_t *p32;
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		p32 = basebuf;
+		p32[0] = rc_grp;
+		p32[1] = rc_effort;
+		p32[2] = rc_en;
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_RATE_CTL, (uint32)basebuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 h264_get_rate_ctl(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_RATE_CTL, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_rate_ctl_byte(struct h264_device *p_h264,uint32_t byte)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_RATE_CTL_BYTE, byte, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_rate_ctl_rdcost(struct h264_device *p_h264,uint32_t rdcost)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_RATE_CTL_RDCOST, rdcost, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_3dnr(struct h264_device *p_h264,uint32_t dnr)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_FLT_3DNR, dnr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_flt_3dnr(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_FLT_3DNR, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_y_crop(struct h264_device *p_h264,uint32_t enable,uint32_t linenum)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_Y_CROP, enable, linenum);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_mb_pipe(struct h264_device *p_h264,uint32_t pipe)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_MB_PIPE, pipe, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_3dnr_lut(struct h264_device *p_h264,uint32_t num,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_3DNR_LUT, num, param);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_min_lut(struct h264_device *p_h264,uint32_t num,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_MIN_LUT, num, param);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_max_lut(struct h264_device *p_h264,uint32_t num,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_MAX_LUT, num, param);
+    }
+    return RET_ERR;
+}
+
+
+int32 h264_set_flt_3dnr_sf(struct h264_device *p_h264,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_3DNR_SF, param, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_3dnr_con(struct h264_device *p_h264,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_3DNR_CON, param, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_flt_3dnr_con1(struct h264_device *p_h264,uint32_t param)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_FLT_3DNR_CON1, param, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_bandwidth_wr(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_BANDWIDTH_WR, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_bandwidth_rd(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_BANDWIDTH_RD, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_cyc_done_num(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_DBG_CYC_DONE_NUM, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_frame_len(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_FRM_LEN, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_dec_del(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_DEC_DEL, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_sta(struct h264_device *p_h264,uint32_t sta)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_STA, sta, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_sta(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_STA, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_get_enc_frame_rdcost(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_ENC_FRM_RDCOST, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_enc_frame_rdcost(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_DEC_CLR_ENC_FUNCS, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_dec_headb_num(struct h264_device *p_h264,uint32_t dec_num)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_DEC_HEADB_NUM, dec_num, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_oe_select(struct h264_device *p_h264,uint8_t enable,uint8_t oe)
+{
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_OE_SELECT, enable, oe);
+	}
+	return RET_ERR;
+}
+
+
+int32 h264_get_mbl_calc(struct h264_device *p_h264)
+{
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_MBL_CALC, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 h264_get_imb_num(struct h264_device *p_h264)
+{
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_FRAME_IMB, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 h264_get_mbl_calc_max(struct h264_device *p_h264)
+{
+	if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+		return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_GET_MBL_CALC_MAX, 0, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 h264_is_err(struct h264_device *p_h264)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_IS_ERR, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 h264_set_err(struct h264_device *p_h264,uint32_t err)
+{
+    if (p_h264 && ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl) {
+        return ((const struct h264_hal_ops *)p_h264->dev.ops)->ioctl(p_h264, H264_IOCTL_SET_ERR, err, 0);
+    }
+    return RET_ERR;
+}

sdk/hal/i2c.c

@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    User/xxx.c
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    01-08-2018
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2018 HUGE-IC</center></h2>
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/i2c.h"
+
+/** @addtogroup Template_Project
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+int32 i2c_open(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr)
+{
+    if (i2c) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->open(i2c, mode, addr_mode, addr);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_close(struct i2c_device *i2c)
+{
+    if (i2c) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->close(i2c);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_set_baudrate(struct i2c_device *i2c, uint32 baudrate)
+{
+    if (i2c) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->baudrate(i2c, baudrate);
+    }
+
+    return RET_ERR;
+}
+
+int32 i2c_ioctl(struct i2c_device *i2c, uint32 cmd, uint32 param)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->ioctl) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->ioctl(i2c, cmd, param);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_read(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->read) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->read(i2c, addr, addr_len, buf, buf_len);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_write(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->write) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->write(i2c, addr, addr_len, buf, buf_len);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_write_scatter(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->write_scatter) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->write_scatter(i2c, addr, addr_len, data, count);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_master_write_table(struct i2c_device *i2c, uint8 cmd_len, uint8 slave_id, scatter_data *data)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->write_table) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->write_table(i2c, cmd_len, slave_id, data);
+    }
+    return RET_ERR; 
+}
+
+int32 i2c_request_irq(struct i2c_device *i2c, i2c_irq_hdl handle, uint32 irq_data, uint32 irq_flag)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->request_irq) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->request_irq(i2c, handle, irq_data, irq_flag);
+    }
+    return RET_ERR;
+}
+
+int32 i2c_release_irq(struct i2c_device *i2c, uint32 irq_flag)
+{
+    if (i2c && ((const struct i2c_hal_ops *)i2c->dev.ops)->release_irq) {
+        return ((const struct i2c_hal_ops *)i2c->dev.ops)->release_irq(i2c, irq_flag);
+    }
+    return RET_ERR;
+}
+
+
+/**
+  * @}
+  */
+
+/*************************** (C) COPYRIGHT 2018 HUGE-IC ***** END OF FILE *****/

sdk/hal/i2s.c

@@ -0,0 +1,70 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/i2s.h"
+
+int32 i2s_open(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits)
+{
+    if (i2s) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->open(i2s, mode, frequency, bits);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_close(struct i2s_device *i2s)
+{
+    if (i2s) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->close(i2s);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_write(struct i2s_device *i2s, const void *buf, uint32 len)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->write) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->write(i2s, buf, len);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_write_scatter(struct i2s_device *i2s, const scatter_data *data, uint32 count)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->write_scatter) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->write_scatter(i2s, data, count);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_read(struct i2s_device *i2s, void *buf, uint32 len)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->read) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->read(i2s, buf, len);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_ioctl(struct i2s_device *i2s, uint32 cmd, uint32 param)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->ioctl) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->ioctl(i2s, cmd, param);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_request_irq(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->request_irq) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->request_irq(i2s, irq_flag, irqhdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 i2s_release_irq(struct i2s_device *i2s, uint32 irq_flag)
+{
+    if (i2s && ((const struct i2s_hal_ops *)i2s->dev.ops)->release_irq) {
+        return ((const struct i2s_hal_ops *)i2s->dev.ops)->release_irq(i2s, irq_flag);
+    }
+    return RET_ERR;
+}
+

sdk/hal/jpeg.c

@@ -0,0 +1,236 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/jpeg.h"
+
+int32 jpg_open(struct jpg_device *p_jpg)
+{
+    if(p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->open) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->open(p_jpg);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_close(struct jpg_device *p_jpg)
+{
+    if(p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->close) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->close(p_jpg);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_init(struct jpg_device *p_jpg, uint32 table_idx, uint32 qt)
+{
+    if(p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->init) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->init(p_jpg, table_idx, qt);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_suspend(struct jpg_device *p_jpg)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->suspend) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->suspend(p_jpg);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_resume(struct jpg_device *p_jpg)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->resume) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->resume(p_jpg);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_is_online(struct jpg_device *p_jpg)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+	    return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_IS_ONLINE, 0, 0);
+	return RET_ERR;
+}
+
+int32 jpg_set_data_from(struct jpg_device *p_jpg, uint8 src_from)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+    	return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_SRC_FROM, src_from, 0);
+	return RET_ERR;
+}
+
+
+
+int32 jpg_set_size(struct jpg_device *p_jpg, uint32 h, uint32 w)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_SIZE, h, w);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_set_hw_check(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_HW_CHK, enable, 0);
+	return RET_ERR;
+}
+
+int32 jpg_open_debug(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+	    return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_OPEN_DBG, enable, 0);
+	return RET_ERR;
+}
+
+int32 jpg_soft_kick(struct jpg_device *p_jpg, uint8 kick)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+	    return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SOFT_KICK, kick, 0);
+	return RET_ERR;
+}
+
+int32 jpg_updata_dqt(struct jpg_device *p_jpg, uint32 *dqtbuf)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_UPDATE_QT, (uint32)dqtbuf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_set_addr(struct jpg_device *p_jpg, uint32 addr, uint32 len)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_ADR, addr, len);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_set_qt(struct jpg_device *p_jpg, uint32 qt)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_QT, qt, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 jpg_dec_len_cfg_enable(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_DEC_LEN_CFG_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 jpg_timeout_cfg_enable(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_TIMEOUT_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 jpg_timeout_cfg(struct jpg_device *p_jpg, uint32 timeout)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_TIMEOUT_CNT, timeout, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 jpg_auto_rekick_cfg(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_DECAUTO_RUN_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 jpg_try_dec_cfg(struct jpg_device *p_jpg, uint8 enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_DEC_FLUSH_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+
+
+int32 jpg_decode_target(struct jpg_device *p_jpg, uint8 to_scaler)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_DECODE_TAG, to_scaler, 0);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_is_idle(struct jpg_device *p_jpg)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+	    return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_IS_IDLE, 0, 0);
+	return RET_ERR;
+}
+
+int32 jpg_set_ready(struct jpg_device *p_jpg)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+	    return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_READY, 0, 0);
+	return RET_ERR;
+}
+
+int32 jpg_select_oe_using(struct jpg_device *p_jpg,uint8_t enable,uint8_t oe)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_OE_SELECT, enable, oe);
+	return RET_ERR;
+}
+
+int32 jpg_get_oe_ready(struct jpg_device *p_jpg)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_GET_OE, 0, 0);
+	return RET_ERR;
+}
+
+int32 jpg_set_oe_state(struct jpg_device *p_jpg,uint8_t oe)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_SET_OE, oe, 0);
+	return RET_ERR;
+}
+
+int32 jpg_set_vsync_dly(struct jpg_device *p_jpg,uint8_t enable)
+{
+	if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl)
+		return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->ioctl(p_jpg, JPG_IOCTL_CMD_VSYNC_DLY, enable, 0);
+	return RET_ERR;
+}
+
+
+
+int32 jpg_decode_photo(struct jpg_device *p_jpg, uint32 photo, uint32 len)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->decode) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->decode(p_jpg, photo, len);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_request_irq(struct jpg_device *p_jpg, jpg_irq_hdl isr, uint32 irq, void *dev_id)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->request_irq) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->request_irq(p_jpg, isr, irq, (uint32)dev_id);
+    }
+    return RET_ERR;
+}
+
+int32 jpg_release_irq(struct jpg_device *p_jpg, uint32 irq_flags)
+{
+    if (p_jpg && ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->release_irq) {
+        return ((const struct jpeg_hal_ops *)p_jpg->dev.ops)->release_irq(p_jpg, irq_flags);
+    }
+    return RET_ERR;
+}
+

sdk/hal/lcdc.c

@@ -0,0 +1,776 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/lcdc.h"
+#include "osal/string.h"
+
+int32 lcdc_suspend(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->suspend) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->suspend(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_resume(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->resume) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->resume(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_init(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->init) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->init(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_deinit(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->deinit) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->deinit(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_open(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->open) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->open(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_close(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->close) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->close(p_lcdc);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_request_irq(struct lcdc_device *p_lcdc, uint32 irq_flags, lcdc_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->request_irq) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->request_irq(p_lcdc, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_release_irq(struct lcdc_device *p_lcdc, uint32 irq_flags)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->release_irq) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->release_irq(p_lcdc, irq_flags);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_baudrate(struct lcdc_device *p_lcdc, uint32 mclk)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->baudrate) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->baudrate(p_lcdc, mclk);
+    }
+    return RET_ERR;
+
+}
+
+int32 lcdc_set_color_mode(struct lcdc_device *p_lcdc, enum lcdc_color_mode cm)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_COLOR_MODE, cm, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_bus_width(struct lcdc_device *p_lcdc, enum lcdc_bus_width bw)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_BUS_MODE, bw, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_interface(struct lcdc_device *p_lcdc, enum lcdc_interface_mode im)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_INTERFACE_MODE, im, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_colrarray(struct lcdc_device *p_lcdc, uint8 colrarray)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_COLRARRAY, colrarray, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p0p1_enable(struct lcdc_device *p_lcdc, uint8 p0_en,uint8 p1_en){
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_P0_P1_EN, p0_en, p1_en);
+	}
+	return RET_ERR;
+
+}
+
+int32 lcdc_set_lcd_vaild_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_LCD_VAILD_SIZE, (w<<16)|h, pixel_dot_num);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_lcd_visible_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_LCD_VISIBLE_SIZE, (w<<16)|h, pixel_dot_num);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_signal_config(struct lcdc_device *p_lcdc, uint8 vs_en,uint8 hs_en,uint8 de_en,uint8 vs_inv,uint8 hs_inv,uint8 de_inv,uint8 clk_inv)
+{
+	uint8 arg = 0;
+	arg  =  (  vs_en<<(0));
+	arg  |= (  hs_en<<(1));
+	arg  |= (  de_en<<(2));
+	arg  |= ( vs_inv<<(3));
+	arg  |= ( hs_inv<<(4));
+	arg  |= ( de_inv<<(5));
+	arg  |= (clk_inv<<(6));
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_SIGNAL_CONFIG, arg, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 lcdc_mcu_signal_config(struct lcdc_device *p_lcdc, uint8 value)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_MCU_SIGNAL_CONFIG, value, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_invalid_line(struct lcdc_device *p_lcdc, uint8 invalid_line)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_INVALID_LINE, invalid_line, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_valid_dot(struct lcdc_device *p_lcdc, uint32 w_start,uint32 h_start)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VALID_DOT, w_start, h_start);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_hlw_vlw(struct lcdc_device *p_lcdc, uint32 hlw,uint32 vlw)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_HLW_VLW, hlw, vlw);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_bigendian(struct lcdc_device *p_lcdc, uint8 en)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VIDEO_BIG_ENDIAN, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_video_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VIDEO_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p0_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P0_ROTATE_Y_SRC_ADDR, yaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p0_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P0_ROTATE_U_SRC_ADDR, uaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p0_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P0_ROTATE_V_SRC_ADDR, vaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p1_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P1_ROTATE_Y_SRC_ADDR, yaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p1_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P1_ROTATE_U_SRC_ADDR, uaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_p1_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P1_ROTATE_V_SRC_ADDR, vaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_rotate_p0_up(struct lcdc_device *p_lcdc, uint8 en)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_P0_UP, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_rotate_p0p1_start_location(struct lcdc_device *p_lcdc, uint32 x0,uint32 y0,uint32 x1,uint32 y1)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_P0P1_ROTATE_START_ADDR, (y0<<16)|x0, (y1<<16)|x1);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_rotate_linebuf_num(struct lcdc_device *p_lcdc, uint32 linebuf)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_LINE_BUF_NUM, linebuf, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_rotate_linebuf_y_addr(struct lcdc_device *p_lcdc, uint32 yaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_LINE_BUF_Y, yaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_rotate_linebuf_u_addr(struct lcdc_device *p_lcdc, uint32 uaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_LINE_BUF_U, uaddr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_rotate_linebuf_v_addr(struct lcdc_device *p_lcdc, uint32 vaddr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_LINE_BUF_V, vaddr, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 lcdc_set_rotate_mirror(struct lcdc_device *p_lcdc, uint8 mirror,enum lcdc_rotate_mode rotate)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_MIRROR, mirror, rotate);
+    }
+    return RET_ERR;
+} 
+
+int32 lcdc_set_rotate_p0p1_size(struct lcdc_device *p_lcdc, uint32 w0,uint32 h0,uint32 w1,uint32 h1)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROTATE_SET_SIZE, (w0<<16)|h0, (w1<<16)|h1);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_video_data_from(struct lcdc_device *p_lcdc, enum lcdc_video_mode vm)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VIDEO_MODE, vm, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_video_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VIDEO_START_ADDR, (y<<16)|x, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_video_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_VIDEO_EN, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_SIZE, (h<<16)|w, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_START_ADDR, y, x);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_dma_addr(struct lcdc_device *p_lcdc, uint32 addr)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_DMA_ADDR, addr, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_lut_addr(struct lcdc_device *p_lcdc, uint32 addr)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_LUTDMA_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 lcdc_set_osd_dma_len(struct lcdc_device *p_lcdc, uint32 len)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_DMA_LEN, len, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_format(struct lcdc_device *p_lcdc, enum lcdc_osd_format osd_format)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_FORMAT, osd_format, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_alpha(struct lcdc_device *p_lcdc, uint32 alpha)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ALPHA, alpha, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_head(struct lcdc_device *p_lcdc, uint32 head, uint32 head_tran)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_HEAD, head, head_tran);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_diap(struct lcdc_device *p_lcdc, uint32 diap, uint32 diap_tran)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_DIAP, diap, diap_tran);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_cfg(struct lcdc_device *p_lcdc, uint32 head, uint32 diap)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_CFG, head, diap);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_EN, en, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_src_addr(struct lcdc_device *p_lcdc, uint32 addr)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_SRC_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_dst_addr(struct lcdc_device *p_lcdc, uint32 addr)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_DST_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_osd_enc_src_len(struct lcdc_device *p_lcdc, uint32 len)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_SRC_LEN, len, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_get_osd_enc_dst_len(struct lcdc_device *p_lcdc)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_GET_OSD_ENC_DST_LEN, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_enc_start_run(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_START, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_set_start_run(struct lcdc_device *p_lcdc)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_START_RUN, 0, 0);
+    }
+    return RET_ERR;
+}
+
+
+int32 lcdc_mcu_write_reg(struct lcdc_device *p_lcdc,uint8 data)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_MCU_CPU_WRITE, data, 0);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_mcu_write_data(struct lcdc_device *p_lcdc,uint8 data)
+{
+    if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+        return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_MCU_CPU_WRITE, data, 1);
+    }
+    return RET_ERR;
+}
+
+int32 lcdc_reg_write_data(struct lcdc_device *p_lcdc,uint8 cmdlen,uint8 reglen, uint8 *buf)
+{
+	uint8_t data_buf[64];
+	data_buf[0] = cmdlen;
+	data_buf[1] = reglen;
+	memcpy(data_buf+2,buf,reglen+cmdlen);
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_REG_CPU_WRITE, (uint32)data_buf, 1);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_reg_read_data(struct lcdc_device *p_lcdc,uint8 cmdlen,uint8 reglen, uint8 *buf)
+{
+	//uint8_t data_buf[64];
+	//data_buf[0] = cmdlen;
+	//data_buf[1] = reglen;
+	//memcpy(data_buf+2,buf,reglen+cmdlen);
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_MCU_CPU_READ, (uint32)buf, 1);
+	}
+	return RET_ERR;
+}
+
+
+int32 lcdc_video_enable_constrast_saturation(struct lcdc_device *p_lcdc, uint8 constrast,uint8 saturation)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_CONSTRAST_SATURATION_EN, constrast, saturation);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_video_constrast_saturation_val(struct lcdc_device *p_lcdc, uint32 constrast,uint32 saturation)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_CONSTRAST_SATURATION_VAL, constrast, saturation);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_video_enable_ccm_gamma(struct lcdc_device *p_lcdc, uint8 ccm, uint8 gamma)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_CCM_GAMMA_EN, ccm, gamma);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_video_enable_auto_ks(struct lcdc_device *p_lcdc, uint8 enable)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_AUTO_KICK_EN, enable,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_set_timeout_info(struct lcdc_device *p_lcdc, uint8 enable,uint8 timeout)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_TIMEOUT_INF, enable,timeout);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_rot_burst_dw16(struct lcdc_device *p_lcdc, uint8 dw16)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_ROT_PSRAM_BURST_SW, dw16,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_qspi_cmd_dw4(struct lcdc_device *p_lcdc, uint8 dw4)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_QSPI_DW4, dw4,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_cmd_auto_send(struct lcdc_device *p_lcdc, uint32 cmd0,  uint32 cmd1)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_TXCMD_AUTO, cmd0,cmd1);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_spi_cs_lock_time(struct lcdc_device *p_lcdc, uint8 cs_setup,uint8 cs_hold,uint8 cs_high)
+{
+	uint32_t cs_time[1];
+	uint8_t *p8;
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		p8 = (uint8_t *)cs_time;
+		p8[0] = cs_setup;
+		p8[1] = cs_hold;
+		p8[2] = cs_high;
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_CS_LOCK_TIME, (uint32)cs_time,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_spi_dummy_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_SPI_DUMMY_EN, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dsi_tear_request(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DSI_TEAR_REQUEST, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dsi_reg_update(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DSI_REG_UPDATE, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dsi_dpi_colorm(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DSI_DPI_COLORM, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dsi_dpi_shutdown(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DSI_DPI_SHUT_DN, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dsi_select_edpi_or_dpi(struct lcdc_device *p_lcdc, uint8 edpi)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_EDSI_ITF_SELECT, edpi,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_clock_alway_on(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_CLK_ALWAY_ON, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_gamma_rgb_table(struct lcdc_device *p_lcdc, uint32 radr,uint32 gadr,uint32 badr)
+{
+	uint32 gamma_tbl[3];
+	gamma_tbl[0] = radr;
+	gamma_tbl[1] = gadr;
+	gamma_tbl[2] = badr;
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_GAMMA_RGB_ADR, (uint32)gamma_tbl,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_te_edge_cfg(struct lcdc_device *p_lcdc, uint8 pullup)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_TE_EDGE_CFG, pullup,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_enc_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_ENC_EN, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_trans_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_OSD_TRANS_EN, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dither_linebuf(struct lcdc_device *p_lcdc, uint32 lineaddr)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DITHER_LINEBUF, lineaddr,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_dither_en(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SET_DITHER_EN, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_clk_gather_select(struct lcdc_device *p_lcdc, uint8 pull)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_CLK_GATHER, pull,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_screen_start(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SCREEN_SHOT_START, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_screen_format(struct lcdc_device *p_lcdc, uint8 format)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SCREEN_SHOT_FORMAT, format,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_screen_yuv_addr(struct lcdc_device *p_lcdc, uint32 yadr,uint32 uadr,uint32 vadr)
+{
+	uint32 yuv_tbl[3];
+	yuv_tbl[0] = yadr;
+	yuv_tbl[1] = uadr;
+	yuv_tbl[2] = vadr;
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_SCREEN_YUVADR, (uint32)yuv_tbl,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_sram_fifo_enable(struct lcdc_device *p_lcdc, uint8 en)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_OSD_USE_SRAM_FIFO_ENABLE, en,0);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_sram_fifo_addr(struct lcdc_device *p_lcdc, uint32 start, uint32 end)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_OSD_SRAM_FIFO_ADDR, start,end);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_osd_spec_color_alpha(struct lcdc_device *p_lcdc, uint8 enable, uint32 color, uint32 alpha)
+{
+	uint32 color_alpha[2];
+	color_alpha[0] = color;
+	color_alpha[1] = alpha;	
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_OSD_USE_SPEC_COLOR_ALPHA, enable,(uint32)color_alpha);
+	}
+	return RET_ERR;
+}
+
+int32 lcdc_get_clk_status(struct lcdc_device *p_lcdc)
+{
+	if (p_lcdc && ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl) {
+		return ((const struct lcdc_hal_ops *)p_lcdc->dev.ops)->ioctl(p_lcdc, LCDC_CLK_STATUS_IS_OK, 0,0);
+	}
+	return RET_ERR;
+}
+
+

sdk/hal/led.c

@@ -0,0 +1,63 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/led.h"
+
+
+int32 led_open(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->open) {
+        return ((const struct led_hal_ops *)led->dev.ops)->open(led, work_mode, seg_cnt, com_cnt);
+    }
+    return RET_ERR;
+}
+
+int32 led_on(struct led_device *led, uint32 num, enum led_com_cnt pos)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->on) {
+        return ((const struct led_hal_ops *)led->dev.ops)->on(led, num, pos);
+    }
+    return RET_ERR;
+}
+
+int32 led_off(struct led_device *led, enum led_com_cnt pos)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->off) {
+        return ((const struct led_hal_ops *)led->dev.ops)->off(led, pos);
+    }
+    return RET_ERR;
+}
+
+int32 led_close(struct led_device *led)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->close) {
+        return ((const struct led_hal_ops *)led->dev.ops)->close(led);
+    }
+    return RET_ERR;
+}
+
+int32 led_ioctl(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->ioctl) {
+        return ((const struct led_hal_ops *)led->dev.ops)->ioctl(led, ioctl_cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 led_request_irq(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->request_irq) {
+        return ((const struct led_hal_ops *)led->dev.ops)->request_irq(led, irq_flag, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 led_release_irq(struct led_device *led, enum led_irq_flag irq_flag)
+{
+    if (led && ((const struct led_hal_ops *)led->dev.ops)->release_irq) {
+        return ((const struct led_hal_ops *)led->dev.ops)->release_irq(led, irq_flag);
+    }
+    return RET_ERR;
+}
+

sdk/hal/netdev.c

@@ -0,0 +1,71 @@
+#include "typesdef.h"
+#include "errno.h"
+#include "list.h"
+#include "dev.h"
+#include "osal/task.h"
+#include "hal/netdev.h"
+
+int32 netdev_open(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->open) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->open(ndev, input_cb, evt_cb, priv);
+    }
+    return -EINVAL;
+}
+
+int32 netdev_close(struct netdev *ndev)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->close) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->close(ndev);
+    }
+    return -EINVAL;
+}
+
+int32 netdev_send_data(struct netdev *ndev, uint8 *p_data, uint32 size)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->send_data) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->send_data(ndev, p_data, size);
+    }
+    return -ENOTSUPP;
+}
+
+int32 netdev_send_scatter_data(struct netdev *ndev, scatter_data *p_data, uint32 count)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->send_scatter_data) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->send_scatter_data(ndev, p_data, count);
+    }
+    return -ENOTSUPP;
+}
+
+
+int32 netdev_ioctl(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->ioctl(ndev, cmd, param1, param2);
+    }
+    return -EINVAL;
+}
+
+int32 netdev_mdio_write(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->mdio_write) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->mdio_write(ndev, phy_addr, reg_addr, data);
+    }
+    return 0;
+}
+
+int32 netdev_mdio_read(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr)
+{
+    if (ndev && ((const struct netdev_hal_ops *)ndev->dev.ops)->mdio_read) {
+        HALDEV_SUSPENDED(ndev);
+        return ((const struct netdev_hal_ops *)ndev->dev.ops)->mdio_read(ndev, phy_addr, reg_addr);
+    }
+    return 0;
+}
+

sdk/hal/of.c

@@ -0,0 +1,72 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/of.h"
+
+
+int32 of_init(struct of_device *p_of)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->init) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->init(p_of);
+    }
+    return RET_ERR;
+}
+
+int32 of_deinit(struct of_device *p_of)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->deinit) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->deinit(p_of);
+    }
+    return RET_ERR;
+}
+
+int32 of_set_instr_mode(struct of_device *p_of,enum of_instr_mode instr_format)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,OF_INSTR_MODE, instr_format,0);
+    }
+    return RET_ERR;
+}
+
+int32 of_set_pixel_num(struct of_device *p_of,uint32 pixel_num)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,CAL_PIXEL_NUM, pixel_num,0);
+    }
+    return RET_ERR;
+}
+
+int32 of_set_row_num(struct of_device *p_of,uint32 row_num)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,CAL_ROW_NUM, row_num,0);
+    }
+    return RET_ERR;
+}
+
+int32 of_set_row_size(struct of_device *p_of,uint32 row_size)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,SET_ROW_SIZE, row_size,0);
+    }
+    return RET_ERR;
+}
+
+int32 of_set_addr(struct of_device *p_of,uint32 addr0,uint32 addr1)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,SET_OF_ADDR, addr0,addr1);
+    }
+    return RET_ERR;
+}
+
+int32 of_get_acc(struct of_device *p_of)
+{
+    if (p_of && ((const struct of_hal_ops *)p_of->dev.ops)->ioctl) {
+        return ((const struct of_hal_ops *)p_of->dev.ops)->ioctl(p_of,GET_CAL_ACC, 0,0);
+    }
+    return RET_ERR;
+}
+

sdk/hal/osd_enc.c

@@ -0,0 +1,106 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/osd_enc.h"
+
+int32 osd_enc_suspend(struct osdenc_device *p_osd)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->suspend) {
+		return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->suspend(p_osd);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_resume(struct osdenc_device *p_osd)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->resume) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->resume(p_osd);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_open(struct osdenc_device *p_osd)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->open) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->open(p_osd);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_close(struct osdenc_device *p_osd)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->close) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->close(p_osd);
+    }
+    return RET_ERR;
+}
+
+
+int32 osd_enc_request_irq(struct osdenc_device *p_osd, uint32 irq_flags, osdenc_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->request_irq) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->request_irq(p_osd, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_release_irq(struct osdenc_device *p_osd, uint32 irq_flags)
+{
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->release_irq) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->release_irq(p_osd, irq_flags);
+    }
+    return RET_ERR;
+}
+
+
+int32 osd_enc_tran_config(struct osdenc_device *p_osd,uint32 head,uint32 head_tran,uint32 diap,uint32 diap_tran){
+	uint32_t encbuf[4];
+	uint32_t *p32;
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+		p32 = (uint32_t *)encbuf;
+		p32[0] = head;
+		p32[1] = head_tran;
+		p32[2] = diap;
+		p32[3] = diap_tran;
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_TRAN_IDENT_TRANS, (uint32)encbuf,0);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_addr(struct osdenc_device *p_osd,uint32 src,uint32 des){
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_ENC_ADR, src,des);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_src_len(struct osdenc_device *p_osd,uint32 len){
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_SET_ENC_RLEN, len,0);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_dlen(struct osdenc_device *p_osd){
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_GET_ENC_DLEN, 0,0);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_set_format(struct osdenc_device *p_osd,uint8 isrgb565){
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_SET_ENC_FORMAT, isrgb565,0);
+    }
+    return RET_ERR;
+}
+
+int32 osd_enc_run(struct osdenc_device *p_osd){
+    if (p_osd && ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl) {
+        return ((const struct osdenc_hal_ops *)p_osd->dev.ops)->ioctl(p_osd, OSD_IOCTL_SET_ENC_RUN, 0,0);
+    }
+    return RET_ERR;
+}
+

sdk/hal/para_in.c

@@ -0,0 +1,52 @@
+#include "sys_config.h"
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/para_in.h"
+
+int32 para_in_open(struct para_in_device *p_dev)
+{
+    if (p_dev && ((const struct para_in_hal_ops *)p_dev->dev.ops)->open) {
+        HALDEV_SUSPENDED(p_dev);
+        return ((const struct para_in_hal_ops *)p_dev->dev.ops)->open(p_dev);
+    }
+    return RET_ERR;
+}
+
+int32 para_in_close(struct para_in_device *p_dev)
+{
+    if (p_dev && ((const struct para_in_hal_ops *)p_dev->dev.ops)->close) {
+        HALDEV_SUSPENDED(p_dev);
+        return ((const struct para_in_hal_ops *)p_dev->dev.ops)->close(p_dev);
+    }
+    return RET_ERR;
+}
+
+int32 para_in_ioctl(struct para_in_device *p_dev, uint32 cmd, uint32 param1, uint32 param2)
+{
+    if (p_dev && ((const struct para_in_hal_ops *)p_dev->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(p_dev);
+        return ((const struct para_in_hal_ops *)p_dev->dev.ops)->ioctl(p_dev, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 para_in_request_irq(struct para_in_device *p_dev, uint32 irq_flags, para_in_irq_hdl handle, uint32 data)
+{
+    if (p_dev && ((const struct para_in_hal_ops *)p_dev->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(p_dev);
+        return ((const struct para_in_hal_ops *)p_dev->dev.ops)->request_irq(p_dev, irq_flags, handle, data);
+    }
+    return RET_ERR;
+}
+
+int32 para_in_release_irq(struct para_in_device *p_dev, uint32 irq_flag)
+{
+    if (p_dev && ((const struct para_in_hal_ops *)p_dev->dev.ops)->release_irq) {
+        HALDEV_SUSPENDED(p_dev);
+        return ((const struct para_in_hal_ops *)p_dev->dev.ops)->release_irq(p_dev, irq_flag);
+    }
+    return RET_ERR;
+}

sdk/hal/pdm.c

@@ -0,0 +1,54 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/pdm.h"
+
+int32 pdm_open(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->open) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->open(pdm, freq, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pdm_read(struct pdm_device *pdm, void *buf, uint32 len)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->read) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->read(pdm, buf, len);
+    }
+    return RET_ERR;
+}
+
+int32 pdm_close(struct pdm_device *pdm)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->close) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->close(pdm);
+    }
+    return RET_ERR;
+}
+
+int32 pdm_request_irq(struct pdm_device *pdm, enum pdm_irq_flag flag, pdm_irq_hdl irq_hdl, uint32 data)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->request_irq) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->request_irq(pdm, flag, irq_hdl, data);
+    }
+    return RET_ERR;
+}
+
+int32 pdm_release_irq(struct pdm_device *pdm, enum pdm_irq_flag irq_flag)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->release_irq) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->release_irq(pdm, irq_flag);
+    }
+    return RET_ERR;
+}
+
+int32 pdm_ioctl(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param)
+{
+    if (pdm && ((const struct pdm_hal_ops *)pdm->dev.ops)->ioctl) {
+        return ((const struct pdm_hal_ops *)pdm->dev.ops)->ioctl(pdm, cmd, param);
+    }
+    return RET_ERR;
+}
+

sdk/hal/prc.c

@@ -0,0 +1,127 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/prc.h"
+
+
+
+
+int32 prc_set_width(struct prc_device *p_prc, uint32 width)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_WIDTH, width,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_suspend(struct prc_device *p_prc)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->suspend) {
+		return ((const struct prc_hal_ops *)p_prc->dev.ops)->suspend(p_prc);
+    }
+    return RET_ERR;
+}
+
+int32 prc_resume(struct prc_device *p_prc)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->resume) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->resume(p_prc);
+    }
+    return RET_ERR;
+}
+
+
+
+int32 prc_set_yuv_mode(struct prc_device *p_prc, uint32 mode)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_YUV_MODE, mode,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_set_yaddr(struct prc_device *p_prc, uint32 addr)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_Y_ADDR, addr,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_set_uaddr(struct prc_device *p_prc, uint32 addr)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_U_ADDR, addr,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_set_vaddr(struct prc_device *p_prc, uint32 addr)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_V_ADDR, addr,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_set_src_addr(struct prc_device *p_prc, uint32 addr)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_SET_SRC_ADDR, addr,0);
+    }
+    return RET_ERR;
+}
+
+
+int32 prc_first_start(struct prc_device *p_prc)
+{
+	if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+		return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_FIRST_KICK, 0,0);
+	}
+	return RET_ERR;
+}
+
+
+int32 prc_run(struct prc_device *p_prc)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->ioctl(p_prc,PRC_IOCTL_CMD_KICK, 0,0);
+    }
+    return RET_ERR;
+}
+
+int32 prc_init(struct prc_device *p_prc)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->init) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->init(p_prc);
+    }
+    return RET_ERR;
+}
+
+int32 prc_deinit(struct prc_device *p_prc)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->deinit) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->deinit(p_prc);
+    }
+    return RET_ERR;
+}
+
+int32 prc_request_irq(struct prc_device *p_prc, uint32 irq_flags, prc_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->request_irq) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->request_irq(p_prc, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 prc_release_irq(struct prc_device *p_prc, uint32 irq_flags)
+{
+    if (p_prc && ((const struct prc_hal_ops *)p_prc->dev.ops)->release_irq) {
+        return ((const struct prc_hal_ops *)p_prc->dev.ops)->release_irq(p_prc, irq_flags);
+    }
+    return RET_ERR;
+}
+
+

sdk/hal/pwm.c

@@ -0,0 +1,79 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/pwm.h"
+
+
+int32 pwm_init(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->init) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->init(pwm, channel, period_sysclkpd_cnt, h_duty_sysclkpd_cnt);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_deinit(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->deinit) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->deinit(pwm, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_start(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->start) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->start(pwm, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_stop(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->stop) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->stop(pwm, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_suspend(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->suspend) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->suspend(pwm, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_resume(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->resume) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->resume(pwm, channel);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_ioctl(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->ioctl) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->ioctl(pwm, channel, ioctl_cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_request_irq(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->request_irq) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->request_irq(pwm, channel, irq_flag, irq_hdl, data);
+    }
+    return RET_ERR;
+}
+
+int32 pwm_release_irq(struct pwm_device *pwm, enum pwm_channel channel)
+{
+    if (pwm && ((const struct pwm_hal_ops *)pwm->dev.ops)->release_irq) {
+        return ((const struct pwm_hal_ops *)pwm->dev.ops)->release_irq(pwm, channel);
+    }
+    return RET_ERR;
+}
+

sdk/hal/rotate.c

@@ -0,0 +1,39 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/rotate.h"
+
+
+int32 rotate_set_addr(struct rotate_device *p_rot, uint32_t src, uint32_t des)
+{
+    if (p_rot && ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl) {
+        return ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl(p_rot, ROTATE_IOCTL_CMD_SET_ADDR, src, des);
+    }
+    return RET_ERR;
+}
+
+int32 rotate_set_size(struct rotate_device *p_rot, uint16_t w, uint16_t h)
+{
+    if (p_rot && ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl) {
+        return ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl(p_rot, ROTATE_IOCTL_CMD_SET_SIZE, w, h);
+    }
+    return RET_ERR;
+}
+
+int32 rotate_run(struct rotate_device *p_rot, uint8_t angle, uint8_t bit_width)
+{
+    if (p_rot && ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl) {
+        return ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl(p_rot, ROTATE_IOCTL_CMD_SET_ANALE_RUN, angle, bit_width);
+    }
+    return RET_ERR;
+}
+
+int32 rotate_get_sta(struct rotate_device *p_rot){
+	if (p_rot && ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl) {
+		return ((const struct rotate_hal_ops *)p_rot->dev.ops)->ioctl(p_rot, ROTATE_IOCTL_CMD_GET_STA, 0,0);
+	}
+	return RET_ERR; 
+}
+

sdk/hal/rtc.c

@@ -0,0 +1,71 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/rtc.h"
+
+
+int32 rtc_open(struct rtc_device *rtc, struct rtc_time_type *rtc_time) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->open) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->open(rtc, rtc_time);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_close(struct rtc_device *rtc) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->close) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->close(rtc);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_set_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->set_time) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->set_time(rtc, rtc_time);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_get_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->get_time) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->get_time(rtc, rtc_time);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_ioctl(struct rtc_device *rtc, uint32 cmd, uint32 param1, uint32 param2) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->ioctl) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->ioctl(rtc, cmd, param1, param2);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_request_irq(struct rtc_device *rtc, uint32 irq_flag, rtc_irq_hdl irq_hdl, uint32 irq_data) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->request_irq) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->request_irq(rtc, irq_flag, irq_hdl, irq_data);
+    }
+
+    return RET_ERR;
+}
+
+int32 rtc_release_irq(struct rtc_device *rtc, uint32 irq_flag) {
+
+    if(rtc && ((const struct rtc_hal_ops *)rtc->dev.ops)->release_irq) {
+        return ((const struct rtc_hal_ops *)rtc->dev.ops)->release_irq(rtc, irq_flag);
+    }
+
+    return RET_ERR;
+}
+
+

sdk/hal/scale.c

@@ -0,0 +1,375 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/scale.h"
+
+int32 scale_suspend(struct scale_device *p_scale)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->suspend) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->suspend(p_scale);
+    }
+    return RET_ERR;
+}
+
+int32 scale_resume(struct scale_device *p_scale)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->resume) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->resume(p_scale);
+    }
+    return RET_ERR;
+}
+
+int32 scale_open(struct scale_device *p_scale)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->open) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->open(p_scale);
+    }
+    return RET_ERR;
+}
+
+int32 scale_close(struct scale_device *p_scale)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->close) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->close(p_scale);
+    }
+    return RET_ERR;
+}
+
+int32 scale_request_irq(struct scale_device *p_scale, uint32 irq_flags, scale_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->request_irq) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->request_irq(p_scale, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 scale_release_irq(struct scale_device *p_scale, uint32 irq_flags)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->release_irq) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->release_irq(p_scale, irq_flags);
+    }
+    return RET_ERR;
+}
+
+
+int32 scale_set_in_out_size(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_IN_OUT_SIZE, (s_h<<16)|s_w, (o_h<<16)|o_w);
+    }
+    return RET_ERR;
+}
+
+int32 scale_set_step(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h)
+{
+    if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+        return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_STEP, (s_h<<16)|s_w, (o_h<<16)|o_w);
+    }
+    return RET_ERR;
+}
+
+int32 scale_set_start_addr(struct scale_device *p_scale, uint32 s_x,uint32 s_y)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_START_ADDR, (s_y<<16)|s_x, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_srambuf_wlen(struct scale_device *p_scale, uint32 wlen)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_SRAMBUF_WLEN, wlen, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_in_yaddr(struct scale_device *p_scale, uint32 yaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_IN_Y_ADDR, yaddr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_in_uaddr(struct scale_device *p_scale, uint32 uaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_IN_U_ADDR, uaddr, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_in_vaddr(struct scale_device *p_scale, uint32 vaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_IN_V_ADDR, vaddr, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_out_yaddr(struct scale_device *p_scale, uint32 yaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_OUT_Y_ADDR, yaddr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_out_uaddr(struct scale_device *p_scale, uint32 uaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_OUT_U_ADDR, uaddr, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_out_vaddr(struct scale_device *p_scale, uint32 vaddr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_OUT_V_ADDR, vaddr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_line_buf_num(struct scale_device *p_scale, uint32 num)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_LINE_BUF_NUM, num, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_line_buf_addr(struct scale_device *p_scale, uint32 addr)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_SRAM_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_dma_to_memory(struct scale_device *p_scale, uint32 en)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_DMA_TO_MEMORY, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_data_from_vpp(struct scale_device *p_scale, uint32 en)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_DATA_FROM, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_get_inbuf_num(struct scale_device *p_scale)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_GET_INBUF_NUM, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_inbuf_num(struct scale_device *p_scale,uint32 num,uint32 start_line)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_INBUF_NUM, num, start_line);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_both_mjpg_h264(struct scale_device *p_scale,uint8 en)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_BOTH_MJPG_H264, en, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_new_frame(struct scale_device *p_scale,uint8 en)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_NEW_FRAME, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_set_end_frame(struct scale_device *p_scale,uint8 en)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_END_FRAME, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_get_heigh_cnt(struct scale_device *p_scale)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_GET_HEIGH_CNT, 0, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_get_is_open(struct scale_device *p_scale)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_GET_IS_OPEN, 0, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0:mjpeg
+//1:h264 decoder
+//memory frame buf yuv420
+//memory frame buf yuv422
+//memory frame buf yuv444
+//memory frame buf rgb888
+*******************************/
+int32 scale_set_input_stream(struct scale_device *p_scale,uint8 stream)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_INPUT_STREAM, stream, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0: all frame
+//1: linebuf
+*******************************/
+int32 scale_set_output_sram_or_frame(struct scale_device *p_scale,uint8 out_to_sram)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_OUT2SRAM_FRAME, out_to_sram, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0: 0
+//1: 90
+//2: 180
+//3: 270
+*******************************/
+int32 scale_set_rotate_cfg(struct scale_device *p_scale,uint8 rotate)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SRAM_ROTATE, rotate, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0: no mirror
+//1: mirror
+*******************************/
+int32 scale_set_mirror(struct scale_device *p_scale,uint8 mirror)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SRAM_MIRROR, mirror, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//8 : 8  word
+//16: 16 word
+//32: 32 word
+//64: 64 word
+*******************************/
+int32 scale_set_psram_burst(struct scale_device *p_scale,uint8 pbus)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_PSRAM_BURST, pbus, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_linebuf_yuv_addr(struct scale_device *p_scale, uint32 yadr,uint32 uadr,uint32 vadr)
+{
+	uint32 addr_tbl[3];
+	addr_tbl[0] = yadr;
+	addr_tbl[1] = uadr;
+	addr_tbl[2] = vadr;
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_LINEBUF_YUV_ADDR, (uint32)addr_tbl,0);
+	}
+	return RET_ERR;
+}
+
+
+int32 scale_set_input_yuv_addr(struct scale_device *p_scale, uint32 yadr,uint32 uadr,uint32 vadr)
+{
+	uint32 addr_tbl[3];
+	addr_tbl[0] = yadr;
+	addr_tbl[1] = uadr;
+	addr_tbl[2] = vadr;
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_INBUF_YUV_ADDR, (uint32)addr_tbl,0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0: yuv420p
+//1: rgb888
+*******************************/
+int32 scale_set_input_format(struct scale_device *p_scale,uint8 format)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_INPUT_FORMAT, format, 0);
+	}
+	return RET_ERR;
+}
+
+/*******************************
+//0: line buf
+//1: all frame
+*******************************/
+int32 scale_is_allframe_or_linebuf(struct scale_device *p_scale,uint8 isframebuf)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_INPUT_IS_FRAMEBUF, isframebuf, 0);
+	}
+	return RET_ERR;
+}
+
+	
+/*******************************
+//0: yuv420p
+//1: rgb888
+*******************************/
+int32 scale_set_output_format(struct scale_device *p_scale,uint8 format)
+{
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_SET_OUTPUT_FORMAT, format, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_get_input_width(struct scale_device *p_scale){
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_GET_INPUT_WIDTH, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 scale_get_input_high(struct scale_device *p_scale){
+	if (p_scale && ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl) {
+		return ((const struct scale_hal_ops *)p_scale->dev.ops)->ioctl(p_scale, SCALE_IOCTL_CMD_GET_INPUT_HIGH, 0, 0);
+	}
+	return RET_ERR;
+}
+

sdk/hal/sdio_slave.c

@@ -0,0 +1,69 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/sdio_slave.h"
+
+int32 sdio_slave_open(struct sdio_slave *slave, enum sdio_slave_speed speed, uint32 flags)
+{
+    if (slave) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->open(slave, speed, flags);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_close(struct sdio_slave *slave)
+{
+    if (slave) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->close(slave);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_write(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync)
+{
+    if (slave && ((const struct sdios_hal_ops *)slave->dev.ops)->write) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->write(slave, buff, len, sync);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_write_scatter(struct sdio_slave *slave, scatter_data *data, uint32 count, int8 sync)
+{
+    if (slave && ((const struct sdios_hal_ops *)slave->dev.ops)->write_scatter) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->write_scatter(slave, data, count, sync);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_read(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync)
+{
+    if (slave && ((const struct sdios_hal_ops *)slave->dev.ops)->read) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->read(slave, buff, len, sync);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_ioctl(struct sdio_slave *slave, uint32 cmd, uint32 param)
+{
+    if (slave && ((const struct sdios_hal_ops *)slave->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->ioctl(slave, cmd, param);
+    }
+    return RET_ERR;
+}
+
+int32 sdio_slave_request_irq(struct sdio_slave *slave, sdio_slave_irq_hdl handle, uint32 data)
+{
+    if (slave && ((const struct sdios_hal_ops *)slave->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(slave);
+        return ((const struct sdios_hal_ops *)slave->dev.ops)->request_irq(slave, handle, data);
+    }
+    return RET_ERR;
+}
+

sdk/hal/sha.c

@@ -0,0 +1,92 @@
+/**
+  ******************************************************************************
+  * @file    User/xxx.c
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    01-08-2023
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2018 HUGE-IC</center></h2>
+  *
+  *
+  *
+  ******************************************************************************
+  */
+#include "typesdef.h"
+#include "errno.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/sha.h"
+
+int32 sha_ioctl(struct sha_dev *dev, uint32 cmd, uint32 para)
+{
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->ioctl) {
+        return ((const struct sha_hal_ops *)dev->dev.ops)->ioctl(dev, cmd, para, 0);
+    }
+    return RET_ERR;
+}
+
+int32 sha_init(struct sha_dev *dev, SHA_TYPE type)
+{
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->init) {
+        return ((const struct sha_hal_ops *)dev->dev.ops)->init(dev, type);
+    }
+    return RET_ERR;
+}
+
+int32 sha_update(struct sha_dev *dev, uint8 *input, uint32 len)
+{
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->update) {
+        return ((const struct sha_hal_ops *)dev->dev.ops)->update(dev, input, len);
+    }
+    return RET_ERR;
+}
+
+int32 sha_final(struct sha_dev *dev, uint8 *output)
+{
+    uint32 ret = 0;
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->final) {
+        ret = ((const struct sha_hal_ops *)dev->dev.ops)->final(dev, output);
+    }
+    return ret;
+}
+
+int32 sha_finup(struct sha_dev *dev, uint8 *input, uint32 len, uint8 *output)
+{
+    uint32 ret = 0;
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->update) {
+        ret = ((const struct sha_hal_ops *)dev->dev.ops)->update(dev, input, len);
+    }
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->final) {
+        ret = ((const struct sha_hal_ops *)dev->dev.ops)->final(dev, output);
+    }
+    return ret;
+}
+
+int32 sha_xform(struct sha_dev *dev, struct sha_req *req)
+{
+    uint32 ret = 0;
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->xform) {
+        ret = ((const struct sha_hal_ops *)dev->dev.ops)->xform(dev, req);
+    }
+    return ret;
+}
+
+int32 sha_requset_irq(struct sha_dev *dev, void *irq_handle, void *args)
+{
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->requset_irq) {
+        return ((const struct sha_hal_ops *)dev->dev.ops)->requset_irq(dev, irq_handle, args);
+    }
+    return RET_ERR;
+}
+
+int32 sha_release_irq(struct sha_dev *dev)
+{
+    if (dev && ((const struct sha_hal_ops *)dev->dev.ops)->release_irq) {
+        return ((const struct sha_hal_ops *)dev->dev.ops)->release_irq(dev);
+    }
+    return RET_ERR;
+}
+

sdk/hal/spi.c

@@ -0,0 +1,88 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/spi.h"
+
+int32 spi_open(struct spi_device *spi, uint32 clk_freq, uint32 work_mode, uint32 wire_mode, uint32 clk_mode)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->open) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->open(spi, clk_freq, work_mode, wire_mode, clk_mode);
+    }
+    return RET_ERR;
+}
+
+int32 spi_close(struct spi_device *spi)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->close) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->close(spi);
+    }
+    return RET_ERR;
+}
+
+int32 spi_ioctl(struct spi_device *spi, uint32 cmd, uint32 param1, uint32 param2)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->ioctl(spi, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 spi_read(struct spi_device *spi, void *buf, uint32 size)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->read) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->read(spi, buf, size);
+    }
+    return RET_ERR;
+}
+
+int32 spi_write(struct spi_device *spi, const void *buf, uint32 size)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->write) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->write(spi, buf, size);
+    }
+    return RET_ERR;
+}
+
+int32 spi_write_scatter(struct spi_device *spi, const scatter_data *data, uint32 count)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->write_scatter) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->write_scatter(spi, data, count);
+    }
+    return RET_ERR;
+}
+
+inline int32 spi_set_cs(struct spi_device *spi, uint32 cs, uint32 value)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->ioctl(spi, SPI_SET_CS, cs, value);
+    }
+    return RET_ERR;
+}
+
+int32 spi_request_irq(struct spi_device *spi, uint32 irq_flag, spi_irq_hdl irqhdl, uint32 irq_data)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->request_irq(spi, irq_flag, irqhdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 spi_release_irq(struct spi_device *spi, uint32 irq_flag)
+{
+    if (spi && ((const struct spi_hal_ops *)spi->dev.ops)->release_irq) {
+        HALDEV_SUSPENDED(spi);
+        return ((const struct spi_hal_ops *)spi->dev.ops)->release_irq(spi, irq_flag);
+    }
+    return RET_ERR;
+}
+
+

sdk/hal/spi_nor.c

@@ -0,0 +1,252 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "osal/semaphore.h"
+#include "dev.h"
+#include "dev/spi/hgspi_xip.h"
+#include "osal/mutex.h"
+#include "osal/string.h"
+#include "hal/spi.h"
+#include "hal/spi_nor.h"
+
+int32 spi_nor_open(struct spi_nor_flash *flash)
+{
+    int32 ret = RET_OK;
+
+    if (flash == NULL) {
+        return -ENODEV;
+    }
+    ASSERT(flash->bus);
+    if (atomic_read(&flash->ref) == 0) {
+        ret = spi_open(flash->spidev, flash->spi_config.clk, SPI_MASTER_MODE,
+                       flash->spi_config.wire_mode, flash->spi_config.clk_mode);
+        ASSERT(!ret);
+        if (flash->bus->open) {
+            flash->bus->open(flash);
+        }
+    }
+    atomic_inc(&flash->ref);
+    return ret;
+}
+
+void spi_nor_close(struct spi_nor_flash *flash)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+
+        if (atomic_dec_and_test(&flash->ref)) {
+            if (flash->bus->close) {
+                flash->bus->close(flash);
+            }
+            spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
+            spi_close(flash->spidev);
+        }
+    }
+}
+
+void spi_nor_read(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 len)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->read(flash, addr, buf, len);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_write(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 len)
+{
+    uint32 remain_size;
+
+    if (flash == NULL) {
+        return;
+    }
+
+    ASSERT(flash->bus);
+    os_mutex_lock(&flash->lock, osWaitForever);
+    /* Flash is written according to page */
+    remain_size = flash->page_size - (addr % flash->page_size);
+    if (remain_size && (len > remain_size)) {
+        flash->bus->program(flash, addr, buf, remain_size);
+        addr += remain_size;
+        buf  += remain_size;
+        len  -= remain_size;
+    }
+    while (len > flash->page_size) {
+        flash->bus->program(flash, addr, buf, flash->page_size);
+        addr += flash->page_size;
+        buf  += flash->page_size;
+        len  -= flash->page_size;
+    }
+
+    flash->bus->program(flash, addr, buf, len);
+    os_mutex_unlock(&flash->lock);
+}
+
+void spi_nor_sector_erase(struct spi_nor_flash *flash, uint32 sector_addr)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->erase(flash, SPI_NOR_ERASE_SECTOR, sector_addr);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_block_erase(struct spi_nor_flash *flash, uint32 block_addr)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->erase(flash, SPI_NOR_ERASE_BLOCK, block_addr);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_chip_erase(struct spi_nor_flash *flash)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->erase(flash, SPI_NOR_ERASE_CHIP, 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_sec_erase(struct spi_nor_flash *flash, uint32 addr)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_SEC_ERASE, addr, 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_sec_program(struct spi_nor_flash *flash, uint32 addr, struct spi_nor_regval *values)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_SEC_PROGRAM, addr, (uint32)values);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_sec_read(struct spi_nor_flash *flash, uint32 addr, struct spi_nor_regval *values)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_SEC_READ, addr, (uint32)values);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_custom_read(struct spi_nor_flash *flash, void *param)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_COSTUM_READ, (uint32)(param), 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_custom_write(struct spi_nor_flash *flash, void *param)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_COSTUM_WRITE, (uint32)(param), 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_custom_erase(struct spi_nor_flash *flash, void *param)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_COSTUM_ERASE, (uint32)(param), 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_power_down(struct spi_nor_flash *flash)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_POWER_DOWN, 0, 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_power_up(struct spi_nor_flash *flash)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_POWER_UP, 0, 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+void spi_nor_read_jedec_id(struct spi_nor_flash *flash, uint8 *buff)
+{
+    if (flash) {
+        ASSERT(flash->bus);
+        os_mutex_lock(&flash->lock, osWaitForever);
+        flash->bus->ioctl(flash, SPI_NOR_CMD_READ_JEDEC_ID, (uint32)buff, 0);
+        os_mutex_unlock(&flash->lock);
+    }
+}
+
+__init int32 spi_nor_attach(struct spi_nor_flash *flash, uint32 dev_id)
+{
+    uint8 id[3];
+    extern struct bp_info bp_info;
+    extern int xip_nor_flash_unbp_convert(struct spi_nor_flash *flash, 
+        uint32_t addrl, uint32_t addru, struct bpreg_cfg *bp);    
+    extern int xip_nor_flash_unbp_convert_tbl(struct spi_nor_flash *flash, 
+        uint32_t addrl, uint32_t addru, struct bpreg_cfg *bp);
+    extern int xip_nor_flash_unbp_update(struct spi_nor_flash *flash, 
+    struct bpreg_cfg *bp, int size);
+
+    ASSERT(flash->size && flash->sector_size);
+    os_mutex_init(&flash->lock);
+    
+    if (flash->bits_of_addr == 0) {
+        flash->bits_of_addr = 24;
+    }
+    flash->bus = spi_nor_bus_get(flash->mode);
+    flash->bpi = &bp_info;
+    flash->bp_conv = NULL;//xip_nor_flash_unbp_convert;
+
+    for (int i = 0;i<bp_info.area_cnt;i++)
+    {
+        os_printf("{0x%x, [0x%x, 0x%x]}\r\n", bp_info.areas[i].bpv | (bp_info.areas[i].tb<<3),
+            bp_info.areas[i].area[0], bp_info.areas[i].area[1]);
+    }
+    ASSERT(flash->bus);
+
+    spi_nor_open(flash);
+    flash->bus->ioctl(flash, SPI_NOR_CMD_READ_JEDEC_ID, (uint32_t)id, 0);
+    if ((id[0] | id[1] | id[2]) == 0 || ((id[0] & id[1] & id[2]) == 0xff)) {
+        return -EIO;
+    }
+
+    flash->vendor_id  = id[0];
+    flash->product_id = (id[1] << 8) | id[2];
+
+    if (flash->bp_conv) {
+        struct bpreg_cfg bp;
+        flash->bp_conv(flash, 0, flash->size, &bp);
+        xip_nor_flash_unbp_update(flash, &bp, 0);
+    }
+
+    spi_nor_close(flash);
+    return dev_register(dev_id, (struct dev_obj *)flash);
+}
+

sdk/hal/sysaes.c

@@ -0,0 +1,23 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/sysaes.h"
+
+int32 sysaes_encrypt(struct sysaes_dev *dev, struct sysaes_para *para)
+{
+    if (dev && ((const struct aes_hal_ops *)dev->dev.ops)->encrypt) {
+        return ((const struct aes_hal_ops *)dev->dev.ops)->encrypt(dev, para);
+    }
+    return RET_ERR;
+}
+
+int32 sysaes_decrypt(struct sysaes_dev *dev, struct sysaes_para *para)
+{
+    if (dev && ((const struct aes_hal_ops *)dev->dev.ops)->decrypt) {
+        return ((const struct aes_hal_ops *)dev->dev.ops)->decrypt(dev, para);
+    }
+    return RET_ERR;
+}
+
+

sdk/hal/timer.c

@@ -0,0 +1,87 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/timer_device.h"
+
+int32 timer_device_open(struct timer_device *timer, enum timer_type type, uint32 flags)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->open) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->open(timer, type, flags);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_close(struct timer_device *timer)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->close) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->close(timer);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_start(struct timer_device *timer, uint32 period_sysclkpd_cnt, timer_irq_hdl cb, uint32 cb_data)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->start) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->start(timer, period_sysclkpd_cnt, cb, cb_data);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_stop(struct timer_device *timer)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->stop) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->stop(timer);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_suspend(struct timer_device *timer)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->suspend) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->suspend(timer);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_resume(struct timer_device *timer)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->resume) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->resume(timer);
+    }
+    return RET_ERR;
+}
+
+int32 timer_device_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->ioctl(timer, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 timer_request_irq(struct timer_device *timer, uint32 irq_flag, timer_irq_hdl cb, uint32 cb_data)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->request_irq(timer, irq_flag, cb, cb_data);
+    }
+    return RET_ERR;
+}
+
+int32 timer_release_irq(struct timer_device *timer, uint32 irq_flag)
+{
+    if (timer && ((const struct timer_hal_ops *)timer->dev.ops)->release_irq) {
+        HALDEV_SUSPENDED(timer);
+        return ((const struct timer_hal_ops *)timer->dev.ops)->release_irq(timer, irq_flag);
+    }
+    return RET_ERR;
+}
+

sdk/hal/tk.c

@@ -0,0 +1,55 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "hal/tk.h"
+
+int32 tk_open(struct tk_device *tk)
+{
+    if (tk)
+    {
+        return ((const struct tk_hal_ops *)tk->dev.ops)->open(tk);
+    }
+    
+    return RET_ERR;
+}
+
+int32 tk_ioctl(struct tk_device *tk, enum touchkey_ioctl_cmd ioctl_cmd, uint32 param)
+{
+    if (tk && ((const struct tk_hal_ops *)tk->dev.ops)->ioctl)
+    {
+        return ((const struct tk_hal_ops *)tk->dev.ops)->ioctl(tk, ioctl_cmd, param);
+    }
+
+    return RET_ERR;
+}
+
+int32 tk_irq_request(struct tk_device *tk, tk_irq_hdl irq_hdl, uint32 irq_flag,  uint32 irq_data)
+{
+    if (tk && ((const struct tk_hal_ops *)tk->dev.ops)->request_irq)
+    {
+        return ((const struct tk_hal_ops *)tk->dev.ops)->request_irq(tk, irq_hdl, irq_flag, irq_data);
+    }
+
+    return RET_ERR;
+}
+
+int32 tk_irq_release(struct tk_device *tk, uint32 irq_flag)
+{
+    if (tk && ((const struct tk_hal_ops *)tk->dev.ops)->release_irq)
+    {
+        return ((const struct tk_hal_ops *)tk->dev.ops)->release_irq(tk, irq_flag);
+    }
+    
+    return RET_ERR;
+}
+
+int32 tk_close(struct tk_device *tk)
+{
+    if (tk)
+    {
+        return ((const struct tk_hal_ops *)tk->dev.ops)->close(tk);
+    }
+    
+    return RET_ERR;
+}

sdk/hal/uart.c

@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file       sdk/hal/uart.h
+  * @author     HUGE-IC Application Team
+  * @version    V1.0.0
+  * @date       2022-01-11
+  * @brief      This file contains all the UART HAL functions.
+  * @copyright  Copyright (c) 2016-2022 HUGE-IC
+  ******************************************************************************
+  * @attention
+  * None
+  *
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "typesdef.h"
+#include "errno.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/uart.h"
+
+/** @defgroup Docxygenid_UART_Driver UART Driver
+  * @brief    Mainly the driver part of the UART module
+  * @{
+  */
+
+
+/** @defgroup Docxygenid_UART_functions UART functions
+  * @ingroup  Docxygenid_UART_Driver
+  * @brief    UART Initialization And Configuration functions
+  * @{
+  */
+
+
+/**
+  * @brief  Open uart with baudrate and the default configuration.
+  * @param  uart      : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  baudrate  : Configure the baudrate for UART.
+  * @return
+  *         - RET_OK  : UART module open successfully.
+  *         - RET_ERR : UART module open unsuccessfully.
+  * @note
+  *         The default configuration is full duplex mode, no parity mode,\n
+  *         data bit is 8bit, stop bit is 1bit.If you need to change the configuration,\n
+  *         you can use the @ref uart_ioctl function to make changes after initialization is complete.
+  */
+int32 uart_open(struct uart_device *uart, uint32 baudrate)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->open(uart, baudrate);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  Close the UART module.
+  * @param  uart : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @return
+  *         - RET_OK  : UART module close successfully.
+  *         - RET_ERR : UART module close unsuccessfully.
+  * @note
+  *         The UART will not be able to send and receive data normally,\n
+  *         and all configurations (including interrupt-related configurations) will be invalid.
+  */
+int32 uart_close(struct uart_device *uart)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->close(uart);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  UART sends a frame of data.
+  * @param  uart  : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  vaule : The data to be sent by the UART, the unit is 1 frame.
+  * @return
+  *         - RET_OK  : UART module send successfully.
+  *         - RET_ERR : UART module send unsuccessfully.
+  * @note
+  *         If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
+  *         if the data bit is 9bit, one frame of data is 9bit.
+  */
+int32 uart_putc(struct uart_device *uart, int8 value)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->putc(uart, value);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  UART receives a frame of data.
+  * @param  uart : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @return
+  *         - value : The data value.
+  * @note
+  *         If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
+  *         if the data bit is 9bit, one frame of data is 9bit.
+  */
+uint8 uart_getc(struct uart_device *uart)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->getc(uart);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  The UART sends data according to the address and data number of the DATA BUFFER.
+  * @param  uart : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  buf  : Start address of DATA BUFFER.
+  * @param  len  : The number of data to be sent, the default unit is 8bit.
+  * @return
+  *         - RET_OK  : UART module send successfully.
+  *         - RET_ERR : UART module send unsuccessfully.
+  * @note
+  *         Send uses CPU by default. To use DMA transmission,\n
+  *         it needs to be configured using the @ref uart_ioctl() function.
+  */
+int32 uart_puts(struct uart_device *uart, uint8 *buf, uint32 len)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->puts(uart, buf, len);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  The UART receive data according to the address and data number of the DATA BUFFER.
+  * @param  uart : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  buf  : Start address of DATA BUFFER.
+  * @param  len  : The number of data to be sent, the default unit is 8bit.
+  * @return
+  *         - RET_OK  : UART module send successfully.
+  *         - RET_ERR : UART module send unsuccessfully.
+  * @note
+  *         Send uses CPU by default. To use DMA transmission,
+  *         it needs to be configured using the @ref uart_ioctl() function.
+  */
+int32 uart_gets(struct uart_device *uart, uint8 *buf, uint32 len)
+{
+    if (uart) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->gets(uart, buf, len);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  Configure the UART module by ioctl_cmd.
+  * @param  uart      : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  ioctl_cmd : Commands to configure the UART module, reference @ref uart_ioctl_cmd.
+  * @param  param1    : Parameter 1, according to the command.
+  * @param  param2    : Parameter 2, according to the command.
+  * @return
+  *         - RET_OK  : UART module configure successfully.
+  *         - RET_ERR : UART module configure unsuccessfully.
+  * @note
+  *         None.
+  */
+int32 uart_ioctl(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2)
+{
+    if (uart && ((const struct uart_hal_ops *)uart->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->ioctl(uart, ioctl_cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  Request interrupt by irq_flag.
+  * @param  uart     : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  irq_hdl  : Interrupt handle, executed after the interrupt is generated.
+  * @param  irq_flag : Interrupt type, reference @ref uart_irq_flag.
+  * @param  irq_data : Parameters for interrupt handler.
+  * @return
+  *         - RET_OK  : UART module request interrupt successfully.
+  *         - RET_ERR : UART module request interrupt unsuccessfully.
+  * @note
+  *         Support multiple interrupts to request together.
+  */
+int32 uart_request_irq(struct uart_device *uart, uart_irq_hdl irq_hdl, uint32 irq_flag,  uint32 irq_data)
+{
+    if (uart && ((const struct uart_hal_ops *)uart->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->request_irq(uart, irq_hdl, irq_flag, irq_data);
+    }
+    return RET_ERR;
+}
+
+/**
+  * @brief  Release interrupt by irq_flag.
+  * @param  uart     : UART handle. Usually use @ref dev_get() function to get the handle.
+  * @param  irq_flag : Interrupt type, reference @ref uart_irq_flag.
+  * @return
+  *         - RET_OK  : UART module release interrupt successfully.
+  *         - RET_ERR : UART module release interrupt unsuccessfully.
+  * @note
+  *         Support multiple interrupts to release together.
+  */
+int32 uart_release_irq(struct uart_device *uart, uint32 irq_flag)
+{
+    if (uart && ((const struct uart_hal_ops *)uart->dev.ops)->release_irq) {
+        HALDEV_SUSPENDED(uart);
+        return ((const struct uart_hal_ops *)uart->dev.ops)->release_irq(uart, irq_flag);
+    }
+    return RET_ERR;
+}
+
+/** @} Docxygenid_UART_functions*/
+
+/** @} Docxygenid_UART_Driver*/
+
+
+
+/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/

sdk/hal/usb_device.c

@@ -0,0 +1,70 @@
+#include "sys_config.h"
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/usb_device.h"
+
+int32 usb_device_open(struct usb_device *p_usb_d, struct usb_device_cfg *p_usbdev_cfg)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->open) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->open(p_usb_d, p_usbdev_cfg);
+    }
+    return RET_ERR;
+}
+
+int32 usb_device_close(struct usb_device *p_usb_d)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->close) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->close(p_usb_d);
+    }
+    return RET_ERR;
+}
+
+int32 usb_device_write(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->write) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->write(p_usb_d, ep, buff, len, sync);
+    }
+    return RET_ERR;
+}
+int32 usb_device_write_scatter(struct usb_device *p_usb_d, uint8 ep, scatter_data *data, uint32 count, uint8 sync)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->write_scatter) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->write_scatter(p_usb_d, ep, data, count, sync);
+    }
+    return RET_ERR;
+}
+
+int32 usb_device_read(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->read) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->read(p_usb_d, ep, buff, len, sync);
+    }
+    return RET_ERR;
+}
+
+int32 usb_device_ioctl(struct usb_device *p_usb_d, uint32 cmd, uint32 param1, uint32 param2)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->ioctl) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->ioctl(p_usb_d, cmd, param1, param2);
+    }
+    return RET_ERR;
+}
+
+int32 usb_device_request_irq(struct usb_device *p_usb_d, usbdev_irq_hdl handle, uint32 data)
+{
+    if (p_usb_d && ((const struct usb_hal_ops *)p_usb_d->dev.ops)->request_irq) {
+        HALDEV_SUSPENDED(p_usb_d);
+        return ((const struct usb_hal_ops *)p_usb_d->dev.ops)->request_irq(p_usb_d, handle, data);
+    }
+    return RET_ERR;
+}
+

sdk/hal/vpp.c

@@ -0,0 +1,624 @@
+#include "typesdef.h"
+#include "list.h"
+#include "errno.h"
+#include "dev.h"
+#include "devid.h"
+#include "hal/vpp.h"
+
+
+
+int32 vpp_suspend(struct vpp_device *p_vpp)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->suspend) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->suspend(p_vpp);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_resume(struct vpp_device *p_vpp)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->resume) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->resume(p_vpp);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_open(struct vpp_device *p_vpp)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->open) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->open(p_vpp);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_is_closed(struct vpp_device *p_vpp)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_IS_CLOSED, 0, 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_close(struct vpp_device *p_vpp)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->close) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->close(p_vpp);
+    }
+    return RET_ERR;
+}
+
+
+int32 vpp_dis_uv_mode(struct vpp_device *p_vpp,uint8 enable_buf0,uint8 enable_buf1){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_DIS_UV_MODE, enable_buf0, enable_buf1);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_threshold(struct vpp_device *p_vpp,uint32 dlt,uint32 dht){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_THRESHOLD, dlt, dht);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water0_rc(struct vpp_device *p_vpp,uint8 enable){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_RC, enable, 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water1_rc(struct vpp_device *p_vpp,uint8 enable){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_RC, enable, 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water0_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_COLOR, y|(u<<8)|(v<<16), 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water1_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_COLOR, y|(u<<8)|(v<<16), 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water0_bitmap(struct vpp_device *p_vpp,uint32 bitmap){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_BMPADR, bitmap, 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water1_bitmap(struct vpp_device *p_vpp,uint32 bitmap){
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_BMPADR, bitmap, 0);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_set_water0_locate(struct vpp_device *p_vpp,uint8 x,uint8 y){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_LOCATED, (y<<8)|x, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_water1_locate(struct vpp_device *p_vpp,uint8 x,uint8 y){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_LOCATED, (y<<8)|x, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_water0_contrast(struct vpp_device *p_vpp,uint8 contrast){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_CONTRAST, contrast, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_water1_contrast(struct vpp_device *p_vpp,uint8 contrast){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_CONTRAST, contrast, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_watermark0_charsize_and_num(struct vpp_device *p_vpp,uint8 w,uint8 h,uint8 num){
+	
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_SIZE_AND_NUM, w|(h<<8), num);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_watermark0_idx(struct vpp_device *p_vpp,uint8 index_num,uint8 index){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_IDX, index, index_num);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_watermark1_size(struct vpp_device *p_vpp,uint8 w,uint8 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_PHOTO_SIZE, (h<<8)|w, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_watermark0_mode(struct vpp_device *p_vpp,uint8 mode){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_MODE, mode, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark1_mode(struct vpp_device *p_vpp,uint8 mode){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_MODE, mode, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark0_enable(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark1_enable(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK1_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_det_enable(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_DET_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_calbuf(struct vpp_device *p_vpp,uint32 calbuf){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_CALBUF, calbuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_range(struct vpp_device *p_vpp,uint16 x_s,uint16 y_s,uint16 x_e,uint16 y_e){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_RANGE, x_s|(y_s<<16), x_e|(y_e<<16));
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_blk_threshold(struct vpp_device *p_vpp,uint8 threshold){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_BLK_THRESHOLD, threshold, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_frame_threshold(struct vpp_device *p_vpp,uint32 threshold){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_FRAME_THRESHOLD, threshold, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_frame_interval(struct vpp_device *p_vpp,uint8 interval){
+	if(interval > 0x1f){
+		//printf("motion interval error:%d\r\n",interval);
+		return RET_ERR;
+	}
+	
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_FRAME_INTERVAL, interval, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_motion_all_frame(struct vpp_device *p_vpp,uint32 allframe){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MOTION_ALL_FRAME_OR_WINDOW, allframe, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_ifp_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_IFP_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_ifp_en(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_IFP_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+// 1 : raw/rgb888      0: yuv422
+int32 vpp_set_mode(struct vpp_device *p_vpp,uint8 mode){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_MODE, mode, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_video_size(struct vpp_device *p_vpp,uint32 w,uint32 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_SIZE, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_ycbcr(struct vpp_device *p_vpp,uint8 ycbcr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_YCBCR, ycbcr, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_buf0_count(struct vpp_device *p_vpp,uint8 cnt){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF0_CNT, cnt, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf0_en(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF0_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_count(struct vpp_device *p_vpp,uint8 cnt){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_CNT, cnt, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_en(struct vpp_device *p_vpp,uint8 enable){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_EN, enable, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_shrink(struct vpp_device *p_vpp,uint8 half){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_SHRINK, half, 0);
+	}
+	return RET_ERR;
+}
+
+//0:DVP   1:DVP1   2:MIPI_CSI0   3:MIPI_CSI1   4:IMAGE_ISP    5:GEN422    6:PARA_IN
+int32 vpp_set_input_interface(struct vpp_device *p_vpp,uint8 mode){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_INPUT_INTERFACE, mode, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf0_y_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF0_Y_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf0_u_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF0_U_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf0_v_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF0_V_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_y_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_Y_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_u_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_U_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_buf1_v_addr(struct vpp_device *p_vpp,uint32 addr)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_BUF1_V_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_y_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ITP_Y_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_u_addr(struct vpp_device *p_vpp,uint32 addr){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ITP_U_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_v_addr(struct vpp_device *p_vpp,uint32 addr)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ITP_V_ADDR, addr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_linebuf(struct vpp_device *p_vpp,uint32 linebuf)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_TAKE_PHOTO_LINEBUF, linebuf, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_enable(struct vpp_device *p_vpp,uint8 en)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ITP_EN, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_itp_auto_close(struct vpp_device *p_vpp,uint8 en)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ITP_AUTO_CLOSE, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_isp_config(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_ISP_CONFIG, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_get_status(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_STA, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_ftusb30_enable(struct vpp_device *p_vpp,uint8 en)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_FTUSB3_EN, en, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_psram_ycnt(struct vpp_device *p_vpp,uint32 w,uint32 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_PSRAM_YCNT, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_psram_uvcnt(struct vpp_device *p_vpp,uint32 w,uint32 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_PSRAM_UVCNT, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_psram1_ycnt(struct vpp_device *p_vpp,uint32 w,uint32 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_PSRAM1_YCNT, w, h);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_psram1_uvcnt(struct vpp_device *p_vpp,uint32 w,uint32 h){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_PSRAM1_UVCNT, w, h);
+	}
+	return RET_ERR;
+}
+
+
+//vppbuf:   1:vpp buf0   2:vpp buf1
+int32 vpp_set_nosram_buf_enable(struct vpp_device *p_vpp,uint8 vppbuf)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_FRAME_SAVE_NO_SRAM, vppbuf, 0);
+	}
+	return RET_ERR;
+}
+
+//vppbuf : 0==>16+2N   1:2N
+int32 vpp_set_sram_buf_mode(struct vpp_device *p_vpp,uint8 vppbuf0,uint8 vppbuf1)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SRAMBUFF_CNT_MODE, vppbuf0, vppbuf1);
+	}
+	return RET_ERR;
+}
+
+//scale : 0==>buf0   1:buf1
+int32 vpp_set_scale_buf_select(struct vpp_device *p_vpp,uint8 scale1,uint8 scale3)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SCALEBUF_SELECT, scale1, scale3);
+	}
+	return RET_ERR;
+}
+
+//0:vpp buf0  1:vpp buf1
+int32 vpp_get_scale1_buf_select(struct vpp_device *p_vpp){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_SCALE1BUF_SELECT, 0, 0);
+	}
+	return RET_ERR;
+}
+
+//0:vpp buf0  1:vpp buf1
+int32 vpp_get_scale3_buf_select(struct vpp_device *p_vpp){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_SCALE3BUF_SELECT, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_nosram_buf1_enable(struct vpp_device *p_vpp,uint8 en)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_F1_SAVE_NO_SRAM, en, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_get_f0_is_psram(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F0_IS_PSRAM, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_get_f1_is_psram(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F1_IS_PSRAM, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_f0_is_enable(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F0_IS_ENABLE, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_get_f1_mode(struct vpp_device *p_vpp){
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F1_MODE, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_f1_is_enable(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F1_IS_ENABLE, 0, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_get_f1_shrink(struct vpp_device *p_vpp)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GET_F1_SHRINK, 0, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_gen420_buf_sel(struct vpp_device *p_vpp,uint8 buf)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_GEN420_BUF_SEL, buf, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_set_watermark0_auto_rc_threshold(struct vpp_device *p_vpp,uint32 cth,uint32 hth)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_THRESHOLD, cth, hth);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark0_auto_rc(struct vpp_device *p_vpp,uint32 en,uint8 y,uint8 u,uint8 v)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_COLOR, en, y|(u<<8)|(v<<16));
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark0_auto_rc_sram_adr(struct vpp_device *p_vpp,uint32 adr)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_HADR, adr, 0);
+	}
+	return RET_ERR;
+}
+
+int32 vpp_set_watermark_auto_rc_mode(struct vpp_device *p_vpp,uint8 mode)
+{
+	if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl) {
+		return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->ioctl(p_vpp, VPP_IOCTL_CMD_SET_WATERMARK0_AUTO_RC_MODE, mode, 0);
+	}
+	return RET_ERR;
+}
+
+
+int32 vpp_request_irq(struct vpp_device *p_vpp, uint32 irq_flags, vpp_irq_hdl irq_hdl, uint32 irq_data)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->request_irq) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->request_irq(p_vpp, irq_flags, irq_hdl, irq_data);
+    }
+    return RET_ERR;
+}
+
+int32 vpp_release_irq(struct vpp_device *p_vpp, uint32 irq_flags)
+{
+    if (p_vpp && ((const struct vpp_hal_ops *)p_vpp->dev.ops)->release_irq) {
+        return ((const struct vpp_hal_ops *)p_vpp->dev.ops)->release_irq(p_vpp, irq_flags);
+    }
+    return RET_ERR;
+}
+
+