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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
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sdk/driver/spi/hgcqspi_hw.h Normal file
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#ifndef _HGCQSPI_HW_H_
#define _HGCQSPI_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @brief SPI register structure
* @{
*/
struct hgcqspi_hw {
__IO uint32 CONFIG; //0x00
__IO uint32 DEV_RDINSTR_CONFIG; //0x04
__IO uint32 DEV_WRINSTR_CONFIG; //0x08
__IO uint32 DEV_DELAY; //0x0c
__IO uint32 READ_DATA_CAPTURE; //0x10
__IO uint32 DEV_SIZE_CONFIG; //0x14
__IO uint32 SRAM_PARTITION; //0x18
__IO uint32 IND_AHB_TRIGGER; //0x1c
__IO uint32 PERIPH_CFG; //0x20
__IO uint32 REMAP_ADD; //0x24
__IO uint32 MODE_BIT; //0x28
__IO uint32 SRAM_FILL_LEVEL; //0x2c
__IO uint32 TX_THRESH; //0x30
__IO uint32 RX_THRESH; //0x34
__IO uint32 WRITE_COMP_CTRL; //0x38
__IO uint32 MAX_NO_OF_POLLS; //0x3c
__IO uint32 INT_STATUS; //0x40
__IO uint32 INT_MASK; //0x44
uint32 RESERVED0[2];
__IO uint32 WRITE_PROT_L; //0x50
__IO uint32 WRITE_PROT_U; //0x54
__IO uint32 WRITE_PROT_CTRL; //0x58
uint32 RESERVED1[1];
__IO uint32 IND_RD_XFER_CTRL; //0x60
__IO uint32 IND_RD_XFER_WMARK; //0x64
__IO uint32 IND_RD_XFER_START_ADD; //0x68
__IO uint32 IND_RD_XFER_NUM_BYTES; //0x6c
__IO uint32 IND_WR_XFER_CTRL; //0x70
__IO uint32 IND_WR_XFER_WMARK; //0x74
__IO uint32 IND_WR_XFER_START_ADD; //0x78
__IO uint32 IND_WR_XFER_NUM_BYTES; //0x7c
__IO uint32 IND_AHB_TRIGGER_RANGE; //0x80
uint32 RESERVED2[2];
__IO uint32 FLASH_CMD_CTRL_MEM; //0x8C
__IO uint32 FLASH_CMD_CTRL; //0x90
__IO uint32 FLASH_CMD_ADD; //0x94
uint32 RESERVED3[2];
__IO uint32 FLASH_CMD_RDATA_L; //0xa0
__IO uint32 FLASH_CMD_RDATA_U; //0xa4
__IO uint32 FLASH_CMD_WDATA_L; //0xa8
__IO uint32 FLASH_CMD_WDATA_U; //0xac
__IO uint32 FLASH_STATUS; //0xb0
__IO uint32 PHY_CONFIG; //0xb4
__IO uint32 PHY_DLL_MASTER_CONFIG; //0xb8
__IO uint32 DLL_OBSERVABLE_L; //0xbc
__IO uint32 DLL_OBSERVABLE_U; //0xc0
uint32 RESERVED4[5];
__IO uint32 NEW_ADD_CONFIG0; //d8
__IO uint32 NEW_ADD_CONFIG1; //dc
__IO uint32 OPCODE_EXT_L; //E0
__IO uint32 OPCODE_EXT_U; //E4
__IO uint32 READ_DATA_CAPTURE_EXT; //0xE8
__IO uint32 WRITE_PROT_CTRL_EXT; //0xEC
__IO uint32 DEV_RDINSTR_CONFIG_CS1; //0xF0
__IO uint32 DEV_WRINSTR_CONFIG_CS1; //0xF4
__IO uint32 MONITOR; //0xF8, for OSPI
__IO uint32 MODULE_ID; //0xfc
};
/** @addtogroup SPI MODULE REGISTER
* @{
*/
#define CQSPI_NAME "cadence-qspi"
#define CQSPI_MAX_CHIPSELECT 1//16
#define CQSPI_AHB_TRIG_ADDR (0x18000000)
/* Operation timeout value */
#define CQSPI_TIMEOUT_MS 500
#define CQSPI_READ_TIMEOUT_MS 10
/* Instruction type */
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_DUMMY_CLKS_MAX 31
#define CQSPI_STIG_DATA_LEN_MAX 8
/* Register map */
#define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
#define CQSPI_REG_RD_INSTR 0x04
#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
#define CQSPI_REG_WR_INSTR 0x08
#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
#define CQSPI_REG_DELAY 0x0C
#define CQSPI_REG_DELAY_TSLCH_LSB 0
#define CQSPI_REG_DELAY_TCHSH_LSB 8
#define CQSPI_REG_DELAY_TSD2D_LSB 16
#define CQSPI_REG_DELAY_TSHSL_LSB 24
#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
#define CQSPI_REG_READCAPTURE 0x10
#define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
#define CQSPI_REG_READCAPTURE_DELAY_LSB 1
#define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
#define CQSPI_REG_SIZE 0x14
#define CQSPI_REG_SIZE_ADDRESS_LSB 0
#define CQSPI_REG_SIZE_PAGE_LSB 4
#define CQSPI_REG_SIZE_BLOCK_LSB 16
#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
#define CQSPI_REG_SRAMPARTITION 0x18
#define CQSPI_REG_INDIRECTTRIGGER 0x1C
#define CQSPI_REG_DMA 0x20
#define CQSPI_REG_DMA_SINGLE_LSB 0
#define CQSPI_REG_DMA_BURST_LSB 8
#define CQSPI_REG_DMA_SINGLE_MASK 0xFF
#define CQSPI_REG_DMA_BURST_MASK 0xFF
#define CQSPI_REG_REMAP 0x24
#define CQSPI_REG_MODE_BIT 0x28
#define CQSPI_REG_SDRAMLEVEL 0x2C
#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
#define CQSPI_REG_IRQSTATUS 0x40
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
#define CQSPI_REG_INDIRECTWR 0x70
#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
#define CQSPI_REG_INDIRECTWRBYTES 0x7C
#define CQSPI_REG_CMDADDRESS 0x94
#define CQSPI_REG_CMDREADDATALOWER 0xA0
#define CQSPI_REG_CMDREADDATAUPPER 0xA4
#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
/* Interrupt status bits */
#define CQSPI_REG_IRQ_MODE_ERR BIT(0)
#define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
#define CQSPI_REG_IRQ_IND_COMP BIT(2)
#define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
#define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
#define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
#define CQSPI_REG_IRQ_WATERMARK BIT(6)
#define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
#define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
CQSPI_REG_IRQ_IND_SRAM_FULL | \
CQSPI_REG_IRQ_IND_COMP)
#define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
CQSPI_REG_IRQ_WATERMARK | \
CQSPI_REG_IRQ_UNDERFLOW)
#define CQSPI_IRQ_STATUS_MASK 0x1FFFF
/*
* Note on opcode nomenclature: some opcodes have a format like
* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
* of I/O lines used for the opcode, address, and data (respectively). The
* FUNCTION has an optional suffix of '4', to represent an opcode which
* requires a 4-byte (32-bit) address.
*/
/* Flash opcodes. */
#define SPINOR_OP_WREN 0x06 /* Write enable */
#define SPINOR_OP_RDSR 0x05 /* Read status register */
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* Used for SST flashes only. */
#define SPINOR_OP_BP 0x02 /* Byte program */
#define SPINOR_OP_WRDI 0x04 /* Write disable */
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
/* Status Register bits. */
#define SR_WIP BIT(0) /* Write in progress */
#define SR_WEL BIT(1) /* Write enable latch */
/* meaning of other SR_* bits may differ between vendors */
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#define SR_TB BIT(5) /* Top/Bottom protect */
#define SR_SRWD BIT(7) /* SR write protect */
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
/* Flag Status Register bits */
#define FSR_READY BIT(7)
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
enum qspi_dev_size {
QSPI_DEV_SIZE_8MB,
QSPI_DEV_SIZE_16MB,
QSPI_DEV_SIZE_32MB,
QSPI_DEV_SIZE_4MB,
};
/**
* @brief ll_qspi_enable
* @param p_qspi :QSPI register structure pointer
* @retval none
*/
__STATIC_INLINE void ll_qspi_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG |= CQSPI_REG_CONFIG_ENABLE_MASK;
}
/**
* @brief ll_qspi_disable
* @param p_qspi :QSPI register structure pointer
* @retval none
*/
__STATIC_INLINE void ll_qspi_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
}
/**
* @brief ll_qspi_cs_sel
* @param p_qspi :QSPI register structure pointer
* @param cs :cs select [0:3]
* @retval none
*/
__STATIC_INLINE void ll_qspi_cs_sel(struct hgcqspi_hw *p_qspi, uint8 cs)
{
p_qspi->CONFIG = (p_qspi->CONFIG & ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK << CQSPI_REG_CONFIG_CHIPSELECT_LSB)) |
((~(BIT(cs)) & CQSPI_REG_CONFIG_CHIPSELECT_MASK) << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param
* @retval none
*/
__STATIC_INLINE void ll_qspi_ahb_decoder_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG |= BIT(23);
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_device_size(struct hgcqspi_hw *p_qspi, uint8 dev_index, enum qspi_dev_size dev_size)
{
uint32 dev_size_reg = p_qspi->DEV_SIZE_CONFIG;
dev_size_reg &= ~((BIT(22)|BIT(21)) << (dev_index*2));
dev_size_reg |= (dev_size << (21 + dev_index*2));
p_qspi->DEV_SIZE_CONFIG = dev_size_reg;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_page_size(struct hgcqspi_hw *p_qspi, uint32 page_size)
{
uint32 dev_size_reg = p_qspi->DEV_SIZE_CONFIG;
dev_size_reg &= 0xFFFF000F;
dev_size_reg |= (page_size & 0x0FFF) << 4;
p_qspi->DEV_SIZE_CONFIG = dev_size_reg;
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param size : blocksiez = power(2, size)
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_block_size(struct hgcqspi_hw *p_qspi, uint32 size)
{
uint32 dev_size_reg = p_qspi->DEV_SIZE_CONFIG;
dev_size_reg &= 0xFFE0FFFF;
dev_size_reg |= (size & 0x01F) << 16;
p_qspi->DEV_SIZE_CONFIG = dev_size_reg;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param
* @retval none
*/
__STATIC_INLINE void ll_qspi_ahb_decoder_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG &= ~(BIT(23));
}
/**
* @brief ll_qspi_set_clk
* @param p_qspi :QSPI register structure pointer
* @param clk_hz :
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_clk(struct hgcqspi_hw *p_qspi, uint32 clk_hz)
{
uint32 div;
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
/* Recalculate the baudrate divisor based on QSPI specification. */
#if 1//FPGA
div = DIV_ROUND_UP(96000000, 2 * clk_hz) - 1;
#else
/* fill this : sys_clock_cfg.syspll_clk */
div = DIV_ROUND_UP(384000000, 2 * clk_hz) - 1;
#endif
/* avoid qspi div2 bug */
if (0 == div) div = 1;
p_qspi->CONFIG = (p_qspi->CONFIG & ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB)) |
((div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB);
}
/**
* @brief ll_qspi_is_idle
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE bool ll_qspi_is_idle(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->CONFIG & BIT(31)) ? TRUE : FALSE;
}
/**
* @brief ll_qspi_is_cmd_done
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE bool ll_qspi_is_cmd_done(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->FLASH_CMD_CTRL & BIT(1)) ? FALSE : TRUE;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE void ll_qspi_wel_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->DEV_WRINSTR_CONFIG &= ~(BIT(8));
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE void ll_qspi_wel_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->DEV_WRINSTR_CONFIG |= BIT(8);
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE bool ll_qspi_is_wel_enable(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->DEV_WRINSTR_CONFIG & BIT(8)) ? FALSE : TRUE;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE void ll_qspi_poll_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->WRITE_COMP_CTRL &= ~(BIT(14));
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE void ll_qspi_poll_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->WRITE_COMP_CTRL |= BIT(14);
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param :
* @retval none
*/
__STATIC_INLINE bool ll_qspi_is_poll_enable(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->WRITE_COMP_CTRL & BIT(14)) ? FALSE : TRUE;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param width : 0/1/2 for data width 1/2/4
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_rd_attr(struct hgcqspi_hw *p_qspi,
uint8 cmd,
uint8 cmd_width,
uint8 addr_width,
uint8 dat_width,
uint8 dummys,
uint8 ddr_en)
{
p_qspi->DEV_RDINSTR_CONFIG = ((dummys & 0x1F) << 24) |
((dat_width & 0x3) << 16) |
((addr_width & 0x3) << 12) |
((ddr_en & 0x1) << 10) |
((cmd_width & 0x3) << 8) |
cmd;
}
/**
* @brief
* @param p_qspi :QSPI register structure pointer
* @param width : 0/1/2 for data width 1/2/4
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_wr_attr(struct hgcqspi_hw *p_qspi,
uint8 cmd,
uint8 cmd_width,
uint8 addr_width,
uint8 dat_width,
uint8 dummys,
uint8 wel_disable)
{
p_qspi->DEV_WRINSTR_CONFIG = ((dummys & 0x1F) << 24) |
((dat_width & 0x3) << 16) |
((addr_width & 0x3) << 12) |
((wel_disable & 0x1) << 8) |
cmd;
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param width :
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_clk_mode(struct hgcqspi_hw *p_qspi, uint8 clock_mode)
{
p_qspi->CONFIG = (p_qspi->CONFIG & ~(BIT(1)|BIT(2))) | ((clock_mode & 0x3) << 1);
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_set_sample_dalay(struct hgcqspi_hw *p_qspi, uint8 delay_ref_clk)
{
delay_ref_clk &= 0xF;
p_qspi->DEV_DELAY = (p_qspi->DEV_DELAY & ~(0xFUL<<1)) | ((delay_ref_clk) << 1);
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_remap_enable(struct hgcqspi_hw *p_qspi, uint32 offset)
{
while(!ll_qspi_is_idle(p_qspi));
p_qspi->REMAP_ADD = offset;
p_qspi->CONFIG |= (BIT(16));
__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
while(!ll_qspi_is_idle(p_qspi));
//csi_dcache_invalid();
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_remap_disable(struct hgcqspi_hw *p_qspi)
{
while(!ll_qspi_is_idle(p_qspi));
p_qspi->CONFIG &= ~(BIT(16));
__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
while(!ll_qspi_is_idle(p_qspi));
//csi_dcache_invalid();
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_dac_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG |= (BIT(7));
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_dac_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->CONFIG &= ~(BIT(7));
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_cs_fix_enable(struct hgcqspi_hw *p_qspi)
{
p_qspi->WRITE_PROT_CTRL |= (BIT(3));
}
/**
* @brief
* @param p_qspi : QSPI register structure pointer
* @param delay_ref_clk : the delay_ref_clk less than divor is better
* @retval none
*/
__STATIC_INLINE void ll_qspi_cs_fix_disable(struct hgcqspi_hw *p_qspi)
{
p_qspi->WRITE_PROT_CTRL &= ~(BIT(3));
}
__STATIC_INLINE uint32 ll_qspi_is_xip_mode(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->CONFIG & (BIT(17)|BIT(18))) ? 1:0;
}
__STATIC_INLINE uint32 ll_qspi_is_dtr_mode(struct hgcqspi_hw *p_qspi)
{
return (p_qspi->DEV_RDINSTR_CONFIG & BIT(10)) ? 1:0;
}
/**
* @brief hg_qspi_set_encrypt_disable_range
* @param p_qspi : QSPI register structure pointer
* @param index : rang 0/1
* @param st_addr_1k :
* @param end_addr_1k :
* @retval none
*/
__STATIC_INLINE void hg_qspi_set_encrypt_disable_range(struct hgcqspi_hw *p_qspi, uint8 index, uint32 st_addr_1k, uint32 end_addr_1k)
{
uint32 reg = (st_addr_1k & 0x7FFF) | ((end_addr_1k & 0x7FFF) << 16);
SYSCTRL_REG_OPT(
if (index) {
SYSCTRL->QSPI_ENCDEC_CON1 = reg;
} else {
SYSCTRL->QSPI_ENCDEC_CON0 = (SYSCTRL->QSPI_ENCDEC_CON0 & BIT(31)) | reg;
}
);
}
enum hgcqspi_flags {
hgcqspi_flags_suspend,
};
#ifdef __cplusplus
}
#endif
#endif /* _HGCQSPI_H_ */

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#ifndef _HGSPI_V1_HW_H_
#define _HGSPI_V1_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup SPI MODULE REGISTER
* @{
*/
/***** CON0(for SPI) Register *****/
/*! SPI slave read status done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_WRONGCMD_IE_EN (1UL << 25)
/*! SPI slave read status done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_WIREMODE_IE_EN (1UL << 24)
/*! SPI slave read status done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_RDSTATUS_IE_EN (1UL << 23)
/*! SPI slave read data done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_RDDATA_IE_EN (1UL << 22)
/*! SPI slave write data done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_WRDATA_IE_EN (1UL << 21)
/*! SPI slave state enable
*/
#define LL_SPI_CON0_SLAVE_STATE_EN (1UL << 20)
/*! SPI frame size
*/
#define LL_SPI_CON0_FRAME_SIZE(n) (((n)&0x3F) << 14)
/*! Get SPI frame size
*/
#define LL_SPI_CON0_GET_FRAME_SIZE(n) (((n)>>14) & 0x3F)
/*! SPI slave CS(NSS) rising edge interrupt enable
*/
#define LL_SPI_CON0_NSS_POS_IE_EN (1UL << 13)
/*! SPI CS(NSS) pin enable
*/
#define LL_SPI_CON0_NSS_PIN_EN (1UL << 12)
/*! SPI CS(NSS) output high
* @note Only valid in SPI master mode
*/
#define LL_SPI_CON0_NSS_HIGH (1UL << 11)
/*! Input data synchronization enable in SPI slave mode
*/
#define LL_SPI_CON0_SLAVE_SYNC_EN (1UL << 7)
/*! Input data synchronization enable in SPI master mode
*/
#define LL_SPI_CON0_MASTER_SYNC_EN (1UL << 6)
/*! The SPI transfers data from the low bit
*/
#define LL_SPI_CON0_LSB_FIRST (1UL << 4)
/*! SPI wire mode
*/
#define LL_SPI_CON0_WIRE_MODE(n) (((n)&0x03) << 2)
/*! Get SPI wire mode
*/
#define LL_SPI_CON0_WIRE_MODE_GET(n) (((n)>>2) & 0x03)
/*! SPI mode
*/
#define LL_SPI_CON0_SPI_MODE(n) (((n)&0x03) << 0)
/***** CON1(for SPI) Register *****/
/*! SPI DMA done interrupt enable
*/
#define LL_SPI_CON1_DMA_IE_EN (1UL << 9)
/*! SPI FIFO overflow interrupt enable
*/
#define LL_SPI_CON1_BUF_OV_IE_EN (1UL << 8)
/*! SPI RX FIFO not empty interrupt enable
*/
#define LL_SPI_CON1_RX_BUF_NOT_EMPTY_IE_EN (1UL << 7)
/*! SPI TX FIFO not full interrupt enable
*/
#define LL_SPI_CON1_TX_BUF_NOT_FULL_IE_EN (1UL << 6)
/*! SPI transfers one frame interrupt enable
*/
#define LL_SPI_CON1_SSP_IE_EN (1UL << 5)
/*! SPI DMA enable
*/
#define LL_SPI_CON1_DMA_EN (1UL << 4)
/*! The SPI is set to the TX direction
*/
#define LL_SPI_CON1_TX_EN (1UL << 3)
/*! SPI working mode
*/
#define LL_SPI_CON1_MODE(n) (((n)&0x01) << 2)
/*! Get SPI working mode
*/
#define LL_SPI_CON1_GET_MODE(n) (((n)>>2) & 0x01)
/*! SPI/IIC selection
*/
#define LL_SPI_CON1_SPI_I2C_SEL(n) (((n)&0x01) << 1)
/*! SPI/IIC module enable
*/
#define LL_SPI_CON1_SSP_EN (1UL << 0)
/***** SSP CMD DATA(for SPI) Register *****/
/*! Write data(32bit)
*/
#define LL_SPI_SSP_CMD_DATA_WRITE(n) (n)
/*! Read data(32bit)
*/
#define LL_SPI_SSP_CMD_DATA_READ(n) (n)
/***** BAUD(for SPI) Register *****/
/*! Set baud rate(16bit)
*/
#define LL_SPI_BAUD(n) (n)
/***** DMA Tx LEN(for SPI) Register *****/
/*! Set DMA Tx length(12bit)
*/
#define LL_SPI_DMA_TX_LEN(n) (n)
/***** DMA Tx CNT(for SPI) Register *****/
/*! The length of the byte of the transmitted data(12bit)
*/
#define LL_SPI_DMA_TX_CNT(n) (n)
/***** DMA Tx STADR(for SPI) Register *****/
/*! DMA Tx start address(13bit)
*/
#define LL_SPI_DMA_TX_STADR(n) (n)
/***** DMA Rx LEN(for SPI) Register *****/
/*! Set DMA Rx length(12bit)
*/
#define LL_SPI_DMA_RX_LEN(n) (n)
/***** DMA Rx CNT(for SPI) Register *****/
/*! The length of the byte of the received data(12bit)
*/
#define LL_SPI_DMA_RX_CNT(n) (n)
/***** DMA Rx STADR(for SPI) Register *****/
/*! DMA Rx start address(13bit)
*/
#define LL_SPI_DMA_RX_STADR(n) (n)
/***** STA(for SPI) Register *****/
/*! SPI Slave wrong cmd pending
*/
#define LL_SPI_STA_SLAVE_WRONG_CMD_PENDING (1UL << 28)
/*! SPI Slave wiremode change pending
*/
#define LL_SPI_STA_SLAVE_WIREMODE_CFG_PENDING (1UL << 23)
/*! SPI Slave read status pending
*/
#define LL_SPI_STA_SLAVE_RDSTATUS_PENDING (1UL << 22)
/*! SPI Slave read data pending
*/
#define LL_SPI_STA_SLAVE_RDDATA_PENDING (1UL << 21)
/*! SPI Slave write data pending
*/
#define LL_SPI_STA_SLAVE_WRDATA_PENDING (1UL << 20)
/*! Clear fifo
*/
#define LL_SPI_STA_CLEAR_BUF_CNT (1UL << 19)
/*! Get how many bytes of valid data in the FIFO
*/
#define LL_SPI_STA_BUF_CNT(n) (((n)>>16) & 0x07)
/*! SPI master receive data busy pending
*/
#define LL_SPI_STA_MASTER_RX_BUSY_PENDING (1UL << 15)
/*! The SPI slave gets the CS pin state
*/
#define LL_SPI_STA_SLAVE_CS_STATE (1UL << 11)
/*! SPI module busy pending
*/
#define LL_SPI_STA_SSP_BUSY_PENDING (1UL << 10)
/*! SPI slave CS(NSS) rising edge detected pending
*/
#define LL_SPI_STA_NSS_POS_PENDING (1UL << 5)
/*! SPI DMA done pending
*/
#define LL_SPI_STA_DMA_PENDING (1UL << 4)
/*! SPI FIFO overflow pending
*/
#define LL_SPI_STA_BUF_OV_PENDING (1UL << 3)
/*! SPI FIFO empty pending
*/
#define LL_SPI_STA_BUF_EMPTY_PENDING (1UL << 2)
/*! SPI FIFO full pending
*/
#define LL_SPI_STA_BUF_FULL_PENDING (1UL << 1)
/*! SPI transfers one frame done pending
*/
#define LL_SPI_STA_DONE_PENDING (1UL << 0)
/***** SLAVESTA(for SPI) Register *****/
#define LL_SPI_SLAVE_STA_TX_LEN(n) (((n)&0xFF) << 16)
#define LL_SPI_SLAVE_STA_RX_LEN(n) (((n)&0xFF) << 8)
#define LL_SPI_SLAVE_STA_RX_READY_EN (1UL << 7)
#define LL_SPI_SLAVE_STA_TX_READY_EN (1UL << 6)
#define LL_SPI_SLAVE_STA_SW_RESERVED (1UL << 5)
#define LL_SPI_SLAVE_STA_WRONG_COMMAND (1UL << 4)
#define LL_SPI_SLAVE_STA_DATA_TOGGLE (1UL << 3)
#define LL_SPI_SLAVE_STA_TX_OVERFLOW (1UL << 2)
#define LL_SPI_SLAVE_STA_RX_READY_FLG (1UL << 1)
#define LL_SPI_SLAVE_STA_TX_READY_FLG (1UL << 0)
/***** SSP_DLY Register *****/
/*! Transfer delay time config
@Note: t = APB_CLK * (n)
*/
#define LL_SPI_AND_IIC_SSP_DLY(n) ((n & 0xFF) << 0)
/** @brief SPI register structure
* @{
*/
struct hgspi_v1_hw {
__IO uint32_t CON0;
__IO uint32_t CON1;
__IO uint32_t CMD_DATA;
__IO uint32_t BAUD;
__IO uint32_t TDMALEN;
__IO uint32_t RDMALEN;
__IO uint32_t TDMACNT;
__IO uint32_t RDMACNT;
__IO uint32_t TSTADR;
__IO uint32_t RSTADR;
__IO uint32_t STA;
__IO uint32_t SLAVESTA;
__IO uint32_t SSP_DLY;
};
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V1_HW_H_ */

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#ifndef _HGGPIO_V4_HW_H_
#define _HGGPIO_V4_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/***** SPICON *****/
/*! Interrupt flag clear, write 1 to clear, write 0 to have no effect
*/
#define LL_SIMPLE_SPI_CON_SPIINTCLR(n) (((n)&0x01) << 10)
/*! SPI interrupt flag
*/
#define LL_SIMPLE_SPI_CON_SPIINT(n) (((n)&0x01) << 9)
/*! SPI status flag
*/
#define LL_SIMPLE_SPI_CON_SPIDONE(n) (((n)&0x01) << 8)
/*! DMA enable flag
*/
#define LL_SIMPLE_SPI_CON_SPIDISYNCEN(n) (((n)&0x01) << 7)
/*! Master or slave control bits
*/
#define LL_SIMPLE_SPI_CON_SPISM(n) (((n)&0x01) << 6)
/*! Send or receive control bits
*/
#define LL_SIMPLE_SPI_CON_SPIRXTX(n) (((n)&0x01) << 5)
/*! 2-wire or 3-wire mode selection
*/
#define LL_SIMPLE_SPI_CON_SPI2W3W(n) (((n)&0x01) << 4)
/*! SPI interrupt enable bit
*/
#define LL_SIMPLE_SPI_CON_SPIINTEN(n) (((n)&0x01) << 3)
/*! Sampling mode selection bit
*/
#define LL_SIMPLE_SPI_CON_SPISMPSEL(n) (((n)&0x01) << 2)
/*! Clock line idle state selection bit
*/
#define LL_SIMPLE_SPI_CON_SPIIDST(n) (((n)&0x01) << 1)
/*! SPI enable bit
*/
#define LL_SIMPLE_SPI_CON_SPIEN(n) (((n)&0x01) << 0)
/*****SPIBAUD *****/
/*! Baud rate setting
*/
#define LL_SIMPLE_SPI_SPIBAUD(n) (((n)&0x0000FFFF) << 0)
/***** SPIDATA *****/
/*! Data register
*/
#define LL_SIMPLE_SPI_SPIDATA(n) (((n)&0x000000FF) << 0)
struct hgspi_v2_hw {
__IO uint32_t CON;
__IO uint32_t BAUD;
__IO uint32_t DATA;
};
#ifdef __cplusplus
}
#endif
#endif /* _HGGPIO_V4_HW_H_ */

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sdk/driver/spi/hgspi_v3.c Normal file
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sdk/driver/spi/hgspi_v3_hw.h Normal file
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#ifndef _HGSPI_V3_HW_H_
#define _HGSPI_V3_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup SPI MODULE REGISTER
* @{
*/
/***** CON0(for SPI) Register *****/
#define LL_SPI_CON0_DUMMY_CNT(n) ((n&0x0F) << 26)
#define LL_SPI_CON0_SLAVE_WRONG_CMD_IE (1UL << 25)
#define LL_SPI_CON0_SLAVE_WIREMODE_CFG_IE (1UL << 24)
/*! SPI slave read status done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_RDSTATUS_IE_EN (1UL << 23)
/*! SPI slave read data done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_RDDATA_IE_EN (1UL << 22)
/*! SPI slave write data done interrupt enable
*/
#define LL_SPI_CON0_SLAVE_WRDATA_IE_EN (1UL << 21)
/*! SPI slave state enable
*/
#define LL_SPI_CON0_SLAVE_STATE_EN (1UL << 20)
/*! SPI frame size
*/
#define LL_SPI_CON0_FRAME_SIZE(n) (((n)&0x3F) << 14)
/*! Get SPI frame size
*/
#define LL_SPI_CON0_GET_FRAME_SIZE(n) (((n)>>14) & 0x3F)
/*! SPI slave CS(NSS) rising edge interrupt enable
*/
#define LL_SPI_CON0_NSS_POS_IE_EN (1UL << 13)
#define LL_SPI_CON0_SSOE(n) ((n&0x01) << 12)
/*! SPI CS(NSS) output high
* @note Only valid in SPI master mode
*/
#define LL_SPI_CON0_NSS_HIGH (1UL << 11)
/*! SPI CS(NSS) pin enable
*/
#define LL_SPI_CON0_NSS_PIN_EN (1UL << 10)
#define LL_SPI_CON0_SPI_HIGH_SPEED(n) ((n&0x3) << 8)
#define LL_SPI_CON0_SLAVE_DATAIN_SEL(n) ((n&0x3) << 6)
/*! The SPI transfers data from the low bit
*/
#define LL_SPI_CON0_LSB_FIRST (1UL << 5)
/*! SPI wire mode
*/
#define LL_SPI_CON0_WIRE_MODE(n) (((n)&0x07) << 2)
/*! Get SPI wire mode
*/
#define LL_SPI_CON0_WIRE_MODE_GET(n) (((n)>>2) & 0x03)
/*! SPI mode
*/
#define LL_SPI_CON0_SPI_MODE(n) (((n)&0x03) << 0)
/***** CON1(for SPI) Register *****/
#define LL_SPI_CON1_PING_PONG_EN(n) ((n&0x1) << 12)
#define LL_SPI_CON1_CLRBUFCNT_CLRSSP_EN(n) ((n&0x1) << 11)
#define LL_SPI_CON1_RX_TIMEOUT_IE(n) ((n&0x1) << 10)
/*! SPI DMA done interrupt enable
*/
#define LL_SPI_CON1_DMA_IE_EN (1UL << 9)
/*! SPI FIFO overflow interrupt enable
*/
#define LL_SPI_CON1_BUF_OV_IE_EN (1UL << 8)
/*! SPI RX FIFO not empty interrupt enable
*/
#define LL_SPI_CON1_RX_BUF_NOT_EMPTY_IE_EN (1UL << 7)
/*! SPI TX FIFO not full interrupt enable
*/
#define LL_SPI_CON1_TX_BUF_NOT_FULL_IE_EN (1UL << 6)
/*! SPI transfers one frame interrupt enable
*/
#define LL_SPI_CON1_SSP_IE_EN (1UL << 5)
/*! SPI DMA enable
*/
#define LL_SPI_CON1_DMA_EN (1UL << 4)
/*! The SPI is set to the TX direction
*/
#define LL_SPI_CON1_TX_EN (1UL << 3)
/*! SPI working mode
*/
#define LL_SPI_CON1_MODE(n) (((n)&0x01) << 2)
/*! Get SPI working mode
*/
#define LL_SPI_CON1_GET_MODE(n) (((n)>>2) & 0x01)
/*! SPI/IIC selection
*/
#define LL_SPI_CON1_SPI_I2C_SEL(n) (((n)&0x01) << 1)
/*! SPI/IIC module enable
*/
#define LL_SPI_CON1_SSP_EN (1UL << 0)
/***** SSP CMD DATA(for SPI) Register *****/
/*! Write data(32bit)
*/
#define LL_SPI_SSP_CMD_DATA_WRITE(n) (n)
/*! Read data(32bit)
*/
#define LL_SPI_SSP_CMD_DATA_READ(n) (n)
/***** TIMECON(for SPI) Register *****/
/*! Set baud rate(16bit)
*/
#define LL_SPI_TIMECON_SPI_RX_DLY(n) ((n&0xFFFF)<<16)
#define LL_SPI_TIMECON_BAUD(n) ((n&0xFFFF)<<0)
/***** DMA Tx LEN(for SPI) Register *****/
/*! Set DMA Tx length(12bit)
*/
#define LL_SPI_DMA_TX_LEN(n) (n)
/***** DMA Tx CNT(for SPI) Register *****/
/*! The length of the byte of the transmitted data(12bit)
*/
#define LL_SPI_DMA_TX_CNT(n) (n)
/***** DMA Tx STADR(for SPI) Register *****/
/*! DMA Tx start address(13bit)
*/
#define LL_SPI_DMA_TX_STADR(n) (n)
/***** DMA Rx LEN(for SPI) Register *****/
/*! Set DMA Rx length(12bit)
*/
#define LL_SPI_DMA_RX_LEN(n) (n)
/***** DMA Rx CNT(for SPI) Register *****/
/*! The length of the byte of the received data(12bit)
*/
#define LL_SPI_DMA_RX_CNT(n) (n)
/***** DMA Rx STADR(for SPI) Register *****/
/*! DMA Rx start address(13bit)
*/
#define LL_SPI_DMA_RX_STADR(n) (n)
/***** STA(for SPI) Register *****/
#define LL_SPI_STA_CLR_BUF_CNT (1UL << 31)
#define LL_SPI_STA_HSYNC_PEND (1UL << 21)
#define LL_SPI_STA_VSYNC_PEND (1UL << 20)
#define LL_SPI_STA_DMA_PPBUF_SEL (1UL << 19)
#define LL_SPI_STA_RX_TIMEOUT_PEND (1UL << 18)
#define LL_SPI_STA_MODF (1UL << 17)
/*! SPI Slave wrong cmd pending
*/
#define LL_SPI_STA_SLAVE_WRONG_CMD_PENDING (1UL << 16)
/*! SPI Slave wiremode change pending
*/
#define LL_SPI_STA_SLAVE_WIREMODE_CFG_PENDING (1UL << 15)
/*! SPI Slave read status pending
*/
#define LL_SPI_STA_SLAVE_RDSTATUS_PENDING (1UL << 14)
/*! SPI Slave read data pending
*/
#define LL_SPI_STA_SLAVE_RDDATA_PENDING (1UL << 13)
/*! SPI Slave write data pending
*/
#define LL_SPI_STA_SLAVE_WRDATA_PENDING (1UL << 12)
/*! Clear fifo
*/
#define LL_SPI_STA_CLEAR_BUF_CNT (1UL << 9)
/*! Get how many bytes of valid data in the FIFO
*/
#define LL_SPI_STA_BUF_CNT(n) (((n)>>9) & 0x07)
/*! SPI master receive data busy pending
*/
#define LL_SPI_STA_MASTER_RX_BUSY_PENDING (1UL << 8)
/*! The SPI slave gets the CS pin state
*/
#define LL_SPI_STA_SLAVE_CS_STATE (1UL << 7)
/*! SPI module busy pending
*/
#define LL_SPI_STA_SSP_BUSY_PENDING (1UL << 6)
/*! SPI slave CS(NSS) rising edge detected pending
*/
#define LL_SPI_STA_NSS_POS_PENDING (1UL << 5)
/*! SPI DMA done pending
*/
#define LL_SPI_STA_DMA_PENDING (1UL << 4)
/*! SPI FIFO overflow pending
*/
#define LL_SPI_STA_BUF_OV_PENDING (1UL << 3)
/*! SPI FIFO empty pending
*/
#define LL_SPI_STA_BUF_EMPTY_PENDING (1UL << 2)
/*! SPI FIFO full pending
*/
#define LL_SPI_STA_BUF_FULL_PENDING (1UL << 1)
/*! SPI transfers one frame done pending
*/
#define LL_SPI_STA_DONE_PENDING (1UL << 0)
/***** RBUF(for SPI) Register *****/
#define LL_SPI_RBUF(n) ((n) & 0xFF)
/***** RX_TIMEOUTCON(for SPI) Register *****/
#define LL_SPI_RX_TIMEOUTCON(n) ((n&0x1FFFFFFF)<<1)
#define LL_SPI_RX_TIMEOUT_EN(n) ((n&0x1)<<0)
/***** RSTADR1(for SPI) Register *****/
#define LL_SPI_RSTADR1(n) (n)
/***** VSYNV_TCON(for SPI) Register *****/
#define LL_SPI_VSYNV_TCON_VSYNC_TIME(n) ((n&0x1FFFFF)<<8)
#define LL_SPI_VSYNV_TCON_VSYNC_MASK_CNT(n) ((n&0x3F)<<1)
#define LL_SPI_VSYNV_TCON_VHSYNC_DETEN(n) ((n&0x01)<<0)
/***** HSYNV_TCON(for SPI) Register *****/
#define LL_SPI_HSYNV_TCON_HSYNC_TIME(n) ((n&0xFFFF)<<8)
#define LL_SPI_HSYNV_TCON_HSYNC_MASK_CNT(n) ((n&0x3F)<<0)
/***** SLAVESTA(for SPI) Register *****/
#define LL_SPI_SLAVE_STA_TX_LEN(n) (((n)&0xFF) << 16)
#define LL_SPI_SLAVE_STA_RX_LEN(n) (((n)&0xFF) << 8)
#define LL_SPI_SLAVE_STA_RX_READY_EN (1UL << 7)
#define LL_SPI_SLAVE_STA_TX_READY_EN (1UL << 6)
#define LL_SPI_SLAVE_STA_SW_RESERVED (1UL << 5)
#define LL_SPI_SLAVE_STA_WRONG_COMMAND (1UL << 4)
#define LL_SPI_SLAVE_STA_DATA_TOGGLE (1UL << 3)
#define LL_SPI_SLAVE_STA_TX_OVERFLOW (1UL << 2)
#define LL_SPI_SLAVE_STA_RX_READY_FLG (1UL << 1)
#define LL_SPI_SLAVE_STA_TX_READY_FLG (1UL << 0)
/** @brief SPI register structure
* @{
*/
struct hgspi_v3_hw {
__IO uint32_t CON0;
__IO uint32_t CON1;
__IO uint32_t CMD_DATA;
__IO uint32_t TIMECON;
__IO uint32_t TDMALEN;
__IO uint32_t RDMALEN;
__IO uint32_t TDMACNT;
__IO uint32_t RDMACNT;
__IO uint32_t TSTADR;
__IO uint32_t RSTADR;
__IO uint32_t STA1;
__IO uint32_t STA2;
__IO uint32_t SLAVESTA;
__IO uint32_t OWNADRCON;
__IO uint32_t RBUF;
__IO uint32_t TIMEOUTCON;
__IO uint32_t RXTIMEOUTCON;
__IO uint32_t RSTADR1;
__IO uint32_t VSYNC_TCON;
__IO uint32_t HSYNC_TCON;
__IO uint32_t LINE_LEN;
};
#ifdef __cplusplus
}
#endif
#endif /* _HGSPI_V3_HW_H_ */