Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
401
sdk/chip/txw82x/system0.c
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401
sdk/chip/txw82x/system0.c
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#include "basic_include.h"
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#include "csi_config.h"
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#include "soc.h"
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#include "csi_core.h"
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#include "csi_kernel.h"
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#include "sys_config.h"
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#include "dev/dma/hg_m2m_dma.h"
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#include "lib/ota/al_typedef.h"
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#ifdef CONFIG_SLEEP
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#include "lib/common/dsleepdata.h"
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#endif
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#include "cpu1_mem.h"
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#include "dev/xspi/hg_xspi_psram.h"
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#include "dev/xspi/hg_xspi_flash.h"
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#include "dev/adc/hgadc_v1.h"
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#include "hal/adc.h"
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extern int main(void);
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extern int32 dev_init(void);
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extern void device_init(void);
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extern int psram_auto_init(int extern_pt, uint32_t clk);
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extern void psram_info(int isready);
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void pmu_watchdog_init(void);
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extern uint32_t g_intstackbase;
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extern uint32_t g_top_irqstack;
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extern uint32_t __heap_start;
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extern uint32_t __heap_end;
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extern uint32_t __psram_heap_start;
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extern uint32_t __psram_heap_end;
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extern unsigned int __al_user_sram_start;
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extern struct os_workqueue main_wkq;
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extern uint8_t assert_holdup;
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extern uint32 psram_rsv_addr;
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uint32 srampool_start = 0;
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uint32 srampool_end = 0;
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uint32 psrampool_start = 0;
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uint32 psrampool_end = 0;
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uint32 __sp_save[3];
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#ifndef SYS_FACTORY_PARAM_SIZE
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#define SYS_FACTORY_PARAM_SIZE 20
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#endif
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//生成func_code=1的参数
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#define FUNCCODE1_HEAD(fun_num,size) (((size) << 8) | ((fun_num)))
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#define FUN_NUM (1) //func_code=1的参数
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#define FUN_NUM_1_SIZE (2+16) //2是保留的2byte,16分别是iocfg、eqcfg、ispcfg, psramcfg
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#ifdef PIN_FROM_PARAM
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const uint16_t __used iocfg_psram[IOCFG_SIZE / 2] = {IOCFG_SIZE};
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#else
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#endif
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#define PARAM_HEAD(size,head) (SYS_FACTORY_PARAM_SIZE|head<<16)
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__initconst const uint16_t __used isp_param[4096 / 2] = {4096, 0};
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__initconst const uint16_t __used eq_param[1024 / 2] = {1024};
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__initconst const uint16_t __used psram_param[4096 / 2] = {4096, 0};
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const uint32_t __used sys_factory_param[SYS_FACTORY_PARAM_SIZE / 2] __at_section("SYS_PARAM") =
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{
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PARAM_HEAD(SYS_FACTORY_PARAM_SIZE,0x2B1A),
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FUNCCODE1_HEAD(FUN_NUM,FUN_NUM_1_SIZE),
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(uint32_t)IOCFG_PARAM_ADDR,
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(uint32_t)eq_param,
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(uint32_t)isp_param,
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(uint32_t)psram_param
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};
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/** recommend usage :
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* 1、CSI (CPU separate) cache use for IBUS : SRAM(0x040000000) FLASH(0x10000000) PSRAM(0x08000000)
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* 32kB*2 DBUS : SRAM(0x200000000) FLASH(0x30000000) PSRAM(0x28000000)
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*
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* 2、CLD (AHB share) cache only for DBUS : PSRAM(0x28000000) can share for CPU0 & CPU1
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* 32KB
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*/
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__SYS_INIT void cache_open(void)
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{
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sysctrl_cpu0_ibus_burst_set(CPU_BURST_SIZE_16B);
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sysctrl_cpu0_l2_dcache_en(1);
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sysctrl_cpu1_l2_dcache_en(0);
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cld_cache_disable();
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csi_cache_reset_profile();
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csi_cache_set_range(0, 0, CACHE_CRCR_8M, 0x0);
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csi_cache_set_range(1, 0, CACHE_CRCR_8M, 0x0);
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csi_cache_set_range(2, 0, CACHE_CRCR_8M, 0x0);
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csi_cache_set_range(3, 0, CACHE_CRCR_8M, 0x0);
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if (!IS_SRAM_ADDR((uint32_t) & (__Vectors))) {
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csi_cache_set_range(0, ((uint32_t) & (__Vectors)) & 0xFFF00000, CACHE_CRCR_8M, 0x1);
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}
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csi_cache_enable_profile();
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csi_icache_enable();
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}
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__SYS_INIT void cache_open_psram(void)
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{
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sysctrl_cpu0_dbus_burst_set(CPU_BURST_SIZE_0B);
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sysctrl_cpu0_l2_dcache_en(1);
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if (!cld_cache_is_enable()) {
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sysctrl_force_cld_allocate_en();
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cld_cache_invalidate_all();
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cld_cache_enable();
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cld_cache_enable_profile();
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}
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#if defined(PSRAM_HEAP)
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if (!SYSCTRL_GET_CPU0_L2_DCACHE_EN) {
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sysctrl_cpu0_dbus_burst_set(CPU_BURST_SIZE_16B);
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csi_cache_set_range(3, PSRAM_BASE, CACHE_CRCR_16M, 0x1);
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csi_dcache_enable();
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}
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#endif
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}
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__SYS_INIT void system_clock_init(void)
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{
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if (!sysctrl_cmu_sysclk_set(DEFAULT_SYS_CLK, 1)) {
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while (1);
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}
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}
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__SYS_INIT void system_set_ace_peris(void)
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{
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uint32_t ie = disable_irq();
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#ifndef SINGLE_CORE
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sysctrl_ace_peris_access_cpu0(ACE_USB20|ACE_USB11|ACE_GMAC|ACE_DISPLAY_TOP|ACE_VIDEO_INTF_TOP|ACE_VIDEO_SUBSYS_TOP|ACE_OSPI_CTRL|ACE_QSPI_CTRL|ACE_H264_CODEC_TOP|ACE_IMAGE_ISP_TOP|ACE_VIDEO_GPU_TOP);
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sysctrl_ace_peris_access_cpu1(ACE_BASEBAND1|ACE_BASEBAND|ACE_RFDIGITAL|ACE_RFDIGCAL_TOP);
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sysctrl_ace_peris_access_cpu_all(ACE_MIX_TOP|ACE_GPIO_TOP|ACE_EFUSE_CTRL|ACE_SYS_SEC_TOP|ACE_PMU);
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#else
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sysctrl_ace_peris_access_cpu0(0xFFFFFFFF);
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sysctrl_ace_peris_access_cpu_all(ACE_BASEBAND1|ACE_BASEBAND|ACE_RFDIGITAL|ACE_RFDIGCAL_TOP);
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#endif
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enable_irq(ie);
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}
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#ifndef SINGLE_CORE
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__SYS_INIT void sys_start_cpu1(uint32_t run_addr)
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{
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os_printf(KERN_NOTICE"kick start cpu1 at %p!\n", run_addr);
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CoreSetting->soft_int_pending = 0;
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CoreSetting->print_level = 0;
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CoreSetting->disable_print = 0;
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CoreSetting->dcache_maint_en = CONFI_CORE_DCACHE_MAINT_EN;
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CoreSetting->dbg_uart_dev = CONFI_CORE_UARTDEV;
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CoreSetting->m2m_dma_dev = (HG_M2M_DMA_NUM > 2) ? 0 : 1; // modify HG_M2M_DMA_NUM CORE0 2 or 3 （core1 use DMA2）
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CoreSetting->adc_dev = 0;
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CoreSetting->wdt1_to = 4;
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CoreSetting->wdt1_irq_hdl = 0;
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CoreSetting->cpu_clk = CONFIG_CORE_CPU_CLK;
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CoreSetting->rxbuf_addr = (uint32_t)(CONFIG_CORE_RXBUF_ADDR);
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CoreSetting->rxbuf_size = CONFIG_CORE_RXBUF_SIZE;
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CoreSetting->heap_addr = (uint32_t)(CONFIG_CORE_HEAP_START);
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CoreSetting->heap_size = CONFIG_CORE_HEAP_SIZE;
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CoreSetting->skbpool_addr = (uint32_t)(CONFIG_CORE_SKB_POOL_ADDR);
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CoreSetting->skbpool_size = CONFIG_CORE_SKB_POOL_SIZE;
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CoreSetting->skbpool_flag = 0;
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CoreSetting->soft_int_pending = 0;
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CoreSetting->vif_maxcnt = 2;
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CoreSetting->bss_maxcnt = 16;
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CoreSetting->sta_maxcnt = 2;
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CoreSetting->bss_lifetime = 30;
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CoreSetting->heap_flag = 0;//SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
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#ifdef LMAC_BGN_PCF
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CoreSetting->afh_en = 1;
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#else
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CoreSetting->afh_en = 0;
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#endif
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CoreSetting->afh_chan_mask = 0x00;
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#if defined(PSRAM_HEAP)
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CoreSetting->psram_rsv_addr_core0 = (uint32_t)os_malloc_psram(32);
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#else
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CoreSetting->psram_rsv_addr_core0 = 0;
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#endif
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sysctrl_cpu1_softrst_en();
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__NOP();
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__NOP();
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__NOP();
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__NOP();
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sysctrl_cpu1_softrst_system_en();
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sysctrl_cpu1_softrst_self_dis();
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sysctrl_set_cpu1_pc_rst_addr(run_addr >> 10);
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sysctrl_cpu1_clk_en();
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sysctrl_set_cpu1_jtag_map(CPU1_JTAG_DISABLE);
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sysctrl_cpu1_softrst_dis();
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while(!CoreSetting->cpu1_ready);
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os_printf(KERN_INFO"CPU1 ready!\r\n");
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}
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#endif
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void cld_cache_irq_handler(void *data)
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{
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os_printf("%s %d\r\n",__func__, __LINE__);
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os_printf("CTRL=%08x\r\n", DCACHE_CTRL->CTRL);
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os_printf("MAINT_STATUS=%08x\r\n", DCACHE_CTRL->MAINT_STATUS);
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os_printf("SECIRQSTAT=%08x\r\n", DCACHE_CTRL->SECIRQSTAT);
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os_printf("NSECIRQSTAT=%08x\r\n", DCACHE_CTRL->NSECIRQSTAT);
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__disable_irq();
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while(1);
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}
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int ll_xip_clock_init(int clk_mhz);
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__SYS_INIT void SystemInit(void)
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{
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IC_SIM_START();
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srampool_start = (uint32)&__heap_start;
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srampool_end = (uint32)&__heap_end;
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#if defined(PSRAM_HEAP)
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psrampool_start = (uint32)&__psram_heap_start;
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psrampool_end = (uint32)&__psram_heap_end;
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#endif
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sysctrl_qspi_lock();
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system_set_ace_peris();
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cache_open();
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*((uint32_t *)(&g_intstackbase)) = 0xDEADBEEF;
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__set_VBR((uint32_t) & (__Vectors));
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SYSCTRL_REG_OPT_INIT();
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sys_reset_pending_clr();
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PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(PMU_WDT_LOCK_SIGN)|BIT(PMU_WDT1_LOCK_SIGN)|BIT(PMU_LPWDT_LOCK_SIGN)|BIT(PMU_BOOT_DIRECT_RUN));
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sysctrl_efuse_pwron_init();
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if (sysctrl_get_softreset_pending()) {
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sysctrl_clr_softreset_pending();
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pmu_set_direct_run_pengding2();
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} else {
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pmu_clr_direct_run_pengding2();
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}
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firmware_info_t info_in_fls = (firmware_info_t)&__al_user_sram_start;
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fls_user_data_t user_data = (fls_user_data_t)info_in_fls->user.user_data;
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if (info_in_fls->user.user_data) {
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if (user_data->fw_magic == (0xC791B319)) {
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} else {
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ll_xip_clock_init(0);
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}
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} else {
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ll_xip_clock_init(0);
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}
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sysctrl_cmu_init();
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#ifndef FPGA_SUPPORT
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system_clock_init();
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#endif
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if (DEFAULT_SYS_CLK > (192*1000000) ) {
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void ll_clock_set_apb0_div(uint8 apb0_div);
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ll_clock_set_apb0_div(2);
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}
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//pmu_vdd_core_set(5);
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pmu_vdd_dis();
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#if defined(CONFIG_SEPARATE_IRQ_SP)
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/* 801 not supported */
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__set_Int_SP((uint32_t)&g_top_irqstack);
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__set_CHR(__get_CHR() | CHR_ISE_Msk);
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#endif
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VIC->TSPR = 0xFF;
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/* Clear active and pending IRQ */
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csi_vic_disable_all_irq();
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csi_vic_clear_all_pending_irq();
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csi_vic_clear_all_active();
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/* All peripheral interrupt priority is set to lowest */
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for (uint32 i = 0; i < IRQ_NUM; i++) {
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csi_vic_set_prio(i, 7);
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}
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csi_coret_config(system_clock_get() / CONFIG_SYSTICK_HZ, CORET_IRQn); //1ms
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csi_vic_enable_irq(CORET_IRQn);
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request_irq(LVD_IRQn, lvd_irq_handler, 0);
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irq_enable(LVD_IRQn);
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cld_cache_irq_enable();
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request_irq(EXT_DCACHE_IRQn, cld_cache_irq_handler, 0);
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irq_enable(EXT_DCACHE_IRQn);
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pmu_clr_deadcode_pending();
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}
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__init static void malloc_init(void)
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{
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uint32 flags = 0;
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#ifdef MEM_TRACE
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flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
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#endif
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sram_heap.name = "sram";
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sram_heap.ops = &mmpool1_ops;
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sysheap_init(&sram_heap, (void *)SYS_HEAP_START, SYS_HEAP_SIZE, flags);
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}
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__init static void malloc_psram_init(void)
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{
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#ifdef PSRAM_HEAP
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uint32 flags = SYSHEAP_FLAGS_MEM_ALIGN_32;
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#ifdef MEM_TRACE
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flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
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#endif
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psram_heap.name = "psram";
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psram_heap.ops = &mmpool1_ops;
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sysheap_init(&psram_heap, (void *)SYS_PSRAM_HEAP_START, SYS_PSRAM_HEAP_SIZE, flags);
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#endif
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}
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__init static int system_psram_init(void)
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{
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extern void add_psram_cfg();
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add_psram_cfg();
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// 240M， 320M, 274M, 160M...
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// 你可以选择你喜欢的频率， 但内部只有几个挡位可以选择， 匹配最接近的配置
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int psram_heap_size = psram_auto_init(0, 320 * 1000000);
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cache_open_psram();
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#ifdef PSRAM_HEAP
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if(psram_heap_size){
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psrampool_end = PSRAM_BASE + psram_heap_size*1024*1024;
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malloc_psram_init();
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psram_rsv_addr = (uint32)os_malloc_psram(32);
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}
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if(!psram_heap_size){
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os_printf("psram not ready\n");
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}
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return psram_heap_size;
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#endif
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}
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__init void pre_main(void)
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{
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CoreSetting->cpu1_ready = 0;
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assert_holdup = ASSERT_HOLDUP;
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save_boot_loader_addr();
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malloc_init();
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int psram_size = system_psram_init();
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#ifdef CSKY_OS
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csi_kernel_init();
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#endif
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#ifdef OHOS
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LOS_KernelInit();
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#endif
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dev_init();
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device_init();
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psram_info(psram_size);
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sysctrl_efuse_validity_handle();
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#ifndef SINGLE_CORE
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adc_open((struct adc_device *)dev_get(HG_ADC0_DEVID));
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irq_enable(CPU_DBG_ON_IRQn);
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csi_vic_set_prio(CPU_DBG_ON_IRQn, 1);
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sys_start_cpu1(0x10001000);
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#endif
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#ifdef CONFIG_SLEEP
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sys_sleepcb_init();
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sys_sleepdata_init();
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#endif
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pmu_watchdog_init();
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VERSION_SHOW();
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module_version_show();
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sys_reset_show();
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os_workqueue_init(&main_wkq, "MAIN", OS_TASK_PRIORITY_NORMAL, NULL, 2048);
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mainwkq_monitor_init();
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os_run_func((os_run_func_t)main, 0, 0, 0);
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#ifdef CSKY_OS
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csi_kernel_start();
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#endif
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#ifdef OHOS
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LOS_Start();
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#endif
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}
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