Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
25
sdk/chip/txw82x/TXW82X_FLASH_ALGORITHM.init
Normal file
25
sdk/chip/txw82x/TXW82X_FLASH_ALGORITHM.init
Normal file
@@ -0,0 +1,25 @@
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# watchdog close : WDT->WDTKEY
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set *(unsigned int *)0x400C1004=0xdddd
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set *(unsigned int *)0x400C1014=0xdddd
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set $psr=0x80000000
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# sysctrl writable : SYSCTRL->SYS_KEY
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set *(unsigned int *)0x40020000=0x3fac87e4
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#CPU1 disable
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set *(unsigned int *)0x4002019c=0
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#reset peripherals
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set *(unsigned int *)0x40020008=0x03
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set *(unsigned int *)0x40021300=0x0
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set *(unsigned int *)0x40021308=0x1
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set *(unsigned int*)0x400180b8=0xe8
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set *(unsigned int*)0x400180b4=0xdddd
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set *(unsigned int*)0x400180bc=0xC053781B
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#vpp disable
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set *(unsigned int*)0x40005100=0
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#shell echo "123"
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403
sdk/chip/txw82x/isr.c
Normal file
403
sdk/chip/txw82x/isr.c
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@@ -0,0 +1,403 @@
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/******************************************************************************
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* @file isr.c
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* @brief source file for the interrupt server route
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include "sys_config.h"
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#include "typesdef.h"
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#include <csi_kernel.h>
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#include "errno.h"
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#include "osal/irq.h"
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#include "osal/string.h"
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extern void isr_run(void (*hdl)(void *data), void *data);
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extern void ck_usart_irqhandler(int32_t idx);
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extern void dw_timer_irqhandler(int32_t idx);
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extern void dw_gpio_irqhandler(int32_t idx);
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extern void systick_handler(void);
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extern void xPortSysTickHandler(void);
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extern void OSTimeTick(void);
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static struct sys_hwirq sys_irqs[IRQ_NUM];
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#define ATTRIBUTE_ISR __attribute__((isr))
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#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
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#if defined(CSKY_OS)
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void csi_intrpt_exit_do(uint32 irqn)
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{
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csi_kernel_intrpt_exit();
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uint32_t in_disable_irq(void);
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if (in_disable_irq()) {
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os_printf(KERN_ERR"!!! sys_irq%d disable irq\r\n", irqn);
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enable_irq(0);
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}
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}
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#define CSI_INTRPT_ENTER(irqn) csi_kernel_intrpt_enter()
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#define CSI_INTRPT_EXIT(irqn) csi_intrpt_exit_do(irqn)
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#else
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#define CSI_INTRPT_ENTER(irqn)
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#define CSI_INTRPT_EXIT(irqn)
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#endif
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#ifdef SYS_IRQ_STAT
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#define SYS_IRQ_STATE_ST(irqn) uint32 _t1_, _t2_; _t1_ = csi_coret_get_value();
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#define SYS_IRQ_STATE_END(irqn) do{ \
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_t2_ = csi_coret_get_value();\
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_t1_ = ((_t1_>_t2_)?(_t1_-_t2_):(csi_coret_get_load()-_t2_+_t1_));\
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sys_irqs[irqn].tot_cycle += _t1_;\
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sys_irqs[irqn].trig_cnt++;\
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if (_t1_ > sys_irqs[irqn].max) {\
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sys_irqs[irqn].max = _t1_;\
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}\
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if (_t1_ < sys_irqs[irqn].min || sys_irqs[irqn].min == 0) {\
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sys_irqs[irqn].min = _t1_;\
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}\
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}while(0)
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#else
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#define SYS_IRQ_STATE_ST(irqn)
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#define SYS_IRQ_STATE_END(irqn)
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#endif
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void irq_enable(uint32 irq)
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{
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csi_vic_enable_irq(irq);
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}
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void irq_disable(uint32 irq)
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{
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csi_vic_disable_irq(irq);
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}
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uint32 disable_irq(void)
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{
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return __disable_irq();
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}
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void irq_priority(uint32 irq, uint32 prio)
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{
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csi_vic_set_prio(irq, prio);
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}
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void enable_irq(uint32 flags)
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{
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if (!flags) {
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__enable_irq();
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}
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}
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uint32_t in_disable_irq(void)
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{
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return __in_disable_irq(__get_PSR());
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}
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#define SYSTEM_ISR_HANDLE_FUNC(func_name,irqn)\
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ATTRIBUTE_ISR void func_name(void)\
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{\
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CSI_INTRPT_ENTER(irqn);\
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isr_run(sys_irqs[irqn].handle, sys_irqs[irqn].data);\
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CSI_INTRPT_EXIT(irqn);\
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}
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#define SYSTEM_IRQ_HANDLE_FUNC(func_name,irqn)\
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ATTRIBUTE_ISR void func_name(void)\
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{\
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CSI_INTRPT_ENTER(irqn);\
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SYS_IRQ_STATE_ST(irqn);\
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if (sys_irqs[irqn].handle) {\
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sys_irqs[irqn].handle(sys_irqs[irqn].data);\
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}\
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SYS_IRQ_STATE_END(irqn);\
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CSI_INTRPT_EXIT(irqn);\
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}
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int32 request_irq(uint32 irq_num, irq_handle handle, void *data)
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{
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if (irq_num < IRQ_NUM) {
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sys_irqs[irq_num].data = data;
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sys_irqs[irq_num].handle = handle;
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return RET_OK;
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} else {
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return -EINVAL;
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}
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}
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int32 release_irq(uint32 irq_num)
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{
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if (irq_num < IRQ_NUM) {
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irq_disable(irq_num);
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sys_irqs[irq_num].handle = NULL;
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sys_irqs[irq_num].data = NULL;
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return RET_OK;
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} else {
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return -EINVAL;
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}
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}
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uint32 sysirq_time(void)
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{
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uint32 irq_time = 0;
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#ifdef SYS_IRQ_STAT
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int i;
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uint32_t cnt;
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uint32_t total;
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uint16_t max, min;
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os_printf(KERN_ALERT"SYS IRQ TIME:\r\n");
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for (i = 0; i < IRQ_NUM; i++) {
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if (sys_irqs[i].trig_cnt) {
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cnt = sys_irqs[i].trig_cnt;
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total = sys_irqs[i].tot_cycle / (DEFAULT_SYS_CLK / 1000000); //us
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max = sys_irqs[i].max / (DEFAULT_SYS_CLK / 1000000); //us
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min = sys_irqs[i].min / (DEFAULT_SYS_CLK / 1000000); //us
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irq_time += total; //us
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sys_irqs[i].trig_cnt = 0;
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sys_irqs[i].tot_cycle = 0;
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sys_irqs[i].max = 0;
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sys_irqs[i].min = 0;
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os_printf(KERN_ALERT" IRQ%-2d: trig:%d,\t total:%dus, \t(max:%d, min:%d, avg:%d)\r\n", i, cnt, total, max, min, total/cnt);
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}
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}
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#endif
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return irq_time;
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}
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__ram ATTRIBUTE_ISR void CPU_SOFT_INT_IRQHandler(void)
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{
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/* only use for CPU1 */
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CSI_INTRPT_ENTER(CPU_SOFT_INT_IRQn);
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SYS_IRQ_STATE_ST(CPU_SOFT_INT_IRQn);
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uint32 flags = disable_irq();
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mcu_watchdog_feed();
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uint32 wdt_feed_time = CoreSetting->cpu_clk/8; // ~0.5s
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uint32 wdt_feed_cnt = CoreSetting->wdt1_to * 4;
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sysctrl_cpu1_kick_cpu0_softint(); //ack
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/* cpu0 critical section : cpu0 cann't lock cpu1 */
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//os_printf(" IRQ 100: trig:%d %d\r\n", SYSCTRL_GET_CPU0_SOFTINT_PENDING, SYSCTRL_GET_CPU1_SOFTINT_PENDING);
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while (CoreSetting->soft_int_pending) {
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wdt_feed_time--;
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if (!wdt_feed_time) {
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if (wdt_feed_cnt) {
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wdt_feed_cnt--;
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mcu_watchdog_feed();
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}
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wdt_feed_time = CoreSetting->cpu_clk/8; // ~0.5s
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}
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}
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sysctrl_cpu1_kick_cpu0_softint();//ack
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enable_irq(flags);
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SYS_IRQ_STATE_END(CPU_SOFT_INT_IRQn);
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CSI_INTRPT_EXIT(CPU_SOFT_INT_IRQn);
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}
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ATTRIBUTE_ISR void CORET_IRQHandler(void)
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{
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CSI_INTRPT_ENTER(CORET_IRQn);
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SYS_IRQ_STATE_ST(CORET_IRQn);
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readl(0xE000E010);
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systick_handler();
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SYS_IRQ_STATE_END(CORET_IRQn);
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CSI_INTRPT_EXIT(CORET_IRQn);
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}
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ATTRIBUTE_ISR void CPU_DBG_ON_IRQHandler(void)
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{
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//BIT0: CPU1 SOFTRESET PENDING , W1C
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CSI_INTRPT_ENTER(CPU_DBG_ON_IRQn);
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SYS_IRQ_STATE_ST(CPU_DBG_ON_IRQn);
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volatile uint32 *dbg = (volatile uint32 *)CPUDBG_BASE;
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uint32_t sys_core1_static(int32 printf_en);
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sys_core1_static(1);
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_os_printf("CPU debug0 ...MB_IRQ_EN=%08x MB_IRQ_STA=%08x\r\n", *(volatile int *)0x80001000, *(volatile int *)0x80001004);
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_os_printf("CPU debug1 ...MB_IRQ_EN=%08x MB_IRQ_STA=%08x\r\n", *(volatile int *)0x80000000, *(volatile int *)0x80000004);
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while (*dbg & (BIT(1) | BIT(2))) {
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// delay_us(2000*100);
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// _os_printf("CPU1 debug ...RD_IRQ_EN=%08x RD_IRQ_STA=%08x\r\n", *(volatile int *)0x80001000, *(volatile int *)0x80001004);
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// _os_printf("CPU0/1_SOFTINT=%08x %08x %08x\r\n", *(volatile uint32 *)(0x80001200), *(volatile uint32 *)(0x80001200), sys_soft_int_cnt, sys_soft_int_wait_cnt);
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}
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SYS_IRQ_STATE_END(CPU_DBG_ON_IRQn);
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CSI_INTRPT_EXIT(CPU_DBG_ON_IRQn);
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}
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//0
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SYSTEM_IRQ_HANDLE_FUNC(USB20DMA_IRQHandler, USB20DMA_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(USB20MC_IRQHandler, USB20MC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(UART0_IRQHandler, UART0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(UART1_IRQHandler, UART1_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(LCD_IRQHandler, LCD_IRQn)
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//5
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SYSTEM_IRQ_HANDLE_FUNC(QSPI_IRQHandler, QSPI_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SPI0_IRQHandler, SPI0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SPI1_IRQHandler, SPI1_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SPI2_IRQHandler, SPI2_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(OSPI_IRQHandler, OSPI_IRQn)
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//10
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SYSTEM_IRQ_HANDLE_FUNC(TIM0_IRQHandler, TIM0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(TIM1_IRQHandler, TIM1_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(TIM2_IRQHandler, TIM2_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(TIM3_IRQHandler, TIM3_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SCALE1_IRQHandler, SCALE1_IRQn)
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//15
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//SYSTEM_IRQ_HANDLE_FUNC(AUDIO_VAD_HS_ALAW_IRQHandler, AUDIO_SUBSYS2_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(AUDIO_ADC_IRQHandler, AUDIO_SUBSYS1_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(AUDIO_DAC_IRQHandler, AUDIO_SUBSYS0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SDIO_IRQHandler, SDIO_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SDHOST1_IRQHandler, SDHOST1_IRQn)
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//20
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SYSTEM_IRQ_HANDLE_FUNC(SDHOST_IRQHandler, SDHOST_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(LMAC_IRQHandler, LMAC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(GMAC_IRQHandler, GMAC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(DUAL_ORG_IRQHandler, DUAL_ORG_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(GEN422_IRQHandler, GEN422_IRQn)
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//25
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//SYSTEM_IRQ_HANDLE_FUNC(CORET_IRQHandler, CORET_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SHA_IRQHandler, SHA_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(CRC_IRQHandler, CRC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(ADKEY0_IRQHandler, ADKEY0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(PD_TMR_IRQHandler, PD_TMR_IRQn)
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//30
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SYSTEM_IRQ_HANDLE_FUNC(WKPND_IRQHandler, WKPND_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(PDWKPND_IRQHandler, PDWKPND_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(LVD_IRQHandler, LVD_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(WDT_IRQHandler, WDT_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SYS_ERR_IRQHandler, SYS_ERR_IRQn)
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//35
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SYSTEM_IRQ_HANDLE_FUNC(IIS0_IRQHandler, IIS0_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(IIS1_IRQHandler, IIS1_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(GPIOA_IRQHandler, GPIOA_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(LO_MNT_IRQHandler, LO_MNT_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(DVP_IRQHandler, DVP_IRQn)
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//40
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SYSTEM_IRQ_HANDLE_FUNC(MJPEG01_IRQHandler, MJPEG01_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(H264ENC_IRQHandler, H264ENC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(VPP_IRQHandler, VPP_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(PRC_IRQHandler, PRC_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(STMR5_IRQHandler, STMR5_IRQn)
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//45
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SYSTEM_IRQ_HANDLE_FUNC(PDM_IRQHandler, PDM_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(LED_TMR_IRQHandler, LED_TMR_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SCALE2_IRQHandler, SCALE2_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(GFSK_IRQHandler, GFSK_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(CMPOUT0_IRQHandler, CMPOUT0_IRQn)
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//50
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SYSTEM_IRQ_HANDLE_FUNC(UART6_IRQHandler, UART6_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(SCALE3_IRQHandler, SCALE3_IRQn)
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SYSTEM_IRQ_HANDLE_FUNC(IMG_ISP_IRQHandler, IMG_ISP_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(MIPI_CSI2_IRQHandler, MIPI_CSI2_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(RF_IRQHandler, RF_IRQn)
|
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|
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|
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//55
|
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SYSTEM_IRQ_HANDLE_FUNC(USB11MC_IRQHandler, USB11_MC_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(USB11DMA_IRQHandler, USB11_DMA_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(RTC_VCCHVD_IRQHandler, RTC_VCCHVD_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(RTC_IRQHandler, RTC_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(MIPI_DSI_IRQHandler, MIPI_DSI_IRQn)
|
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|
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|
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//60
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||||
SYSTEM_IRQ_HANDLE_FUNC(PARA_OUT_IRQHandler, PARA_OUT_IRQn)
|
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SYSTEM_IRQ_HANDLE_FUNC(M2M0_IRQHandler, M2M_DMA0_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CAN_IRQHandler, CAN_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(EXT_DCACHE_IRQHandler, EXT_DCACHE_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CPU_SPINLOCK_IRQHandler, CPU_SPINLOCK_IRQn)
|
||||
|
||||
|
||||
//65
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CPU_BOX_RECV_IRQHandler, CPU_RECV_MAIL_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CPU_BOX_SEND_IRQHandler, CPU_SEND_MAIL_IRQn)
|
||||
//SYSTEM_IRQ_HANDLE_FUNC(CPU_DBG_ON_IRQHandler, CPU_DBG_ON_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(OSPI_FIFO_IRQHandler, OSPI_FIFO_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(OSPI_EFF_IRQHandler, OSPI_EFF_IRQn)
|
||||
|
||||
|
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//70
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GEN420_IRQHandler, GEN420_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(SYS_AES_IRQHandler, SYS_AES_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(PKA_IRQHandler, PKA_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(WDT1_IRQHandler, WDT1_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GPIOB_IRQHandler, GPIOB_IRQn)
|
||||
|
||||
|
||||
//75
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GPIOC_IRQHandler, GPIOC_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GPIOD_IRQHandler, GPIOD_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GPIOE_IRQHandler, GPIOE_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(GPIOF_IRQHandler, GPIOF_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(DVP1_IRQHandler, DVP1_IRQn)
|
||||
|
||||
|
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//80
|
||||
SYSTEM_IRQ_HANDLE_FUNC(PNG_IRQHandler, PNG_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(STMR4_IRQHandler, STMR4_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(STMR3_IRQHandler, STMR3_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(STMR2_IRQHandler, STMR2_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(STMR1_IRQHandler, STMR1_IRQn)
|
||||
|
||||
|
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//85
|
||||
SYSTEM_IRQ_HANDLE_FUNC(STMR0_IRQHandler, STMR0_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CMPOUT1_IRQHandler, CMPOUT1_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(UART5_IRQHandler, UART5_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(UART4_IRQHandler, UART4_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(MIPI1_CSI2_IRQHandler, MIPI1_CSI2_IRQn)
|
||||
|
||||
|
||||
//90
|
||||
SYSTEM_IRQ_HANDLE_FUNC(DMA2D_IRQHandler, DMA2D_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(CSC_IRQHandler, CSC_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(OSD_ENC_IRQHandler, OSD_ENC_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(USB20PHY_IRQHandler, USB20PHY_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(PARA_IN_IRQHandler, PARA_IN_IRQn)
|
||||
|
||||
|
||||
//95
|
||||
SYSTEM_IRQ_HANDLE_FUNC(M2M1_IRQHandler, M2M_DMA1_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(WKUP_IRQHandler, WKUP_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(SAM_IRQHandler, SAM_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(LIN_IRQHandler, LIN_IRQn)
|
||||
SYSTEM_IRQ_HANDLE_FUNC(LIN1_IRQHandler, LIN1_IRQn)
|
||||
|
||||
|
||||
//100
|
||||
//RES: default_handler
|
||||
//RES: default_handler
|
||||
//RES: default_handler
|
||||
//RES: default_handler
|
||||
//RES: default_handler
|
||||
|
||||
|
||||
//105
|
||||
SYSTEM_IRQ_HANDLE_FUNC(M2M2_IRQHandler, M2M_DMA2_IRQn)
|
||||
|
||||
|
||||
1314
sdk/chip/txw82x/pin_function.c
Normal file
1314
sdk/chip/txw82x/pin_function.c
Normal file
File diff suppressed because it is too large
Load Diff
60
sdk/chip/txw82x/rpc0.c
Normal file
60
sdk/chip/txw82x/rpc0.c
Normal file
@@ -0,0 +1,60 @@
|
||||
#include "basic_include.h"
|
||||
#include "lib/common/rbuffer.h"
|
||||
#include "lib/common/sysevt.h"
|
||||
#include "lib/rpc/cpurpc.h"
|
||||
#include "lib/umac/ieee80211.h"
|
||||
#include "lib/lvgl_rotate_rpc/lvgl_rotate_rpc.h"
|
||||
|
||||
extern void *sys_wifi_register(uint32 priv);
|
||||
extern int32 sys_wifi_recv(void *priv, uint8 *data, uint32 len, uint32 flags);
|
||||
extern int32 sys_wifi_event_cb(uint8 ifidx, uint16 evt, uint32 param1, uint32 param2);
|
||||
extern int32 atcmd_recv(uint8 *data, int32 len);
|
||||
extern int32 hci_host_recv(uint32 data, uint32 len);
|
||||
|
||||
static const void *rpc_funcs[CPU0_RPC_FUNCID_NUM] = {
|
||||
NULL,
|
||||
RPC_FUNC_DEF(sys_wifi_register),
|
||||
RPC_FUNC_DEF(sys_wifi_recv),
|
||||
RPC_FUNC_DEF(sys_event_new),
|
||||
RPC_FUNC_DEF(sys_wifi_event_cb),
|
||||
RPC_FUNC_DEF(atcmd_recv),
|
||||
|
||||
//BT
|
||||
RPC_FUNC_DEF(hci_host_recv),
|
||||
|
||||
//lvgl
|
||||
RPC_FUNC_DEF(lvgl_frame_rotate_rpc_sync),
|
||||
};
|
||||
|
||||
const void *cpu_rpc_func(uint32 func_id)
|
||||
{
|
||||
if (func_id < ARRAY_SIZE(rpc_funcs)) {
|
||||
return rpc_funcs[func_id];
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int32 cpu1_run_func(void *func, uint32 p1, uint32 p2, uint32 p3)
|
||||
{
|
||||
uint32 args[] = {(uint32)func, p1, p2, p3};
|
||||
return CPU_RPC_CALL(cpu1_run_func);
|
||||
}
|
||||
|
||||
void *cpu1_new_task(const char * name, os_task_func_t func, void * arg, uint32 prio, uint32 time, void * stack, uint32 stack_size)
|
||||
{
|
||||
uint32 args[] = {(uint32)name, (uint32)func, (uint32)arg, (uint32)prio, (uint32)time, (uint32)stack, stack_size};
|
||||
return (void*)(CPU_RPC_CALL(cpu1_new_task));
|
||||
}
|
||||
|
||||
int32 lmac_ioctl(void * lops, uint32 cmd, uint32 param1, uint32 param2)
|
||||
{
|
||||
uint32 args[] = {(uint32)lops, cmd, param1, param2};
|
||||
return CPU_RPC_CALL(lmac_ioctl_rpc);
|
||||
}
|
||||
|
||||
int32 cpu1_atcmd_recv(char *data, uint32 len)
|
||||
{
|
||||
uint32 args[] = {(uint32)data, len};
|
||||
return CPU_RPC_CALL(cpu1_atcmd_recv);
|
||||
}
|
||||
|
||||
401
sdk/chip/txw82x/system0.c
Normal file
401
sdk/chip/txw82x/system0.c
Normal file
@@ -0,0 +1,401 @@
|
||||
#include "basic_include.h"
|
||||
#include "csi_config.h"
|
||||
#include "soc.h"
|
||||
#include "csi_core.h"
|
||||
#include "csi_kernel.h"
|
||||
#include "sys_config.h"
|
||||
#include "dev/dma/hg_m2m_dma.h"
|
||||
#include "lib/ota/al_typedef.h"
|
||||
#ifdef CONFIG_SLEEP
|
||||
#include "lib/common/dsleepdata.h"
|
||||
#endif
|
||||
#include "cpu1_mem.h"
|
||||
#include "dev/xspi/hg_xspi_psram.h"
|
||||
#include "dev/xspi/hg_xspi_flash.h"
|
||||
#include "dev/adc/hgadc_v1.h"
|
||||
#include "hal/adc.h"
|
||||
|
||||
extern int main(void);
|
||||
extern int32 dev_init(void);
|
||||
extern void device_init(void);
|
||||
extern int psram_auto_init(int extern_pt, uint32_t clk);
|
||||
extern void psram_info(int isready);
|
||||
void pmu_watchdog_init(void);
|
||||
|
||||
extern uint32_t g_intstackbase;
|
||||
extern uint32_t g_top_irqstack;
|
||||
extern uint32_t __heap_start;
|
||||
extern uint32_t __heap_end;
|
||||
extern uint32_t __psram_heap_start;
|
||||
extern uint32_t __psram_heap_end;
|
||||
extern unsigned int __al_user_sram_start;
|
||||
extern struct os_workqueue main_wkq;
|
||||
extern uint8_t assert_holdup;
|
||||
extern uint32 psram_rsv_addr;
|
||||
|
||||
uint32 srampool_start = 0;
|
||||
uint32 srampool_end = 0;
|
||||
uint32 psrampool_start = 0;
|
||||
uint32 psrampool_end = 0;
|
||||
uint32 __sp_save[3];
|
||||
|
||||
|
||||
#ifndef SYS_FACTORY_PARAM_SIZE
|
||||
#define SYS_FACTORY_PARAM_SIZE 20
|
||||
#endif
|
||||
|
||||
//生成func_code=1的参数
|
||||
#define FUNCCODE1_HEAD(fun_num,size) (((size) << 8) | ((fun_num)))
|
||||
#define FUN_NUM (1) //func_code=1的参数
|
||||
#define FUN_NUM_1_SIZE (2+16) //2是保留的2byte,16分别是iocfg、eqcfg、ispcfg, psramcfg
|
||||
|
||||
|
||||
#ifdef PIN_FROM_PARAM
|
||||
const uint16_t __used iocfg_psram[IOCFG_SIZE / 2] = {IOCFG_SIZE};
|
||||
#else
|
||||
#endif
|
||||
|
||||
#define PARAM_HEAD(size,head) (SYS_FACTORY_PARAM_SIZE|head<<16)
|
||||
|
||||
__initconst const uint16_t __used isp_param[4096 / 2] = {4096, 0};
|
||||
__initconst const uint16_t __used eq_param[1024 / 2] = {1024};
|
||||
__initconst const uint16_t __used psram_param[4096 / 2] = {4096, 0};
|
||||
|
||||
const uint32_t __used sys_factory_param[SYS_FACTORY_PARAM_SIZE / 2] __at_section("SYS_PARAM") =
|
||||
{
|
||||
PARAM_HEAD(SYS_FACTORY_PARAM_SIZE,0x2B1A),
|
||||
FUNCCODE1_HEAD(FUN_NUM,FUN_NUM_1_SIZE),
|
||||
(uint32_t)IOCFG_PARAM_ADDR,
|
||||
(uint32_t)eq_param,
|
||||
(uint32_t)isp_param,
|
||||
(uint32_t)psram_param
|
||||
};
|
||||
|
||||
|
||||
/** recommend usage :
|
||||
* 1、CSI (CPU separate) cache use for IBUS : SRAM(0x040000000) FLASH(0x10000000) PSRAM(0x08000000)
|
||||
* 32kB*2 DBUS : SRAM(0x200000000) FLASH(0x30000000) PSRAM(0x28000000)
|
||||
*
|
||||
* 2、CLD (AHB share) cache only for DBUS : PSRAM(0x28000000) can share for CPU0 & CPU1
|
||||
* 32KB
|
||||
*/
|
||||
__SYS_INIT void cache_open(void)
|
||||
{
|
||||
sysctrl_cpu0_ibus_burst_set(CPU_BURST_SIZE_16B);
|
||||
|
||||
sysctrl_cpu0_l2_dcache_en(1);
|
||||
sysctrl_cpu1_l2_dcache_en(0);
|
||||
cld_cache_disable();
|
||||
|
||||
csi_cache_reset_profile();
|
||||
csi_cache_set_range(0, 0, CACHE_CRCR_8M, 0x0);
|
||||
csi_cache_set_range(1, 0, CACHE_CRCR_8M, 0x0);
|
||||
csi_cache_set_range(2, 0, CACHE_CRCR_8M, 0x0);
|
||||
csi_cache_set_range(3, 0, CACHE_CRCR_8M, 0x0);
|
||||
if (!IS_SRAM_ADDR((uint32_t) & (__Vectors))) {
|
||||
csi_cache_set_range(0, ((uint32_t) & (__Vectors)) & 0xFFF00000, CACHE_CRCR_8M, 0x1);
|
||||
}
|
||||
|
||||
csi_cache_enable_profile();
|
||||
csi_icache_enable();
|
||||
}
|
||||
|
||||
__SYS_INIT void cache_open_psram(void)
|
||||
{
|
||||
sysctrl_cpu0_dbus_burst_set(CPU_BURST_SIZE_0B);
|
||||
|
||||
sysctrl_cpu0_l2_dcache_en(1);
|
||||
if (!cld_cache_is_enable()) {
|
||||
sysctrl_force_cld_allocate_en();
|
||||
cld_cache_invalidate_all();
|
||||
cld_cache_enable();
|
||||
cld_cache_enable_profile();
|
||||
}
|
||||
|
||||
#if defined(PSRAM_HEAP)
|
||||
if (!SYSCTRL_GET_CPU0_L2_DCACHE_EN) {
|
||||
sysctrl_cpu0_dbus_burst_set(CPU_BURST_SIZE_16B);
|
||||
csi_cache_set_range(3, PSRAM_BASE, CACHE_CRCR_16M, 0x1);
|
||||
csi_dcache_enable();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
__SYS_INIT void system_clock_init(void)
|
||||
{
|
||||
if (!sysctrl_cmu_sysclk_set(DEFAULT_SYS_CLK, 1)) {
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
__SYS_INIT void system_set_ace_peris(void)
|
||||
{
|
||||
uint32_t ie = disable_irq();
|
||||
#ifndef SINGLE_CORE
|
||||
sysctrl_ace_peris_access_cpu0(ACE_USB20|ACE_USB11|ACE_GMAC|ACE_DISPLAY_TOP|ACE_VIDEO_INTF_TOP|ACE_VIDEO_SUBSYS_TOP|ACE_OSPI_CTRL|ACE_QSPI_CTRL|ACE_H264_CODEC_TOP|ACE_IMAGE_ISP_TOP|ACE_VIDEO_GPU_TOP);
|
||||
sysctrl_ace_peris_access_cpu1(ACE_BASEBAND1|ACE_BASEBAND|ACE_RFDIGITAL|ACE_RFDIGCAL_TOP);
|
||||
sysctrl_ace_peris_access_cpu_all(ACE_MIX_TOP|ACE_GPIO_TOP|ACE_EFUSE_CTRL|ACE_SYS_SEC_TOP|ACE_PMU);
|
||||
#else
|
||||
sysctrl_ace_peris_access_cpu0(0xFFFFFFFF);
|
||||
sysctrl_ace_peris_access_cpu_all(ACE_BASEBAND1|ACE_BASEBAND|ACE_RFDIGITAL|ACE_RFDIGCAL_TOP);
|
||||
#endif
|
||||
enable_irq(ie);
|
||||
}
|
||||
|
||||
#ifndef SINGLE_CORE
|
||||
__SYS_INIT void sys_start_cpu1(uint32_t run_addr)
|
||||
{
|
||||
os_printf(KERN_NOTICE"kick start cpu1 at %p!\n", run_addr);
|
||||
|
||||
CoreSetting->soft_int_pending = 0;
|
||||
CoreSetting->print_level = 0;
|
||||
CoreSetting->disable_print = 0;
|
||||
CoreSetting->dcache_maint_en = CONFI_CORE_DCACHE_MAINT_EN;
|
||||
CoreSetting->dbg_uart_dev = CONFI_CORE_UARTDEV;
|
||||
CoreSetting->m2m_dma_dev = (HG_M2M_DMA_NUM > 2) ? 0 : 1; // modify HG_M2M_DMA_NUM CORE0 2 or 3 （core1 use DMA2）
|
||||
CoreSetting->adc_dev = 0;
|
||||
CoreSetting->wdt1_to = 4;
|
||||
CoreSetting->wdt1_irq_hdl = 0;
|
||||
CoreSetting->cpu_clk = CONFIG_CORE_CPU_CLK;
|
||||
CoreSetting->rxbuf_addr = (uint32_t)(CONFIG_CORE_RXBUF_ADDR);
|
||||
CoreSetting->rxbuf_size = CONFIG_CORE_RXBUF_SIZE;
|
||||
CoreSetting->heap_addr = (uint32_t)(CONFIG_CORE_HEAP_START);
|
||||
CoreSetting->heap_size = CONFIG_CORE_HEAP_SIZE;
|
||||
CoreSetting->skbpool_addr = (uint32_t)(CONFIG_CORE_SKB_POOL_ADDR);
|
||||
CoreSetting->skbpool_size = CONFIG_CORE_SKB_POOL_SIZE;
|
||||
CoreSetting->skbpool_flag = 0;
|
||||
CoreSetting->soft_int_pending = 0;
|
||||
CoreSetting->vif_maxcnt = 2;
|
||||
CoreSetting->bss_maxcnt = 16;
|
||||
CoreSetting->sta_maxcnt = 2;
|
||||
CoreSetting->bss_lifetime = 30;
|
||||
CoreSetting->heap_flag = 0;//SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
|
||||
#ifdef LMAC_BGN_PCF
|
||||
CoreSetting->afh_en = 1;
|
||||
#else
|
||||
CoreSetting->afh_en = 0;
|
||||
#endif
|
||||
CoreSetting->afh_chan_mask = 0x00;
|
||||
#if defined(PSRAM_HEAP)
|
||||
CoreSetting->psram_rsv_addr_core0 = (uint32_t)os_malloc_psram(32);
|
||||
#else
|
||||
CoreSetting->psram_rsv_addr_core0 = 0;
|
||||
#endif
|
||||
sysctrl_cpu1_softrst_en();
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
sysctrl_cpu1_softrst_system_en();
|
||||
sysctrl_cpu1_softrst_self_dis();
|
||||
sysctrl_set_cpu1_pc_rst_addr(run_addr >> 10);
|
||||
sysctrl_cpu1_clk_en();
|
||||
sysctrl_set_cpu1_jtag_map(CPU1_JTAG_DISABLE);
|
||||
sysctrl_cpu1_softrst_dis();
|
||||
while(!CoreSetting->cpu1_ready);
|
||||
os_printf(KERN_INFO"CPU1 ready!\r\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
void cld_cache_irq_handler(void *data)
|
||||
{
|
||||
os_printf("%s %d\r\n",__func__, __LINE__);
|
||||
os_printf("CTRL=%08x\r\n", DCACHE_CTRL->CTRL);
|
||||
os_printf("MAINT_STATUS=%08x\r\n", DCACHE_CTRL->MAINT_STATUS);
|
||||
os_printf("SECIRQSTAT=%08x\r\n", DCACHE_CTRL->SECIRQSTAT);
|
||||
os_printf("NSECIRQSTAT=%08x\r\n", DCACHE_CTRL->NSECIRQSTAT);
|
||||
__disable_irq();
|
||||
while(1);
|
||||
}
|
||||
|
||||
int ll_xip_clock_init(int clk_mhz);
|
||||
__SYS_INIT void SystemInit(void)
|
||||
{
|
||||
IC_SIM_START();
|
||||
|
||||
srampool_start = (uint32)&__heap_start;
|
||||
srampool_end = (uint32)&__heap_end;
|
||||
#if defined(PSRAM_HEAP)
|
||||
psrampool_start = (uint32)&__psram_heap_start;
|
||||
psrampool_end = (uint32)&__psram_heap_end;
|
||||
#endif
|
||||
|
||||
sysctrl_qspi_lock();
|
||||
|
||||
system_set_ace_peris();
|
||||
cache_open();
|
||||
|
||||
*((uint32_t *)(&g_intstackbase)) = 0xDEADBEEF;
|
||||
__set_VBR((uint32_t) & (__Vectors));
|
||||
|
||||
SYSCTRL_REG_OPT_INIT();
|
||||
sys_reset_pending_clr();
|
||||
|
||||
PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(PMU_WDT_LOCK_SIGN)|BIT(PMU_WDT1_LOCK_SIGN)|BIT(PMU_LPWDT_LOCK_SIGN)|BIT(PMU_BOOT_DIRECT_RUN));
|
||||
sysctrl_efuse_pwron_init();
|
||||
|
||||
if (sysctrl_get_softreset_pending()) {
|
||||
sysctrl_clr_softreset_pending();
|
||||
pmu_set_direct_run_pengding2();
|
||||
} else {
|
||||
pmu_clr_direct_run_pengding2();
|
||||
}
|
||||
|
||||
firmware_info_t info_in_fls = (firmware_info_t)&__al_user_sram_start;
|
||||
fls_user_data_t user_data = (fls_user_data_t)info_in_fls->user.user_data;
|
||||
if (info_in_fls->user.user_data) {
|
||||
if (user_data->fw_magic == (0xC791B319)) {
|
||||
|
||||
} else {
|
||||
ll_xip_clock_init(0);
|
||||
}
|
||||
} else {
|
||||
ll_xip_clock_init(0);
|
||||
}
|
||||
|
||||
sysctrl_cmu_init();
|
||||
|
||||
#ifndef FPGA_SUPPORT
|
||||
system_clock_init();
|
||||
#endif
|
||||
if (DEFAULT_SYS_CLK > (192*1000000) ) {
|
||||
void ll_clock_set_apb0_div(uint8 apb0_div);
|
||||
ll_clock_set_apb0_div(2);
|
||||
}
|
||||
|
||||
//pmu_vdd_core_set(5);
|
||||
pmu_vdd_dis();
|
||||
|
||||
#if defined(CONFIG_SEPARATE_IRQ_SP)
|
||||
/* 801 not supported */
|
||||
__set_Int_SP((uint32_t)&g_top_irqstack);
|
||||
__set_CHR(__get_CHR() | CHR_ISE_Msk);
|
||||
#endif
|
||||
|
||||
VIC->TSPR = 0xFF;
|
||||
/* Clear active and pending IRQ */
|
||||
csi_vic_disable_all_irq();
|
||||
csi_vic_clear_all_pending_irq();
|
||||
csi_vic_clear_all_active();
|
||||
|
||||
/* All peripheral interrupt priority is set to lowest */
|
||||
for (uint32 i = 0; i < IRQ_NUM; i++) {
|
||||
csi_vic_set_prio(i, 7);
|
||||
}
|
||||
|
||||
csi_coret_config(system_clock_get() / CONFIG_SYSTICK_HZ, CORET_IRQn); //1ms
|
||||
csi_vic_enable_irq(CORET_IRQn);
|
||||
request_irq(LVD_IRQn, lvd_irq_handler, 0);
|
||||
irq_enable(LVD_IRQn);
|
||||
|
||||
cld_cache_irq_enable();
|
||||
request_irq(EXT_DCACHE_IRQn, cld_cache_irq_handler, 0);
|
||||
irq_enable(EXT_DCACHE_IRQn);
|
||||
|
||||
pmu_clr_deadcode_pending();
|
||||
}
|
||||
|
||||
__init static void malloc_init(void)
|
||||
{
|
||||
uint32 flags = 0;
|
||||
#ifdef MEM_TRACE
|
||||
flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
|
||||
#endif
|
||||
sram_heap.name = "sram";
|
||||
sram_heap.ops = &mmpool1_ops;
|
||||
sysheap_init(&sram_heap, (void *)SYS_HEAP_START, SYS_HEAP_SIZE, flags);
|
||||
}
|
||||
|
||||
__init static void malloc_psram_init(void)
|
||||
{
|
||||
#ifdef PSRAM_HEAP
|
||||
uint32 flags = SYSHEAP_FLAGS_MEM_ALIGN_32;
|
||||
#ifdef MEM_TRACE
|
||||
flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
|
||||
#endif
|
||||
psram_heap.name = "psram";
|
||||
psram_heap.ops = &mmpool1_ops;
|
||||
sysheap_init(&psram_heap, (void *)SYS_PSRAM_HEAP_START, SYS_PSRAM_HEAP_SIZE, flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
__init static int system_psram_init(void)
|
||||
{
|
||||
extern void add_psram_cfg();
|
||||
add_psram_cfg();
|
||||
|
||||
// 240M， 320M, 274M, 160M...
|
||||
// 你可以选择你喜欢的频率， 但内部只有几个挡位可以选择， 匹配最接近的配置
|
||||
int psram_heap_size = psram_auto_init(0, 320 * 1000000);
|
||||
cache_open_psram();
|
||||
|
||||
#ifdef PSRAM_HEAP
|
||||
if(psram_heap_size){
|
||||
psrampool_end = PSRAM_BASE + psram_heap_size*1024*1024;
|
||||
malloc_psram_init();
|
||||
psram_rsv_addr = (uint32)os_malloc_psram(32);
|
||||
}
|
||||
|
||||
if(!psram_heap_size){
|
||||
os_printf("psram not ready\n");
|
||||
}
|
||||
return psram_heap_size;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
__init void pre_main(void)
|
||||
{
|
||||
CoreSetting->cpu1_ready = 0;
|
||||
assert_holdup = ASSERT_HOLDUP;
|
||||
|
||||
save_boot_loader_addr();
|
||||
malloc_init();
|
||||
|
||||
int psram_size = system_psram_init();
|
||||
|
||||
#ifdef CSKY_OS
|
||||
csi_kernel_init();
|
||||
#endif
|
||||
#ifdef OHOS
|
||||
LOS_KernelInit();
|
||||
#endif
|
||||
|
||||
dev_init();
|
||||
device_init();
|
||||
|
||||
psram_info(psram_size);
|
||||
|
||||
sysctrl_efuse_validity_handle();
|
||||
|
||||
#ifndef SINGLE_CORE
|
||||
adc_open((struct adc_device *)dev_get(HG_ADC0_DEVID));
|
||||
irq_enable(CPU_DBG_ON_IRQn);
|
||||
csi_vic_set_prio(CPU_DBG_ON_IRQn, 1);
|
||||
sys_start_cpu1(0x10001000);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SLEEP
|
||||
sys_sleepcb_init();
|
||||
sys_sleepdata_init();
|
||||
#endif
|
||||
pmu_watchdog_init();
|
||||
|
||||
VERSION_SHOW();
|
||||
module_version_show();
|
||||
sys_reset_show();
|
||||
os_workqueue_init(&main_wkq, "MAIN", OS_TASK_PRIORITY_NORMAL, NULL, 2048);
|
||||
mainwkq_monitor_init();
|
||||
os_run_func((os_run_func_t)main, 0, 0, 0);
|
||||
|
||||
#ifdef CSKY_OS
|
||||
csi_kernel_start();
|
||||
#endif
|
||||
#ifdef OHOS
|
||||
LOS_Start();
|
||||
#endif
|
||||
}
|
||||
|
||||
95
sdk/chip/txw82x/ticker_api.c
Normal file
95
sdk/chip/txw82x/ticker_api.c
Normal file
@@ -0,0 +1,95 @@
|
||||
#include "sys_config.h"
|
||||
#include "tx_platform.h"
|
||||
#ifdef TXW80X
|
||||
#include "txw80x/ticker.h"
|
||||
#endif
|
||||
|
||||
#ifdef TXW81X
|
||||
#include "txw83x/ticker.h"
|
||||
#endif
|
||||
#include "osal/irq.h"
|
||||
#include "list.h"
|
||||
#include "dev.h"
|
||||
|
||||
#if 0
|
||||
#define SIMPLE_TIMER0(offset) (*((uint32 *)(0x40015B00 + offset)))
|
||||
|
||||
/**
|
||||
* @brief The tick timer is initialized.
|
||||
* @param None
|
||||
* @retval None
|
||||
* @note Use the lowest priority interrupt.
|
||||
*/
|
||||
void hw_timer_init(void)
|
||||
{
|
||||
//STMR0_CTL
|
||||
SIMPLE_TIMER0(0x00) = (4 << 8) | (7 << 0);
|
||||
//STMR0_CNT
|
||||
SIMPLE_TIMER0(0x04) = 0;
|
||||
//STMR0_PR
|
||||
SIMPLE_TIMER0(0x04) = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the tick of the timer.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
uint32 hw_timer_get_tick(uint8 start)
|
||||
{
|
||||
uint32 cnt = 0;
|
||||
uint32_t v = sys_get_sysclk()/1000000;
|
||||
|
||||
if(start){
|
||||
__disable_irq();
|
||||
//STMR0_CNT
|
||||
SIMPLE_TIMER0(0x04) = 0;
|
||||
//TMR_EN
|
||||
SIMPLE_TIMER0(0x00) |= (1 << 4);
|
||||
//*(uint32_t *)(HG_GPIOC_BASE+36) |= BIT(7);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}else{
|
||||
__disable_irq();
|
||||
//*(uint32_t *)(HG_GPIOC_BASE+36) &= ~ BIT(7);
|
||||
//TMR_CNT
|
||||
cnt = SIMPLE_TIMER0(0x04);
|
||||
//TMR_EN
|
||||
SIMPLE_TIMER0(0x00) &= ~(1 << 4);
|
||||
__enable_irq();
|
||||
return (16*cnt)/v;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Use the CPU precision delay function
|
||||
* @param n :
|
||||
* @retval None
|
||||
* @note for CK803 : period_count = 3*n+1
|
||||
*/
|
||||
__attribute__((noinline, naked)) void __delay_asm(uint32 n)
|
||||
{
|
||||
__asm__(" \
|
||||
delay_asm_L1: \
|
||||
DECGT32 R0, R0, 1 \n\
|
||||
BT32 delay_asm_L1 \n\
|
||||
rts \n\
|
||||
");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Use the CPU to delay approximately us
|
||||
* @param n : the number of us to delay
|
||||
* @retval None
|
||||
* @note only work for SYS_CLK
|
||||
*/
|
||||
void delay_us(uint32 n)
|
||||
{
|
||||
uint32 temp = sys_get_sysclk()/1000000*n;
|
||||
|
||||
if(temp > 47) {
|
||||
__delay_asm((temp - 47)/3);
|
||||
}
|
||||
}
|
||||
|
||||
102
sdk/chip/txw82x/trap_c.c
Normal file
102
sdk/chip/txw82x/trap_c.c
Normal file
@@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file trap_c.c
|
||||
* @brief source file for the trap process
|
||||
* @version V1.0
|
||||
* @date 12. December 2017
|
||||
******************************************************************************/
|
||||
#include "typesdef.h"
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <csi_config.h>
|
||||
#include <csi_core.h>
|
||||
#include "osal/string.h"
|
||||
#include "osal/task.h"
|
||||
#include <k_api.h>
|
||||
#include <csi_kernel.h>
|
||||
|
||||
extern void csi_kernel_task_dump(k_task_handle_t task_handle, void* stack);
|
||||
extern void hgprintf(const char *fmt, ...);
|
||||
extern void trap_data_dump(void);
|
||||
extern void trap_hdl_run(void);
|
||||
|
||||
#define trap_err(fmt,...) hgprintf(KERN_ERR fmt, ##__VA_ARGS__)
|
||||
|
||||
#if defined(__E804DF__) /* CPU0 */
|
||||
void trap_c(uint32_t *regs)
|
||||
{
|
||||
int i;
|
||||
uint32_t vec = (__get_PSR() & PSR_VEC_Msk) >> PSR_VEC_Pos;
|
||||
|
||||
disable_print(0);
|
||||
print_level(8);
|
||||
trap_err("---------------------------------------------------------------\r\n");
|
||||
trap_err("CPU Exception: NO.%u\r\n", vec);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
trap_err("r%d: %08x\t", i, regs[i]);
|
||||
if ((i % 4) == 3) {
|
||||
trap_err("\n");
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
trap_err("vr%d: %08x\t", i, regs[i + 32]);
|
||||
if ((i % 4) == 3) {
|
||||
trap_err("\n");
|
||||
}
|
||||
}
|
||||
|
||||
trap_err("epsr: %8x\n", regs[48]);
|
||||
trap_err("epc : %8x\n", regs[49]);
|
||||
os_task_dump(os_task_current(), (void* )regs[14]);
|
||||
trap_data_dump();
|
||||
trap_hdl_run();
|
||||
mcu_reset();
|
||||
}
|
||||
|
||||
#else /* CPU0 */
|
||||
void trap_c(uint32_t *regs)
|
||||
{
|
||||
int i;
|
||||
uint32_t vec = (__get_PSR() & PSR_VEC_Msk) >> PSR_VEC_Pos;
|
||||
|
||||
mcu_watchdog_feed();
|
||||
mcu_watchdog_timeout(20);
|
||||
disable_print(0);
|
||||
trap_err("---------------------------------------------------------------\r\n");
|
||||
trap_err("CPU Exception: NO.%u\r\n", vec);
|
||||
for (i = 0; i < 16; i++) {
|
||||
trap_err("r%d: %08x\t", i, regs[i]);
|
||||
if ((i % 4) == 3) {
|
||||
trap_err("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
trap_err("r28 : %08x\r\n", regs[16]);
|
||||
trap_err("epsr: %08x\r\n", regs[17]);
|
||||
trap_err("epc : %08x\r\n", regs[18]);
|
||||
csi_kernel_task_dump((k_task_handle_t)g_active_task[0], (void* )regs[14]);
|
||||
trap_data_dump();
|
||||
trap_hdl_run();
|
||||
mcu_reset();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
224
sdk/chip/txw82x/vectors.S
Normal file
224
sdk/chip/txw82x/vectors.S
Normal file
@@ -0,0 +1,224 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file vectors.S
|
||||
* @brief define default vector handlers. Should use with
|
||||
* GCC for CSKY Embedded Processors
|
||||
* @version V1.0
|
||||
* @date 28. Nove 2017
|
||||
******************************************************************************/
|
||||
|
||||
#include <csi_config.h>
|
||||
|
||||
.import trap_c
|
||||
|
||||
.section .trap_stack
|
||||
.align 2
|
||||
.globl g_trapstackalloc
|
||||
.global g_trapstackbase
|
||||
.global g_top_trapstack
|
||||
g_trapstackalloc:
|
||||
g_trapstackbase:
|
||||
#if defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
|
||||
.space 512
|
||||
#else
|
||||
.space 768
|
||||
#endif
|
||||
g_top_trapstack:
|
||||
|
||||
.text
|
||||
|
||||
/******************************************************************************
|
||||
* Functions:
|
||||
* void trap(void);
|
||||
* default exception handler
|
||||
******************************************************************************/
|
||||
.global trap
|
||||
.type trap, %function
|
||||
trap:
|
||||
psrset ee
|
||||
subi sp, 4
|
||||
stw r0, (sp)
|
||||
|
||||
lrw r0, g_top_trapstack
|
||||
#if defined(__E804DF__) /* CPU0 */
|
||||
subi r0, 200
|
||||
stm r0-r31, (r0)
|
||||
|
||||
ldw r1, (sp)
|
||||
addi sp, 4
|
||||
stw sp, (r0, 56) /* save r14 */
|
||||
mov sp, r0
|
||||
stw r1, (sp) /* save r0 */
|
||||
|
||||
addi r0, 128
|
||||
fstms vr0-vr15, (r0)
|
||||
mov r0, sp
|
||||
|
||||
mfcr r1, epsr
|
||||
stw r1, (sp, 192)
|
||||
mfcr r1, epc
|
||||
stw r1, (sp, 196)
|
||||
#else /* CPU1 */
|
||||
subi r0, 76
|
||||
stm r0-r15, (r0)
|
||||
stw r28, (r0, 64)
|
||||
|
||||
ldw r1, (sp)
|
||||
addi sp, 4
|
||||
stw sp, (r0, 56) /* save r14 */
|
||||
mov sp, r0
|
||||
stw r1, (sp) /* save r0 */
|
||||
|
||||
mfcr r1, epsr
|
||||
stw r1, (sp, 68)
|
||||
mfcr r1, epc
|
||||
stw r1, (sp, 72)
|
||||
#endif
|
||||
|
||||
|
||||
jbsr trap_c
|
||||
|
||||
.align 2
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
br trap
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_weak_handler handler_name Default_Handler_name
|
||||
.weak \handler_name
|
||||
.globl \handler_name
|
||||
.set \handler_name, \Default_Handler_name
|
||||
.endm
|
||||
|
||||
//weak function
|
||||
def_weak_handler USB20DMA_IRQHandler, Default_Handler
|
||||
def_weak_handler USB20MC_IRQHandler, Default_Handler
|
||||
def_weak_handler UART0_IRQHandler, Default_Handler
|
||||
def_weak_handler UART1_IRQHandler, Default_Handler
|
||||
def_weak_handler LCD_IRQHandler, Default_Handler
|
||||
def_weak_handler QSPI_IRQHandler, Default_Handler
|
||||
def_weak_handler SPI0_IRQHandler, Default_Handler
|
||||
def_weak_handler SPI1_IRQHandler, Default_Handler
|
||||
def_weak_handler SPI2_IRQHandler, Default_Handler
|
||||
def_weak_handler OSPI_IRQHandler, Default_Handler
|
||||
def_weak_handler TIM0_IRQHandler, Default_Handler
|
||||
def_weak_handler TIM1_IRQHandler, Default_Handler
|
||||
def_weak_handler TIM2_IRQHandler, Default_Handler
|
||||
def_weak_handler TIM3_IRQHandler, Default_Handler
|
||||
def_weak_handler SCALE1_IRQHandler, Default_Handler
|
||||
def_weak_handler AUDIO_DAC_IRQHandler, Default_Handler
|
||||
def_weak_handler AUDIO_ADC_IRQHandler, Default_Handler
|
||||
def_weak_handler AUDIO_VAD_HS_ALAW_IRQHandler, Default_Handler
|
||||
def_weak_handler SDIO_IRQHandler, Default_Handler
|
||||
def_weak_handler SDHOST1_IRQHandler, Default_Handler
|
||||
def_weak_handler SDHOST_IRQHandler, Default_Handler
|
||||
def_weak_handler LMAC_IRQHandler, Default_Handler
|
||||
def_weak_handler GMAC_IRQHandler, Default_Handler
|
||||
def_weak_handler DUAL_ORG_IRQHandler, Default_Handler
|
||||
def_weak_handler GEN422_IRQHandler, Default_Handler
|
||||
def_weak_handler CORET_IRQHandler, Default_Handler
|
||||
def_weak_handler SHA_IRQHandler, Default_Handler
|
||||
def_weak_handler CRC_IRQHandler, Default_Handler
|
||||
def_weak_handler ADKEY0_IRQHandler, Default_Handler
|
||||
def_weak_handler PD_TMR_IRQHandler, Default_Handler
|
||||
def_weak_handler WKPND_IRQHandler, Default_Handler
|
||||
def_weak_handler PDWKPND_IRQHandler, Default_Handler
|
||||
def_weak_handler LVD_IRQHandler, Default_Handler
|
||||
def_weak_handler WDT_IRQHandler, Default_Handler
|
||||
def_weak_handler SYS_ERR_IRQHandler, Default_Handler
|
||||
def_weak_handler IIS0_IRQHandler, Default_Handler
|
||||
def_weak_handler IIS1_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOA_IRQHandler, Default_Handler
|
||||
def_weak_handler LO_MNT_IRQHandler, Default_Handler
|
||||
def_weak_handler DVP_IRQHandler, Default_Handler
|
||||
def_weak_handler MJPEG01_IRQHandler, Default_Handler
|
||||
def_weak_handler H264ENC_IRQHandler, Default_Handler
|
||||
def_weak_handler VPP_IRQHandler, Default_Handler
|
||||
def_weak_handler PRC_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR5_IRQHandler, Default_Handler
|
||||
def_weak_handler PDM_IRQHandler, Default_Handler
|
||||
def_weak_handler LED_TMR_IRQHandler, Default_Handler
|
||||
def_weak_handler SCALE2_IRQHandler, Default_Handler
|
||||
def_weak_handler GFSK_IRQHandler, Default_Handler
|
||||
def_weak_handler CMPOUT0_IRQHandler, Default_Handler
|
||||
def_weak_handler UART6_IRQHandler, Default_Handler
|
||||
def_weak_handler SCALE3_IRQHandler, Default_Handler
|
||||
def_weak_handler IMG_ISP_IRQHandler, Default_Handler
|
||||
def_weak_handler MIPI_CSI2_IRQHandler, Default_Handler
|
||||
def_weak_handler RF_IRQHandler, Default_Handler
|
||||
def_weak_handler USB11MC_IRQHandler, Default_Handler
|
||||
def_weak_handler USB11DMA_IRQHandler, Default_Handler
|
||||
def_weak_handler RTC_VCCHVD_IRQHandler, Default_Handler
|
||||
def_weak_handler RTC_IRQHandler, Default_Handler
|
||||
def_weak_handler MIPI_DSI_IRQHandler, Default_Handler
|
||||
def_weak_handler PARA_OUT_IRQHandler, Default_Handler
|
||||
def_weak_handler M2M0_IRQHandler, Default_Handler
|
||||
def_weak_handler CAN_IRQHandler, Default_Handler
|
||||
def_weak_handler EXT_DCACHE_IRQHandler, Default_Handler
|
||||
def_weak_handler CPU_SPINLOCK_IRQHandler, Default_Handler
|
||||
def_weak_handler CPU_SEND_MAIL_IRQHandler, Default_Handler
|
||||
def_weak_handler CPU_RECV_MAIL_IRQHandler, Default_Handler
|
||||
def_weak_handler CPU_DBG_ON_IRQHandler, Default_Handler
|
||||
def_weak_handler CPU_SOFT_INT_IRQHandler, Default_Handler
|
||||
def_weak_handler OSPI_FIFO_IRQHandler, Default_Handler
|
||||
def_weak_handler OSPI_EFF_IRQHandler, Default_Handler
|
||||
def_weak_handler GEN420_IRQHandler, Default_Handler
|
||||
def_weak_handler SYS_AES_IRQHandler, Default_Handler
|
||||
def_weak_handler PKA_IRQHandler, Default_Handler
|
||||
def_weak_handler WDT1_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOB_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOC_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOD_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOE_IRQHandler, Default_Handler
|
||||
def_weak_handler GPIOF_IRQHandler, Default_Handler
|
||||
def_weak_handler DVP1_IRQHandler, Default_Handler
|
||||
def_weak_handler PNG_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR4_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR3_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR2_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR1_IRQHandler, Default_Handler
|
||||
def_weak_handler STMR0_IRQHandler, Default_Handler
|
||||
def_weak_handler CMPOUT1_IRQHandler, Default_Handler
|
||||
def_weak_handler UART5_IRQHandler, Default_Handler
|
||||
def_weak_handler UART4_IRQHandler, Default_Handler
|
||||
def_weak_handler MIPI1_CSI2_IRQHandler, Default_Handler
|
||||
def_weak_handler DMA2D_IRQHandler, Default_Handler
|
||||
def_weak_handler CSC_IRQHandler, Default_Handler
|
||||
def_weak_handler OSD_ENC_IRQHandler, Default_Handler
|
||||
def_weak_handler USB20PHY_IRQHandler, Default_Handler
|
||||
def_weak_handler PARA_IN_IRQHandler, Default_Handler
|
||||
def_weak_handler M2M1_IRQHandler, Default_Handler
|
||||
def_weak_handler WKUP_IRQHandler, Default_Handler
|
||||
def_weak_handler SAM_IRQHandler, Default_Handler
|
||||
def_weak_handler LIN_IRQHandler, Default_Handler
|
||||
def_weak_handler LIN1_IRQHandler, Default_Handler
|
||||
|
||||
def_weak_handler rev0_IRQHandler, Default_Handler
|
||||
def_weak_handler rev1_IRQHandler, Default_Handler
|
||||
def_weak_handler rev2_IRQHandler, Default_Handler
|
||||
def_weak_handler rev3_IRQHandler, Default_Handler
|
||||
def_weak_handler rev4_IRQHandler, Default_Handler
|
||||
|
||||
def_weak_handler M2M2_IRQHandler, Default_Handler
|
||||
|
||||
def_weak_handler Reset_Handler, Default_Handler
|
||||
def_weak_handler trap0_handler, Default_Handler
|
||||
def_weak_handler tspend_handler, Default_Handler
|
||||
Reference in New Issue
Block a user