Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources
This commit is contained in:
9
project/utilities/aft_build.sh
Normal file
9
project/utilities/aft_build.sh
Normal file
@@ -0,0 +1,9 @@
|
||||
#!/bin/bash
|
||||
|
||||
cp -f ./Obj/txw4101.ihex project.hex
|
||||
cp -f ../../../../tools/makecode/BinScript.exe BinScript.exe
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||||
cp -f ../../../../tools/makecode/crc.exe crc.exe
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||||
cp -f ../../../../tools/makecode/makecode.exe makecode.exe
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||||
|
||||
BinScript.exe BinScript.BinScript
|
||||
makecode.exe
|
||||
0
project/utilities/flashinit
Normal file
0
project/utilities/flashinit
Normal file
331
project/utilities/gcc_csky.ld
Normal file
331
project/utilities/gcc_csky.ld
Normal file
@@ -0,0 +1,331 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file gcc_csky.ld
|
||||
* @brief csky linker file
|
||||
* @version V1.0
|
||||
* @date 2025.4.12
|
||||
* SRAM0-0: 0x20000000 ~ 0x20003FFF 16KB
|
||||
* SRAM0-1: 0x20004000 ~ 0x2001FFFF 112KB
|
||||
* SRAM1: 0x20020000 ~ 0x2003FFFF 128KB
|
||||
* SRAM2-0: 0x20040000 ~ 0x20057FFF 96KB
|
||||
* SRAM2-1: 0x20058000 ~ 0x2005FFFF 32KB (DCAHCE)
|
||||
* SRAM2-2: 0x20060000 ~ 0x20067FFF 32KB (CPU1 I/D CACHE)
|
||||
* SRAM2-3: 0x20068000 ~ 0x2006BF00 16KB (末尾256byte为CoreSetting数据)
|
||||
* SRAM3: 0x20080000 ~ 0x2009FFFF 128KB (H264)
|
||||
******************************************************************************/
|
||||
MEMORY
|
||||
{
|
||||
ISRAM : ORIGIN = 0x04001000 , LENGTH = 0x2a000
|
||||
SRAM : ORIGIN = 0x20006b44 , LENGTH = 0x40000 /*起始地址为CoreCode BSS结束地址 */
|
||||
SRAM2 : ORIGIN = 0x20068000 , LENGTH = 0x3A00 /*末尾预留256byte做为CoreSetting数据*/
|
||||
FLASH : ORIGIN = 0x10000000 , LENGTH = 0x200000
|
||||
PSRAM : ORIGIN = 0x28000000 , LENGTH = 0x800000
|
||||
SRAM0 : ORIGIN = 0x20001100 , LENGTH = 0x2F00 /*SRAM0 16 - 4KB for sleep*/
|
||||
ALUSER-SRAM : ORIGIN = 0x2006BA00 , LENGTH = 0x400 /* 二次loader的固件参数区 ALUSER-SRAM 1KB */
|
||||
FW_INFO : ORIGIN = 0x2006BE00 , LENGTH = 0x100
|
||||
}
|
||||
|
||||
__heap_size = 0x40000;
|
||||
|
||||
PROVIDE (__ram_end = 0x20058000);
|
||||
PROVIDE (__heap_end = 0x20058000);
|
||||
PROVIDE (__sleep_data_start = 0x20000200);
|
||||
PROVIDE (__sleep_data_stop = 0x20001000);
|
||||
PROVIDE (__psram_heap_end = 0x29000000);
|
||||
PROVIDE (_data0_lma_start = 0);
|
||||
PROVIDE (__data0_start__ = 0);
|
||||
PROVIDE (__data0_end__ = 0);
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", FLASH);
|
||||
REGION_ALIAS("REGION_RODATA", FLASH);
|
||||
REGION_ALIAS("REGION_DATA", SRAM);
|
||||
REGION_ALIAS("REGION_BSS", SRAM);
|
||||
REGION_ALIAS("REGION_INIT", SRAM);
|
||||
REGION_ALIAS("REGION_PSRAM_HEAP", PSRAM);
|
||||
REGION_ALIAS("REGION_NOLOAD_PSRAM", PSRAM);
|
||||
REGION_ALIAS("REGION_DATA2", SRAM2);
|
||||
REGION_ALIAS("REGION_OTA_VMA", SRAM);
|
||||
REGION_ALIAS("REGION_TEXT2", SRAM2);
|
||||
REGION_ALIAS("REGION_DSLEEP", SRAM0);
|
||||
REGION_ALIAS("REGION_ALUSER", ALUSER-SRAM);
|
||||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text : AT(ADDR(.text)) {
|
||||
. = ALIGN(0x4) ;
|
||||
__code_start = .;
|
||||
KEEP(*startup.o(.vectors))
|
||||
. = ALIGN(0x10) ;
|
||||
KEEP(*(SYS_PARAM)) /*如果预留参数区的Size 大于4K时 不能再放在此位置*/
|
||||
. = ALIGN(0x1000);
|
||||
. = . + 0x61fb4; /*预留CodeCode Size大小区间*/
|
||||
. = ALIGN(0x4);
|
||||
__stext = . ;
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.text.*)
|
||||
*(INIT.TXT)
|
||||
*(INIT.TXT.*)
|
||||
*(.gnu.warning)
|
||||
*(.stub)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.jcr)
|
||||
KEEP (*(.init*))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN (4) ;
|
||||
PROVIDE(__ctbp = .);
|
||||
*(.call_table_data)
|
||||
*(.call_table_text)
|
||||
. = ALIGN(4) ;
|
||||
__etext = . ;
|
||||
} > REGION_TEXT
|
||||
|
||||
.rodata : {
|
||||
. = ALIGN(0x4) ;
|
||||
__srodata = .;
|
||||
*(.rdata)
|
||||
*(.rdata*)
|
||||
*(.rdata1)
|
||||
*(.rdata.*)
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata*)
|
||||
*(.rodata.*)
|
||||
*(.rodata.str1.4)
|
||||
*(INIT.RO)
|
||||
*(INIT.RO.*)
|
||||
. = ALIGN(0x4) ;
|
||||
|
||||
__modver_start = .;
|
||||
KEEP(*(.modver))
|
||||
__modver_end = .;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
__CTOR_LIST__ = . ;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.ctors)))
|
||||
LONG(0)
|
||||
__CTOR_END__ = . ;
|
||||
__DTOR_LIST__ = . ;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.dtors)))
|
||||
LONG(0)
|
||||
__DTOR_END__ = . ;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
} > REGION_RODATA
|
||||
|
||||
.dsleep : {
|
||||
__data0_start__ = . ;
|
||||
__dsleep_start = .;
|
||||
*(.dsleep.*)
|
||||
. = ALIGN(0x4) ;
|
||||
__dsleep_end = .;
|
||||
__data0_end__ = . ;
|
||||
} > REGION_DSLEEP AT>REGION_RODATA
|
||||
_data0_lma_start = LOADADDR(.dsleep);
|
||||
_data0_lma_end = LOADADDR(.dsleep) + SIZEOF(.dsleep);
|
||||
|
||||
.data : {
|
||||
. = ALIGN(4) ;
|
||||
__sdata = . ;
|
||||
__data_start__ = . ;
|
||||
data_start = . ;
|
||||
|
||||
|
||||
*(INIT.DAT)
|
||||
*(INIT.DAT.*)
|
||||
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
*(.gnu.linkonce.r*)
|
||||
*(.bobj)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.data1)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.data1)
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table*)
|
||||
__start_init_call = .;
|
||||
*(.initcall.init)
|
||||
__stop_init_call = .;
|
||||
__start_cmd = .;
|
||||
*(.bootloaddata.cmd)
|
||||
. = ALIGN(4) ;
|
||||
__stop_cmd = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(__libc_atexit)
|
||||
*(__libc_subinit)
|
||||
*(__libc_subfreeres)
|
||||
*(.note.ABI-tag)
|
||||
*(.ram.text)
|
||||
. = ALIGN(0x4) ;
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA AT>REGION_RODATA
|
||||
_data_lma_start = LOADADDR(.data);
|
||||
_data_lma_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
.fw_info : {
|
||||
__fw_info_start = .;
|
||||
. += 160;
|
||||
__fw_info_end = .;
|
||||
} > FW_INFO
|
||||
|
||||
.no_init (NOLOAD) : {
|
||||
*(.irq_stack);
|
||||
*(.trap_stack);
|
||||
*(.no_init);
|
||||
} > REGION_BSS
|
||||
|
||||
.ota : {
|
||||
. = ALIGN(0x4) ;
|
||||
_ota_vma_start = . ;
|
||||
KEEP (*(.otacode))
|
||||
_ota_vma_end = . ;
|
||||
} > REGION_OTA_VMA AT > REGION_RODATA
|
||||
_ota_lma_start = LOADADDR(.ota);
|
||||
_ota_lma_end = LOADADDR(.ota) + SIZEOF(.ota);
|
||||
|
||||
|
||||
.iis : AT(LOADADDR(.ota) + SIZEOF(.ota)) {
|
||||
. = ALIGN(0x4) ;
|
||||
iis_start = .;
|
||||
KEEP (*(.iiscode))
|
||||
} > REGION_OTA_VMA
|
||||
_iis_start = LOADADDR(.iis);
|
||||
_iis_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
__code_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
|
||||
._al_user_sram (NOLOAD): {
|
||||
. = ALIGN(0x4) ;
|
||||
__al_user_sram_start = .;
|
||||
*(.al_user_data)
|
||||
__al_user_sram_current = .;
|
||||
} > REGION_ALUSER AT > REGION_BSS
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sbss = ALIGN(0x4) ;
|
||||
__bss_start__ = . ;
|
||||
*(.dynsbss)
|
||||
*(.sbss.ota)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4) ;
|
||||
__ebss = . ;
|
||||
__end = . ;
|
||||
end = . ;
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._user_heap : {
|
||||
. = ALIGN(0x4) ;
|
||||
__heap_start = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._psram_data (NOLOAD): {
|
||||
*(.psram.src)
|
||||
*(.psram.data)
|
||||
} > REGION_NOLOAD_PSRAM
|
||||
|
||||
.psram_heap : {
|
||||
. = ALIGN(4) ;
|
||||
__psram_heap_start = .;
|
||||
} > REGION_PSRAM_HEAP
|
||||
|
||||
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > REGION_BSS
|
||||
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } > REGION_BSS
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
|
||||
.preinit_array :{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
|
||||
.init_array :{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
|
||||
.fini_array :{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
|
||||
.junk 0 : { *(.rel*) *(.rela*) }
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
}
|
||||
|
||||
|
||||
/* ROM Functions */
|
||||
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
|
||||
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
|
||||
|
||||
/* INPUT(romcode.ld) */
|
||||
memset = 0x00000568;
|
||||
memcpy = 0x00000608;
|
||||
memcmp = 0x00000688;
|
||||
331
project/utilities/gcc_csky.ld.i
Normal file
331
project/utilities/gcc_csky.ld.i
Normal file
@@ -0,0 +1,331 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file gcc_csky.ld
|
||||
* @brief csky linker file
|
||||
* @version V1.0
|
||||
* @date 2025.4.12
|
||||
* SRAM0-0: 0x20000000 ~ 0x20003FFF 16KB
|
||||
* SRAM0-1: 0x20004000 ~ 0x2001FFFF 112KB
|
||||
* SRAM1: 0x20020000 ~ 0x2003FFFF 128KB
|
||||
* SRAM2-0: 0x20040000 ~ 0x20057FFF 96KB
|
||||
* SRAM2-1: 0x20058000 ~ 0x2005FFFF 32KB (DCAHCE)
|
||||
* SRAM2-2: 0x20060000 ~ 0x20067FFF 32KB (CPU1 I/D CACHE)
|
||||
* SRAM2-3: 0x20068000 ~ 0x2006BF00 16KB (末尾256byte为CoreSetting数据)
|
||||
* SRAM3: 0x20080000 ~ 0x2009FFFF 128KB (H264)
|
||||
******************************************************************************/
|
||||
MEMORY
|
||||
{
|
||||
ISRAM : ORIGIN = 0x04001000 , LENGTH = 0x2a000
|
||||
SRAM : ORIGIN = COREBSS_END , LENGTH = 0x40000 /*起始地址为CoreCode BSS结束地址 */
|
||||
SRAM2 : ORIGIN = 0x20068000 , LENGTH = 0x3A00 /*末尾预留256byte做为CoreSetting数据*/
|
||||
FLASH : ORIGIN = 0x10000000 , LENGTH = 0x200000
|
||||
PSRAM : ORIGIN = 0x28000000 , LENGTH = 0x800000
|
||||
SRAM0 : ORIGIN = 0x20001100 , LENGTH = 0x2F00 /*SRAM0 16 - 4KB for sleep*/
|
||||
ALUSER-SRAM : ORIGIN = 0x2006BA00 , LENGTH = 0x400 /* 二次loader的固件参数区 ALUSER-SRAM 1KB */
|
||||
FW_INFO : ORIGIN = 0x2006BE00 , LENGTH = 0x100
|
||||
}
|
||||
|
||||
__heap_size = 0x40000;
|
||||
|
||||
PROVIDE (__ram_end = 0x20058000);
|
||||
PROVIDE (__heap_end = 0x20058000);
|
||||
PROVIDE (__sleep_data_start = 0x20000200);
|
||||
PROVIDE (__sleep_data_stop = 0x20001000);
|
||||
PROVIDE (__psram_heap_end = 0x29000000);
|
||||
PROVIDE (_data0_lma_start = 0);
|
||||
PROVIDE (__data0_start__ = 0);
|
||||
PROVIDE (__data0_end__ = 0);
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", FLASH);
|
||||
REGION_ALIAS("REGION_RODATA", FLASH);
|
||||
REGION_ALIAS("REGION_DATA", SRAM);
|
||||
REGION_ALIAS("REGION_BSS", SRAM);
|
||||
REGION_ALIAS("REGION_INIT", SRAM);
|
||||
REGION_ALIAS("REGION_PSRAM_HEAP", PSRAM);
|
||||
REGION_ALIAS("REGION_NOLOAD_PSRAM", PSRAM);
|
||||
REGION_ALIAS("REGION_DATA2", SRAM2);
|
||||
REGION_ALIAS("REGION_OTA_VMA", SRAM);
|
||||
REGION_ALIAS("REGION_TEXT2", SRAM2);
|
||||
REGION_ALIAS("REGION_DSLEEP", SRAM0);
|
||||
REGION_ALIAS("REGION_ALUSER", ALUSER-SRAM);
|
||||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text : AT(ADDR(.text)) {
|
||||
. = ALIGN(0x4) ;
|
||||
__code_start = .;
|
||||
KEEP(*startup.o(.vectors))
|
||||
. = ALIGN(0x10) ;
|
||||
KEEP(*(SYS_PARAM)) /*如果预留参数区的Size 大于4K时 不能再放在此位置*/
|
||||
. = ALIGN(0x1000);
|
||||
. = . + CORECODE_SIZE; /*预留CodeCode Size大小区间*/
|
||||
. = ALIGN(0x4);
|
||||
__stext = . ;
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.text.*)
|
||||
*(INIT.TXT)
|
||||
*(INIT.TXT.*)
|
||||
*(.gnu.warning)
|
||||
*(.stub)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.jcr)
|
||||
KEEP (*(.init*))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN (4) ;
|
||||
PROVIDE(__ctbp = .);
|
||||
*(.call_table_data)
|
||||
*(.call_table_text)
|
||||
. = ALIGN(4) ;
|
||||
__etext = . ;
|
||||
} > REGION_TEXT
|
||||
|
||||
.rodata : {
|
||||
. = ALIGN(0x4) ;
|
||||
__srodata = .;
|
||||
*(.rdata)
|
||||
*(.rdata*)
|
||||
*(.rdata1)
|
||||
*(.rdata.*)
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata*)
|
||||
*(.rodata.*)
|
||||
*(.rodata.str1.4)
|
||||
*(INIT.RO)
|
||||
*(INIT.RO.*)
|
||||
. = ALIGN(0x4) ;
|
||||
|
||||
__modver_start = .;
|
||||
KEEP(*(.modver))
|
||||
__modver_end = .;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
__CTOR_LIST__ = . ;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.ctors)))
|
||||
LONG(0)
|
||||
__CTOR_END__ = . ;
|
||||
__DTOR_LIST__ = . ;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.dtors)))
|
||||
LONG(0)
|
||||
__DTOR_END__ = . ;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
} > REGION_RODATA
|
||||
|
||||
.dsleep : {
|
||||
__data0_start__ = . ;
|
||||
__dsleep_start = .;
|
||||
*(.dsleep.*)
|
||||
. = ALIGN(0x4) ;
|
||||
__dsleep_end = .;
|
||||
__data0_end__ = . ;
|
||||
} > REGION_DSLEEP AT>REGION_RODATA
|
||||
_data0_lma_start = LOADADDR(.dsleep);
|
||||
_data0_lma_end = LOADADDR(.dsleep) + SIZEOF(.dsleep);
|
||||
|
||||
.data : {
|
||||
. = ALIGN(4) ;
|
||||
__sdata = . ;
|
||||
__data_start__ = . ;
|
||||
data_start = . ;
|
||||
|
||||
|
||||
*(INIT.DAT)
|
||||
*(INIT.DAT.*)
|
||||
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
*(.gnu.linkonce.r*)
|
||||
*(.bobj)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.data1)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.data1)
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table*)
|
||||
__start_init_call = .;
|
||||
*(.initcall.init)
|
||||
__stop_init_call = .;
|
||||
__start_cmd = .;
|
||||
*(.bootloaddata.cmd)
|
||||
. = ALIGN(4) ;
|
||||
__stop_cmd = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(__libc_atexit)
|
||||
*(__libc_subinit)
|
||||
*(__libc_subfreeres)
|
||||
*(.note.ABI-tag)
|
||||
*(.ram.text)
|
||||
. = ALIGN(0x4) ;
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA AT>REGION_RODATA
|
||||
_data_lma_start = LOADADDR(.data);
|
||||
_data_lma_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
.fw_info : {
|
||||
__fw_info_start = .;
|
||||
. += 160;
|
||||
__fw_info_end = .;
|
||||
} > FW_INFO
|
||||
|
||||
.no_init (NOLOAD) : {
|
||||
*(.irq_stack);
|
||||
*(.trap_stack);
|
||||
*(.no_init);
|
||||
} > REGION_BSS
|
||||
|
||||
.ota : {
|
||||
. = ALIGN(0x4) ;
|
||||
_ota_vma_start = . ;
|
||||
KEEP (*(.otacode))
|
||||
_ota_vma_end = . ;
|
||||
} > REGION_OTA_VMA AT > REGION_RODATA
|
||||
_ota_lma_start = LOADADDR(.ota);
|
||||
_ota_lma_end = LOADADDR(.ota) + SIZEOF(.ota);
|
||||
|
||||
|
||||
.iis : AT(LOADADDR(.ota) + SIZEOF(.ota)) {
|
||||
. = ALIGN(0x4) ;
|
||||
iis_start = .;
|
||||
KEEP (*(.iiscode))
|
||||
} > REGION_OTA_VMA
|
||||
_iis_start = LOADADDR(.iis);
|
||||
_iis_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
__code_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
|
||||
._al_user_sram (NOLOAD): {
|
||||
. = ALIGN(0x4) ;
|
||||
__al_user_sram_start = .;
|
||||
*(.al_user_data)
|
||||
__al_user_sram_current = .;
|
||||
} > REGION_ALUSER AT > REGION_BSS
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sbss = ALIGN(0x4) ;
|
||||
__bss_start__ = . ;
|
||||
*(.dynsbss)
|
||||
*(.sbss.ota)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4) ;
|
||||
__ebss = . ;
|
||||
__end = . ;
|
||||
end = . ;
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._user_heap : {
|
||||
. = ALIGN(0x4) ;
|
||||
__heap_start = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._psram_data (NOLOAD): {
|
||||
*(.psram.src)
|
||||
*(.psram.data)
|
||||
} > REGION_NOLOAD_PSRAM
|
||||
|
||||
.psram_heap : {
|
||||
. = ALIGN(4) ;
|
||||
__psram_heap_start = .;
|
||||
} > REGION_PSRAM_HEAP
|
||||
|
||||
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > REGION_BSS
|
||||
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } > REGION_BSS
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
|
||||
.preinit_array :{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
|
||||
.init_array :{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
|
||||
.fini_array :{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
|
||||
.junk 0 : { *(.rel*) *(.rela*) }
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
}
|
||||
|
||||
|
||||
/* ROM Functions */
|
||||
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
|
||||
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
|
||||
|
||||
/* INPUT(romcode.ld) */
|
||||
memset = 0x00000568;
|
||||
memcpy = 0x00000608;
|
||||
memcmp = 0x00000688;
|
||||
331
project/utilities/gcc_csky.ld.n
Normal file
331
project/utilities/gcc_csky.ld.n
Normal file
@@ -0,0 +1,331 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file gcc_csky.ld
|
||||
* @brief csky linker file
|
||||
* @version V1.0
|
||||
* @date 2025.4.12
|
||||
* SRAM0-0: 0x20000000 ~ 0x20003FFF 16KB
|
||||
* SRAM0-1: 0x20004000 ~ 0x2001FFFF 112KB
|
||||
* SRAM1: 0x20020000 ~ 0x2003FFFF 128KB
|
||||
* SRAM2-0: 0x20040000 ~ 0x20057FFF 96KB
|
||||
* SRAM2-1: 0x20058000 ~ 0x2005FFFF 32KB (DCAHCE)
|
||||
* SRAM2-2: 0x20060000 ~ 0x20067FFF 32KB (CPU1 I/D CACHE)
|
||||
* SRAM2-3: 0x20068000 ~ 0x2006BF00 16KB (末尾256byte为CoreSetting数据)
|
||||
* SRAM3: 0x20080000 ~ 0x2009FFFF 128KB (H264)
|
||||
******************************************************************************/
|
||||
MEMORY
|
||||
{
|
||||
ISRAM : ORIGIN = 0x04001000 , LENGTH = 0x2a000
|
||||
SRAM : ORIGIN = 0x20006b44 , LENGTH = 0x40000 /*起始地址为CoreCode BSS结束地址 */
|
||||
SRAM2 : ORIGIN = 0x20068000 , LENGTH = 0x3A00 /*末尾预留256byte做为CoreSetting数据*/
|
||||
FLASH : ORIGIN = 0x10000000 , LENGTH = 0x200000
|
||||
PSRAM : ORIGIN = 0x28000000 , LENGTH = 0x800000
|
||||
SRAM0 : ORIGIN = 0x20001100 , LENGTH = 0x2F00 /*SRAM0 16 - 4KB for sleep*/
|
||||
ALUSER-SRAM : ORIGIN = 0x2006BA00 , LENGTH = 0x400 /* 二次loader的固件参数区 ALUSER-SRAM 1KB */
|
||||
FW_INFO : ORIGIN = 0x2006BE00 , LENGTH = 0x100
|
||||
}
|
||||
|
||||
__heap_size = 0x40000;
|
||||
|
||||
PROVIDE (__ram_end = 0x20058000);
|
||||
PROVIDE (__heap_end = 0x20058000);
|
||||
PROVIDE (__sleep_data_start = 0x20000200);
|
||||
PROVIDE (__sleep_data_stop = 0x20001000);
|
||||
PROVIDE (__psram_heap_end = 0x29000000);
|
||||
PROVIDE (_data0_lma_start = 0);
|
||||
PROVIDE (__data0_start__ = 0);
|
||||
PROVIDE (__data0_end__ = 0);
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", FLASH);
|
||||
REGION_ALIAS("REGION_RODATA", FLASH);
|
||||
REGION_ALIAS("REGION_DATA", SRAM);
|
||||
REGION_ALIAS("REGION_BSS", SRAM);
|
||||
REGION_ALIAS("REGION_INIT", SRAM);
|
||||
REGION_ALIAS("REGION_PSRAM_HEAP", PSRAM);
|
||||
REGION_ALIAS("REGION_NOLOAD_PSRAM", PSRAM);
|
||||
REGION_ALIAS("REGION_DATA2", SRAM2);
|
||||
REGION_ALIAS("REGION_OTA_VMA", SRAM);
|
||||
REGION_ALIAS("REGION_TEXT2", SRAM2);
|
||||
REGION_ALIAS("REGION_DSLEEP", SRAM0);
|
||||
REGION_ALIAS("REGION_ALUSER", ALUSER-SRAM);
|
||||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text : AT(ADDR(.text)) {
|
||||
. = ALIGN(0x4) ;
|
||||
__code_start = .;
|
||||
KEEP(*startup.o(.vectors))
|
||||
. = ALIGN(0x10) ;
|
||||
KEEP(*(SYS_PARAM)) /*如果预留参数区的Size 大于4K时 不能再放在此位置*/
|
||||
. = ALIGN(0x1000);
|
||||
. = . + 0x61fb4; /*预留CodeCode Size大小区间*/
|
||||
. = ALIGN(0x4);
|
||||
__stext = . ;
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.text.*)
|
||||
*(INIT.TXT)
|
||||
*(INIT.TXT.*)
|
||||
*(.gnu.warning)
|
||||
*(.stub)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.jcr)
|
||||
KEEP (*(.init*))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN (4) ;
|
||||
PROVIDE(__ctbp = .);
|
||||
*(.call_table_data)
|
||||
*(.call_table_text)
|
||||
. = ALIGN(4) ;
|
||||
__etext = . ;
|
||||
} > REGION_TEXT
|
||||
|
||||
.rodata : {
|
||||
. = ALIGN(0x4) ;
|
||||
__srodata = .;
|
||||
*(.rdata)
|
||||
*(.rdata*)
|
||||
*(.rdata1)
|
||||
*(.rdata.*)
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata*)
|
||||
*(.rodata.*)
|
||||
*(.rodata.str1.4)
|
||||
*(INIT.RO)
|
||||
*(INIT.RO.*)
|
||||
. = ALIGN(0x4) ;
|
||||
|
||||
__modver_start = .;
|
||||
KEEP(*(.modver))
|
||||
__modver_end = .;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
__CTOR_LIST__ = . ;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.ctors)))
|
||||
LONG(0)
|
||||
__CTOR_END__ = . ;
|
||||
__DTOR_LIST__ = . ;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
KEEP(*(SORT(.dtors)))
|
||||
LONG(0)
|
||||
__DTOR_END__ = . ;
|
||||
|
||||
. = ALIGN(0x4) ;
|
||||
} > REGION_RODATA
|
||||
|
||||
.dsleep : {
|
||||
__data0_start__ = . ;
|
||||
__dsleep_start = .;
|
||||
*(.dsleep.*)
|
||||
. = ALIGN(0x4) ;
|
||||
__dsleep_end = .;
|
||||
__data0_end__ = . ;
|
||||
} > REGION_DSLEEP AT>REGION_RODATA
|
||||
_data0_lma_start = LOADADDR(.dsleep);
|
||||
_data0_lma_end = LOADADDR(.dsleep) + SIZEOF(.dsleep);
|
||||
|
||||
.data : {
|
||||
. = ALIGN(4) ;
|
||||
__sdata = . ;
|
||||
__data_start__ = . ;
|
||||
data_start = . ;
|
||||
|
||||
|
||||
*(INIT.DAT)
|
||||
*(INIT.DAT.*)
|
||||
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
*(.gnu.linkonce.r*)
|
||||
*(.bobj)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.data1)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.data1)
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table*)
|
||||
__start_init_call = .;
|
||||
*(.initcall.init)
|
||||
__stop_init_call = .;
|
||||
__start_cmd = .;
|
||||
*(.bootloaddata.cmd)
|
||||
. = ALIGN(4) ;
|
||||
__stop_cmd = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(__libc_atexit)
|
||||
*(__libc_subinit)
|
||||
*(__libc_subfreeres)
|
||||
*(.note.ABI-tag)
|
||||
*(.ram.text)
|
||||
. = ALIGN(0x4) ;
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA AT>REGION_RODATA
|
||||
_data_lma_start = LOADADDR(.data);
|
||||
_data_lma_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
.fw_info : {
|
||||
__fw_info_start = .;
|
||||
. += 160;
|
||||
__fw_info_end = .;
|
||||
} > FW_INFO
|
||||
|
||||
.no_init (NOLOAD) : {
|
||||
*(.irq_stack);
|
||||
*(.trap_stack);
|
||||
*(.no_init);
|
||||
} > REGION_BSS
|
||||
|
||||
.ota : {
|
||||
. = ALIGN(0x4) ;
|
||||
_ota_vma_start = . ;
|
||||
KEEP (*(.otacode))
|
||||
_ota_vma_end = . ;
|
||||
} > REGION_OTA_VMA AT > REGION_RODATA
|
||||
_ota_lma_start = LOADADDR(.ota);
|
||||
_ota_lma_end = LOADADDR(.ota) + SIZEOF(.ota);
|
||||
|
||||
|
||||
.iis : AT(LOADADDR(.ota) + SIZEOF(.ota)) {
|
||||
. = ALIGN(0x4) ;
|
||||
iis_start = .;
|
||||
KEEP (*(.iiscode))
|
||||
} > REGION_OTA_VMA
|
||||
_iis_start = LOADADDR(.iis);
|
||||
_iis_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
__code_end = LOADADDR(.iis) + SIZEOF(.iis);
|
||||
|
||||
._al_user_sram (NOLOAD): {
|
||||
. = ALIGN(0x4) ;
|
||||
__al_user_sram_start = .;
|
||||
*(.al_user_data)
|
||||
__al_user_sram_current = .;
|
||||
} > REGION_ALUSER AT > REGION_BSS
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sbss = ALIGN(0x4) ;
|
||||
__bss_start__ = . ;
|
||||
*(.dynsbss)
|
||||
*(.sbss.ota)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4) ;
|
||||
__ebss = . ;
|
||||
__end = . ;
|
||||
end = . ;
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._user_heap : {
|
||||
. = ALIGN(0x4) ;
|
||||
__heap_start = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._psram_data (NOLOAD): {
|
||||
*(.psram.src)
|
||||
*(.psram.data)
|
||||
} > REGION_NOLOAD_PSRAM
|
||||
|
||||
.psram_heap : {
|
||||
. = ALIGN(4) ;
|
||||
__psram_heap_start = .;
|
||||
} > REGION_PSRAM_HEAP
|
||||
|
||||
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > REGION_BSS
|
||||
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } > REGION_BSS
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
|
||||
.preinit_array :{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
|
||||
.init_array :{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
|
||||
.fini_array :{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
|
||||
.junk 0 : { *(.rel*) *(.rela*) }
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
}
|
||||
|
||||
|
||||
/* ROM Functions */
|
||||
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
|
||||
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
|
||||
|
||||
/* INPUT(romcode.ld) */
|
||||
memset = 0x00000568;
|
||||
memcpy = 0x00000608;
|
||||
memcmp = 0x00000688;
|
||||
193
project/utilities/gcc_csky_qspiboot.ld
Normal file
193
project/utilities/gcc_csky_qspiboot.ld
Normal file
@@ -0,0 +1,193 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file gcc_csky.ld
|
||||
* @brief csky linker file
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
MEMORY
|
||||
{
|
||||
I-SRAM : ORIGIN = 0x0 , LENGTH = 0x80000 /* I-SRAM 128KB */
|
||||
D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000 /* D-SRAM 512KB */
|
||||
O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000 /* off-chip SRAM 8MB */
|
||||
FLASH : ORIGIN = 0x18000000 , LENGTH = 0x200000 /* MCP FLASH 2MB */
|
||||
SRAM : ORIGIN = 0x20002000 , LENGTH = 0x46000 /* on-chip SRAM 288KB */
|
||||
LMAC_BUF : ORIGIN = 0x20051000 , LENGTH = 18*1024 /* on-chip SRAM 18KB */
|
||||
}
|
||||
|
||||
__heap_size = 0x11000;
|
||||
|
||||
PROVIDE (__ram_end = 0x20048000);
|
||||
PROVIDE (__heap_end = 0x20048000);
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", FLASH);
|
||||
REGION_ALIAS("REGION_RODATA", FLASH);
|
||||
REGION_ALIAS("REGION_DATA", SRAM);
|
||||
REGION_ALIAS("REGION_BSS", SRAM);
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
SECTIONS
|
||||
{
|
||||
.text : AT(ADDR(.text)) {
|
||||
. = ALIGN(0x4) ;
|
||||
KEEP(*startup.o(.vectors))
|
||||
KEEP(*(SYS_PARAM))
|
||||
*(.dsleep_data)
|
||||
__stext = . ;
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.text.*)
|
||||
*(.gnu.warning)
|
||||
*(.stub)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.glue_7t)
|
||||
*(.glue_7)
|
||||
*(.jcr)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN (4) ;
|
||||
PROVIDE(__ctbp = .);
|
||||
*(.call_table_data)
|
||||
*(.call_table_text)
|
||||
. = ALIGN(0x10) ;
|
||||
__etext = . ;
|
||||
} > REGION_TEXT
|
||||
.rodata : {
|
||||
. = ALIGN(0x4) ;
|
||||
__srodata = .;
|
||||
*(.rdata)
|
||||
*(.rdata*)
|
||||
*(.rdata1)
|
||||
*(.rdata.*)
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata*)
|
||||
*(.rodata.*)
|
||||
*(.rodata.str1.4)
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
. = ALIGN(0x4) ;
|
||||
__erodata = .;
|
||||
} > REGION_RODATA
|
||||
|
||||
.data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)){
|
||||
. = ALIGN(0x4) ;
|
||||
__sdata = . ;
|
||||
__data_start__ = . ;
|
||||
data_start = . ;
|
||||
*(.got.plt)
|
||||
*(.got)
|
||||
*(.gnu.linkonce.r*)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.data1)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.data1)
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table*)
|
||||
__start_init_call = .;
|
||||
*(.initcall.init)
|
||||
__stop_init_call = .;
|
||||
__start_cmd = .;
|
||||
*(.bootloaddata.cmd)
|
||||
. = ALIGN(4) ;
|
||||
__stop_cmd = .;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(__libc_atexit)
|
||||
*(__libc_subinit)
|
||||
*(__libc_subfreeres)
|
||||
*(.note.ABI-tag)
|
||||
. = ALIGN(0x4) ;
|
||||
__edata = .;
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA
|
||||
|
||||
__dsleep_ro_start__ = LOADADDR(.rodata) + SIZEOF(.rodata) + SIZEOF(.data);
|
||||
.dsleep : AT(__dsleep_ro_start__) {
|
||||
__dsleep_code_start__ = .;
|
||||
KEEP(*(.dsleep_vector))
|
||||
*(.dsleep_txt)
|
||||
*(.lmac_dsleep_txt)
|
||||
*(.wphy_dsleep_txt)
|
||||
*(.rf_digicali_dsleep_txt)
|
||||
__dsleep_code_end__ = .;
|
||||
} > LMAC_BUF
|
||||
|
||||
.dsleep_buf (NOLOAD) : {
|
||||
*(.dsleep_stack)
|
||||
*(.lmac_dsleep_data)
|
||||
*(.wphy_dsleep_data)
|
||||
*(.rf_digicali_dsleep_data)
|
||||
} > LMAC_BUF
|
||||
|
||||
/* 当.dsleep的代码是放到sram，则在bss之前需要预留.dsleep加载代码的空间 */
|
||||
.fill_dsleep_code (NOLOAD) : {
|
||||
. = . + (((__dsleep_ro_start__ & 0x20000000) == 0x20000000) ? SIZEOF(.dsleep) : 0);
|
||||
} > REGION_DATA
|
||||
|
||||
.no_init (NOLOAD) : {
|
||||
*(.stack);
|
||||
*(.no_init);
|
||||
} > REGION_BSS
|
||||
.bss : {
|
||||
. = ALIGN(0x4) ;
|
||||
__sbss = ALIGN(0x4) ;
|
||||
__bss_start__ = . ;
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(0x4) ;
|
||||
__ebss = . ;
|
||||
__end = . ;
|
||||
end = . ;
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS
|
||||
._user_heap : {
|
||||
. = ALIGN(0x4) ;
|
||||
__heap_start = .;
|
||||
} > REGION_BSS
|
||||
|
||||
._pdata_w 0x28800000 (NOLOAD): {
|
||||
*(.psram.src)
|
||||
}
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
}
|
||||
|
||||
|
||||
/* ROM Functions */
|
||||
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
|
||||
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
|
||||
|
||||
/* INPUT(romcode.ld) */
|
||||
|
||||
46
project/utilities/gdb.init
Normal file
46
project/utilities/gdb.init
Normal file
@@ -0,0 +1,46 @@
|
||||
# ROM Writable : SYSCTRL->SYS_CON3[4]
|
||||
# set *(unsigned int *)0x40020010=0x08000010
|
||||
|
||||
# watchdog close : WDT->WDTKEY
|
||||
set *(unsigned int *)0x400C1004=0xdddd
|
||||
set *(unsigned int *)0x400C1014=0xdddd
|
||||
#//LP WDT
|
||||
set *(unsigned int*)0x400180b8=0xe8
|
||||
set *(unsigned int*)0x400180b4=0xdddd
|
||||
set *(unsigned int*)0x400180bc=0xC053781B
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020000=0x3fac87e4
|
||||
# stop cpu1
|
||||
#set *(unsigned int *)0x4002019c=0x0
|
||||
# sysclk = osc : SYSCTRL->CLK_CON0
|
||||
#set *(unsigned int *)0x40020044=0x00000001
|
||||
# ROM writeable : SYSCTRL->SYS_CON3 BIT(4)
|
||||
#set *(unsigned int *)0x40020010=0x00802138
|
||||
# ROM Writable : SYSCTRL->SYS_CON6
|
||||
#set *(unsigned int *)0x4002001c=0x01C0CCA4
|
||||
# CQSPI IO MAP : GPIOB->AFRL, default 0
|
||||
# CQSPI IO MAP : GPIOB->MODE
|
||||
#set *(unsigned int *)0x40020B00=0x02AA0000
|
||||
# QSPI clk : QSPI->CONFIG
|
||||
#set *(unsigned int *)0x40000000=0x00200081
|
||||
# SPIFLASH write enable : QSPI->FLASH_CMD_CTRL
|
||||
#set *(unsigned int *)0x40000090=0x06000001
|
||||
# QUAL MODE enable : QSPI->FLASH_CMD_WDATA_L && QSPI->FLASH_CMD_CTRL
|
||||
#set *(unsigned int *)0x400000A8=0x2
|
||||
#set *(unsigned int *)0x40000090=0x31008001
|
||||
|
||||
# QSPI DUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0801003B
|
||||
# QSPI QUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0802006B
|
||||
|
||||
# chip erase : QSPI->FLASH_CMD_CTRL
|
||||
#set *(unsigned int *)0x40000090=0xC7000001
|
||||
# delay 4000ms
|
||||
#shell sleep 7s
|
||||
#shell ping -c 3 -w 5 android.xx.xxx.com
|
||||
#shell ping -c 10 -i 5 www.google.com
|
||||
|
||||
#restore ../txw4302803/Obj/txw4302_core.ihex
|
||||
#restore ./Obj/txw4302_app.ihex
|
||||
|
||||
86
project/utilities/gdb_flash_24Mhz.init
Normal file
86
project/utilities/gdb_flash_24Mhz.init
Normal file
@@ -0,0 +1,86 @@
|
||||
#set breakpoint always-inserted on
|
||||
# watchdog close : WDT->WDTKEY
|
||||
set *(unsigned int *)0x400c1004=0xdddd
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020000=0x3fac87e4
|
||||
# sysclk = osc : SYSCTRL->CLK_CON0
|
||||
set *(unsigned int *)0x40020044=0x00000009
|
||||
set *(unsigned int *)0x40020048=0x00000000
|
||||
# ROM Writable : SYSCTRL->SYS_CON3[4]
|
||||
set *(unsigned int *)0x40020010=0x08000010
|
||||
#set *(unsigned int *)0x00000000=0x180000E8
|
||||
|
||||
# MONITOR disable : SYSMNT CTRL
|
||||
set *(unsigned int *)0x40021300=0x0
|
||||
set *(unsigned int *)0x40021308=0x1
|
||||
|
||||
# CQSPI IO MAP: GPIOB->PUPL/H
|
||||
set *(unsigned int *)0x40020B10=0x00111111
|
||||
set *(unsigned int *)0x40020B14=0x00000000
|
||||
# CQSPI IO MAP : GPIOB->MODE
|
||||
set *(unsigned int *)0x40020B00=0x00000000
|
||||
# CQSPI IO MAP : SYSCTRL->QSPI_MAP_CON
|
||||
set *(unsigned int *)0x40020184=0x00053A21
|
||||
|
||||
# VCC_FLASH POWER ON
|
||||
# pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
|
||||
# pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 | BIT(23)); \
|
||||
set *(unsigned int *)0x400180B8=0x00000044
|
||||
set *(unsigned int *)0x400180B4=0x32c046a4
|
||||
set *(unsigned int *)0x400180BC=0xc053781b
|
||||
set *(unsigned int *)0x400180B8=0x00000010
|
||||
set *(unsigned int *)0x400180B4=0x20880400
|
||||
set *(unsigned int *)0x400180BC=0xc053781b
|
||||
# QSPI clk(96Mhz source) : QSPI->CONFIG
|
||||
#set *(unsigned int *)0x40000000=0x00F90081
|
||||
set *(unsigned int *)0x40000000=0x80883881
|
||||
# QSPI clk(96Mhz source) : QSPI->CONFIG
|
||||
#READ_DATA_CAPTURE
|
||||
set *(unsigned int *)0x40000010=0x00000003
|
||||
# QSPI DELAY: QSPI->DEV_DELAY
|
||||
set *(unsigned int *)0x4000000C=0x02020202
|
||||
# QSPI write protect low addr : QSPI->WRITE_PROT_L
|
||||
set *(unsigned int *)0x40000050=0x00000000
|
||||
# QSPI write protect high addr : QSPI->WRITE_PROT_H
|
||||
set *(unsigned int *)0x40000054=0x00020000
|
||||
# QSPI write protect enable : QSPI->WRITE_PROT_CTRL
|
||||
set *(unsigned int *)0x40000058=0x0
|
||||
|
||||
# FLASH reset
|
||||
set *(unsigned int *)0x40000090=0x66000001
|
||||
set *(unsigned int *)0x40000090=0x99000001
|
||||
|
||||
# SPIFLASH write enable : QSPI->FLASH_CMD_CTRL
|
||||
set *(unsigned int *)0x40000090=0x06000001
|
||||
# QUAL MODE enable : QSPI->FLASH_CMD_WDATA_L && QSPI->FLASH_CMD_CTRL
|
||||
set *(unsigned int *)0x400000A8=0x0200
|
||||
set *(unsigned int *)0x40000090=0x01009001
|
||||
|
||||
# QSPI DUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0801003B
|
||||
# QSPI QUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0802006B
|
||||
set *(unsigned int *)0x40000004=0x0802006B
|
||||
|
||||
#READ_DATA_CAPTURE_EXT
|
||||
|
||||
# QSPI poll disable
|
||||
#set *(unsigned int *)0x40000038=0x00014005
|
||||
# QSPI WEL disable
|
||||
#set *(unsigned int *)0x40000008=0x00000102
|
||||
|
||||
# scramble enable
|
||||
#set *(unsigned int *)0x40020188=0x80000000
|
||||
|
||||
# chip erase : QSPI->FLASH_CMD_CTRL
|
||||
#set *(unsigned int *)0x40000090=0xC7000001
|
||||
# delay 4000ms
|
||||
#shell sleep 7s
|
||||
#shell ping -c 3 -w 5 android.xx.xxx.com
|
||||
shell ping -c 10 -i 5 www.google.com
|
||||
|
||||
#softreset
|
||||
#set $chr=0xabcd0009
|
||||
set $pc=0x10040190
|
||||
|
||||
|
||||
234
project/utilities/gdb_psram_both.init
Normal file
234
project/utilities/gdb_psram_both.init
Normal file
@@ -0,0 +1,234 @@
|
||||
#set breakpoint always-inserted on
|
||||
# watchdog close : WDT->WDTKEY
|
||||
set *(unsigned int *)0x400C1004=0xdddd
|
||||
set *(unsigned int *)0x400C1014=0xdddd
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020000=0x3fac87e4
|
||||
#set *(unsigned int *)0x40020000=~0x0fac87e4
|
||||
|
||||
#/* msrom */
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020000=0x3fac87e4
|
||||
# ROM Writable : SYSCTRL->SYS_CON3[4]
|
||||
set *(unsigned int *)0x40020010=0x00000010
|
||||
|
||||
|
||||
set *(unsigned int *)0x4002019c=0x0
|
||||
# sysclk = osc : SYSCTRL->CLK_CON0
|
||||
set *(unsigned int *)0x40020044=0x0000000b
|
||||
set *(unsigned int *)0x40020048=0x00000000
|
||||
# ROM Writable : SYSCTRL->SYS_CON3[4]
|
||||
set *(unsigned int *)0x40020010=0x08000010
|
||||
#set *(unsigned int *)0x00000000=0x180000E8
|
||||
|
||||
|
||||
#rst pin cfg
|
||||
set *(unsigned int *)0x400e0000 = 0x40000000
|
||||
set *(unsigned int *)0x400e0024 = 0x00008000
|
||||
|
||||
#reset
|
||||
#SYSCTRL->CLK_CON4 &= ~BIT(20);
|
||||
#delay_ms(10);
|
||||
#SYSCTRL->CLK_CON4 |= BIT(20);
|
||||
#delay_ms(10);
|
||||
set *(unsigned int *)0x40020040= (*(unsigned int *)0x40020040 & 0xfffeffff)
|
||||
set *(unsigned int *)0x40020040= (*(unsigned int *)0x40020040 | 0x00010000)
|
||||
|
||||
#0xe3ff4a57 60MHZ 0xe2ff4a57 80MHZ
|
||||
set *(unsigned int *)0x40020054=0xe2ff4a57
|
||||
|
||||
#odd_even clk (8/16wire)
|
||||
#SYSCTRL->SYS_CON15 |= (BIT(14) | BIT(15));
|
||||
set *(unsigned int *)0x40020040= (*(unsigned int *)0x40020040 | 0x0000c000)
|
||||
|
||||
|
||||
#SET IO
|
||||
#restore ./utilities/ospi_io_cfg binary 0x400201A8
|
||||
#set *(unsigned int *)0x400201cc = 0
|
||||
set *(unsigned int *)0x400201a8 = 0x01871404
|
||||
set *(unsigned int *)0x400201ac = 0x16a4a0e6
|
||||
set *(unsigned int *)0x400201c4 = 0x2728c1ac
|
||||
set *(unsigned int *)0x400201c8 = 0x000bdab4
|
||||
set *(unsigned int *)0x400201cc = 0x00000000
|
||||
set *(unsigned int *)0x400201d0 = 0xffffffff
|
||||
set *(unsigned int *)0x400201d4 = 0xffffffff
|
||||
|
||||
#OSPI CFG
|
||||
restore ./utilities/ospi_cfg binary 0x40001000
|
||||
|
||||
set *(unsigned int *)0x400201d0 = 0xffffffff
|
||||
set *(unsigned int *)0x400201d4 = 0xffffffff
|
||||
|
||||
|
||||
#p_qspi->PHY_CONFIG = (p_qspi->PHY_CONFIG & ~(0x7FUL << 16)) | ((delay & 0x7FUL) << 16) | BIT(30);
|
||||
# rx0, tx
|
||||
set *(unsigned int*)0x400010b4 = (*(unsigned int*)0x400010b4 & (~0xffffff)) | (2) | (12 << 16)
|
||||
# rx1
|
||||
set *(unsigned int*)0x400010c4 = (*(unsigned int*)0x400010c4 & (~0xff)) | (2)
|
||||
#p_qspi->PHY_CONFIG = (p_qspi->PHY_CONFIG & ~(0x7FUL << 0)) | ((delay & 0x7FUL) << 0) | BIT(30);
|
||||
#p_qspi->NEW_ADD_CONFIG3 = (p_qspi->NEW_ADD_CONFIG3 & ~(0x7FUL << 0)) | ((delay & 0x7FUL) << 0);
|
||||
set *(unsigned int *)0x400010b4 = (*(unsigned int *)0x400010b4 & 0x7fffffff)
|
||||
set *(unsigned int *)0x400010b4 = (*(unsigned int *)0x400010b4 | 0x80000000)
|
||||
shell ping -c 10 -i 5 www.google.com
|
||||
#rwreg start
|
||||
#p_qspi->NEW_ADD_CONFIG2 = (p_qspi->NEW_ADD_CONFIG2 & ~(0x1UL << 22)) | ((0x1UL) << 22);
|
||||
set *(unsigned int *)0x400010d4 = 0x00d03f3f
|
||||
shell ping -c 10 -i 5 www.google.com
|
||||
|
||||
|
||||
#OSPI->DEV_WRINSTR_CONFIG = WR_OPC(wr_opc) | WEL_DISEN(0x1) | ADDR_TM(0x3) | DATA_TM(0x3) | WR_DUMMY(wr_dummy);
|
||||
set *(unsigned int *)0x40001008 = 0x00033160
|
||||
set *(unsigned int *)0x40001004 = 0x03033fe0
|
||||
set *(unsigned int *)0x4000100C = 0x02020202
|
||||
|
||||
#reset
|
||||
|
||||
|
||||
#dummy & various lc
|
||||
set *(unsigned short *)0x28001000 = 0x8f07
|
||||
|
||||
#OSPI->DEV_WRINSTR_CONFIG = WR_OPC(wr_opc) | WEL_DISEN(0x1) | ADDR_TM(0x3) | DATA_TM(0x3) | WR_DUMMY(wr_dummy);
|
||||
#OSPI->DEV_RDINSTR_CONFIG = WR_OPC(wr_opc) | WEL_DISEN(0x1) | ADDR_TM(0x3) | DATA_TM(0x3) | WR_DUMMY(wr_dummy);
|
||||
set *(unsigned int *)0x40001004 = 0x05033fa0
|
||||
set *(unsigned int *)0x40001008 = 0x05033120
|
||||
|
||||
#rwreg end
|
||||
#p_qspi->NEW_ADD_CONFIG2 = (p_qspi->NEW_ADD_CONFIG2 & ~(0x1UL << 22)) | ((0x0UL) << 22) ;
|
||||
set *(unsigned int *)0x400010d4 = 0x00903f3f
|
||||
|
||||
#reset
|
||||
#set *(unsigned int *)0x40020040= (*(unsigned int *)0x40020040 | 0x0000c000)
|
||||
#0xe3ff4a57 60MHZ 0xe2ff4a57 80MHZ
|
||||
set *(unsigned int *)0x40020054=0xe4ff4a57
|
||||
|
||||
|
||||
# load cpu1 psram code
|
||||
#restore ./../txw4302803/Obj/txw4302_core.ihex
|
||||
#restore ./../txw4302803/txw4302803.bin binary 0x28000000
|
||||
#restore ./../txw4302803/Obj/txw4302_core.elf
|
||||
#tb sys_main_loop
|
||||
#restore ./../txw4302803/Obj/txw4302_core.elf
|
||||
#tb sys_main_loop
|
||||
|
||||
|
||||
|
||||
|
||||
#set breakpoint always-inserted on
|
||||
# watchdog close : WDT->WDTKEY
|
||||
set *(unsigned int *)0x400c1004=0xdddd
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020000=0x3fac87e4
|
||||
# sysclk = osc : SYSCTRL->CLK_CON0
|
||||
set *(unsigned int *)0x40020044=0x00000009
|
||||
set *(unsigned int *)0x40020048=0x00000000
|
||||
# ROM Writable : SYSCTRL->SYS_CON3[4]
|
||||
set *(unsigned int *)0x40020010=0x08000010
|
||||
#set *(unsigned int *)0x00000000=0x180000E8
|
||||
|
||||
|
||||
|
||||
|
||||
# MONITOR disable : SYSMNT CTRL
|
||||
set *(unsigned int *)0x40021300=0x0
|
||||
set *(unsigned int *)0x40021308=0x1
|
||||
|
||||
|
||||
|
||||
|
||||
# CQSPI IO MAP: GPIOB->PUPL/H
|
||||
set *(unsigned int *)0x40020B10=0x00111111
|
||||
set *(unsigned int *)0x40020B14=0x00000000
|
||||
# CQSPI IO MAP : GPIOB->MODE
|
||||
set *(unsigned int *)0x40020B00=0x00000000
|
||||
# CQSPI IO MAP : SYSCTRL->QSPI_MAP_CON
|
||||
set *(unsigned int *)0x40020184=0x00053A21
|
||||
|
||||
|
||||
|
||||
|
||||
# VCC_FLASH POWER ON
|
||||
# pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
|
||||
# pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 | BIT(23)); \
|
||||
set *(unsigned int *)0x400180B8=0x00000044
|
||||
set *(unsigned int *)0x400180B4=0x32c046a4
|
||||
set *(unsigned int *)0x400180BC=0xc053781b
|
||||
set *(unsigned int *)0x400180B8=0x00000010
|
||||
set *(unsigned int *)0x400180B4=0x20880400
|
||||
set *(unsigned int *)0x400180BC=0xc053781b
|
||||
# QSPI clk(96Mhz source) : QSPI->CONFIG
|
||||
#set *(unsigned int *)0x40000000=0x00F90081
|
||||
set *(unsigned int *)0x40000000=0x80883881
|
||||
# QSPI clk(96Mhz source) : QSPI->CONFIG
|
||||
#READ_DATA_CAPTURE
|
||||
set *(unsigned int *)0x40000010=0x00000003
|
||||
# QSPI DELAY: QSPI->DEV_DELAY
|
||||
set *(unsigned int *)0x4000000C=0x02020202
|
||||
# QSPI write protect low addr : QSPI->WRITE_PROT_L
|
||||
set *(unsigned int *)0x40000050=0x00000000
|
||||
# QSPI write protect high addr : QSPI->WRITE_PROT_H
|
||||
set *(unsigned int *)0x40000054=0x00020000
|
||||
# QSPI write protect enable : QSPI->WRITE_PROT_CTRL
|
||||
set *(unsigned int *)0x40000058=0x0
|
||||
|
||||
|
||||
|
||||
|
||||
# FLASH reset
|
||||
set *(unsigned int *)0x40000090=0x66000001
|
||||
set *(unsigned int *)0x40000090=0x99000001
|
||||
|
||||
|
||||
|
||||
|
||||
# SPIFLASH write enable : QSPI->FLASH_CMD_CTRL
|
||||
set *(unsigned int *)0x40000090=0x06000001
|
||||
# QUAL MODE enable : QSPI->FLASH_CMD_WDATA_L && QSPI->FLASH_CMD_CTRL
|
||||
set *(unsigned int *)0x400000A8=0x0200
|
||||
set *(unsigned int *)0x40000090=0x01009001
|
||||
|
||||
|
||||
|
||||
|
||||
# QSPI DUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0801003B
|
||||
# QSPI QUAL MODE : QSPI->DEV_RDINSTR_CONFIG
|
||||
#set *(unsigned int *)0x40000004=0x0802006B
|
||||
set *(unsigned int *)0x40000004=0x0802006B
|
||||
|
||||
|
||||
|
||||
|
||||
#READ_DATA_CAPTURE_EXT
|
||||
|
||||
|
||||
|
||||
|
||||
# QSPI poll disable
|
||||
#set *(unsigned int *)0x40000038=0x00014005
|
||||
# QSPI WEL disable
|
||||
#set *(unsigned int *)0x40000008=0x00000102
|
||||
|
||||
|
||||
|
||||
|
||||
# scramble enable
|
||||
#set *(unsigned int *)0x40020188=0x80000000
|
||||
|
||||
|
||||
|
||||
|
||||
# chip erase : QSPI->FLASH_CMD_CTRL
|
||||
#set *(unsigned int *)0x40000090=0xC7000001
|
||||
|
||||
|
||||
|
||||
|
||||
#softreset
|
||||
#set $chr=0xabcd0009
|
||||
set $pc=*(unsigned int *)0x10040000
|
||||
|
||||
|
||||
|
||||
|
||||
# sysctrl writable : SYSCTRL->SYS_KEY
|
||||
set *(unsigned int *)0x40020028=0x00300000
|
||||
BIN
project/utilities/ospi_80_80cfg
Normal file
BIN
project/utilities/ospi_80_80cfg
Normal file
Binary file not shown.
BIN
project/utilities/ospi_cfg
Normal file
BIN
project/utilities/ospi_cfg
Normal file
Binary file not shown.
BIN
project/utilities/ospi_io_cfg
Normal file
BIN
project/utilities/ospi_io_cfg
Normal file
Binary file not shown.
458
project/utilities/romcode.ld
Normal file
458
project/utilities/romcode.ld
Normal file
@@ -0,0 +1,458 @@
|
||||
ll_spi_init = 0x00007d6c;
|
||||
hgusb20_intr_dis = 0x00006bd4;
|
||||
ll_spi_rx = 0x00007f2c;
|
||||
strcpy = 0x00001820;
|
||||
ll_uart_txdma_kick = 0x00006a74;
|
||||
sdio_s_set_ds = 0x00003a14;
|
||||
hgusb20_clear_ep = 0x00006e70;
|
||||
sys_aes_init = 0x00007d10;
|
||||
fabs = 0x000001a8;
|
||||
disable_wphy_device_cont_tx = 0x0000618c;
|
||||
config_wphy_device_dpd_coef = 0x00006300;
|
||||
sys_aes_key_bitlen_sel = 0x00007cec;
|
||||
ll_simple_spi_init = 0x0000a674;
|
||||
hgusb20_irq_dma = 0x00007734;
|
||||
fw_upg_addr = 0x2005247c;
|
||||
crc16_modbus_calc = 0x00003018;
|
||||
close_wphy = 0x0000adb0;
|
||||
ll_iic_slave_rx = 0x0000828c;
|
||||
hgusb20_wifi_reset = 0x00007a8c;
|
||||
ll_crc_start = 0x00006afc;
|
||||
ll_m2m_memcpy = 0x000082fc;
|
||||
os_critical_close = 0x00001b2c;
|
||||
hgusb20_irq_set = 0x00007678;
|
||||
printf = 0x00001080;
|
||||
stdout = 0x20052420;
|
||||
ll_sdio_s_tx_kick = 0x000092f0;
|
||||
hgusb20_ep0_clrrx_pkt0 = 0x00006d30;
|
||||
uart_s_set_speed = 0x000042b4;
|
||||
get_wphy_device_avg_evm = 0x00006164;
|
||||
tbl_usb_language_id = 0x0000e06c;
|
||||
sdio_s_tx = 0x00003ab4;
|
||||
config_phy_tx_norm_mode = 0x0000ae6c;
|
||||
get_wphy_device_gfsk_tx_crc = 0x000063c4;
|
||||
ll_wdt_feed = 0x000064d4;
|
||||
ll_timer_ir_enable = 0x00007c64;
|
||||
ll_spi_buf_rx = 0x00007fd4;
|
||||
spiflash_boot = 0x00005eb8;
|
||||
md5_vector = 0x0000bc3c;
|
||||
ll_clock_syspll_config = 0x0000961c;
|
||||
ll_clock_hirc_enable = 0x00009370;
|
||||
fw_upg_blk_addr = 0x20052480;
|
||||
ll_uart_init = 0x00006860;
|
||||
tbl_usb_str_manufacturer = 0x0000e070;
|
||||
spi_cfg = 0x0000debc;
|
||||
strerror = 0x00002d48;
|
||||
config_phy_tx_sine_mode = 0x0000ae2c;
|
||||
ll_spi_config = 0x00007d88;
|
||||
hgwphy_bgn_attach = 0x0000b18c;
|
||||
qspi_flash_port_deinit = 0x00004df8;
|
||||
usb20 = 0x2004768c;
|
||||
ll_sys_clock_globle_set = 0x0000abfc;
|
||||
ll_m2m_memset = 0x00008320;
|
||||
hgusb20_ep0_clr_feature = 0x00006fdc;
|
||||
sdio_boot = 0x20052468;
|
||||
ll_tk_stop = 0x0000a664;
|
||||
hgusb20_dev_reset = 0x00006f1c;
|
||||
ll_gpio_iomap_output_config = 0x0000650c;
|
||||
get_wphy_device_rx_gain_para = 0x00006374;
|
||||
ll_sdio_s_irq_config = 0x0000925c;
|
||||
atol = 0x000014f4;
|
||||
ll_iic_master_tx = 0x00008190;
|
||||
ll_simple_uart_init = 0x0000a6f0;
|
||||
hgusb20_stall_ep = 0x00006df0;
|
||||
tbl_winusb_device_descriptor = 0x0000e1ac;
|
||||
ll_clock_set_sys_clk_src = 0x000093c4;
|
||||
ll_sys_clock_init = 0x0000abb8;
|
||||
hgusb20_ep0_get_status = 0x00006f64;
|
||||
config_dpd = 0x0000afb0;
|
||||
SHA1Update = 0x0000cbd8;
|
||||
ll_gmac_get_tx_frame_status = 0x00008cac;
|
||||
ll_qspi_controller_init = 0x00009224;
|
||||
sha256_init = 0x0000cee0;
|
||||
errno = 0x200524d0;
|
||||
open_wphy = 0x0000ace8;
|
||||
hgusb20_dev_init = 0x00006d88;
|
||||
ll_qspi_set_prefetch = 0x00009170;
|
||||
ll_gpio_pull_config = 0x00006680;
|
||||
tbl_winusb_compatible_id_feature_descriptor = 0x0000e184;
|
||||
get_wphy_avg_evm = 0x0000aea4;
|
||||
ll_spi_dma_start = 0x00007e7c;
|
||||
uart_s_rx = 0x0000431c;
|
||||
CORE_SEC_OPT = 0x0000932c;
|
||||
trig_calc_bk_noise = 0x0000b0d4;
|
||||
sha256_done = 0x0000cff0;
|
||||
spi_boot = 0x20052674;
|
||||
freq_offset_sign_ext = 0x0000b178;
|
||||
sys_aes_start = 0x00007d2c;
|
||||
SHA1Init = 0x0000cba8;
|
||||
ll_tk_ch_kick = 0x0000a658;
|
||||
ll_iic_master_rx = 0x000081c8;
|
||||
spi_s_tx = 0x00003e8c;
|
||||
enable_auto_sig_err_rst = 0x0000af9c;
|
||||
qspi_flash_poweroff = 0x00004ec8;
|
||||
fwinfo_check_fwinfo_hdr = 0x000044f8;
|
||||
hgusb20_irq_handler_set = 0x00007658;
|
||||
ll_iic_master_buf_tx = 0x00008218;
|
||||
ll_spi_dma_config = 0x00007e54;
|
||||
config_wphy_device_en_gfsk_wphy = 0x000063b0;
|
||||
memcpy = 0x00001908;
|
||||
hgusb20_ep0_set_feature = 0x00007020;
|
||||
sys_aes_get_pending = 0x00007cfc;
|
||||
atcmd_fwupg = 0x0000d8e0;
|
||||
ll_m2m_dma_init = 0x000082a4;
|
||||
fw_upg_prepare = 0x00004534;
|
||||
tbl_winusb20_wcidbos = 0x0000e160;
|
||||
spiflash_read = 0x00005ab0;
|
||||
ll_qspi_set_write_protect = 0x00009130;
|
||||
puts = 0x000010b8;
|
||||
hgusb20_ep0_set_configuration = 0x00007294;
|
||||
ll_tk_config = 0x0000a584;
|
||||
sys_aes_set_irq = 0x00007cb0;
|
||||
hgusb20_ep0_get_wcid_descriptor = 0x00007360;
|
||||
ll_gmac_start = 0x00008684;
|
||||
crc16_modbus_cfg = 0x0000d870;
|
||||
ll_iis_disable = 0x0000848c;
|
||||
hgusb20_ep0_func = 0x000074ec;
|
||||
ll_clock_test_clk_en = 0x00009350;
|
||||
ll_iic_irq_config = 0x000080c0;
|
||||
get_wphy_device_rx_gfsk_gain_para = 0x00006388;
|
||||
hgusb20_reset2device_mode = 0x00006b38;
|
||||
ll_gpio_analog_config = 0x000064ec;
|
||||
hgusb20_ep0_descriptor = 0x00007150;
|
||||
hgusb20_dev_rx = 0x000048a0;
|
||||
ll_suptmr_deinit = 0x00009ed4;
|
||||
strtoll = 0x00001518;
|
||||
ll_qspi_cmd_quad_enable = 0x00008e74;
|
||||
crc32_calc = 0x0000303c;
|
||||
ll_gmac_init = 0x00008504;
|
||||
qspi_flash_power_reset = 0x00004ef0;
|
||||
disable_wphy = 0x0000acb4;
|
||||
xmodem_receive = 0x00004ac0;
|
||||
strtoul = 0x00001198;
|
||||
ll_iic_master_buf_rx = 0x0000825c;
|
||||
config_wphy_device_cca_th = 0x00006224;
|
||||
adj_gain_value = 0x0000afc0;
|
||||
ll_gmac_send_frame = 0x00008a7c;
|
||||
ll_ir_timer_irq_config = 0x00007afc;
|
||||
hgusb20_switch_stable_device = 0x00006bc4;
|
||||
get_wphy_err_code = 0x0000aeb0;
|
||||
ll_led_timer_deinit = 0x00009da8;
|
||||
uart_s_tx = 0x000042ec;
|
||||
ll_iis_soft_rst = 0x00008494;
|
||||
isspace = 0x0000106c;
|
||||
boot = 0x200524d8;
|
||||
ll_crc_init = 0x00006a98;
|
||||
ll_spi_set_wire_mode = 0x00007e88;
|
||||
get_wphy_device_gfsk_rx_crc = 0x000063dc;
|
||||
ll_simple_spi_deinit = 0x0000a67c;
|
||||
ll_gmac_irq_config = 0x00008600;
|
||||
config_phy_tx_waveform_mode = 0x0000b158;
|
||||
ll_timer_deinit = 0x00007a98;
|
||||
sdio_slave_init = 0x00003d18;
|
||||
enable_wphy_device = 0x00006114;
|
||||
ll_crc_deinit = 0x00006ab4;
|
||||
usb_irq_ids = 0x200524a4;
|
||||
usb_test_mode_tbl = 0x0000df98;
|
||||
hgusb20_ep_set_txrdy = 0x00007998;
|
||||
strncasecmp = 0x00004c3c;
|
||||
ll_simple_uart_irq_config = 0x0000a708;
|
||||
sha256_vector = 0x0000d0e8;
|
||||
ll_clock_set_apb0_div = 0x000093fc;
|
||||
ll_timer_sync_start = 0x00007c7c;
|
||||
MD5Final = 0x0000bbc4;
|
||||
sdio_port_init = 0x00003b18;
|
||||
hgusb20_ep0_tx = 0x00006cb4;
|
||||
qspi_flash_deinit = 0x0000503c;
|
||||
config_wphy_device_gfsk_crc_init = 0x000063f4;
|
||||
ll_spi_deinit = 0x00007d7c;
|
||||
tbl_winusb20_wcid_descriptor_set = 0x0000e0bc;
|
||||
tbl_winusb_device_interface_guids = 0x0000e1c0;
|
||||
Te0 = 0x0000e8f8;
|
||||
ll_qspi_cmd_enter_qpi_mode = 0x00008eec;
|
||||
ll_ir_timer_config = 0x00007bd8;
|
||||
strtol = 0x00001298;
|
||||
crc32_cfg = 0x0000d88c;
|
||||
usb_test_packet = 0x0000dfa0;
|
||||
ll_spi_buf_tx = 0x00007f54;
|
||||
adj_gfsk_gain_value = 0x0000affc;
|
||||
ll_gmac_config = 0x00008554;
|
||||
uart_s_set_ds = 0x000042cc;
|
||||
config_cca_th = 0x0000af60;
|
||||
cfg_wphy_gfsk_ch = 0x0000b0c4;
|
||||
hgusb20_irq = 0x00007798;
|
||||
ll_uart_deinit = 0x00006874;
|
||||
spiflash_init = 0x000058a4;
|
||||
tbl_usb_str_serial_number = 0x0000e09c;
|
||||
cfg_wphy_gfsk_crc_init = 0x0000b0b4;
|
||||
get_wphy_device_tx_psdu_crc = 0x0000629c;
|
||||
strtod = 0x00001b6c;
|
||||
ll_suptmr_comm_config = 0x00009eec;
|
||||
spiflash_deinit = 0x000059b0;
|
||||
spi_s_rx_len_exp = 0x20052478;
|
||||
ll_gmac_setup_send_frame = 0x00008af8;
|
||||
ll_gpio_iomap_input_config = 0x0000655c;
|
||||
atof = 0x0000150c;
|
||||
ll_iic_dma_config = 0x00008154;
|
||||
disable_rx_agc = 0x0000af28;
|
||||
disable_auto_sig_err_rst = 0x0000af88;
|
||||
disable_gfsk_wphy = 0x0000b068;
|
||||
config_wphy_device_gfsk_ch = 0x00006408;
|
||||
sdio_s_rx = 0x00003ac4;
|
||||
ll_tk_sf_kick = 0x0000a638;
|
||||
strcat = 0x000018ec;
|
||||
ll_spi_irq_config = 0x00007dfc;
|
||||
hgusb20_init = 0x0000762c;
|
||||
sys_aes_set_mode = 0x00007cc4;
|
||||
adjust_wphy_device_gain_value = 0x00006328;
|
||||
tbl_usb_str_product = 0x0000e080;
|
||||
ll_tk_deinit = 0x0000a53c;
|
||||
sha256_process = 0x0000cf30;
|
||||
get_rx_freq_offset = 0x0000aed0;
|
||||
config_phy_tx_tri_mode = 0x0000ae4c;
|
||||
tbl_usb_config_all_descriptor_wifi = 0x0000e040;
|
||||
config_wphy_device_tx_tri_mode = 0x00006244;
|
||||
hgusb20_bot_reset = 0x00006ee0;
|
||||
sdio_rx_len_exp = 0x20052470;
|
||||
Td0 = 0x0000e3f8;
|
||||
ll_sdio_s_rx_kick = 0x00009320;
|
||||
ll_led_timer_init = 0x00009d9c;
|
||||
os_critical_enter = 0x00001b24;
|
||||
fw_upg_program = 0x00004578;
|
||||
ll_timer_ir_set_code_0 = 0x00007c74;
|
||||
sdio_s_set_speed = 0x00003aa8;
|
||||
ll_gpio_pin_lock_config = 0x00006810;
|
||||
ll_clock_exosc_enable = 0x00009398;
|
||||
uart_s_xfer_done = 0x20052488;
|
||||
soft_dereset_phy = 0x0000ac74;
|
||||
ll_timer_ir_disable = 0x00007c6c;
|
||||
sys_aes_set_block_num = 0x00007ca4;
|
||||
ll_uart_work_mode_change = 0x00006a84;
|
||||
memchr = 0x00001ae8;
|
||||
ll_qspi_cmd_device_reset = 0x00008fb8;
|
||||
stdin = 0x20052440;
|
||||
ll_spi_tx = 0x00007ef0;
|
||||
enable_rx_agc = 0x0000af3c;
|
||||
ll_spi_set_clock_mode = 0x00007ec4;
|
||||
delay_ms_systick = 0x0000aae8;
|
||||
qspi_flash_port_init = 0x00004d54;
|
||||
rand = 0x00001170;
|
||||
ll_uart_dma_config = 0x00006a34;
|
||||
ll_gmac_get_rx_frame_status = 0x00008cc4;
|
||||
enable_gfsk_wphy = 0x0000b03c;
|
||||
SysTickCnt = 0x200524bc;
|
||||
ll_gpio_iomap_inout_config = 0x000065fc;
|
||||
get_wphy_scrambler_init = 0x0000ae8c;
|
||||
enable_wphy_cont_tx = 0x0000acb8;
|
||||
ll_timer_config = 0x00007b3c;
|
||||
isupper = 0x00001b04;
|
||||
qspi_flash_init = 0x00004f20;
|
||||
ll_iic_dma_start = 0x00008184;
|
||||
ll_timer_irq_config = 0x00007a9c;
|
||||
ll_timer_start = 0x00007c54;
|
||||
ll_crc_stop = 0x00006b30;
|
||||
ll_led_config = 0x00009c24;
|
||||
hgusb20_wifi_init = 0x000079c4;
|
||||
ll_sdio_s_config = 0x00009264;
|
||||
sdio_interrupt_handle = 0x00003c54;
|
||||
ll_led_timer_irq_config = 0x00009e24;
|
||||
ll_qspi_set_clk = 0x000091a8;
|
||||
strcasecmp = 0x00004bf8;
|
||||
get_wphy_device_err_code = 0x000061b4;
|
||||
ll_iis_dma_config = 0x00008470;
|
||||
spi_base_pins = 0x0000de84;
|
||||
get_rx_gain_para = 0x0000afd8;
|
||||
hgusb20_wifi_ep_init = 0x000079c8;
|
||||
qspi_flash_poweron = 0x00004ea0;
|
||||
ll_gmac_mdio_read = 0x000088b4;
|
||||
ll_crc_config = 0x00006ab8;
|
||||
hgusb20_ep0_clrrx_contious = 0x00006d04;
|
||||
os_critical_exit = 0x00001b28;
|
||||
ll_iis_config = 0x0000835c;
|
||||
get_wphy_device_scrambler_init = 0x00006134;
|
||||
memcmp = 0x0000199c;
|
||||
hgusb20_ep0_get_descriptor = 0x0000719c;
|
||||
ll_qspi_cmd_release_power_down = 0x00009020;
|
||||
ll_gmac_mdio_write = 0x000086cc;
|
||||
adjust_wphy_device_gfsk_gain_value = 0x00006340;
|
||||
crc16_xmodem = 0x00004a90;
|
||||
isalpha = 0x00001b0c;
|
||||
ll_timer_init = 0x00007a94;
|
||||
disable_wphy_device = 0x00006124;
|
||||
crc8_calc = 0x00002ff4;
|
||||
config_wphy_device_tx_sine_mode = 0x00006234;
|
||||
ll_tk_init = 0x0000a520;
|
||||
delay_us = 0x0000aa3c;
|
||||
_ctype = 0x0000dd84;
|
||||
hgusb20_ep_rx_kick = 0x00007898;
|
||||
ll_gmac_deinit = 0x000085c8;
|
||||
disable_wphy_cont_tx = 0x0000acc8;
|
||||
enable_wphy_device_auto_sig_err_rst = 0x000062c4;
|
||||
ll_gmac_stop = 0x00008694;
|
||||
strtoull = 0x000013b8;
|
||||
disable_wphy_device_auto_sig_err_rst = 0x000062d8;
|
||||
rijndaelKeySetupEnc = 0x0000d17c;
|
||||
get_tx_psdu_crc16 = 0x0000acac;
|
||||
ll_iic_slave_tx = 0x00008298;
|
||||
config_wphy_rx_max_gain_state = 0x00006214;
|
||||
memset = 0x00001740;
|
||||
ll_suptmrx_config = 0x0000a02c;
|
||||
ll_m2m_dma_config = 0x000082e8;
|
||||
ll_m2m_dma_irq_config = 0x000082ec;
|
||||
ll_uart232_config = 0x000068fc;
|
||||
delay_ms = 0x0000aa68;
|
||||
hgusb20_ep0_request = 0x000074a8;
|
||||
ll_wdt_stop = 0x000064dc;
|
||||
close_wphy_device = 0x00006090;
|
||||
open_wphy_device = 0x00006080;
|
||||
uart_s_boot = 0x000045d8;
|
||||
srand = 0x0000118c;
|
||||
hgusb20_dev_tx = 0x0000487c;
|
||||
atcmd_bootl = 0x0000d8d8;
|
||||
cp_mode = 0x00002e60;
|
||||
get_wphy_device_rx_freq_offset = 0x0000635c;
|
||||
soft_reset_wphy_device = 0x00006264;
|
||||
config_wphy_device_dpd = 0x000062ec;
|
||||
soft_dereset_wphy_device = 0x00006274;
|
||||
ll_wdt_start = 0x000064c4;
|
||||
ll_wdt_config = 0x00006474;
|
||||
ll_suptmr_init = 0x00009e88;
|
||||
ll_uart_rxdma_kick = 0x00006a64;
|
||||
ll_clock_sys_clk_select = 0x0000942c;
|
||||
hgusb20_int_init_b = 0x00006d60;
|
||||
Td4s = 0x0000e7f8;
|
||||
hgusb20_ep0_class = 0x0000742c;
|
||||
get_wphy_device_tx_crc = 0x0000619c;
|
||||
sdio_s_func1_cis = 0x200475d0;
|
||||
ll_clock_test_clk_sel = 0x0000935c;
|
||||
hgusb20_ep0_set_address = 0x0000708c;
|
||||
spi_s_set_speed = 0x00003f00;
|
||||
ll_iis_init = 0x00008344;
|
||||
strcmp = 0x00001668;
|
||||
ll_iic_init = 0x00008040;
|
||||
config_wphy_device_low_pwr_th = 0x000062b4;
|
||||
ll_iic_deinit = 0x0000804c;
|
||||
ll_iis_irq_config = 0x00008448;
|
||||
ll_iis_deinit = 0x00008350;
|
||||
sys_clock_cfg = 0x200524a8;
|
||||
flash_memory_init = 0x000043f4;
|
||||
cfg_phy_tx_gain = 0x0000ada4;
|
||||
ll_gmac_allow_send_frame = 0x00008a68;
|
||||
ll_gpio_afio_config = 0x00006618;
|
||||
ll_m2m_dma_deinit = 0x000082dc;
|
||||
ll_gpio_ospeed_config = 0x00006828;
|
||||
MD5Init = 0x0000baf8;
|
||||
ll_wdt_deinit = 0x000064b4;
|
||||
os_critical_open = 0x00001b20;
|
||||
strtof = 0x000014e8;
|
||||
sys_aes_set_key = 0x00007c90;
|
||||
hgusb20_config_desc_prepare = 0x00006bec;
|
||||
dev_register = 0x0000641c;
|
||||
ll_led_init = 0x00009bfc;
|
||||
get_wphy_avg_power = 0x0000ae98;
|
||||
stderr = 0x20052400;
|
||||
ll_ir_timer_dma_config = 0x00007c24;
|
||||
ll_clock_usb_clk_en = 0x00009778;
|
||||
ll_timer_stop = 0x00007c5c;
|
||||
ll_qspi_cmd_busy_wait = 0x00008d90;
|
||||
hgusb20_ep_set_rxrdy = 0x00007994;
|
||||
ll_clock_is_exist = 0x00009494;
|
||||
enable_wphy = 0x0000b154;
|
||||
MD5Update = 0x0000bb20;
|
||||
spi_s_set_ds = 0x00003f0c;
|
||||
config_rx_max_gain_state = 0x0000af50;
|
||||
enable_wphy_device_cont_tx = 0x0000617c;
|
||||
fputc = 0x0000a810;
|
||||
config_wphy_device_tx_norm_mode = 0x00006254;
|
||||
tbl_usb_config_all_descriptor_gen = 0x0000e034;
|
||||
ll_simple_uart_config = 0x0000a74c;
|
||||
spi_rx_buf = 0x00005a60;
|
||||
get_rx_gfsk_gain_para = 0x0000b018;
|
||||
tbl_usb_device_descriptor = 0x0000e058;
|
||||
ll_tk_irq_config = 0x0000a540;
|
||||
get_wphy_device_agc_info = 0x000061cc;
|
||||
sysctrl_qspi_get_src_clk = 0x0000a794;
|
||||
hgsdio20_s_func1_cis = 0x0000e27c;
|
||||
isdigit = 0x00001afc;
|
||||
SHA1Final = 0x0000cc68;
|
||||
ll_tk_data = 0x0000a66c;
|
||||
qspi_flash_bootload_code = 0x000054a4;
|
||||
get_wphy_device_avg_power = 0x0000614c;
|
||||
ll_timer_ir_set_code_1 = 0x00007c78;
|
||||
aes_decrypt_encrypt = 0x00004ca4;
|
||||
ll_simple_spi_irq_config = 0x0000a684;
|
||||
spi_s_rx = 0x00003ec0;
|
||||
config_wphy_device_dis_gfsk_wphy = 0x0000639c;
|
||||
ll_spi_set_sample_delay = 0x00007ed4;
|
||||
sdio_s_dummy_buf = 0x2004759c;
|
||||
ll_gmac_receive_frame = 0x00008bb8;
|
||||
config_wphy_device_rx_gain_tab = 0x00006204;
|
||||
ll_led_timer_config = 0x00009db4;
|
||||
ll_qspi_cmd_write_enable = 0x00008e30;
|
||||
enable_wphy_device_rx_agc = 0x000061f4;
|
||||
ll_clock_usbpll_config = 0x00009674;
|
||||
SHA1Transform = 0x0000bc94;
|
||||
hgsdio20_s_speed_list = 0x0000e2b4;
|
||||
ll_uart_irq_config = 0x0000687c;
|
||||
sys_aes_set_key_src = 0x00007cd8;
|
||||
ll_clock_syspll_set = 0x000094e0;
|
||||
ll_simple_spi_config = 0x0000a69c;
|
||||
soft_reset_phy = 0x0000ac8c;
|
||||
ll_gmac_has_received_frame = 0x00008a30;
|
||||
get_wphy_gfsk_tx_crc = 0x0000b094;
|
||||
ll_wdt_init = 0x00006470;
|
||||
ll_qspi_cmd_exit_qpi_mode = 0x00008f64;
|
||||
ll_tk_scan_kick = 0x0000a64c;
|
||||
atoi = 0x00001500;
|
||||
ll_crc_wait_done_pending = 0x00006b20;
|
||||
hgusb20_dev_set_speed = 0x00004870;
|
||||
config_low_pwr_th = 0x0000b12c;
|
||||
ll_qspi_cmd_flash_64kb_erase = 0x00009064;
|
||||
ll_gmac_get_setup_frame_status = 0x00008c94;
|
||||
hgsdio20_s_func0_cis = 0x0000e268;
|
||||
config_wphy_device_tx_gain = 0x00006314;
|
||||
spiflash_bootloader = 0x00005c8c;
|
||||
ll_uart485_config = 0x000069c4;
|
||||
ll_tk_hw_kick = 0x0000a62c;
|
||||
crc8_itu_cfg = 0x0000d8a8;
|
||||
strlen = 0x000017e0;
|
||||
__cskyvprintfprintf = 0x0000109c;
|
||||
get_rx_psdu_crc16 = 0x0000aca4;
|
||||
hgusb20_init_globle = 0x00006b34;
|
||||
sdio_s_func0_cis = 0x200475bc;
|
||||
get_wphy_device_rx_psdu_crc = 0x00006284;
|
||||
get_wphy_device_info = 0x000060a0;
|
||||
sys_aes_clear_pending = 0x00007d04;
|
||||
hgusb20_dev_set_ds = 0x0000486c;
|
||||
rcons = 0x0000ecf8;
|
||||
ll_gmac_delay = 0x000084f0;
|
||||
abs = 0x00001290;
|
||||
strchr = 0x00001988;
|
||||
get_wphy_tx_crc = 0x0000acd8;
|
||||
fputs = 0x00001124;
|
||||
cfg_dpd_coef = 0x0000ad78;
|
||||
ll_qspi_cmd_issue = 0x00008cd4;
|
||||
spi_read_cfg_nor = 0x0000dedc;
|
||||
hgusb20_ep_tx_kick = 0x00007918;
|
||||
ll_crc_continue = 0x00006b08;
|
||||
ll_clock_set_sys_clk_div = 0x000093e4;
|
||||
get_wphy_gfsk_rx_crc = 0x0000b0a4;
|
||||
hgusb20_ep0_transfer = 0x000070cc;
|
||||
ll_iic_config = 0x00008058;
|
||||
ll_simple_uart_deinit = 0x0000a6fc;
|
||||
get_bk_noise = 0x0000b0e4;
|
||||
__jpeg_htable = 0x0000fc00;
|
||||
get_wphy_agc_info = 0x0000aec4;
|
||||
hgusb20_wifi_xfer_reset = 0x00007868;
|
||||
debug_select_interface = 0x0000a7e8;
|
||||
sha1_vector = 0x0000cd2c;
|
||||
ll_spi_get_wire_mode = 0x00007ee8;
|
||||
hgusb20_ep0_standard = 0x000072d4;
|
||||
disable_wphy_device_rx_agc = 0x000061e4;
|
||||
sys_reset = 0x0000aac8;
|
||||
ll_iis_enable = 0x00008480;
|
||||
ll_clock_set_apb1_div = 0x00009414;
|
||||
ll_led_deinit = 0x00009c10;
|
||||
qspi_flash_boot = 0x000055c8;
|
||||
config_rx_gain_tab = 0x0000b100;
|
||||
get_core_clock = 0x0000aafc;
|
||||
82
project/utilities/romcode_fpga.ld
Normal file
82
project/utilities/romcode_fpga.ld
Normal file
@@ -0,0 +1,82 @@
|
||||
strcat = 0x000018ec;
|
||||
strchr = 0x00001988;
|
||||
strcmp = 0x00001668;
|
||||
strcpy = 0x00001820;
|
||||
memset = 0x00001740;
|
||||
memcpy = 0x00001908;
|
||||
memcmp = 0x0000199c;
|
||||
memchr = 0x00001ae8;
|
||||
strcasecmp = 0x00004b4c;
|
||||
strncasecmp = 0x00004b90;
|
||||
printf = 0x00001080;
|
||||
puts = 0x000010b8;
|
||||
strerror = 0x00002d48;
|
||||
rand = 0x00001170;
|
||||
srand = 0x0000118c;
|
||||
abs = 0x00001290;
|
||||
fabs = 0x000001a8;
|
||||
atof = 0x0000150c;
|
||||
atoi = 0x00001500;
|
||||
atol = 0x000014f4;
|
||||
strtol = 0x00001298;
|
||||
strtoll = 0x00001518;
|
||||
strtoul = 0x00001198;
|
||||
strtoull = 0x000013b8;
|
||||
strtof = 0x000014e8;
|
||||
strtod = 0x00001b6c;
|
||||
isupper = 0x00001b04;
|
||||
isspace = 0x0000106c;
|
||||
isdigit = 0x00001afc;
|
||||
isalpha = 0x00001b0c;
|
||||
|
||||
SHA1Init = 0x0000ca60;
|
||||
SHA1Transform = 0x0000bb4c;
|
||||
SHA1Update = 0x0000ca90;
|
||||
sha1_vector = 0x0000cbe4;
|
||||
SHA1Final = 0x0000cb20;
|
||||
sha256_init = 0x0000cd98;
|
||||
sha256_done = 0x0000cea8;
|
||||
sha256_vector = 0x0000cfa0;
|
||||
sha256_process = 0x0000cde8;
|
||||
|
||||
MD5Init = 0x0000b9b0;
|
||||
MD5Update = 0x0000b9d8;
|
||||
md5_vector = 0x0000baf4;
|
||||
MD5Final = 0x0000ba7c;
|
||||
/**/
|
||||
hgusb20_intr_dis = 0x00006b50;
|
||||
hgusb20_int_init_b = 0x00006cdc;
|
||||
hgusb20_clear_ep = 0x00006dec;
|
||||
hgusb20_ep0_clrrx_pkt0 = 0x00006cac;
|
||||
hgusb20_ep0_clr_feature = 0x00006f58;
|
||||
hgusb20_stall_ep = 0x00006d6c;
|
||||
hgusb20_ep0_get_status = 0x00006ee0;
|
||||
hgusb20_ep0_set_feature = 0x00006f9c;
|
||||
hgusb20_ep0_set_configuration = 0x00007210;
|
||||
hgusb20_ep0_get_wcid_descriptor = 0x000072dc;
|
||||
hgusb20_reset2device_mode = 0x00006ab4;
|
||||
hgusb20_switch_stable_device = 0x00006b40;
|
||||
hgusb20_ep_set_txrdy = 0x00007914;
|
||||
hgusb20_ep0_tx = 0x00006c30;
|
||||
hgusb20_ep_rx_kick = 0x00007814;
|
||||
hgusb20_ep0_class = 0x000073a8;
|
||||
hgusb20_ep0_set_address = 0x00007008;
|
||||
hgusb20_ep_set_rxrdy = 0x00007910;
|
||||
hgusb20_ep_tx_kick = 0x00007894;
|
||||
hgusb20_ep0_transfer = 0x00007048;
|
||||
hgusb20_ep0_descriptor = 0x000070cc;
|
||||
tbl_usb_language_id = 0x0000df1c;
|
||||
tbl_usb_str_manufacturer = 0x0000df20;
|
||||
tbl_winusb_device_descriptor = 0x0000e05c;
|
||||
tbl_winusb_compatible_id_feature_descriptor = 0x0000e034;
|
||||
tbl_winusb20_wcidbos = 0x0000e010;
|
||||
usb_test_packet = 0x0000de50;
|
||||
usb_test_mode_tbl = 0x0000de48;
|
||||
tbl_winusb20_wcid_descriptor_set = 0x0000df6c;
|
||||
tbl_winusb_device_interface_guids = 0x0000e070;
|
||||
tbl_usb_str_serial_number = 0x0000df4c;
|
||||
tbl_usb_str_product = 0x0000df30;
|
||||
tbl_usb_config_all_descriptor_wifi = 0x0000def0;
|
||||
tbl_usb_config_all_descriptor_gen = 0x0000dee4;
|
||||
tbl_usb_device_descriptor = 0x0000df08;
|
||||
|
||||
455
project/utilities/romcode_fpga_org.ld
Normal file
455
project/utilities/romcode_fpga_org.ld
Normal file
@@ -0,0 +1,455 @@
|
||||
ll_spi_init = 0x00007ce8;
|
||||
|
||||
ll_spi_rx = 0x00007ea8;
|
||||
|
||||
ll_uart_txdma_kick = 0x000069f0;
|
||||
sdio_s_set_ds = 0x000038c8;
|
||||
|
||||
sys_aes_init = 0x00007c8c;
|
||||
|
||||
disable_wphy_device_cont_tx = 0x00006108;
|
||||
config_wphy_device_dpd_coef = 0x0000627c;
|
||||
sys_aes_key_bitlen_sel = 0x00007c68;
|
||||
ll_simple_spi_init = 0x0000a5e4;
|
||||
hgusb20_irq_dma = 0x000076b0;
|
||||
fw_upg_addr = 0x2005247c;
|
||||
crc16_modbus_calc = 0x00002ecc;
|
||||
close_wphy = 0x0000ac68;
|
||||
ll_iic_slave_rx = 0x00008208;
|
||||
hgusb20_wifi_reset = 0x00007a08;
|
||||
ll_crc_start = 0x00006a78;
|
||||
ll_m2m_memcpy = 0x00008278;
|
||||
os_critical_close = 0x00001b2c;
|
||||
hgusb20_irq_set = 0x000075f4;
|
||||
|
||||
ll_sdio_s_tx_kick = 0x00009264;
|
||||
|
||||
uart_s_set_speed = 0x00004208;
|
||||
get_wphy_device_avg_evm = 0x000060e0;
|
||||
|
||||
sdio_s_tx = 0x00003968;
|
||||
config_phy_tx_norm_mode = 0x0000ad24;
|
||||
get_wphy_device_gfsk_tx_crc = 0x00006340;
|
||||
ll_wdt_feed = 0x00006450;
|
||||
ll_timer_ir_enable = 0x00007be0;
|
||||
ll_spi_buf_rx = 0x00007f50;
|
||||
spiflash_boot = 0x00005e34;
|
||||
|
||||
ll_clock_syspll_config = 0x0000958c;
|
||||
ll_clock_hirc_enable = 0x000092e4;
|
||||
fw_upg_blk_addr = 0x20052480;
|
||||
ll_uart_init = 0x000067dc;
|
||||
|
||||
spi_cfg = 0x0000dd6c;
|
||||
|
||||
config_phy_tx_sine_mode = 0x0000ace4;
|
||||
ll_spi_config = 0x00007d04;
|
||||
hgwphy_bgn_attach = 0x0000b044;
|
||||
qspi_flash_port_deinit = 0x00004d4c;
|
||||
usb20 = 0x2004768c;
|
||||
ll_sys_clock_globle_set = 0x0000aab4;
|
||||
ll_m2m_memset = 0x0000829c;
|
||||
|
||||
sdio_boot = 0x20052468;
|
||||
ll_tk_stop = 0x0000a5d4;
|
||||
hgusb20_dev_reset = 0x00006e98;
|
||||
ll_gpio_iomap_output_config = 0x00006488;
|
||||
get_wphy_device_rx_gain_para = 0x000062f0;
|
||||
ll_sdio_s_irq_config = 0x000091d0;
|
||||
|
||||
ll_iic_master_tx = 0x0000810c;
|
||||
ll_simple_uart_init = 0x0000a660;
|
||||
|
||||
|
||||
ll_clock_set_sys_clk_src = 0x00009338;
|
||||
ll_sys_clock_init = 0x0000aa70;
|
||||
|
||||
config_dpd = 0x0000ae68;
|
||||
|
||||
ll_gmac_get_tx_frame_status = 0x00008c28;
|
||||
ll_qspi_controller_init = 0x00009198;
|
||||
|
||||
errno = 0x200524d0;
|
||||
open_wphy = 0x0000aba0;
|
||||
hgusb20_dev_init = 0x00006d04;
|
||||
ll_qspi_set_prefetch = 0x000090ec;
|
||||
ll_gpio_pull_config = 0x000065fc;
|
||||
|
||||
get_wphy_avg_evm = 0x0000ad5c;
|
||||
ll_spi_dma_start = 0x00007df8;
|
||||
uart_s_rx = 0x00004270;
|
||||
CORE_SEC_OPT = 0x000092a0;
|
||||
trig_calc_bk_noise = 0x0000af8c;
|
||||
|
||||
spi_boot = 0x20052674;
|
||||
freq_offset_sign_ext = 0x0000b030;
|
||||
sys_aes_start = 0x00007ca8;
|
||||
|
||||
ll_tk_ch_kick = 0x0000a5c8;
|
||||
ll_iic_master_rx = 0x00008144;
|
||||
spi_s_tx = 0x00003dd0;
|
||||
enable_auto_sig_err_rst = 0x0000ae54;
|
||||
qspi_flash_poweroff = 0x00004e1c;
|
||||
fwinfo_check_fwinfo_hdr = 0x0000444c;
|
||||
hgusb20_irq_handler_set = 0x000075d4;
|
||||
ll_iic_master_buf_tx = 0x00008194;
|
||||
ll_spi_dma_config = 0x00007dd0;
|
||||
config_wphy_device_en_gfsk_wphy = 0x0000632c;
|
||||
|
||||
|
||||
sys_aes_get_pending = 0x00007c78;
|
||||
atcmd_fwupg = 0x0000d790;
|
||||
ll_m2m_dma_init = 0x00008220;
|
||||
fw_upg_prepare = 0x00004488;
|
||||
|
||||
spiflash_read = 0x00005a2c;
|
||||
ll_qspi_set_write_protect = 0x000090ac;
|
||||
|
||||
|
||||
ll_tk_config = 0x0000a4f4;
|
||||
sys_aes_set_irq = 0x00007c2c;
|
||||
|
||||
ll_gmac_start = 0x00008600;
|
||||
crc16_modbus_cfg = 0x0000d720;
|
||||
ll_iis_disable = 0x00008408;
|
||||
hgusb20_ep0_func = 0x00007468;
|
||||
ll_clock_test_clk_en = 0x000092c4;
|
||||
ll_iic_irq_config = 0x0000803c;
|
||||
get_wphy_device_rx_gfsk_gain_para = 0x00006304;
|
||||
|
||||
ll_gpio_analog_config = 0x00006468;
|
||||
|
||||
hgusb20_dev_rx = 0x000047f4;
|
||||
ll_suptmr_deinit = 0x00009e44;
|
||||
|
||||
ll_qspi_cmd_quad_enable = 0x00008df0;
|
||||
crc32_calc = 0x00002ef0;
|
||||
ll_gmac_init = 0x00008480;
|
||||
qspi_flash_power_reset = 0x00004e44;
|
||||
disable_wphy = 0x0000ab6c;
|
||||
xmodem_receive = 0x00004a14;
|
||||
|
||||
ll_iic_master_buf_rx = 0x000081d8;
|
||||
config_wphy_device_cca_th = 0x000061a0;
|
||||
adj_gain_value = 0x0000ae78;
|
||||
ll_gmac_send_frame = 0x000089f8;
|
||||
ll_ir_timer_irq_config = 0x00007a78;
|
||||
|
||||
get_wphy_err_code = 0x0000ad68;
|
||||
ll_led_timer_deinit = 0x00009d18;
|
||||
uart_s_tx = 0x00004240;
|
||||
ll_iis_soft_rst = 0x00008410;
|
||||
stdout = 0x20052420;
|
||||
boot = 0x200524d8;
|
||||
ll_crc_init = 0x00006a14;
|
||||
ll_spi_set_wire_mode = 0x00007e04;
|
||||
get_wphy_device_gfsk_rx_crc = 0x00006358;
|
||||
ll_simple_spi_deinit = 0x0000a5ec;
|
||||
ll_gmac_irq_config = 0x0000857c;
|
||||
config_phy_tx_waveform_mode = 0x0000b010;
|
||||
ll_timer_deinit = 0x00007a14;
|
||||
sdio_slave_init = 0x00003c5c;
|
||||
enable_wphy_device = 0x00006090;
|
||||
ll_crc_deinit = 0x00006a30;
|
||||
usb_irq_ids = 0x200524a4;
|
||||
|
||||
|
||||
|
||||
ll_simple_uart_irq_config = 0x0000a678;
|
||||
|
||||
ll_clock_set_apb0_div = 0x00009370;
|
||||
ll_timer_sync_start = 0x00007bf8;
|
||||
|
||||
sdio_port_init = 0x000039cc;
|
||||
|
||||
qspi_flash_deinit = 0x00004f90;
|
||||
config_wphy_device_gfsk_crc_init = 0x00006370;
|
||||
ll_spi_deinit = 0x00007cf8;
|
||||
|
||||
Te0 = 0x0000e7a8;
|
||||
ll_qspi_cmd_enter_qpi_mode = 0x00008e68;
|
||||
ll_ir_timer_config = 0x00007b54;
|
||||
|
||||
crc32_cfg = 0x0000d73c;
|
||||
|
||||
ll_spi_buf_tx = 0x00007ed0;
|
||||
adj_gfsk_gain_value = 0x0000aeb4;
|
||||
ll_gmac_config = 0x000084d0;
|
||||
uart_s_set_ds = 0x00004220;
|
||||
config_cca_th = 0x0000ae18;
|
||||
cfg_wphy_gfsk_ch = 0x0000af7c;
|
||||
hgusb20_irq = 0x00007714;
|
||||
ll_uart_deinit = 0x000067f0;
|
||||
spiflash_init = 0x00005820;
|
||||
|
||||
cfg_wphy_gfsk_crc_init = 0x0000af6c;
|
||||
get_wphy_device_tx_psdu_crc = 0x00006218;
|
||||
|
||||
ll_suptmr_comm_config = 0x00009e5c;
|
||||
spiflash_deinit = 0x0000592c;
|
||||
spi_s_rx_len_exp = 0x20052478;
|
||||
ll_gmac_setup_send_frame = 0x00008a74;
|
||||
ll_gpio_iomap_input_config = 0x000064d8;
|
||||
|
||||
ll_iic_dma_config = 0x000080d0;
|
||||
disable_rx_agc = 0x0000ade0;
|
||||
disable_auto_sig_err_rst = 0x0000ae40;
|
||||
disable_gfsk_wphy = 0x0000af20;
|
||||
config_wphy_device_gfsk_ch = 0x00006384;
|
||||
sdio_s_rx = 0x00003978;
|
||||
ll_tk_sf_kick = 0x0000a5a8;
|
||||
|
||||
ll_spi_irq_config = 0x00007d78;
|
||||
hgusb20_init = 0x000075a8;
|
||||
sys_aes_set_mode = 0x00007c40;
|
||||
adjust_wphy_device_gain_value = 0x000062a4;
|
||||
|
||||
ll_tk_deinit = 0x0000a4ac;
|
||||
|
||||
get_rx_freq_offset = 0x0000ad88;
|
||||
config_phy_tx_tri_mode = 0x0000ad04;
|
||||
|
||||
config_wphy_device_tx_tri_mode = 0x000061c0;
|
||||
hgusb20_bot_reset = 0x00006e5c;
|
||||
sdio_rx_len_exp = 0x20052470;
|
||||
Td0 = 0x0000e2a8;
|
||||
ll_sdio_s_rx_kick = 0x00009294;
|
||||
ll_led_timer_init = 0x00009d0c;
|
||||
os_critical_enter = 0x00001b24;
|
||||
fw_upg_program = 0x000044cc;
|
||||
ll_timer_ir_set_code_0 = 0x00007bf0;
|
||||
sdio_s_set_speed = 0x0000395c;
|
||||
ll_gpio_pin_lock_config = 0x0000678c;
|
||||
ll_clock_exosc_enable = 0x0000930c;
|
||||
uart_s_xfer_done = 0x20052488;
|
||||
soft_dereset_phy = 0x0000ab2c;
|
||||
ll_timer_ir_disable = 0x00007be8;
|
||||
sys_aes_set_block_num = 0x00007c20;
|
||||
ll_uart_work_mode_change = 0x00006a00;
|
||||
|
||||
ll_qspi_cmd_device_reset = 0x00008f34;
|
||||
stdin = 0x20052440;
|
||||
ll_spi_tx = 0x00007e6c;
|
||||
enable_rx_agc = 0x0000adf4;
|
||||
ll_spi_set_clock_mode = 0x00007e40;
|
||||
delay_ms_systick = 0x0000a9a8;
|
||||
qspi_flash_port_init = 0x00004ca8;
|
||||
|
||||
ll_uart_dma_config = 0x000069b0;
|
||||
ll_gmac_get_rx_frame_status = 0x00008c40;
|
||||
enable_gfsk_wphy = 0x0000aef4;
|
||||
SysTickCnt = 0x200524bc;
|
||||
ll_gpio_iomap_inout_config = 0x00006578;
|
||||
get_wphy_scrambler_init = 0x0000ad44;
|
||||
enable_wphy_cont_tx = 0x0000ab70;
|
||||
ll_timer_config = 0x00007ab8;
|
||||
|
||||
qspi_flash_init = 0x00004e74;
|
||||
ll_iic_dma_start = 0x00008100;
|
||||
ll_timer_irq_config = 0x00007a18;
|
||||
ll_timer_start = 0x00007bd0;
|
||||
ll_crc_stop = 0x00006aac;
|
||||
ll_led_config = 0x00009b94;
|
||||
hgusb20_wifi_init = 0x00007940;
|
||||
ll_sdio_s_config = 0x000091d8;
|
||||
sdio_interrupt_handle = 0x00003b98;
|
||||
ll_led_timer_irq_config = 0x00009d94;
|
||||
ll_qspi_set_clk = 0x00009124;
|
||||
|
||||
get_wphy_device_err_code = 0x00006130;
|
||||
ll_iis_dma_config = 0x000083ec;
|
||||
spi_base_pins = 0x0000dd34;
|
||||
get_rx_gain_para = 0x0000ae90;
|
||||
hgusb20_wifi_ep_init = 0x00007944;
|
||||
qspi_flash_poweron = 0x00004df4;
|
||||
ll_gmac_mdio_read = 0x00008830;
|
||||
ll_crc_config = 0x00006a34;
|
||||
hgusb20_ep0_clrrx_contious = 0x00006c80;
|
||||
os_critical_exit = 0x00001b28;
|
||||
ll_iis_config = 0x000082d8;
|
||||
get_wphy_device_scrambler_init = 0x000060b0;
|
||||
|
||||
hgusb20_ep0_get_descriptor = 0x00007118;
|
||||
ll_qspi_cmd_release_power_down = 0x00008f9c;
|
||||
ll_gmac_mdio_write = 0x00008648;
|
||||
adjust_wphy_device_gfsk_gain_value = 0x000062bc;
|
||||
crc16_xmodem = 0x000049e4;
|
||||
|
||||
ll_timer_init = 0x00007a10;
|
||||
disable_wphy_device = 0x000060a0;
|
||||
crc8_calc = 0x00002ea8;
|
||||
config_wphy_device_tx_sine_mode = 0x000061b0;
|
||||
ll_tk_init = 0x0000a490;
|
||||
delay_us = 0x0000a92c;
|
||||
_ctype = 0x0000dc34;
|
||||
|
||||
ll_gmac_deinit = 0x00008544;
|
||||
disable_wphy_cont_tx = 0x0000ab80;
|
||||
enable_wphy_device_auto_sig_err_rst = 0x00006240;
|
||||
ll_gmac_stop = 0x00008610;
|
||||
|
||||
disable_wphy_device_auto_sig_err_rst = 0x00006254;
|
||||
rijndaelKeySetupEnc = 0x0000d034;
|
||||
get_tx_psdu_crc16 = 0x0000ab64;
|
||||
ll_iic_slave_tx = 0x00008214;
|
||||
config_wphy_rx_max_gain_state = 0x00006190;
|
||||
|
||||
ll_suptmrx_config = 0x00009f9c;
|
||||
ll_m2m_dma_config = 0x00008264;
|
||||
ll_m2m_dma_irq_config = 0x00008268;
|
||||
ll_uart232_config = 0x00006878;
|
||||
delay_ms = 0x0000a94c;
|
||||
hgusb20_ep0_request = 0x00007424;
|
||||
ll_wdt_stop = 0x00006458;
|
||||
close_wphy_device = 0x0000600c;
|
||||
open_wphy_device = 0x00005ffc;
|
||||
uart_s_boot = 0x0000452c;
|
||||
|
||||
hgusb20_dev_tx = 0x000047d0;
|
||||
atcmd_bootl = 0x0000d788;
|
||||
cp_mode = 0x00002e70;
|
||||
get_wphy_device_rx_freq_offset = 0x000062d8;
|
||||
soft_reset_wphy_device = 0x000061e0;
|
||||
config_wphy_device_dpd = 0x00006268;
|
||||
soft_dereset_wphy_device = 0x000061f0;
|
||||
ll_wdt_start = 0x00006440;
|
||||
ll_wdt_config = 0x000063f0;
|
||||
ll_suptmr_init = 0x00009df8;
|
||||
ll_uart_rxdma_kick = 0x000069e0;
|
||||
ll_clock_sys_clk_select = 0x000093a0;
|
||||
|
||||
Td4s = 0x0000e6a8;
|
||||
|
||||
get_wphy_device_tx_crc = 0x00006118;
|
||||
sdio_s_func1_cis = 0x200475d0;
|
||||
ll_clock_test_clk_sel = 0x000092d0;
|
||||
|
||||
spi_s_set_speed = 0x00003e44;
|
||||
ll_iis_init = 0x000082c0;
|
||||
|
||||
ll_iic_init = 0x00007fbc;
|
||||
config_wphy_device_low_pwr_th = 0x00006230;
|
||||
ll_iic_deinit = 0x00007fc8;
|
||||
ll_iis_irq_config = 0x000083c4;
|
||||
ll_iis_deinit = 0x000082cc;
|
||||
sys_clock_cfg = 0x200524a8;
|
||||
flash_memory_init = 0x00004348;
|
||||
cfg_phy_tx_gain = 0x0000ac5c;
|
||||
ll_gmac_allow_send_frame = 0x000089e4;
|
||||
ll_gpio_afio_config = 0x00006594;
|
||||
ll_m2m_dma_deinit = 0x00008258;
|
||||
ll_gpio_ospeed_config = 0x000067a4;
|
||||
|
||||
ll_wdt_deinit = 0x00006430;
|
||||
os_critical_open = 0x00001b20;
|
||||
|
||||
sys_aes_set_key = 0x00007c0c;
|
||||
hgusb20_config_desc_prepare = 0x00006b68;
|
||||
dev_register = 0x00006398;
|
||||
ll_led_init = 0x00009b6c;
|
||||
get_wphy_avg_power = 0x0000ad50;
|
||||
stderr = 0x20052400;
|
||||
ll_ir_timer_dma_config = 0x00007ba0;
|
||||
ll_clock_usb_clk_en = 0x000096e8;
|
||||
ll_timer_stop = 0x00007bd8;
|
||||
ll_qspi_cmd_busy_wait = 0x00008d0c;
|
||||
|
||||
ll_clock_is_exist = 0x00009408;
|
||||
enable_wphy = 0x0000b00c;
|
||||
|
||||
spi_s_set_ds = 0x00003e50;
|
||||
config_rx_max_gain_state = 0x0000ae08;
|
||||
enable_wphy_device_cont_tx = 0x000060f8;
|
||||
fputc = 0x0000a72c;
|
||||
config_wphy_device_tx_norm_mode = 0x000061d0;
|
||||
|
||||
ll_simple_uart_config = 0x0000a6bc;
|
||||
spi_rx_buf = 0x000059dc;
|
||||
get_rx_gfsk_gain_para = 0x0000aed0;
|
||||
|
||||
ll_tk_irq_config = 0x0000a4b0;
|
||||
get_wphy_device_agc_info = 0x00006148;
|
||||
hgsdio20_s_func1_cis = 0x0000e12c;
|
||||
|
||||
|
||||
ll_tk_data = 0x0000a5dc;
|
||||
qspi_flash_bootload_code = 0x000053f8;
|
||||
get_wphy_device_avg_power = 0x000060c8;
|
||||
ll_timer_ir_set_code_1 = 0x00007bf4;
|
||||
aes_decrypt_encrypt = 0x00004bf8;
|
||||
ll_simple_spi_irq_config = 0x0000a5f4;
|
||||
spi_s_rx = 0x00003e04;
|
||||
config_wphy_device_dis_gfsk_wphy = 0x00006318;
|
||||
ll_spi_set_sample_delay = 0x00007e50;
|
||||
sdio_s_dummy_buf = 0x2004759c;
|
||||
ll_gmac_receive_frame = 0x00008b34;
|
||||
config_wphy_device_rx_gain_tab = 0x00006180;
|
||||
ll_led_timer_config = 0x00009d24;
|
||||
ll_qspi_cmd_write_enable = 0x00008dac;
|
||||
enable_wphy_device_rx_agc = 0x00006170;
|
||||
ll_clock_usbpll_config = 0x000095e4;
|
||||
|
||||
hgsdio20_s_speed_list = 0x0000e164;
|
||||
ll_uart_irq_config = 0x000067f8;
|
||||
sys_aes_set_key_src = 0x00007c54;
|
||||
ll_clock_syspll_set = 0x00009450;
|
||||
ll_simple_spi_config = 0x0000a60c;
|
||||
soft_reset_phy = 0x0000ab44;
|
||||
ll_gmac_has_received_frame = 0x000089ac;
|
||||
get_wphy_gfsk_tx_crc = 0x0000af4c;
|
||||
ll_wdt_init = 0x000063ec;
|
||||
ll_qspi_cmd_exit_qpi_mode = 0x00008ee0;
|
||||
ll_tk_scan_kick = 0x0000a5bc;
|
||||
|
||||
ll_crc_wait_done_pending = 0x00006a9c;
|
||||
hgusb20_dev_set_speed = 0x000047c4;
|
||||
config_low_pwr_th = 0x0000afe4;
|
||||
ll_qspi_cmd_flash_64kb_erase = 0x00008fe0;
|
||||
ll_gmac_get_setup_frame_status = 0x00008c10;
|
||||
hgsdio20_s_func0_cis = 0x0000e118;
|
||||
config_wphy_device_tx_gain = 0x00006290;
|
||||
spiflash_bootloader = 0x00005c08;
|
||||
ll_uart485_config = 0x00006940;
|
||||
ll_tk_hw_kick = 0x0000a59c;
|
||||
crc8_itu_cfg = 0x0000d758;
|
||||
strlen = 0x000017e0;
|
||||
__cskyvprintfprintf = 0x0000109c;
|
||||
get_rx_psdu_crc16 = 0x0000ab5c;
|
||||
hgusb20_init_globle = 0x00006ab0;
|
||||
sdio_s_func0_cis = 0x200475bc;
|
||||
get_wphy_device_rx_psdu_crc = 0x00006200;
|
||||
get_wphy_device_info = 0x0000601c;
|
||||
sys_aes_clear_pending = 0x00007c80;
|
||||
hgusb20_dev_set_ds = 0x000047c0;
|
||||
rcons = 0x0000eba8;
|
||||
ll_gmac_delay = 0x0000846c;
|
||||
|
||||
|
||||
get_wphy_tx_crc = 0x0000ab90;
|
||||
fputs = 0x00001124;
|
||||
cfg_dpd_coef = 0x0000ac30;
|
||||
ll_qspi_cmd_issue = 0x00008c50;
|
||||
spi_read_cfg_nor = 0x0000dd8c;
|
||||
|
||||
ll_crc_continue = 0x00006a84;
|
||||
ll_clock_set_sys_clk_div = 0x00009358;
|
||||
get_wphy_gfsk_rx_crc = 0x0000af5c;
|
||||
|
||||
ll_iic_config = 0x00007fd4;
|
||||
ll_simple_uart_deinit = 0x0000a66c;
|
||||
get_bk_noise = 0x0000af9c;
|
||||
__jpeg_htable = 0x0000fc00;
|
||||
get_wphy_agc_info = 0x0000ad7c;
|
||||
hgusb20_wifi_xfer_reset = 0x000077e4;
|
||||
debug_select_interface = 0x0000a704;
|
||||
|
||||
ll_spi_get_wire_mode = 0x00007e64;
|
||||
hgusb20_ep0_standard = 0x00007250;
|
||||
disable_wphy_device_rx_agc = 0x00006160;
|
||||
sys_reset = 0x0000a988;
|
||||
ll_iis_enable = 0x000083fc;
|
||||
ll_clock_set_apb1_div = 0x00009388;
|
||||
ll_led_deinit = 0x00009b80;
|
||||
qspi_flash_boot = 0x0000551c;
|
||||
config_rx_gain_tab = 0x0000afb8;
|
||||
get_core_clock = 0x0000a9bc;
|
||||
458
project/utilities/romcode_org.ld
Normal file
458
project/utilities/romcode_org.ld
Normal file
@@ -0,0 +1,458 @@
|
||||
ll_spi_init = 0x00007d6c;
|
||||
hgusb20_intr_dis = 0x00006bd4;
|
||||
ll_spi_rx = 0x00007f2c;
|
||||
strcpy = 0x00001820;
|
||||
ll_uart_txdma_kick = 0x00006a74;
|
||||
sdio_s_set_ds = 0x00003a14;
|
||||
hgusb20_clear_ep = 0x00006e70;
|
||||
sys_aes_init = 0x00007d10;
|
||||
fabs = 0x000001a8;
|
||||
disable_wphy_device_cont_tx = 0x0000618c;
|
||||
config_wphy_device_dpd_coef = 0x00006300;
|
||||
sys_aes_key_bitlen_sel = 0x00007cec;
|
||||
ll_simple_spi_init = 0x0000a674;
|
||||
hgusb20_irq_dma = 0x00007734;
|
||||
fw_upg_addr = 0x2005247c;
|
||||
crc16_modbus_calc = 0x00003018;
|
||||
close_wphy = 0x0000adb0;
|
||||
ll_iic_slave_rx = 0x0000828c;
|
||||
hgusb20_wifi_reset = 0x00007a8c;
|
||||
ll_crc_start = 0x00006afc;
|
||||
ll_m2m_memcpy = 0x000082fc;
|
||||
os_critical_close = 0x00001b2c;
|
||||
hgusb20_irq_set = 0x00007678;
|
||||
printf = 0x00001080;
|
||||
stdout = 0x20052420;
|
||||
ll_sdio_s_tx_kick = 0x000092f0;
|
||||
hgusb20_ep0_clrrx_pkt0 = 0x00006d30;
|
||||
uart_s_set_speed = 0x000042b4;
|
||||
get_wphy_device_avg_evm = 0x00006164;
|
||||
tbl_usb_language_id = 0x0000e06c;
|
||||
sdio_s_tx = 0x00003ab4;
|
||||
config_phy_tx_norm_mode = 0x0000ae6c;
|
||||
get_wphy_device_gfsk_tx_crc = 0x000063c4;
|
||||
ll_wdt_feed = 0x000064d4;
|
||||
ll_timer_ir_enable = 0x00007c64;
|
||||
ll_spi_buf_rx = 0x00007fd4;
|
||||
spiflash_boot = 0x00005eb8;
|
||||
md5_vector = 0x0000bc3c;
|
||||
ll_clock_syspll_config = 0x0000961c;
|
||||
ll_clock_hirc_enable = 0x00009370;
|
||||
fw_upg_blk_addr = 0x20052480;
|
||||
ll_uart_init = 0x00006860;
|
||||
tbl_usb_str_manufacturer = 0x0000e070;
|
||||
spi_cfg = 0x0000debc;
|
||||
strerror = 0x00002d48;
|
||||
config_phy_tx_sine_mode = 0x0000ae2c;
|
||||
ll_spi_config = 0x00007d88;
|
||||
hgwphy_bgn_attach = 0x0000b18c;
|
||||
qspi_flash_port_deinit = 0x00004df8;
|
||||
usb20 = 0x2004768c;
|
||||
ll_sys_clock_globle_set = 0x0000abfc;
|
||||
ll_m2m_memset = 0x00008320;
|
||||
hgusb20_ep0_clr_feature = 0x00006fdc;
|
||||
sdio_boot = 0x20052468;
|
||||
ll_tk_stop = 0x0000a664;
|
||||
hgusb20_dev_reset = 0x00006f1c;
|
||||
ll_gpio_iomap_output_config = 0x0000650c;
|
||||
get_wphy_device_rx_gain_para = 0x00006374;
|
||||
ll_sdio_s_irq_config = 0x0000925c;
|
||||
atol = 0x000014f4;
|
||||
ll_iic_master_tx = 0x00008190;
|
||||
ll_simple_uart_init = 0x0000a6f0;
|
||||
hgusb20_stall_ep = 0x00006df0;
|
||||
tbl_winusb_device_descriptor = 0x0000e1ac;
|
||||
ll_clock_set_sys_clk_src = 0x000093c4;
|
||||
ll_sys_clock_init = 0x0000abb8;
|
||||
hgusb20_ep0_get_status = 0x00006f64;
|
||||
config_dpd = 0x0000afb0;
|
||||
SHA1Update = 0x0000cbd8;
|
||||
ll_gmac_get_tx_frame_status = 0x00008cac;
|
||||
ll_qspi_controller_init = 0x00009224;
|
||||
sha256_init = 0x0000cee0;
|
||||
errno = 0x200524d0;
|
||||
open_wphy = 0x0000ace8;
|
||||
hgusb20_dev_init = 0x00006d88;
|
||||
ll_qspi_set_prefetch = 0x00009170;
|
||||
ll_gpio_pull_config = 0x00006680;
|
||||
tbl_winusb_compatible_id_feature_descriptor = 0x0000e184;
|
||||
get_wphy_avg_evm = 0x0000aea4;
|
||||
ll_spi_dma_start = 0x00007e7c;
|
||||
uart_s_rx = 0x0000431c;
|
||||
CORE_SEC_OPT = 0x0000932c;
|
||||
trig_calc_bk_noise = 0x0000b0d4;
|
||||
sha256_done = 0x0000cff0;
|
||||
spi_boot = 0x20052674;
|
||||
freq_offset_sign_ext = 0x0000b178;
|
||||
sys_aes_start = 0x00007d2c;
|
||||
SHA1Init = 0x0000cba8;
|
||||
ll_tk_ch_kick = 0x0000a658;
|
||||
ll_iic_master_rx = 0x000081c8;
|
||||
spi_s_tx = 0x00003e8c;
|
||||
enable_auto_sig_err_rst = 0x0000af9c;
|
||||
qspi_flash_poweroff = 0x00004ec8;
|
||||
fwinfo_check_fwinfo_hdr = 0x000044f8;
|
||||
hgusb20_irq_handler_set = 0x00007658;
|
||||
ll_iic_master_buf_tx = 0x00008218;
|
||||
ll_spi_dma_config = 0x00007e54;
|
||||
config_wphy_device_en_gfsk_wphy = 0x000063b0;
|
||||
memcpy = 0x00001908;
|
||||
hgusb20_ep0_set_feature = 0x00007020;
|
||||
sys_aes_get_pending = 0x00007cfc;
|
||||
atcmd_fwupg = 0x0000d8e0;
|
||||
ll_m2m_dma_init = 0x000082a4;
|
||||
fw_upg_prepare = 0x00004534;
|
||||
tbl_winusb20_wcidbos = 0x0000e160;
|
||||
spiflash_read = 0x00005ab0;
|
||||
ll_qspi_set_write_protect = 0x00009130;
|
||||
puts = 0x000010b8;
|
||||
hgusb20_ep0_set_configuration = 0x00007294;
|
||||
ll_tk_config = 0x0000a584;
|
||||
sys_aes_set_irq = 0x00007cb0;
|
||||
hgusb20_ep0_get_wcid_descriptor = 0x00007360;
|
||||
ll_gmac_start = 0x00008684;
|
||||
crc16_modbus_cfg = 0x0000d870;
|
||||
ll_iis_disable = 0x0000848c;
|
||||
hgusb20_ep0_func = 0x000074ec;
|
||||
ll_clock_test_clk_en = 0x00009350;
|
||||
ll_iic_irq_config = 0x000080c0;
|
||||
get_wphy_device_rx_gfsk_gain_para = 0x00006388;
|
||||
hgusb20_reset2device_mode = 0x00006b38;
|
||||
ll_gpio_analog_config = 0x000064ec;
|
||||
hgusb20_ep0_descriptor = 0x00007150;
|
||||
hgusb20_dev_rx = 0x000048a0;
|
||||
ll_suptmr_deinit = 0x00009ed4;
|
||||
strtoll = 0x00001518;
|
||||
ll_qspi_cmd_quad_enable = 0x00008e74;
|
||||
crc32_calc = 0x0000303c;
|
||||
ll_gmac_init = 0x00008504;
|
||||
qspi_flash_power_reset = 0x00004ef0;
|
||||
disable_wphy = 0x0000acb4;
|
||||
xmodem_receive = 0x00004ac0;
|
||||
strtoul = 0x00001198;
|
||||
ll_iic_master_buf_rx = 0x0000825c;
|
||||
config_wphy_device_cca_th = 0x00006224;
|
||||
adj_gain_value = 0x0000afc0;
|
||||
ll_gmac_send_frame = 0x00008a7c;
|
||||
ll_ir_timer_irq_config = 0x00007afc;
|
||||
hgusb20_switch_stable_device = 0x00006bc4;
|
||||
get_wphy_err_code = 0x0000aeb0;
|
||||
ll_led_timer_deinit = 0x00009da8;
|
||||
uart_s_tx = 0x000042ec;
|
||||
ll_iis_soft_rst = 0x00008494;
|
||||
isspace = 0x0000106c;
|
||||
boot = 0x200524d8;
|
||||
ll_crc_init = 0x00006a98;
|
||||
ll_spi_set_wire_mode = 0x00007e88;
|
||||
get_wphy_device_gfsk_rx_crc = 0x000063dc;
|
||||
ll_simple_spi_deinit = 0x0000a67c;
|
||||
ll_gmac_irq_config = 0x00008600;
|
||||
config_phy_tx_waveform_mode = 0x0000b158;
|
||||
ll_timer_deinit = 0x00007a98;
|
||||
sdio_slave_init = 0x00003d18;
|
||||
enable_wphy_device = 0x00006114;
|
||||
ll_crc_deinit = 0x00006ab4;
|
||||
usb_irq_ids = 0x200524a4;
|
||||
usb_test_mode_tbl = 0x0000df98;
|
||||
hgusb20_ep_set_txrdy = 0x00007998;
|
||||
strncasecmp = 0x00004c3c;
|
||||
ll_simple_uart_irq_config = 0x0000a708;
|
||||
sha256_vector = 0x0000d0e8;
|
||||
ll_clock_set_apb0_div = 0x000093fc;
|
||||
ll_timer_sync_start = 0x00007c7c;
|
||||
MD5Final = 0x0000bbc4;
|
||||
sdio_port_init = 0x00003b18;
|
||||
hgusb20_ep0_tx = 0x00006cb4;
|
||||
qspi_flash_deinit = 0x0000503c;
|
||||
config_wphy_device_gfsk_crc_init = 0x000063f4;
|
||||
ll_spi_deinit = 0x00007d7c;
|
||||
tbl_winusb20_wcid_descriptor_set = 0x0000e0bc;
|
||||
tbl_winusb_device_interface_guids = 0x0000e1c0;
|
||||
Te0 = 0x0000e8f8;
|
||||
ll_qspi_cmd_enter_qpi_mode = 0x00008eec;
|
||||
ll_ir_timer_config = 0x00007bd8;
|
||||
strtol = 0x00001298;
|
||||
crc32_cfg = 0x0000d88c;
|
||||
usb_test_packet = 0x0000dfa0;
|
||||
ll_spi_buf_tx = 0x00007f54;
|
||||
adj_gfsk_gain_value = 0x0000affc;
|
||||
ll_gmac_config = 0x00008554;
|
||||
uart_s_set_ds = 0x000042cc;
|
||||
config_cca_th = 0x0000af60;
|
||||
cfg_wphy_gfsk_ch = 0x0000b0c4;
|
||||
hgusb20_irq = 0x00007798;
|
||||
ll_uart_deinit = 0x00006874;
|
||||
spiflash_init = 0x000058a4;
|
||||
tbl_usb_str_serial_number = 0x0000e09c;
|
||||
cfg_wphy_gfsk_crc_init = 0x0000b0b4;
|
||||
get_wphy_device_tx_psdu_crc = 0x0000629c;
|
||||
strtod = 0x00001b6c;
|
||||
ll_suptmr_comm_config = 0x00009eec;
|
||||
spiflash_deinit = 0x000059b0;
|
||||
spi_s_rx_len_exp = 0x20052478;
|
||||
ll_gmac_setup_send_frame = 0x00008af8;
|
||||
ll_gpio_iomap_input_config = 0x0000655c;
|
||||
atof = 0x0000150c;
|
||||
ll_iic_dma_config = 0x00008154;
|
||||
disable_rx_agc = 0x0000af28;
|
||||
disable_auto_sig_err_rst = 0x0000af88;
|
||||
disable_gfsk_wphy = 0x0000b068;
|
||||
config_wphy_device_gfsk_ch = 0x00006408;
|
||||
sdio_s_rx = 0x00003ac4;
|
||||
ll_tk_sf_kick = 0x0000a638;
|
||||
strcat = 0x000018ec;
|
||||
ll_spi_irq_config = 0x00007dfc;
|
||||
hgusb20_init = 0x0000762c;
|
||||
sys_aes_set_mode = 0x00007cc4;
|
||||
adjust_wphy_device_gain_value = 0x00006328;
|
||||
tbl_usb_str_product = 0x0000e080;
|
||||
ll_tk_deinit = 0x0000a53c;
|
||||
sha256_process = 0x0000cf30;
|
||||
get_rx_freq_offset = 0x0000aed0;
|
||||
config_phy_tx_tri_mode = 0x0000ae4c;
|
||||
tbl_usb_config_all_descriptor_wifi = 0x0000e040;
|
||||
config_wphy_device_tx_tri_mode = 0x00006244;
|
||||
hgusb20_bot_reset = 0x00006ee0;
|
||||
sdio_rx_len_exp = 0x20052470;
|
||||
Td0 = 0x0000e3f8;
|
||||
ll_sdio_s_rx_kick = 0x00009320;
|
||||
ll_led_timer_init = 0x00009d9c;
|
||||
os_critical_enter = 0x00001b24;
|
||||
fw_upg_program = 0x00004578;
|
||||
ll_timer_ir_set_code_0 = 0x00007c74;
|
||||
sdio_s_set_speed = 0x00003aa8;
|
||||
ll_gpio_pin_lock_config = 0x00006810;
|
||||
ll_clock_exosc_enable = 0x00009398;
|
||||
uart_s_xfer_done = 0x20052488;
|
||||
soft_dereset_phy = 0x0000ac74;
|
||||
ll_timer_ir_disable = 0x00007c6c;
|
||||
sys_aes_set_block_num = 0x00007ca4;
|
||||
ll_uart_work_mode_change = 0x00006a84;
|
||||
memchr = 0x00001ae8;
|
||||
ll_qspi_cmd_device_reset = 0x00008fb8;
|
||||
stdin = 0x20052440;
|
||||
ll_spi_tx = 0x00007ef0;
|
||||
enable_rx_agc = 0x0000af3c;
|
||||
ll_spi_set_clock_mode = 0x00007ec4;
|
||||
delay_ms_systick = 0x0000aae8;
|
||||
qspi_flash_port_init = 0x00004d54;
|
||||
rand = 0x00001170;
|
||||
ll_uart_dma_config = 0x00006a34;
|
||||
ll_gmac_get_rx_frame_status = 0x00008cc4;
|
||||
enable_gfsk_wphy = 0x0000b03c;
|
||||
SysTickCnt = 0x200524bc;
|
||||
ll_gpio_iomap_inout_config = 0x000065fc;
|
||||
get_wphy_scrambler_init = 0x0000ae8c;
|
||||
enable_wphy_cont_tx = 0x0000acb8;
|
||||
ll_timer_config = 0x00007b3c;
|
||||
isupper = 0x00001b04;
|
||||
qspi_flash_init = 0x00004f20;
|
||||
ll_iic_dma_start = 0x00008184;
|
||||
ll_timer_irq_config = 0x00007a9c;
|
||||
ll_timer_start = 0x00007c54;
|
||||
ll_crc_stop = 0x00006b30;
|
||||
ll_led_config = 0x00009c24;
|
||||
hgusb20_wifi_init = 0x000079c4;
|
||||
ll_sdio_s_config = 0x00009264;
|
||||
sdio_interrupt_handle = 0x00003c54;
|
||||
ll_led_timer_irq_config = 0x00009e24;
|
||||
ll_qspi_set_clk = 0x000091a8;
|
||||
strcasecmp = 0x00004bf8;
|
||||
get_wphy_device_err_code = 0x000061b4;
|
||||
ll_iis_dma_config = 0x00008470;
|
||||
spi_base_pins = 0x0000de84;
|
||||
get_rx_gain_para = 0x0000afd8;
|
||||
hgusb20_wifi_ep_init = 0x000079c8;
|
||||
qspi_flash_poweron = 0x00004ea0;
|
||||
ll_gmac_mdio_read = 0x000088b4;
|
||||
ll_crc_config = 0x00006ab8;
|
||||
hgusb20_ep0_clrrx_contious = 0x00006d04;
|
||||
os_critical_exit = 0x00001b28;
|
||||
ll_iis_config = 0x0000835c;
|
||||
get_wphy_device_scrambler_init = 0x00006134;
|
||||
memcmp = 0x0000199c;
|
||||
hgusb20_ep0_get_descriptor = 0x0000719c;
|
||||
ll_qspi_cmd_release_power_down = 0x00009020;
|
||||
ll_gmac_mdio_write = 0x000086cc;
|
||||
adjust_wphy_device_gfsk_gain_value = 0x00006340;
|
||||
crc16_xmodem = 0x00004a90;
|
||||
isalpha = 0x00001b0c;
|
||||
ll_timer_init = 0x00007a94;
|
||||
disable_wphy_device = 0x00006124;
|
||||
crc8_calc = 0x00002ff4;
|
||||
config_wphy_device_tx_sine_mode = 0x00006234;
|
||||
ll_tk_init = 0x0000a520;
|
||||
delay_us = 0x0000aa3c;
|
||||
_ctype = 0x0000dd84;
|
||||
hgusb20_ep_rx_kick = 0x00007898;
|
||||
ll_gmac_deinit = 0x000085c8;
|
||||
disable_wphy_cont_tx = 0x0000acc8;
|
||||
enable_wphy_device_auto_sig_err_rst = 0x000062c4;
|
||||
ll_gmac_stop = 0x00008694;
|
||||
strtoull = 0x000013b8;
|
||||
disable_wphy_device_auto_sig_err_rst = 0x000062d8;
|
||||
rijndaelKeySetupEnc = 0x0000d17c;
|
||||
get_tx_psdu_crc16 = 0x0000acac;
|
||||
ll_iic_slave_tx = 0x00008298;
|
||||
config_wphy_rx_max_gain_state = 0x00006214;
|
||||
memset = 0x00001740;
|
||||
ll_suptmrx_config = 0x0000a02c;
|
||||
ll_m2m_dma_config = 0x000082e8;
|
||||
ll_m2m_dma_irq_config = 0x000082ec;
|
||||
ll_uart232_config = 0x000068fc;
|
||||
delay_ms = 0x0000aa68;
|
||||
hgusb20_ep0_request = 0x000074a8;
|
||||
ll_wdt_stop = 0x000064dc;
|
||||
close_wphy_device = 0x00006090;
|
||||
open_wphy_device = 0x00006080;
|
||||
uart_s_boot = 0x000045d8;
|
||||
srand = 0x0000118c;
|
||||
hgusb20_dev_tx = 0x0000487c;
|
||||
atcmd_bootl = 0x0000d8d8;
|
||||
cp_mode = 0x00002e60;
|
||||
get_wphy_device_rx_freq_offset = 0x0000635c;
|
||||
soft_reset_wphy_device = 0x00006264;
|
||||
config_wphy_device_dpd = 0x000062ec;
|
||||
soft_dereset_wphy_device = 0x00006274;
|
||||
ll_wdt_start = 0x000064c4;
|
||||
ll_wdt_config = 0x00006474;
|
||||
ll_suptmr_init = 0x00009e88;
|
||||
ll_uart_rxdma_kick = 0x00006a64;
|
||||
ll_clock_sys_clk_select = 0x0000942c;
|
||||
hgusb20_int_init_b = 0x00006d60;
|
||||
Td4s = 0x0000e7f8;
|
||||
hgusb20_ep0_class = 0x0000742c;
|
||||
get_wphy_device_tx_crc = 0x0000619c;
|
||||
sdio_s_func1_cis = 0x200475d0;
|
||||
ll_clock_test_clk_sel = 0x0000935c;
|
||||
hgusb20_ep0_set_address = 0x0000708c;
|
||||
spi_s_set_speed = 0x00003f00;
|
||||
ll_iis_init = 0x00008344;
|
||||
strcmp = 0x00001668;
|
||||
ll_iic_init = 0x00008040;
|
||||
config_wphy_device_low_pwr_th = 0x000062b4;
|
||||
ll_iic_deinit = 0x0000804c;
|
||||
ll_iis_irq_config = 0x00008448;
|
||||
ll_iis_deinit = 0x00008350;
|
||||
sys_clock_cfg = 0x200524a8;
|
||||
flash_memory_init = 0x000043f4;
|
||||
cfg_phy_tx_gain = 0x0000ada4;
|
||||
ll_gmac_allow_send_frame = 0x00008a68;
|
||||
ll_gpio_afio_config = 0x00006618;
|
||||
ll_m2m_dma_deinit = 0x000082dc;
|
||||
ll_gpio_ospeed_config = 0x00006828;
|
||||
MD5Init = 0x0000baf8;
|
||||
ll_wdt_deinit = 0x000064b4;
|
||||
os_critical_open = 0x00001b20;
|
||||
strtof = 0x000014e8;
|
||||
sys_aes_set_key = 0x00007c90;
|
||||
hgusb20_config_desc_prepare = 0x00006bec;
|
||||
dev_register = 0x0000641c;
|
||||
ll_led_init = 0x00009bfc;
|
||||
get_wphy_avg_power = 0x0000ae98;
|
||||
stderr = 0x20052400;
|
||||
ll_ir_timer_dma_config = 0x00007c24;
|
||||
ll_clock_usb_clk_en = 0x00009778;
|
||||
ll_timer_stop = 0x00007c5c;
|
||||
ll_qspi_cmd_busy_wait = 0x00008d90;
|
||||
hgusb20_ep_set_rxrdy = 0x00007994;
|
||||
ll_clock_is_exist = 0x00009494;
|
||||
enable_wphy = 0x0000b154;
|
||||
MD5Update = 0x0000bb20;
|
||||
spi_s_set_ds = 0x00003f0c;
|
||||
config_rx_max_gain_state = 0x0000af50;
|
||||
enable_wphy_device_cont_tx = 0x0000617c;
|
||||
fputc = 0x0000a810;
|
||||
config_wphy_device_tx_norm_mode = 0x00006254;
|
||||
tbl_usb_config_all_descriptor_gen = 0x0000e034;
|
||||
ll_simple_uart_config = 0x0000a74c;
|
||||
spi_rx_buf = 0x00005a60;
|
||||
get_rx_gfsk_gain_para = 0x0000b018;
|
||||
tbl_usb_device_descriptor = 0x0000e058;
|
||||
ll_tk_irq_config = 0x0000a540;
|
||||
get_wphy_device_agc_info = 0x000061cc;
|
||||
sysctrl_qspi_get_src_clk = 0x0000a794;
|
||||
hgsdio20_s_func1_cis = 0x0000e27c;
|
||||
isdigit = 0x00001afc;
|
||||
SHA1Final = 0x0000cc68;
|
||||
ll_tk_data = 0x0000a66c;
|
||||
qspi_flash_bootload_code = 0x000054a4;
|
||||
get_wphy_device_avg_power = 0x0000614c;
|
||||
ll_timer_ir_set_code_1 = 0x00007c78;
|
||||
aes_decrypt_encrypt = 0x00004ca4;
|
||||
ll_simple_spi_irq_config = 0x0000a684;
|
||||
spi_s_rx = 0x00003ec0;
|
||||
config_wphy_device_dis_gfsk_wphy = 0x0000639c;
|
||||
ll_spi_set_sample_delay = 0x00007ed4;
|
||||
sdio_s_dummy_buf = 0x2004759c;
|
||||
ll_gmac_receive_frame = 0x00008bb8;
|
||||
config_wphy_device_rx_gain_tab = 0x00006204;
|
||||
ll_led_timer_config = 0x00009db4;
|
||||
ll_qspi_cmd_write_enable = 0x00008e30;
|
||||
enable_wphy_device_rx_agc = 0x000061f4;
|
||||
ll_clock_usbpll_config = 0x00009674;
|
||||
SHA1Transform = 0x0000bc94;
|
||||
hgsdio20_s_speed_list = 0x0000e2b4;
|
||||
ll_uart_irq_config = 0x0000687c;
|
||||
sys_aes_set_key_src = 0x00007cd8;
|
||||
ll_clock_syspll_set = 0x000094e0;
|
||||
ll_simple_spi_config = 0x0000a69c;
|
||||
soft_reset_phy = 0x0000ac8c;
|
||||
ll_gmac_has_received_frame = 0x00008a30;
|
||||
get_wphy_gfsk_tx_crc = 0x0000b094;
|
||||
ll_wdt_init = 0x00006470;
|
||||
ll_qspi_cmd_exit_qpi_mode = 0x00008f64;
|
||||
ll_tk_scan_kick = 0x0000a64c;
|
||||
atoi = 0x00001500;
|
||||
ll_crc_wait_done_pending = 0x00006b20;
|
||||
hgusb20_dev_set_speed = 0x00004870;
|
||||
config_low_pwr_th = 0x0000b12c;
|
||||
ll_qspi_cmd_flash_64kb_erase = 0x00009064;
|
||||
ll_gmac_get_setup_frame_status = 0x00008c94;
|
||||
hgsdio20_s_func0_cis = 0x0000e268;
|
||||
config_wphy_device_tx_gain = 0x00006314;
|
||||
spiflash_bootloader = 0x00005c8c;
|
||||
ll_uart485_config = 0x000069c4;
|
||||
ll_tk_hw_kick = 0x0000a62c;
|
||||
crc8_itu_cfg = 0x0000d8a8;
|
||||
strlen = 0x000017e0;
|
||||
__cskyvprintfprintf = 0x0000109c;
|
||||
get_rx_psdu_crc16 = 0x0000aca4;
|
||||
hgusb20_init_globle = 0x00006b34;
|
||||
sdio_s_func0_cis = 0x200475bc;
|
||||
get_wphy_device_rx_psdu_crc = 0x00006284;
|
||||
get_wphy_device_info = 0x000060a0;
|
||||
sys_aes_clear_pending = 0x00007d04;
|
||||
hgusb20_dev_set_ds = 0x0000486c;
|
||||
rcons = 0x0000ecf8;
|
||||
ll_gmac_delay = 0x000084f0;
|
||||
abs = 0x00001290;
|
||||
strchr = 0x00001988;
|
||||
get_wphy_tx_crc = 0x0000acd8;
|
||||
fputs = 0x00001124;
|
||||
cfg_dpd_coef = 0x0000ad78;
|
||||
ll_qspi_cmd_issue = 0x00008cd4;
|
||||
spi_read_cfg_nor = 0x0000dedc;
|
||||
hgusb20_ep_tx_kick = 0x00007918;
|
||||
ll_crc_continue = 0x00006b08;
|
||||
ll_clock_set_sys_clk_div = 0x000093e4;
|
||||
get_wphy_gfsk_rx_crc = 0x0000b0a4;
|
||||
hgusb20_ep0_transfer = 0x000070cc;
|
||||
ll_iic_config = 0x00008058;
|
||||
ll_simple_uart_deinit = 0x0000a6fc;
|
||||
get_bk_noise = 0x0000b0e4;
|
||||
__jpeg_htable = 0x0000fc00;
|
||||
get_wphy_agc_info = 0x0000aec4;
|
||||
hgusb20_wifi_xfer_reset = 0x00007868;
|
||||
debug_select_interface = 0x0000a7e8;
|
||||
sha1_vector = 0x0000cd2c;
|
||||
ll_spi_get_wire_mode = 0x00007ee8;
|
||||
hgusb20_ep0_standard = 0x000072d4;
|
||||
disable_wphy_device_rx_agc = 0x000061e4;
|
||||
sys_reset = 0x0000aac8;
|
||||
ll_iis_enable = 0x00008480;
|
||||
ll_clock_set_apb1_div = 0x00009414;
|
||||
ll_led_deinit = 0x00009c10;
|
||||
qspi_flash_boot = 0x000055c8;
|
||||
config_rx_gain_tab = 0x0000b100;
|
||||
get_core_clock = 0x0000aafc;
|
||||
BIN
project/utilities/sched_cfg
Normal file
BIN
project/utilities/sched_cfg
Normal file
Binary file not shown.
Reference in New Issue
Block a user