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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
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69
csky/csi_kernel/rhino/pwrmgmt/cpu_pwr_api.h Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
14jan2018, init vesion
*/
/*
DESCRIPTION
This file provides APIs for management CPU power.
*/
#ifndef __cpu_pwr_api_h__
#define __cpu_pwr_api_h__
#ifdef __cplusplus
extern "C" {
#endif
#include "k_api.h"
#include "cpu_pwr_hal_lib.h"
/*
* CPU power management operates in one of three possible modes:
*
* CPU_IDLE_MODE_RUN:
* In this CPU mode of operation, idle CPU power management is disabled.
*
* CPU_IDLE_MODE_SLEEP:
* the CPUs sleep when idle, but system clock interupts wakes up the CPU
* at every tick.
*
* CPU_IDLE_MODE_TICKLESS: CPUs sleep when idle, potentially for multiple
* ticks at a time.
*/
typedef enum cpu_idle_mode
{
CPU_IDLE_MODE_RUN = 0,
CPU_IDLE_MODE_SLEEP = 1,
CPU_IDLE_MODE_TICKLESS = 2
} CPU_IDLE_MODE;
#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
extern kstat_t cpu_pwr_p_state_set (uint32_t cpuIndex, cpu_pstate_t cpuPState);
extern kstat_t cpu_pwr_p_state_get (uint32_t cpuIndex, cpu_pstate_t * pCpuPState);
extern kstat_t cpu_pwr_p_state_capability_get (uint32_t cpuIndex, uint32_t * pSupportBitsetP);
#endif /* RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT */
extern kstat_t cpu_pwr_c_state_set (cpu_cstate_t);
extern kstat_t cpu_pwr_c_state_get (uint32_t cpuIndex, cpu_cstate_t * pCpuCState);
extern kstat_t cpu_pwr_c_state_capability_get (uint32_t cpuIndex, uint32_t * pSupportBitsetC);
extern kstat_t cpu_pwr_idle_mode_set (CPU_IDLE_MODE mode);
extern kstat_t cpu_pwr_idle_mode_get (CPU_IDLE_MODE * pMode);
#if RHINO_CONFIG_CPU_TICKLESS
extern kstat_t tickless_task_ignore (ktask_t * p_tcb);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __cpu_pwr_api_h__ */

30
csky/csi_kernel/rhino/pwrmgmt/cpu_pwr_config.h Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef __k_config_pwr_mgmt_h__
#define __k_config_pwr_mgmt_h__
/* cpu power management configuration */
#ifndef RHINO_CONFIG_CPU_TICKLESS
#define RHINO_CONFIG_CPU_TICKLESS 1
#endif
#ifndef RHINO_CONFIG_CPU_PWR_MGMT_SHOW
#define RHINO_CONFIG_CPU_PWR_MGMT_SHOW 0
#endif
#ifndef RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
#define RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT 0
#endif
#ifndef RHINO_CONFIG_PWR_DEBUG
#define RHINO_CONFIG_PWR_DEBUG 0
#endif
#ifndef RHINO_PWR_MGMT_ERR
#define RHINO_PWR_MGMT_ERR -1
#endif
#endif /* __k_config_pwr_mgmt_h__ */

118
csky/csi_kernel/rhino/pwrmgmt/cpu_pwr_hal_lib.h Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
14jan2018, init vesion
*/
#ifndef __cpu_pwr_hal_lib_h__
#define __cpu_pwr_hal_lib_h__
#ifdef __cplusplus
extern "C" {
#endif
#include "k_cpuset.h"
#include "pwr_state.h"
#include "dl_list.h"
#include "k_err.h"
/* defines */
#define CPU_PWR_TOPO_LEVEL_ROOT 0
#define CPU_PWR_TOPO_LEVEL_1 1
#define CPU_PWR_TOPO_LEVEL_2 2
#define CPU_PWR_TOPO_LEVEL_3 3
#define CPU_PWR_TOPO_LEVEL_4 4
#define CPU_PWR_TOPO_LEVEL_5 5
#define CPU_PWR_NODE_NAME_LEN 64
#define CPU_PWR_ROOT_NODE_NAME "cpu_pwr_root"
#define CPU_STATE_BIT(n) (1 << (n))
#define CPU_FREQ_UNKNOW (-1)
#define CPU_VOLT_UNKNOW (-1)
#define CPU_LATENCY_UNKNOW (-1)
typedef struct
{
uint32_t state;
uint32_t value;
} state_val_pair_t;
struct cpu_pwr;
typedef kstat_t (*FUNC_CPU_PSTATE_SET) (struct cpu_pwr * p_cpu_node, uint32_t cpu_state);
typedef kstat_t (*FUNC_CPU_CSTATE_SET) (uint32_t cpu_state, int master);
typedef kstat_t (*FUNC_CPU_STATE_GET) (struct cpu_pwr * p_cpu_node, uint32_t * pCpuState);
typedef struct cpu_pwr
{
uint32_t supportBitsetC;
int stateNumC;
state_val_pair_t * pPairLatency;
atomic_val_t stateUpdatingC;
cpu_cstate_t currentCState;
cpu_cstate_t desireCState;
FUNC_CPU_CSTATE_SET cpuCStateSetFunc;
#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
uint32_t supportBitsetP;
int stateNumP;
state_val_pair_t * pPairFreq;
state_val_pair_t * pPairVolt;
atomic_val_t stateUpdatingP;
cpu_pstate_t currentPState;
cpu_pstate_t desirePState;
FUNC_CPU_PSTATE_SET cpuPStateSetFunc;
#endif /* RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT */
#ifdef RHINO_CONFIG_SMP
cpuset_t childLiveCpuSet;
uint32_t childIndexMask;
#endif /* RHINO_CONFIG_SMP */
char * name;
uint32_t unit;
uint32_t level;
DL_NODE node;
DL_LIST childList;
struct cpu_pwr * pParent;
} cpu_pwr_t;
extern void cpu_pwr_hal_lib_init (void);
extern void cpu_pwr_child_add (cpu_pwr_t * p_cpu_parent, cpu_pwr_t * pCpuChild);
extern kstat_t cpu_pwr_node_init_static (uint32_t,char *,uint32_t,cpu_pwr_t *);
extern kstat_t cpu_pwr_node_init_dyn (uint32_t,char*,uint32_t,cpu_pwr_t **);
extern cpu_pwr_t * cpu_pwr_node_find_by_name (char * pName,uint32_t index);
extern kstat_t cpu_pwr_leaf_node_record (cpu_pwr_t * p_cpu_node, uint32_t cpuIndex);
extern kstat_t cpu_pwr_c_method_set_by_level (uint32_t level, FUNC_CPU_CSTATE_SET cpuCStateSetFunc);
extern kstat_t cpu_pwr_c_state_capability_set (uint32_t cpuIndex, uint32_t supportBitsetC);
extern kstat_t cpu_pwr_c_state_capability_set_by_level (uint32_t level, uint32_t supportBitsetC);
extern kstat_t cpu_pwr_c_state_latency_save (uint32_t cpuIndex, cpu_cstate_t cpu_state, uint32_t latency);
extern uint32_t cpu_pwr_c_state_latency_get (uint32_t cpuIndex, cpu_cstate_t CState);
extern void cpu_pwr_child_index_mask_set (uint32_t, uint32_t);
#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
extern kstat_t cpu_pwr_p_method_set_by_level (uint32_t level, FUNC_CPU_PSTATE_SET cpuPStateSetFunc);
extern kstat_t cpu_pwr_cur_p_state_update_directly (uint32_t cpuIndex, cpu_pstate_t cpuPState);
extern kstat_t cpu_pwr_p_state_capability_set (uint32_t cpuIndex, uint32_t supportBitsetP);
extern kstat_t cpu_pwr_p_state_capability_set_by_level (uint32_t level, uint32_t supportBitsetP);
extern kstat_t cpu_pwr_freq_save (uint32_t cpuIndex, cpu_pstate_t cpu_state, uint32_t cpuFreq);
extern kstat_t cpu_pwr_volt_save (uint32_t cpuIndex, cpu_pstate_t cpu_state, uint32_t cpuVolt);
extern uint32_t cpu_pwr_freq_get_by_p_state (cpu_pwr_t * p_cpu_node, cpu_pstate_t PState);
extern uint32_t cpu_pwr_volt_get_by_p_state (cpu_pwr_t * p_cpu_node, cpu_pstate_t PState);
#endif /*RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT*/
#ifdef __cplusplus
}
#endif
#endif /* __cpu_pwr_hal_lib_h__ */

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csky/csi_kernel/rhino/pwrmgmt/cpu_pwr_lib.h Normal file
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/* cpu_pwr_lib.c - CPU power manager common library */
/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
14jan2018, init vesion
*/
#ifndef __cpu_pwr_lib_h__
#define __cpu_pwr_lib_h__
#ifdef __cplusplus
extern "C" {
#endif
#include "k_api.h"
#include "k_cpuset.h"
#include "pwr_state.h"
#include "dl_list.h"
#ifndef container_of
#define container_of(ptr, type, member) \
((type *)((char *)(ptr) - offsetof(type,member)))
#endif /* container_of */
/* Maximum number of CPUs */
#ifdef RHINO_CONFIG_SMP
#define CPUS_NUM_MAX 4
#else
#define CPUS_NUM_MAX 1
#endif /* RHINO_CONFIG_SMP */
extern void cpu_pwrmgmt_init(void);
extern void cpu_pwr_down (void);
extern void cpu_pwr_up (void);
extern void cpu_pwr_enabled (int enabled);
#if RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT
extern void (*_func_cpu_pwr_idle_enter_hook) (void);
extern void (*_func_cpu_pwr_int_enter_hook) (void);
extern void (*_func_cpu_pwr_int_exit_hook) (void);
#endif /* RHINO_CONFIG_CPU_PWR_P_STATE_SUPPORT */
extern void (*_func_cpu_tickless_up) (void);
extern void (*_func_cpu_tickless_down) (void);
extern kstat_t (*_func_tickless_ignore_list_add) (klist_t *p_tick_node);
#ifdef __cplusplus
}
#endif
#endif /* __cpu_pwr_lib_h__ */

45
csky/csi_kernel/rhino/pwrmgmt/cpu_tickless.h Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
14jan2018, init vesion
*/
#ifndef __cpu_tickless_h__
#define __cpu_tickless_h__
#ifdef __cplusplus
extern "C" {
#endif
#include "k_api.h"
#include "pwr_state.h"
typedef kstat_t (*FUNC_ONE_SHOT_INIT) (void);
typedef uint32_t (*FUNC_ONE_SHOT_SECONDS_MAX) (void);
typedef kstat_t (*FUNC_ONE_SHOT_START) (uint64_t planUse);
typedef kstat_t (*FUNC_ONE_SHOT_STOP) (uint64_t * pPassedUs);
typedef struct
{
FUNC_ONE_SHOT_INIT one_shot_init;
FUNC_ONE_SHOT_SECONDS_MAX one_shot_seconds_max;
FUNC_ONE_SHOT_START one_shot_start;
FUNC_ONE_SHOT_STOP one_shot_stop;
}one_shot_timer_t;
extern kstat_t tickless_init (void);
extern void tickless_c_states_add(uint32_t c_state_set);
extern void tickless_one_shot_timer_save
(cpu_cstate_t c_state, one_shot_timer_t * p_timer);
#ifdef __cplusplus
}
#endif
#endif /* __cpu_tickless_h__ */

189
csky/csi_kernel/rhino/pwrmgmt/dl_list.h Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/* double linked list header */
#ifndef __dl_list_h__
#define __dl_list_h__
#ifdef __cplusplus
extern "C" {
#endif
/* defines */
/* typedefs */
typedef struct _rhino_dlnode /* Node of a linked list. */
{
struct _rhino_dlnode* next; /* Points at the next node in the list */
struct _rhino_dlnode* previous; /* Points at the previous node in the list */
} _RHINO_DL_NODE;
typedef struct /* Header for a linked list. */
{
_RHINO_DL_NODE* head; /* header of list */
_RHINO_DL_NODE* tail; /* tail of list */
} _RHINO_DL_LIST;
typedef _RHINO_DL_NODE DL_NODE;
typedef _RHINO_DL_LIST DL_LIST;
/* DLL_INIT() initialize the specified list to an empty list. */
#define DLL_INIT(list) \
{ \
((DL_LIST *)(list))->head = NULL; \
((DL_LIST *)(list))->tail = NULL; \
}
/* DLL_ADD() adds the specified node to the end of the specified list. */
#define DLL_ADD(list, node) \
{ \
DL_NODE* listTail = (list)->tail; \
DLL_INSERT ((list), listTail, (node)); \
}
/*
* DLL_INSERT() inserts the specified node in the specified list.
* The new node is placed following the specified 'previous' node in the list.
* If the specified previous node is NULL, the node is inserted at the head
* of the list.
*/
#define DLL_INSERT(list, previousNode, node) \
{ \
DL_NODE *temp; \
if ((previousNode) == NULL) \
{ \
temp = ((DL_LIST *)(list))->head; \
((DL_LIST *)(list))->head = (DL_NODE *)(node); \
} \
else \
{ \
temp = ((DL_NODE *)(previousNode))->next; \
((DL_NODE *)(previousNode))->next = (DL_NODE *)(node); \
} \
if (temp == NULL) \
{ \
((DL_LIST *)(list))->tail = (DL_NODE *)(node); \
} \
else \
{ \
temp->previous = (DL_NODE *)(node); \
} \
((DL_NODE *)(node))->next = temp; \
((DL_NODE *)(node))->previous = (DL_NODE *)(previousNode); \
}
/* DLL_REMOVE() Remove the specified node in the doubly linked list.*/
#define DLL_REMOVE(list, node) \
{ \
if (((DL_NODE *)(node))->previous == NULL) \
{ \
((DL_LIST *)(list))->head = ((DL_NODE *)(node))->next; \
} \
else \
{ \
((DL_NODE *)(node))->previous->next = ((DL_NODE *)(node))->next; \
} \
if (((DL_NODE *)(node))->next == NULL) \
{ \
((DL_LIST *)(list))->tail = ((DL_NODE *)(node))->previous; \
} \
else \
{ \
((DL_NODE *)(node))->next->previous = ((DL_NODE *)(node))->previous; \
} \
}
/*
* DLL_FIRST() finds the first node in a doubly linked list.
*
* RETURNS: Pointer to the first node in a list, or NULL if the list is empty.
*/
#define DLL_FIRST(pList) \
( \
(((DL_LIST *)(pList))->head) \
)
/*
* DLL_LAST () finds the last node in a doubly linked list.
*
* RETURNS: Pointer to the last node in list, or NULL if the list is empty.
*/
#define DLL_LAST(pList) \
( \
(((DL_LIST *)(pList))->tail) \
)
/*
* DLL_NEXT() locates the node immediately after the node pointed to by the pNode.
*
* RETURNS: Pointer to the next node in list, or NULL if there is no next node.
*/
#define DLL_NEXT(pNode) \
( \
(((DL_NODE *)(pNode))->next) \
)
/*
* DLL_PREVIOUS() locates the node immediately before the node pointed
* to by the pNode.
*
* RETURNS: Pointer to the preceding node in the list, or
* NULL if there is no next node.
*/
#define DLL_PREVIOUS(pNode) \
( \
(((DL_NODE *)(pNode))->previous) \
)
/*
* DLL_EMPTY() is used to check if list is empty.
* RETURNS: TRUE if list is empty. FALSE otherwise
*/
#define DLL_EMPTY(pList) \
( \
(((DL_LIST *)pList)->head == NULL) \
)
/*
* DLL_GET() gets the first node from the specified list, deletes the node
* from the list, and returns a pointer to the node gotten.
*
* RETURNS: Pointer to the first node in list, or NULL if there is list empty.
*/
#define DLL_GET(list, node) \
{ \
(node) = (void *)((DL_LIST *)(list))->head; \
if ((node) != NULL) \
{ \
((DL_LIST *)(list))->head = ((DL_NODE *)(node))->next; \
if (((DL_NODE *)(node))->next == NULL) \
{ \
((DL_LIST *)(list))->tail = NULL; \
} \
else \
{ \
((DL_NODE *)(node))->next->previous = NULL; \
} \
} \
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __dl_list_h__ */

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csky/csi_kernel/rhino/pwrmgmt/pwr_debug.h Normal file
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/* pwr_debug.c - CPU power manager debug header file */
/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
21jan2018,WangMin writen.
*/
#ifndef __pwr_debug_h__
#define __pwr_debug_h__
#ifdef __cplusplus
extern "C" {
#endif
#include "stdio.h"
#define DBG_OFF 0x00000000
#define DBG_WARN 0x00000001
#define DBG_ERR 0x00000002
#define DBG_INFO 0x00000004
#define DBG_ALL 0xffffffff
extern int pwr_debug_level;
#undef PWR_DEBUG_LINE_INFO
#if RHINO_CONFIG_PWR_DEBUG
#ifdef PWR_DEBUG_LINE_INFO
#define PWR_DBG(lvl,...) \
printf("%s,%d\n",__FILE__,__LINE__); \
do { \
if (pwr_debug_level >= lvl) \
{ \
printf(__VA_ARGS__); \
} \
} \
while (0)
#else /* PWR_DEBUG_LINE_INFO */
#define PWR_DBG(lvl,...) \
do { \
if (pwr_debug_level >= lvl) \
{ \
printf(__VA_ARGS__); \
} \
} \
while (0)
#endif /* ！PWR_DEBUG_LINE_INFO */
#else /* RHINO_CONFIG_PWR_DEBUG */
#define PWR_DBG(lvl,...)
#endif /* ! RHINO_CONFIG_PWR_DEBUG */
#ifdef __cplusplus
}
#endif
#endif /* __pwr_debug_h__ */

117
csky/csi_kernel/rhino/pwrmgmt/pwr_state.h Normal file
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/* vxbPwrStates.h - device power state definitions */
/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
modification history
--------------------
21jan2018,WangMin writen.
*/
/*
DESCRIPTION
This file provides base type define power state.
*/
#ifndef __pwr_state_h__
#define __pwr_state_h__
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* CPU states */
typedef enum
{
CPU_CSTATE_C0 = 0, /* Operating */
CPU_CSTATE_C1 = 1, /* Halt -- not executing put powered on */
CPU_CSTATE_C2 = 2, /* not execuing with lower power than C1 */
CPU_CSTATE_C3 = 3, /* not execuing with lower power than C2 */
CPU_CSTATE_C4 = 4, /* not execuing with lower power than C3 */
CPU_CSTATE_C5 = 5,
CPU_CSTATE_C6 = 6,
CPU_CSTATE_C7 = 7,
CPU_CSTATE_C8 = 8,
CPU_CSTATE_C9 = 9,
CPU_CSTATE_C10 = 10,
CPU_CSTATE_C11 = 11,
CPU_CSTATE_C12 = 12,
CPU_CSTATE_C13 = 13,
CPU_CSTATE_C14 = 14,
CPU_CSTATE_C15 = 15,
CPU_CSTATE_C16 = 16,
CPU_CSTATE_C17 = 17,
CPU_CSTATE_C18 = 18,
CPU_CSTATE_C19 = 19,
CPU_CSTATE_C20 = 20,
CPU_CSTATE_C21 = 21,
CPU_CSTATE_C22 = 22,
CPU_CSTATE_C23 = 23,
CPU_CSTATE_C24 = 24,
CPU_CSTATE_C25 = 25,
CPU_CSTATE_C26 = 26,
CPU_CSTATE_C27 = 27,
CPU_CSTATE_C28 = 28,
CPU_CSTATE_C29 = 29,
CPU_CSTATE_C30 = 30,
CPU_CSTATE_C31 = 31,
CPU_CSTATE_MAX = 31,
CPU_CSTATE_NONE = 0xFF
} cpu_cstate_t;
/* Performance states */
typedef enum
{
CPU_PSTATE_P0 = 0, /* Max power and clock */
CPU_PSTATE_P1 = 1,
CPU_PSTATE_P2 = 2,
CPU_PSTATE_P3 = 3,
CPU_PSTATE_P4 = 4,
CPU_PSTATE_P5 = 5,
CPU_PSTATE_P6 = 6,
CPU_PSTATE_P7 = 7,
CPU_PSTATE_P8 = 8,
CPU_PSTATE_P9 = 9,
CPU_PSTATE_P10 = 10,
CPU_PSTATE_P11 = 11,
CPU_PSTATE_P12 = 12,
CPU_PSTATE_P13 = 13,
CPU_PSTATE_P14 = 14,
CPU_PSTATE_P15 = 15,
CPU_PSTATE_P16 = 16,
CPU_PSTATE_P17 = 17,
CPU_PSTATE_P18 = 18,
CPU_PSTATE_P19 = 19,
CPU_PSTATE_P20 = 20,
CPU_PSTATE_P21 = 21,
CPU_PSTATE_P22 = 22,
CPU_PSTATE_P23 = 23,
CPU_PSTATE_P24 = 24,
CPU_PSTATE_P25 = 25,
CPU_PSTATE_P26 = 26,
CPU_PSTATE_P27 = 27,
CPU_PSTATE_P28 = 28,
CPU_PSTATE_P29 = 29,
CPU_PSTATE_P30 = 30,
CPU_PSTATE_P31 = 31,
CPU_PSTATE_MAX = 32,
CPU_PSTATE_NONE = 0xFF
} cpu_pstate_t;
#ifdef __cplusplus
}
#endif
#endif /* __pwr_state_h__ */