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Initial commit: TXW82x FPV v2.7.0.7-42229 SDK + project sources

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zouhaitao
2026-07-06 11:30:13 +08:00
commit e76462eeb7
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155
csky/csi_kernel/rhino/board/board_cpu_pwr.c Normal file
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#include "k_api.h"
#include "cpu_pwr_config.h"
//#if RHINO_CONFIG_CPU_PWR_MGMT
#include "cpu_pwr_hal_lib.h"
#include "pwr_debug.h"
#include "soc.h"
#if RHINO_CONFIG_CPU_TICKLESS
#include "cpu_tickless.h"
#endif /*RHINO_CONFIG_CPU_TICKLESS*/
#ifdef CONFIG_TEE_CA
#include "drv_tee.h"
#endif
/* forward declarations */
extern cpu_pwr_t *p_cpu_pwr_root_node;
#if RHINO_CONFIG_CPU_TICKLESS
extern one_shot_timer_t tim_one_shot; /* wakeup source for C1 */
#endif /* RHINO_CONFIG_CPU_TICKLESS */
static cpu_pwr_t cpu_pwr_node_package_0;
static cpu_pwr_t cpu_pwr_node_core_0;
static kstat_t board_cpu_c_state_set
(
uint32_t cpuCState,
int master
)
{
switch (cpuCState) {
case CPU_CSTATE_C0:
//printf("enter C0\n");
if (master) {
}
break;
case CPU_CSTATE_C1:
/*
* put CPU into C1 state
* to put CPU into C1 state.
*/
//printf("enter C1\n");
#ifdef CONFIG_CHIP_CH2201
*(volatile unsigned int *)(0xe000e1c0) = 0xffffffff; // reload wakeup_IRQ
//*(volatile unsigned int *)(0xe000e280) = 0xffffffff; // clear pend IRQ
csi_vic_set_wakeup_irq(RTC_IRQn);
csi_vic_set_wakeup_irq(UART2_IRQn);
csi_vic_set_wakeup_irq(UART1_IRQn);
csi_vic_set_wakeup_irq(UART0_IRQn);
csi_vic_set_wakeup_irq(CORET_IRQn);
csi_vic_set_wakeup_irq(GPIOA_IRQn);
csi_vic_set_wakeup_irq(GPIOB_IRQn);
csi_vic_set_wakeup_irq(TIMA0_IRQn);
#ifdef CONFIG_TEE_CA
csi_tee_enter_lpm(0, 0, TEE_LPM_MODE_WAIT);
#else
__WFI();
#endif
#endif
break;
default:
PWR_DBG(DBG_ERR, "invalid C state: C%d\n", cpuCState);
break;
}
return RHINO_SUCCESS;
}
kstat_t board_cpu_pwr_topo_create(void)
{
cpu_pwr_t *pCpuNode = NULL;
cpu_pwr_t *pParentL1 = NULL; /* parent of level 1 */
cpu_pwr_t *pParentL2 = NULL; /* parent of level 2 */
kstat_t retVal = RHINO_SUCCESS;
uint32_t cpuIndex = 0; /* 0 for UP */
if (p_cpu_pwr_root_node == NULL) {
return RHINO_PWR_MGMT_ERR;
}
pParentL1 = p_cpu_pwr_root_node;
pCpuNode = &cpu_pwr_node_package_0;
retVal = cpu_pwr_node_init_static(CPU_PWR_TOPO_LEVEL_1, "package", 0, pCpuNode);
if (retVal != RHINO_SUCCESS) {
return RHINO_PWR_MGMT_ERR;
}
/* add this node as a child of p_cpu_pwr_root_node */
cpu_pwr_child_add(pParentL1, pCpuNode);
pParentL2 = pCpuNode;
pCpuNode = &cpu_pwr_node_core_0;
retVal = cpu_pwr_node_init_static(CPU_PWR_TOPO_LEVEL_2, "core", 0, pCpuNode);
if (retVal != RHINO_SUCCESS) {
return RHINO_PWR_MGMT_ERR;
}
cpu_pwr_child_add(pParentL2, pCpuNode);
/* record this node as leaf node in the topology */
retVal = cpu_pwr_leaf_node_record(pCpuNode, cpuIndex);
if (retVal == RHINO_PWR_MGMT_ERR) {
return RHINO_PWR_MGMT_ERR;
}
retVal = cpu_pwr_c_method_set_by_level(CPU_PWR_TOPO_LEVEL_2,
board_cpu_c_state_set);
if (retVal == RHINO_PWR_MGMT_ERR) {
return RHINO_PWR_MGMT_ERR;
}
retVal = cpu_pwr_c_state_capability_set_by_level(CPU_PWR_TOPO_LEVEL_2,
CPU_STATE_BIT(CPU_CSTATE_C0)
| CPU_STATE_BIT(CPU_CSTATE_C1)
);
if (retVal == RHINO_PWR_MGMT_ERR) {
return RHINO_PWR_MGMT_ERR;
}
cpu_pwr_c_state_latency_save(cpuIndex, CPU_CSTATE_C0, 0);
cpu_pwr_c_state_latency_save(cpuIndex, CPU_CSTATE_C1, 0);
tickless_one_shot_timer_save(CPU_CSTATE_C1, &tim_one_shot);
#if RHINO_CONFIG_CPU_TICKLESS
tickless_c_states_add(CPU_STATE_BIT(CPU_CSTATE_C0)
| CPU_STATE_BIT(CPU_CSTATE_C1)
);
#endif /* RHINO_CONFIG_CPU_TICKLESS */
return retVal;
}
//#endif /* RHINO_CONFIG_CPU_PWR_MGMT */

129
csky/csi_kernel/rhino/board/board_cpu_pwr_rtc.c Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
* This file supplied RTC one-shot start/stop services for CPU tickless
* module, verifyied on STM32L496-DISCOVERY with C3/C4 mode.
* C3: stop mode.
* C4: standby mode.
*/
#include "k_api.h"
#include "cpu_pwr_config.h"
//#if (RHINO_CONFIG_CPU_PWR_MGMT > 0)
//#if (RHINO_CONFIG_CPU_TICKLESS > 0)
#include "cpu_tickless.h"
#include "drv_rtc.h"
#define RTC_ONE_SHOT_DBG
extern void SystemClock_Config(void);
#define RTC_WAKEUP_SOURCE_FREQ_2000HZ
//#define RTC_WAKEUP_SOURCE_FREQ_1HZ
/* According reference manual of STM32496G, RTC_WUTR is 16bit */
#define RTC_WAKE_UP_RGE_MAX 0xffff
//static uint32_t one_shot_enabled = 0;
//static uint32_t one_shot_start_value = 0;
static uint32_t one_shot_max_period = 0;/* seconds */
//static kspinlock_t rtc_spin;
//static RTC_HandleTypeDef RtcHandle;
#ifdef RTC_ONE_SHOT_DBG
//static int rtc_wakeup_irq_count = 0;
#endif /* RTC_ONE_SHOT_DBG */
static kstat_t rtc_init(void);
static uint32_t rtc_one_shot_max_seconds(void);
static kstat_t rtc_one_shot_start(uint64_t planUs);
static kstat_t rtc_one_shot_stop(uint64_t *pPassedUs);
one_shot_timer_t rtc_one_shot = {
rtc_init,
rtc_one_shot_max_seconds,
rtc_one_shot_start,
rtc_one_shot_stop,
};
static uint32_t rtc_one_shot_max_seconds(void)
{
return one_shot_max_period;
}
static kstat_t rtc_init(void)
{
return RHINO_SUCCESS;
}
/*******************************************************************************
*
* rtc_one_shot_start - enable the timer in oneshot mode
*
* This function enables the timer in oneshot mode, the interrupt will be fired
* after servral microseconds which is indicated by planUs.
*
* RETURNS: RHINO_SUCCESS or RHINO_PWR_MGMT_ERR if timer is not enabled
*
* ERRNO
*/
static kstat_t rtc_one_shot_start(uint64_t planUs)
{
return RHINO_SUCCESS;
}
/*******************************************************************************
*
* one_shot_planed_cnt - cancel the timer which was in oneshot mode
*
* This function is called to cancel the timer which was in oneshot mode.
* the time has passed(microseconds) will be return in pPassedUs.
*
* RETURNS: RHINO_SUCCESS or RHINO_PWR_MGMT_ERR if timer is not disabled
*
* ERRNO: N/A
*/
static kstat_t rtc_one_shot_stop
(
uint64_t *pPassedUs /* OUT */
)
{
return RHINO_SUCCESS;
}
/*******************************************************************************
*
* RTC_WKUP_IRQHandler - ISR handle of RTC wakeup interrupt
*
* This function will replace weak one which is defined in
* startup_stm32l496xx_keil.s
*
* RETURNS: N/A
*
* ERRNO: N/A
*/
void RTC_WKUP_IRQHandler(void)
{
}
#ifdef RTC_ONE_SHOT_DBG
void rtc_info_show(void)
{
}
#endif /* RTC_ONE_SHOT_DBG */
//#endif /* RHINO_CONFIG_CPU_TICKLESS */
//#endif /* RHINO_CONFIG_CPU_PWR_MGMT */

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csky/csi_kernel/rhino/board/board_cpu_pwr_systick.c Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
DESCRIPTION
This file provides two fundtions systick_suspend()/systick_resume()
which is used by cpu tickless module to suspend/resume system tick
interrupt.
Differrent board may has different way to suspend/resume system tick
interrupt, please reference your board/soc user manual to find the
detail for how to implement these two functions.
*/
#include "k_api.h"
#include "cpu_pwr_config.h"
#include "port.h"
#include "csi_core.h"
#if (RHINO_CONFIG_CPU_PWR_MGMT > 0)
extern uint32_t csi_coret_suspend();
extern uint32_t csi_coret_resume();
void systick_suspend(void)
{
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk | CORET_CTRL_TICKINT_Msk;
}
void systick_resume(void)
{
CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
CORET_CTRL_TICKINT_Msk |
CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
}
#else
void systick_suspend(void)
{
}
void systick_resume(void)
{
}
#endif /* RHINO_CONFIG_CPU_PWR_MGMT */

152
csky/csi_kernel/rhino/board/board_cpu_pwr_timer.c Normal file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
* According user manual of STM32L496-DISCOVERY
* TIM2 and TIM5 are 32-bit timer, other timer is 16-bit.
* This file will use TIM5 to supply one-shot start/stop service
* for CPU tickless module.
* verifyied on STM32L496-DISCOVERY with C1/C2 mode.
* C1: sleep mode.
* C2: low power sleep mode.
*/
#include "k_api.h"
#include "cpu_pwr_config.h"
//#if (RHINO_CONFIG_CPU_PWR_MGMT > 0)
//#if (RHINO_CONFIG_CPU_TICKLESS > 0)
#include "cpu_tickless.h"
//#include "drv_timer.h"
#include "soc.h"
//#define TIM_DBG
#ifndef CONFIG_LPM_TICKLESS_SYSTIM
#define CONFIG_LPM_TICKLESS_SYSTIM 0
#endif
extern int aos_lpm_register_device(uint8_t level, void *func, void *param);
timer_handle_t wakeup_timer;
static uint32_t init_flag = 0;
static kspinlock_t tim_spin;
static kstat_t tim_timer_init(void);
static uint32_t tim_one_shot_max_seconds(void);
static kstat_t tim_one_shot_start(uint64_t planUs);
static kstat_t tim_one_shot_stop(uint64_t *pPassedUs);
one_shot_timer_t tim_one_shot = {
tim_timer_init,
tim_one_shot_max_seconds,
tim_one_shot_start,
tim_one_shot_stop,
};
void timer_event_cb(int32_t idx, timer_event_e event)
{
#ifdef TIM_DBG
printf("time out\n");
#endif
}
kstat_t tim_timer_init(void)
{
if (init_flag == 1) {
return RHINO_SUCCESS;
}
krhino_spin_init(&tim_spin);
wakeup_timer = csi_timer_initialize(CONFIG_LPM_TICKLESS_SYSTIM, timer_event_cb);
csi_timer_config(wakeup_timer, TIMER_MODE_FREE_RUNNING);
#ifdef CONFIG_LPM
aos_lpm_register_device(0, csi_timer_power_control, wakeup_timer);
#endif
init_flag = 1;
return RHINO_SUCCESS;
}
/* return the max period(in second) that could trigger interrupt */
uint32_t tim_one_shot_max_seconds(void)
{
/* the max 32 bit value / count frequency */
return 0xffffffff / drv_get_sys_freq();
}
/*******************************************************************************
*
* tim_one_shot_start - enable the timer in oneshot mode
*
* This function enables the timer in oneshot mode, the interrupt will be fired
* after servral microseconds which is indicated by planUs.
*
* RETURNS: RHINO_SUCCESS or RHINO_PWR_MGMT_ERR if timer is not enabled
*
* ERRNO
*/
kstat_t tim_one_shot_start
(
uint64_t planUs /* IN */
)
{
krhino_spin_lock_irq_save(&tim_spin);
#ifdef TIM_DBG
printf("tim_one_shot_start %d\n", planUs);
#endif
csi_timer_set_timeout(wakeup_timer, planUs);
csi_timer_start(wakeup_timer);
krhino_spin_unlock_irq_restore(&tim_spin);
return RHINO_SUCCESS;
}
/*******************************************************************************
*
* tim_one_shot_stop - cancel the timer which was in oneshot mode
*
* This function is called to cancel the timer which was in oneshot mode.
* the time has passed(microseconds) will be return in pPassedUs.
*
* RETURNS: RHINO_SUCCESS or RHINO_PWR_MGMT_ERR if timer is not disabled
*
* ERRNO: N/A
*/
kstat_t tim_one_shot_stop
(
uint64_t *pPassedUs /* OUT */
)
{
uint32_t load_val = 0;
uint32_t current_val = 0;
*pPassedUs = 0;
krhino_spin_lock_irq_save(&tim_spin);
csi_timer_get_load_value(wakeup_timer, &load_val);
csi_timer_get_current_value(wakeup_timer, &current_val);
*pPassedUs = (load_val - current_val) ? (load_val - current_val) : 0;
*pPassedUs = *pPassedUs * 1000000 / drv_get_sys_freq();
#ifdef TIM_DBG
printf("tim_one_shot_stop, pPassedUs %u, load_val %u, current_val %u\n", *pPassedUs, load_val, current_val);
#endif
csi_timer_stop(wakeup_timer);
krhino_spin_unlock_irq_restore(&tim_spin);
return RHINO_SUCCESS;
}
//#endif /* RHINO_CONFIG_CPU_TICKLESS */
//#endif /* RHINO_CONFIG_CPU_PWR_MGMT */