213 lines
7.9 KiB
C
213 lines
7.9 KiB
C
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/**
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******************************************************************************
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* @file E:\work\venus_v2\SW\trunk\verify\test\audio\dsd1793.h
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* @author Troy
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* @version V1.0.0
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* @date 01-31-2023
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* @brief This file contains all the dsd1793 firmware functions.
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******************************************************************************
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* @attention
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*
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*
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*
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*
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*
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******************************************************************************
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*/
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#ifndef __DSD1793_H
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#define __DSD1793_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if 1
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/*!
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* IIC config
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*/
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//PIN ADDR1, PIN ADDR0
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//00, 01, 10, 11
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#define DSD1793_PIN_ADDR0 (0)
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#define DSD1793_PIN_ADDR1 (0)
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#define DSD1793_DSD_MODE (1)
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#define DSD1793_PCM_MODE (0)
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#define DSD1793_IIC (HG_I2C1_DEVID)
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#define DSD1793_IIC_DEVICE_ADDR ((0x4<<4) | (0xC | (DSD1793_PIN_ADDR1) | (DSD1793_PIN_ADDR0)))
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#define DSD1793_IIC_SCL_PIN (PC_13)
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#define DSD1793_IIC_SDA_PIN (PC_14)
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#if 0
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//#define DSD1793_IIC_SCL_GPIO_PORT (GPIOC)
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//#define DSD1793_IIC_SCL_PIN_NUM (13)
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//#define DSD1793_IIC_SDA_GPIO_PORT (GPIOC)
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//#define DSD1793_IIC_SDA_PIN_NUM (14)
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//#define DSD1793_IIC_SCL_PIN_BIT (BIT(DSD1793_IIC_SCL_PIN_NUM))
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//#define DSD1793_IIC_SDA_PIN_BIT (BIT(DSD1793_IIC_SDA_PIN_NUM))
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#define SMAPLE_FRQUENCY (48000)
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#define OVER_SAMPLE_RATE (192)
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#define __SYSCLK (SYS_CLK)
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#define SCK_IIS (0)
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#define SCK_TIMER (0)
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#define DSD1793_SCK_GPIO_PORT (GPIOD)
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#define DSD1793_SCK_GPIO_PIN_NUM (14)
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#define DSD1793_SCK_GPIO_PIN_BIT (BIT(DSD1793_SCK_GPIO_PIN_NUM))
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#define __dsd1793_iic_module_init()\
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do{\
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TYPE_LL_IIC_INIT _init;\
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TYPE_LL_IIC_CFG _cfg;\
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memset(&_cfg, 0, sizeof(TYPE_LL_IIC_CFG));\
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memset(&_init, 0, sizeof(TYPE_LL_IIC_INIT));\
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_cfg.presc = 8;\
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_cfg.scldel = 15;\
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_cfg.sdadel = 15;\
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_cfg.scll = 31;\
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_cfg.sclh = 31;\
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_cfg.work_mode = LL_IIC_MASTER_MODE;\
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ll_iic_init(DSD1793_IIC, &_init);\
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ll_iic_config(DSD1793_IIC, &_cfg);\
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}while(0);
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#define __dsd1793_iic_io_init()\
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do{\
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ll_gpio_iomap_inout_config(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OUT_SPI2_SCK_OUT,\
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LL_GPIO_IN_SPI2_SCK_IN);\
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ll_gpio_iomap_inout_config(DSD1793_IIC_SDA_GPIO_PORT, DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OUT_SPI2_IO0_OUT,\
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LL_GPIO_IN_SPI2_IO0_IN);\
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ll_gpio_ospeed_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OSPEED_3);\
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ll_gpio_ospeed_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OSPEED_3);\
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ll_gpio_pull_config(DSD1793_IIC_SCL_GPIO_PORT , DSD1793_IIC_SCL_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
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ll_gpio_pull_config(DSD1793_IIC_SDA_GPIO_PORT , DSD1793_IIC_SDA_PIN_NUM, LL_GPIO_OPENDRAIN_PULL_UP, LL_GPIO_PULL_LEVEL_4_7K);\
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ll_gpio_bit_set(DSD1793_IIC_SCL_GPIO_PORT, DSD1793_IIC_SCL_PIN_BIT);\
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ll_gpio_bit_set(DSD1793_IIC_SDA_GPIO_PORT,DSD1793_IIC_SDA_PIN_BIT);\
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}while(0);
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#if (SCK_IIS)
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#define __dsd1793_sck_init()\
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do{\
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TYPE_LL_IIS_INIT _init;\
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TYPE_LL_IIS_CFG _cfg;\
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memset(&_init, 0, sizeof(TYPE_LL_IIS_INIT));\
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memset(&_cfg, 0, sizeof(TYPE_LL_IIS_CFG));\
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_cfg.mode = LL_IIS_MASTER_MODE;\
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_cfg.work_mode = LL_IIS_SIMPLEX_TX;\
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_cfg.channel_mode = LL_IIS_STEREO_MODE;\
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_cfg.ws_pol = LL_IIS_LOW_FOR_LEFT_CHANNEL;\
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_cfg.bck_pol = LL_IIS_SAMPLE_IN_RISING_EDGE;\
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_cfg.data_format = LL_IIS_STANDARD_MODE;\
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_cfg.mclk_sel = LL_IIS_MCLK_SEL_SYS_PLL;\
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_cfg.mclk_output = LL_IIS_MCLK_OUT_ENABLE;\
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_cfg.mclk_div = 16;\
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_cfg.baudrate = 29;\
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_cfg.ws = 31;\
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_cfg.bit = 31;\
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ll_gpio_iomap_inout_config(DSD1793_SCK_GPIO_PORT, DSD1793_SCK_GPIO_PIN_NUM, LL_GPIO_OUT_IIS0_MCLK_OUT , LL_GPIO_IN_IIS0_MCLK_IN__LCD_D19_IN_MASK2_6);\
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ll_iis_config(IIS0, &_cfg);\
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}while(0);
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#endif
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#if (SCK_TIMER)
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#define __dsd1793_sck_init()\
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do{\
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TYPE_LL_TIMER_CFG _timer_cfg;\
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TYPE_LL_TIMER_INIT _timer_init_cfg;\
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memset(&_timer_cfg, 0, sizeof(TYPE_LL_TIMER_CFG));\
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memset(&_timer_init_cfg, 0, sizeof(TYPE_LL_TIMER_INIT));\
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ll_timer_init(TIMER0, &_timer_init_cfg);\
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_timer_cfg.work_mode_sel = LL_TIMER_MODE_PWM;\
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_timer_cfg.in_src_sel = LL_TIMER_IN_SRC_SYS_CLK;\
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_timer_cfg.prescaler_sel = 0;\
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_timer_cfg.period_val = (__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE)) - 1;\
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_timer_cfg.pwm_val = ((__SYSCLK/(SMAPLE_FRQUENCY*OVER_SAMPLE_RATE))/2) - 1;\
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_timer_cfg.count_val = 0;\
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ll_timer_config(TIMER0, &_timer_cfg);;\
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ll_gpio_ospeed_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), 7);\
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ll_gpio_iomap_output_config(DSD1793_SCK_GPIO_PORT, (DSD1793_SCK_GPIO_PIN_NUM), LL_GPIO_OUT_M1_9_LCD_DATA_O_12__TMR0_PWM_OUT);\
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ll_timer_start(TIMER0);\
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}while(0);
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#endif
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#define __dsd1793_iic_write_1byte(data)\
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do{\
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ll_iic_master_tx(DSD1793_IIC, data, LL_IIC_NONE_FLAG);\
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}while(0);
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#define __dsd1793_iic_read_1byte(data)\
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do{\
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data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_NONE_FLAG);\
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}while(0);
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#define __dsd1793_iic_write(reg, p_data, len)\
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do{\
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uint8 *__p_data = (uint8 *)p_data;\
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if(__p_data){\
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ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
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__dsd1793_iic_write_1byte(reg);\
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if(len){\
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for(uint16 __len=0; __len<len-1; __len++){\
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__dsd1793_iic_write_1byte(*__p_data++);\
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}\
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}\
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ll_iic_master_tx(DSD1793_IIC, *__p_data, LL_IIC_STOP_FLAG);\
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}\
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}while(0);
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#define __dsd1793_iic_read(reg, p_data, len)\
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do{\
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uint8 *__p_data = (uint8 *)p_data;\
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if(__p_data){\
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ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 0, LL_IIC_START_FLAG);\
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__dsd1793_iic_write_1byte(reg);\
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ll_iic_master_tx(DSD1793_IIC, DSD1793_IIC_DEVICE_ADDR<<1 | 1, LL_IIC_START_FLAG);\
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if(len){\
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for(uint16 __len=0; __len<len-1; __len++){\
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__dsd1793_iic_read_1byte(*__p_data++);\
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}\
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}\
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*__p_data = ll_iic_master_rx(DSD1793_IIC, LL_IIC_STOP_FLAG | LL_IIC_NACK_FLAG);\
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}\
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}while(0);
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#endif
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#define __dsd1793_delay_ms(x) os_sleep_ms(x)
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/*!
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* DSD1793 reg index define
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*/
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#define DSD1793_REG16 16
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#define DSD1793_REG17 17
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#define DSD1793_REG18 18
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#define DSD1793_REG19 19
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#define DSD1793_REG20 20
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#define DSD1793_REG21 21
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#define DSD1793_REG22 22
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void dsd1793_reg_write_l8bit(uint16 reg, uint16 val_l8bit);
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void dsd1793_reg_read_l8bit(uint16 reg, uint16 *val_l8bit);
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void dsd1793_init(void);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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/******************************** END OF FILE *****/
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