165 lines
4.9 KiB
C
165 lines
4.9 KiB
C
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#ifndef _HGUART_V4_HW_H_
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#define _HGUART_V4_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***** UARTCON *****/
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/*! Timeout interrupt en
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*/
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#define LL_SIMPLE_UART_CON_TO_IE (1UL << 31)
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/*! Timeout function en
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*/
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#define LL_SIMPLE_UART_CON_TO_EN (1UL << 30)
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/*! Timeout pending
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*/
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#define LL_SIMPLE_UART_CON_CLRTOPEND (1UL << 29)
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/*! Transmission completed The 1byte flag was cleared to zero
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*/
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#define LL_SIMPLE_UART_CON_CLRTXDONE (1UL << 28)
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/*! The frame receiving error detection flag is cleared to zero
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*/
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#define LL_SIMPLE_UART_CON_CLRFERR (1UL << 27)
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/*! The receive cache register is not null flag cleared
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*/
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#define LL_SIMPLE_UART_CON_CLRRXDONE (1UL << 26)
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/*! DMA interrupt flag cleared to zero
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*/
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#define LL_SIMPLE_UART_CON_CLRDMAPEND (1UL << 25)
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/*! Receive address interrupt flag cleared to zero
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*/
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#define LL_SIMPLE_UART_CON_CLRRXADDRPEND (1UL << 24)
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/*! Transmission completed 1byte flag. This bit is 0 when the module is disabled
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*/
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#define LL_SIMPLE_UART_CON_TXDONE (1UL << 21)
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/*! Frame receiving error detection flag
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*/
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#define LL_SIMPLE_UART_CON_FERR (1UL << 20)
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/*! Receive cache register is not empty flag, this bit is 0 when the module is not enabled
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*/
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#define LL_SIMPLE_UART_CON_RXBUFNOTEMPTY (1UL << 19)
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/*! The send cache register is an empty flag. This bit is 0 when the module is disabled
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*/
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#define LL_SIMPLE_UART_CON_TXBUFEMPTY (1UL << 18)
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/*! The DMA completion flag bit, which is set to 1 when a send or receive is complete using DMA
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*/
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#define LL_SIMPLE_UART_CON_DMAPEND (1UL << 17)
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/*! Receive address interrupt flag RXADDRPEND
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*/
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#define LL_SIMPLE_UART_CON_RXADDRPEND (1UL << 16)
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/*! RX_TIMEOUT PENDING
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*/
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#define LL_SIMPLE_UART_CON_TO_PENDING (1UL << 15)
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/*! Select UART output with which PWM carrier:
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*/
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#define LL_SIMPLE_UART_CON_CARRIER_SEL(n) (((n)&0x09) << 11)
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/*! Set the CARRIER_SEL bit to the PWM carrier mode enable bit. Specify the carrier_sel bit for the specific PWM carrier of the TIMER
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*/
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#define LL_SIMPLE_UART_CON_PWM_CARRIER_EN (1UL << 10)
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/*! The receiving address was interrupted. Procedure
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*/
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#define LL_SIMPLE_UART_CON_RXADDRIE (1UL << 9)
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/*! Error detection interrupt enabled
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*/
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#define LL_SIMPLE_UART_CON_FERRIE (1UL << 8)
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/*! DMA interrupt enabled
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*/
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#define LL_SIMPLE_UART_CON_DMA_IE (1UL << 7)
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/*! Stop bit setting
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*/
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#define LL_SIMPLE_UART_CON_STOPBIT (1UL << 6)
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/*! The 9bit function was enabled
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*/
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#define LL_SIMPLE_UART_CON_BIT9EN (1UL << 5)
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/*! The Uart function was enabled
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*/
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#define LL_SIMPLE_UART_CON_UARTEN (1UL << 4)
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/*! Send data inversely
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*/
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#define LL_SIMPLE_UART_CON_TXINV (1UL << 3)
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/*! The received data is reversed
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*/
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#define LL_SIMPLE_UART_CON_RXINV (1UL << 2)
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/*! Send 1byte to enable the interrupt
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*/
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#define LL_SIMPLE_UART_CON_UARTTXIE (1UL << 1)
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/*! The receiving interrupt function was enabled
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*/
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#define LL_SIMPLE_UART_CON_UARTRXIE (1UL << 0)
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/***** UARTBAUD *****/
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/*! Baud rate setting
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*/
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#define LL_SIMPLE_UART_UARTBAUD(n) (((n)&0x0003FFFF) << 0)
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/***** UARTDATA *****/
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/*! Data register
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*/
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#define LL_SIMPLE_UART_UARTDATA(n) (((n)&0x000000FF) << 0)
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/***** UARTTOCON *****/
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/*! TOCON register
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*/
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#define LL_SIMPLE_UART_TOCON(n) (((n)&0x0000FFFF) << 0)
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/***** UARTDMAADR *****/
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/*! DMAADR register
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*/
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#define LL_SIMPLE_UART_UARTDMAADR(n) (((n)&0xFFFFFFFF) << 0)
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/***** UARTDMALEN *****/
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/*! DMALEN register
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*/
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#define LL_SIMPLE_UART_UARTDMALEN(n) (((n)&0x000007FF) << 0)
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/***** UARTDMACON *****/
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/*!DMACON register
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*/
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#define LL_SIMPLE_UART_UART_TX_USEDMA_KEY (1UL << 3)
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#define LL_SIMPLE_UART_UART_RX_USEDMA_KEY (1UL << 2)
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#define LL_SIMPLE_UART_UART_TX_USEDMA (1UL << 1)
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#define LL_SIMPLE_UART_UART_RX_USEDMA (1UL << 0)
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/**
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* @brief Simple Universal Synchronous Asynchronous Receiver Transmitter
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*/
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struct hguart_v4_hw{
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__IO uint32_t CON;
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__IO uint32_t BAUD;
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__IO uint32_t DATA;
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__IO uint32_t TOCON;
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__IO uint32_t DMAADR;
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__IO uint32_t DMALEN;
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__IO uint32_t DMACON;
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__IO uint32_t DMACNT;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HGUART_V4_HW_H_ */
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