260 lines
7.5 KiB
C
260 lines
7.5 KiB
C
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#ifndef _HGSPI_V1_HW_H_
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#define _HGSPI_V1_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup SPI MODULE REGISTER
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* @{
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*/
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/***** CON0(for SPI) Register *****/
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/*! SPI slave read status done interrupt enable
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*/
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#define LL_SPI_CON0_SLAVE_WRONGCMD_IE_EN (1UL << 25)
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/*! SPI slave read status done interrupt enable
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*/
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#define LL_SPI_CON0_SLAVE_WIREMODE_IE_EN (1UL << 24)
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/*! SPI slave read status done interrupt enable
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*/
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#define LL_SPI_CON0_SLAVE_RDSTATUS_IE_EN (1UL << 23)
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/*! SPI slave read data done interrupt enable
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*/
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#define LL_SPI_CON0_SLAVE_RDDATA_IE_EN (1UL << 22)
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/*! SPI slave write data done interrupt enable
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*/
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#define LL_SPI_CON0_SLAVE_WRDATA_IE_EN (1UL << 21)
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/*! SPI slave state enable
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*/
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#define LL_SPI_CON0_SLAVE_STATE_EN (1UL << 20)
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/*! SPI frame size
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*/
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#define LL_SPI_CON0_FRAME_SIZE(n) (((n)&0x3F) << 14)
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/*! Get SPI frame size
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*/
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#define LL_SPI_CON0_GET_FRAME_SIZE(n) (((n)>>14) & 0x3F)
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/*! SPI slave CS(NSS) rising edge interrupt enable
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*/
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#define LL_SPI_CON0_NSS_POS_IE_EN (1UL << 13)
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/*! SPI CS(NSS) pin enable
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*/
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#define LL_SPI_CON0_NSS_PIN_EN (1UL << 12)
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/*! SPI CS(NSS) output high
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* @note Only valid in SPI master mode
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*/
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#define LL_SPI_CON0_NSS_HIGH (1UL << 11)
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/*! Input data synchronization enable in SPI slave mode
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*/
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#define LL_SPI_CON0_SLAVE_SYNC_EN (1UL << 7)
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/*! Input data synchronization enable in SPI master mode
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*/
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#define LL_SPI_CON0_MASTER_SYNC_EN (1UL << 6)
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/*! The SPI transfers data from the low bit
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*/
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#define LL_SPI_CON0_LSB_FIRST (1UL << 4)
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/*! SPI wire mode
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*/
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#define LL_SPI_CON0_WIRE_MODE(n) (((n)&0x03) << 2)
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/*! Get SPI wire mode
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*/
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#define LL_SPI_CON0_WIRE_MODE_GET(n) (((n)>>2) & 0x03)
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/*! SPI mode
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*/
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#define LL_SPI_CON0_SPI_MODE(n) (((n)&0x03) << 0)
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/***** CON1(for SPI) Register *****/
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/*! SPI DMA done interrupt enable
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*/
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#define LL_SPI_CON1_DMA_IE_EN (1UL << 9)
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/*! SPI FIFO overflow interrupt enable
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*/
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#define LL_SPI_CON1_BUF_OV_IE_EN (1UL << 8)
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/*! SPI RX FIFO not empty interrupt enable
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*/
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#define LL_SPI_CON1_RX_BUF_NOT_EMPTY_IE_EN (1UL << 7)
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/*! SPI TX FIFO not full interrupt enable
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*/
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#define LL_SPI_CON1_TX_BUF_NOT_FULL_IE_EN (1UL << 6)
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/*! SPI transfers one frame interrupt enable
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*/
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#define LL_SPI_CON1_SSP_IE_EN (1UL << 5)
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/*! SPI DMA enable
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*/
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#define LL_SPI_CON1_DMA_EN (1UL << 4)
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/*! The SPI is set to the TX direction
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*/
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#define LL_SPI_CON1_TX_EN (1UL << 3)
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/*! SPI working mode
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*/
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#define LL_SPI_CON1_MODE(n) (((n)&0x01) << 2)
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/*! Get SPI working mode
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*/
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#define LL_SPI_CON1_GET_MODE(n) (((n)>>2) & 0x01)
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/*! SPI/IIC selection
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*/
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#define LL_SPI_CON1_SPI_I2C_SEL(n) (((n)&0x01) << 1)
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/*! SPI/IIC module enable
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*/
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#define LL_SPI_CON1_SSP_EN (1UL << 0)
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/***** SSP CMD DATA(for SPI) Register *****/
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/*! Write data(32bit)
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*/
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#define LL_SPI_SSP_CMD_DATA_WRITE(n) (n)
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/*! Read data(32bit)
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*/
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#define LL_SPI_SSP_CMD_DATA_READ(n) (n)
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/***** BAUD(for SPI) Register *****/
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/*! Set baud rate(16bit)
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*/
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#define LL_SPI_BAUD(n) (n)
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/***** DMA Tx LEN(for SPI) Register *****/
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/*! Set DMA Tx length(12bit)
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*/
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#define LL_SPI_DMA_TX_LEN(n) (n)
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/***** DMA Tx CNT(for SPI) Register *****/
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/*! The length of the byte of the transmitted data(12bit)
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*/
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#define LL_SPI_DMA_TX_CNT(n) (n)
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/***** DMA Tx STADR(for SPI) Register *****/
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/*! DMA Tx start address(13bit)
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*/
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#define LL_SPI_DMA_TX_STADR(n) (n)
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/***** DMA Rx LEN(for SPI) Register *****/
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/*! Set DMA Rx length(12bit)
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*/
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#define LL_SPI_DMA_RX_LEN(n) (n)
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/***** DMA Rx CNT(for SPI) Register *****/
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/*! The length of the byte of the received data(12bit)
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*/
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#define LL_SPI_DMA_RX_CNT(n) (n)
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/***** DMA Rx STADR(for SPI) Register *****/
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/*! DMA Rx start address(13bit)
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*/
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#define LL_SPI_DMA_RX_STADR(n) (n)
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/***** STA(for SPI) Register *****/
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/*! SPI Slave wrong cmd pending
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*/
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#define LL_SPI_STA_SLAVE_WRONG_CMD_PENDING (1UL << 28)
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/*! SPI Slave wiremode change pending
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*/
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#define LL_SPI_STA_SLAVE_WIREMODE_CFG_PENDING (1UL << 23)
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/*! SPI Slave read status pending
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*/
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#define LL_SPI_STA_SLAVE_RDSTATUS_PENDING (1UL << 22)
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/*! SPI Slave read data pending
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*/
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#define LL_SPI_STA_SLAVE_RDDATA_PENDING (1UL << 21)
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/*! SPI Slave write data pending
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*/
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#define LL_SPI_STA_SLAVE_WRDATA_PENDING (1UL << 20)
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/*! Clear fifo
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*/
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#define LL_SPI_STA_CLEAR_BUF_CNT (1UL << 19)
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/*! Get how many bytes of valid data in the FIFO
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*/
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#define LL_SPI_STA_BUF_CNT(n) (((n)>>16) & 0x07)
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/*! SPI master receive data busy pending
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*/
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#define LL_SPI_STA_MASTER_RX_BUSY_PENDING (1UL << 15)
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/*! The SPI slave gets the CS pin state
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*/
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#define LL_SPI_STA_SLAVE_CS_STATE (1UL << 11)
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/*! SPI module busy pending
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*/
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#define LL_SPI_STA_SSP_BUSY_PENDING (1UL << 10)
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/*! SPI slave CS(NSS) rising edge detected pending
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*/
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#define LL_SPI_STA_NSS_POS_PENDING (1UL << 5)
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/*! SPI DMA done pending
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*/
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#define LL_SPI_STA_DMA_PENDING (1UL << 4)
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/*! SPI FIFO overflow pending
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*/
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#define LL_SPI_STA_BUF_OV_PENDING (1UL << 3)
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/*! SPI FIFO empty pending
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*/
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#define LL_SPI_STA_BUF_EMPTY_PENDING (1UL << 2)
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/*! SPI FIFO full pending
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*/
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#define LL_SPI_STA_BUF_FULL_PENDING (1UL << 1)
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/*! SPI transfers one frame done pending
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*/
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#define LL_SPI_STA_DONE_PENDING (1UL << 0)
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/***** SLAVESTA(for SPI) Register *****/
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#define LL_SPI_SLAVE_STA_TX_LEN(n) (((n)&0xFF) << 16)
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#define LL_SPI_SLAVE_STA_RX_LEN(n) (((n)&0xFF) << 8)
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#define LL_SPI_SLAVE_STA_RX_READY_EN (1UL << 7)
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#define LL_SPI_SLAVE_STA_TX_READY_EN (1UL << 6)
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#define LL_SPI_SLAVE_STA_SW_RESERVED (1UL << 5)
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#define LL_SPI_SLAVE_STA_WRONG_COMMAND (1UL << 4)
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#define LL_SPI_SLAVE_STA_DATA_TOGGLE (1UL << 3)
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#define LL_SPI_SLAVE_STA_TX_OVERFLOW (1UL << 2)
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#define LL_SPI_SLAVE_STA_RX_READY_FLG (1UL << 1)
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#define LL_SPI_SLAVE_STA_TX_READY_FLG (1UL << 0)
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/***** SSP_DLY Register *****/
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/*! Transfer delay time config
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@Note: t = APB_CLK * (n)
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*/
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#define LL_SPI_AND_IIC_SSP_DLY(n) ((n & 0xFF) << 0)
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/** @brief SPI register structure
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* @{
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*/
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struct hgspi_v1_hw {
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__IO uint32_t CON0;
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__IO uint32_t CON1;
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__IO uint32_t CMD_DATA;
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__IO uint32_t BAUD;
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__IO uint32_t TDMALEN;
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__IO uint32_t RDMALEN;
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__IO uint32_t TDMACNT;
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__IO uint32_t RDMACNT;
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__IO uint32_t TSTADR;
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__IO uint32_t RSTADR;
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__IO uint32_t STA;
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__IO uint32_t SLAVESTA;
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__IO uint32_t SSP_DLY;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HGSPI_V1_HW_H_ */
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