334 lines
9.3 KiB
C
334 lines
9.3 KiB
C
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/*
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* Copyright (C) 2024 ZHUHAI TAIXIN Co., Ltd. All rights reserved.
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*
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*/
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/******************************************************************************
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* @file cld_cahce.h
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* @brief cldache Access Layer Header File
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* @version V1.0
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* @date 2024.5.29
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******************************************************************************/
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#ifndef __CLD_CACHE_H_GENERIC
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#define __CLD_CACHE_H_GENERIC
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#include <stdint.h>
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#include <csi_gcc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*******************************************************************************
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* definitions
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******************************************************************************/
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/**
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\ingroup
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@{
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*/
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/* definitions */
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typedef struct
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{
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__I uint32_t HWPARAMS; //0x000
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__I uint32_t reserve0[3]; //0x004-0x00c
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__IO uint32_t CTRL; //0x010
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__I uint32_t NSEC_ACCESS; //0x014
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__I uint32_t reserve1[2]; //0x018-0x01c
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__O uint32_t MAINT_CTRL_ALL; //0x020
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__O uint32_t MAINT_CTRL_LINES; //0x024
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__I uint32_t MAINT_STATUS; //0x028
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__I uint32_t reserve2[53]; //0x02c-0x0fc
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__I uint32_t SECIRQSTAT; //0x100;
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__O uint32_t SECIRQSCLR; //0x104;
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__IO uint32_t SECIRQEN; //0x108;
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__I uint32_t SECIRQINFO1; //0x10C;
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__I uint32_t SECIRQINFO2; //0x110;
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__I uint32_t reserve3[11]; //0x114-0x13c
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__I uint32_t NSECIRQSTAT; //0x140;
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__O uint32_t NSECIRQSCLR; //0x144;
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__IO uint32_t NSECIRQEN; //0x148;
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__I uint32_t NSECIRQINFO1; //0x14C;
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__I uint32_t NSECIRQINFO2; //0x150;
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__I uint32_t reserve4[107]; //0x154-0x2fc
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__I uint32_t SECHIT; //0x300;
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__I uint32_t SECMISS; //0x304;
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__IO uint32_t SECSTATCTRL; //0x308;
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__I uint32_t reserve5[1]; //0x30c
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__I uint32_t NSECHIT; //0x310;
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__I uint32_t NSECMISS; //0x314;
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__IO uint32_t NSECSTATCTRL; //0x318;
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__I uint32_t reserve6[813]; //0x31c-0xFCC
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__I uint32_t PIDR4; //0xFD0;
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__I uint32_t PIDR5; //0xFD4;
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__I uint32_t PIDR6; //0xFD8;
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__I uint32_t PIDR7; //0xFDC;
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__I uint32_t PIDR0; //0xFE0;
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__I uint32_t PIDR1; //0xFE4;
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__I uint32_t PIDR2; //0xFE8;
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__I uint32_t PIDR3; //0xFEC;
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__I uint32_t CIDR0; //0xFF0;
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__I uint32_t CIDR1; //0xFF4;
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__I uint32_t CIDR2; //0xFF8;
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__I uint32_t CIDR3; //0xFFC;
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} DCACHE_CTRL_TypeDef;
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#define DCACHE_CTRL_BASE2 ((uint32_t)0x50000000)
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#define DCACHE_CTRL ((DCACHE_CTRL_TypeDef *) DCACHE_CTRL_BASE2)
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/* THE memory is forced non-sec */
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#define DCACHE_MAINT_NO_SEC ((uint32_t)0x00000004)
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#define DCACHE_STA_ENABLE ((uint32_t)0x00000001)
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#define DCACHE_STA_ONGOING_EN ((uint32_t)0x00000002)
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#define DCACHE_STA_ONGOING_MAINT ((uint32_t)0x00000004)
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#define DCACHE_STA_ONGOING_PWR_MAINT ((uint32_t)0x00000008)
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#define DCACHE_STA_IS_CLEAN ((uint32_t)0x00000010)
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static inline uint32_t cld_cache_get_status(void)
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{
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return DCACHE_CTRL->MAINT_STATUS;
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}
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static inline uint32_t cld_cache_is_maint_done(void)
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{
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return (0x4 == (DCACHE_CTRL->SECIRQSTAT & 0xC));
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}
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static inline uint32_t cld_cache_is_maint_ignore(void)
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{
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return (DCACHE_CTRL->SECIRQSTAT & 0x8);
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}
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static inline void cld_cache_clr_maint_done(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0x4;
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}
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static inline void cld_cache_clr_maint_ignore(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0x8;
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}
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static inline void cld_cache_clr_all_pending(void)
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{
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DCACHE_CTRL->SECIRQSCLR = 0xFF;
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}
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static inline uint32_t cld_cache_is_enable(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ENABLE;
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}
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static inline uint32_t cld_cache_is_clean(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_IS_CLEAN;
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}
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static inline uint32_t cld_cache_is_ongoing_enable(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_EN;
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}
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static inline uint32_t cld_cache_is_ongoing_maint(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_MAINT;
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}
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static inline uint32_t cld_cache_is_ongoing_pwr_maint(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & DCACHE_STA_ONGOING_PWR_MAINT;
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}
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static inline uint32_t cld_cache_is_ongoing(void)
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{
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return DCACHE_CTRL->MAINT_STATUS & (DCACHE_STA_ONGOING_PWR_MAINT | DCACHE_STA_ONGOING_MAINT | DCACHE_STA_ONGOING_EN);
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}
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static inline void cld_cache_force_write_through(void)
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{
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DCACHE_CTRL->CTRL |= 1UL << 1;
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}
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/* TXW82x S_NS ONLY */
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#define CLD_CACHE_MAINT_OPT_ATOMIC(opt)\
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do {\
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uint32 __disable_irq(void);\
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void __enable_irq(void);\
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uint32 flag = __disable_irq();\
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cld_cache_clr_all_pending();\
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opt;\
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while (!cld_cache_is_maint_done());\
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if(!flag) __enable_irq();\
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} while (0);
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#define CLD_CACHE_MAINT_OPT(opt)\
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do {\
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cld_cache_clr_all_pending();\
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opt;\
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while (!cld_cache_is_maint_done());\
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} while (0);
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#define CLD_CACHE_MAINT_OPT_WAIT() //do { while (cld_cache_is_ongoing_maint()); } while (0)
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#define CLD_CACHE_MAINT_FB_KICKOFF()\
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do {\
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extern uint32 psram_rsv_addr;\
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = (psram_rsv_addr & 0xFFFFFFE0) | 0x2 | DCACHE_MAINT_NO_SEC;);\
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*(uint32 volatile*)((uint32_t)psram_rsv_addr);\
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} while(0)
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static inline void cld_cache_clean_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 1;);
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}
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static inline void cld_cache_invalidate_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 2;);
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}
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static inline void cld_cache_clean_invalidate_all(void)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_ALL = 3;);
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}
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static inline void cld_cache_disable(void)
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{
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__DSB();
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cld_cache_invalidate_all();
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DCACHE_CTRL->CTRL &= ~(1UL << 0);
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while (cld_cache_is_enable());
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while (cld_cache_is_ongoing_maint());
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}
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static inline void cld_cache_enable(void)
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{
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cld_cache_disable();
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/* deny powerdown \ enable nsec stat、 maintain lines */
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DCACHE_CTRL->CTRL |= 1UL << 0 | 0x10 | 0x70000;
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while (!cld_cache_is_enable());
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}
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static inline void cld_cache_irq_enable(void)
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{
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/* ONLY ERROR : XOM_ERR(not support) & TR_ERR */
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DCACHE_CTRL->SECIRQEN = 0x90;
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}
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static inline void cld_cache_clean_line(uint32_t addr)
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{
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = ((uint32_t)addr & (0xFFFFFFFF << 5)) | 0x1 | DCACHE_MAINT_NO_SEC;);
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CLD_CACHE_MAINT_OPT_WAIT();
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}
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/**
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\brief D-Cache Clean by address
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\details Cleans D-Cache for the given address
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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static inline void cld_cache_clean_range (uint32_t *addr, int32_t dsize)
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{
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int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
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uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
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int32_t linesize = 32;
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op_addr |= 0x1 | DCACHE_MAINT_NO_SEC;
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while (op_size > 0) {
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
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CLD_CACHE_MAINT_OPT_WAIT();
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}
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__DSB();
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}
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/**
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\brief D-Cache Clean and Invalidate by address
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\details Cleans and invalidates D_Cache for the given address
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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static inline void cld_cache_clean_invalid_range (uint32_t *addr, int32_t dsize)
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{
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int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
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uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
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int32_t linesize = 32;
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op_addr |= 0x3 | DCACHE_MAINT_NO_SEC;
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while (op_size > 0) {
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
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CLD_CACHE_MAINT_OPT_WAIT();
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}
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__DSB();
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}
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/**
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\brief D-Cache Invalidate by address
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\details Cleans and invalidates D_Cache for the given address
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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static inline void cld_cache_invalid_range (uint32_t *addr, int32_t dsize)
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{
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int32_t op_size = ((uint32_t)addr & 0x1F) + dsize;
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uint32_t op_addr = (uint32_t)addr & (0xFFFFFFFF << 5);
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int32_t linesize = 32;
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op_addr |= 0x2 | DCACHE_MAINT_NO_SEC;
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CLD_CACHE_MAINT_FB_KICKOFF();
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while (op_size > 0) {
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CLD_CACHE_MAINT_OPT_ATOMIC(DCACHE_CTRL->MAINT_CTRL_LINES = op_addr; op_addr += linesize; op_size -= linesize;);
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CLD_CACHE_MAINT_OPT_WAIT();
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}
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__DSB();
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}
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static inline uint32_t cld_cache_get_nsec_hits(void)
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{
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return DCACHE_CTRL->NSECHIT;
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}
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static inline uint32_t cld_cache_get_nsec_miss(void)
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{
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return DCACHE_CTRL->NSECMISS;
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}
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static inline void cld_cache_reset_profile(void)
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{
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DCACHE_CTRL->NSECSTATCTRL |= 0x2;
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}
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static inline void cld_cache_enable_profile(void)
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{
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while (cld_cache_is_ongoing());
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DCACHE_CTRL->NSECSTATCTRL |= 0x1;
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}
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static inline void cld_cache_disable_profile(void)
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{
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DCACHE_CTRL->NSECSTATCTRL &= ~ 0x1;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CLD_CACHE_H_GENERIC */
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