386 lines
11 KiB
C
386 lines
11 KiB
C
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "hal/dma.h"
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#include "osal/string.h"
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int32 dma_pause(struct dma_device *dma, uint32 ch)
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{
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if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->pause) {
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return ((const struct dma_hal_ops *)dma->dev.ops)->pause(dma, ch);
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}
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return RET_ERR;
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}
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int32 dma_resume(struct dma_device *dma, uint32 ch)
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{
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if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->resume) {
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return ((const struct dma_hal_ops *)dma->dev.ops)->resume(dma, ch);
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}
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return RET_ERR;
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}
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#pragma GCC push_options
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#pragma GCC optimize ("O3")
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void cache_deal_invalid(void *dst,uint32 n){
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uint8 *d1;
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uint8 *d2;
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uint8 st_head,end_head;
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d1 = (uint8 *)dst;
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st_head = (uint32)d1%32;
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end_head = 32 - ((uint32)d1+n)%32;
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n = n+st_head+end_head;
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d1 = d1 - st_head;
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d2 = (uint8 *)((uint32)d1&0x0fffffff);
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memcpy(d2,d1,32);
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memcpy(d2+n-32,d1+n-32,32);
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sys_dcache_invalid_range((void *)d1, n);
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}
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void cache_deal_writeback(void *dst,uint32 n){
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uint8 *d1;
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uint8 *d2;
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uint8 st_head,end_head;
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d1 = (uint8 *)dst;
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st_head = ((uint32)d1 % 32);
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end_head = 32 - ((uint32)d1+n)%32;
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n = n+st_head+end_head;
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d1 = d1 - st_head;
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d2 = (uint8 *)((uint32)d1&0x0fffffff);
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memcpy(d2,d1,32);
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memcpy(d2+n-32,d1+n-32,32);
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sys_dcache_clean_range((void *)d1, n);
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}
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void dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n)
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{
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uint8 dma_buf[64];
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uint8 *s,*d;
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uint8 *s1,*d1,*s2,*d2;
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uint32 i = 0;
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uint32 addr;
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ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
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struct dma_xfer_data xfer_data;
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if(n <= 64){
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s1 = (uint8 *)src;
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d1 = (uint8 *)dst;
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for(i = 0;i < n;i++){
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d1[i] = s1[i];
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}
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return;
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}
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s1 = (uint8 *)src;
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d1 = (uint8 *)dst;
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// for(i = 0;i < 16;i++){ //处理头
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// dma_buf[i] = s1[i];
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// }
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memcpy(dma_buf, s1, 32);
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s2 = (uint8 *)src+n-32;
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d2 = (uint8 *)dst+n-32;
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// for(i = 0;i < 16;i++){ //处理头
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// dma_buf[i+16] = s2[i];
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// }
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memcpy(dma_buf+32, s2, 32);
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n = n - 64;
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s = (uint8 *)src+32;
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d = (uint8 *)dst+32;
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xfer_data.dest = (uint32)d;
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xfer_data.src = (uint32)s;
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xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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xfer_data.element_num = n;
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xfer_data.dir = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
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xfer_data.src_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_id = 0;
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xfer_data.src_id = 0;
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xfer_data.irq_hdl = NULL;
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xfer_data.endian = 0;
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addr = (uint32)s;
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addr = addr&((0x7FFFFFFUL << 5));
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s = (uint8*)addr;
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addr = (uint32)d;
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addr = addr&((0x7FFFFFFUL << 5));
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d = (uint8*)addr;//&CACHE_CIR_INV_ADDR_Msk;
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sys_dcache_clean_range((void *)s, (int32_t)s2-(int32_t)s); //cache->psram
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sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d); //psram cache invalid //最后一行可能没有无效化
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// printf("===============s:%08x d:%08x\r\n\r\n",s,d);
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// xfer_data.irq_data = 0;
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((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
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// sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);
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// for(i = 0;i < 16;i++){ //处理头
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// d1[i] = dma_buf[i];
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// }
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memcpy(d1, dma_buf, 32);
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// for(i = 0;i < 16;i++){ //处理尾
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// d2[i] = dma_buf[i+16];
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// }
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memcpy(d2, dma_buf+32, 32);
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}
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void dma_memcpy_no_cache(struct dma_device *dma, void *dst, const void *src, uint32 n)
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{
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//uint8 dma_buf[64];
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uint8 *s,*d;
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//uint8 *s1,*d1,*s2,*d2;
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//uint32 i = 0;
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uint32 addr;
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ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
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struct dma_xfer_data xfer_data;
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s = (uint8 *)src;
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d = (uint8 *)dst;
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xfer_data.dest = (uint32)d;
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xfer_data.src = (uint32)s;
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xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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xfer_data.element_num = n;
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xfer_data.dir = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
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xfer_data.src_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_id = 0;
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xfer_data.src_id = 0;
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xfer_data.irq_hdl = NULL;
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xfer_data.endian = 0;
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addr = (uint32)s;
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((const struct dma_hal_ops *)dma->dev.ops)->only_hw_xfer(dma, &xfer_data);
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}
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void dma_memset_word(struct dma_device *dma, void *dst, uint32 c, uint32 n)
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{
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uint32 val = c;
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uint8 *d, *d1, *d2;
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uint32 i = 0;
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uint32 size = 0;
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uint32 addr;
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if(n <= 64){
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d1 = (uint8 *)dst;
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i = (uint32)dst % 4;
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size = i + n;
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for(;i < (size);i++){
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*d1++ = (val >> ((i % 4)<<3));
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}
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return;
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}
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d1 = (uint8 *)(dst);
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d2 = (uint8 *)(dst+n-32);
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n = n - 64;
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d = (uint8 *)(dst+32);
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ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
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struct dma_xfer_data xfer_data;
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xfer_data.dest = (uint32)d;
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xfer_data.src = (uint32)&val;
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xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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xfer_data.element_num = n;
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xfer_data.dir = (((uint32)dst) < SRAM_BASE) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
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xfer_data.src_addr_mode = DMA_XFER_MODE_RECYCLE;
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xfer_data.dst_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_id = 0;
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xfer_data.src_id = 0;
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xfer_data.irq_hdl = NULL;
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xfer_data.irq_data = 0;
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xfer_data.endian = 0;
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addr = (uint32)d;
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addr = addr&((0x7FFFFFFUL << 5));
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d = (uint8 *)addr;//&CACHE_CIR_INV_ADDR_Msk;
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sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d);
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((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
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i = (uint32)dst % 4;
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size = i + 32;
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for(;i < (size);i++){ //处理头
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*d1++ = (val >> ((i % 4)<<3));
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}
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i = (uint32)d2 % 4;
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size = i + 32;
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for(;i < (size);i++){ //处理尾
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*d2++ = (val >> ((i % 4)<<3));
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}
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}
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void dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n)
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{
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uint32 val = c | (c<<8) | (c<<16) | (c<<24);
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dma_memset_word(dma, dst, val, n);
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}
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#pragma GCC pop_options
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void dma_memcpy_endian(struct dma_device *dma, void *dst, const void *src, uint32 n, enum dma_endian_type type)
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{
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uint32 dma_buf[16];
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uint8 *s,*d;
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uint8 *s1, *d1, *s2, *d2;
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uint16 *s3, *d3, *s4;
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uint32 *s5, *d5, *s6;
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uint32 i = 0;
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uint32 addr;
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uint32 ret = RET_OK;
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ASSERT(dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer);
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struct dma_xfer_data xfer_data;
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switch (type)
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{
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case DMA_ENDIAN_TYPE_NO_OVERTURN:
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s1 = (uint8 *)src;
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d1 = (uint8 *)dst;
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s2 = (uint8 *)dma_buf;
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if (n <= 64)
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{
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for(i = 0; i < (n >> type); i++){
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*d1++ = *s1++;
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}
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} else {
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for(i = 0; i < (32 >> type); i++){ // 处理头
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*s2++ = *s1++;
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}
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s1 = (uint8 *)((uint32)src+n-32);
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for(i = 0; i < (32 >> type); i++){ // 处理尾
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*s2++ = *s1++;
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}
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}
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break;
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case DMA_ENDIAN_TYPE_16BIT_OVERTURN:
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s3 = (uint16 *)src;
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d3 = (uint16 *)dst;
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s4 = (uint16 *)dma_buf;
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ret = (n % 2 != 0);
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if (!ret)
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{
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if (n <= 64)
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{
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for(i = 0; i < (n >> type); i++){
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*d3++ = __REVSH(*s3++);
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}
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} else {
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for(i = 0; i < (32 >> type); i++){ // 处理头
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*s4++ = __REVSH(*s3++);
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}
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s3 = (uint16 *)((uint32)src+n-32);
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for(i = 0; i < (32 >> type); i++){ // 处理尾
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*s4++ = __REVSH(*s3++);
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}
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}
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} else {
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os_printf("dma memcpy size : %d endian: %d err\r\n", n, type);
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}
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break;
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case DMA_ENDIAN_TYPE_32BIT_OVERTURN:
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s5 = (uint32 *)src;
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d5 = (uint32 *)dst;
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s6 = (uint32 *)dma_buf;
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ret = (n % 4 != 0);
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if (!ret)
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{
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if (n <= 64)
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{
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for(i = 0; i < (n >> type); i++){
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*d5++ = __REV(*s5++);
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}
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} else {
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for(i = 0; i < (32 >> type); i++){ // 处理头
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*s6++ = __REV(*s5++);
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}
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s5 = (uint32 *)((uint32)src+n-32);
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for(i = 0; i < (32 >> type); i++){ // 处理尾
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*s6++ = __REV(*s5++);
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}
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}
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} else {
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os_printf("dma memcpy size : %d endian: %d err\r\n", n, type);
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}
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break;
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default:
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os_printf("dma memcpy endian type err!");
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ret = RET_ERR;
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break;
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}
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if (ret || (n <= 64)) return;
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s1 = (uint8 *)src;
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d1 = (uint8 *)dst;
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s2 = (uint8 *)(src+n-32);
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d2 = (uint8 *)(dst+n-32);
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n = n - 64;
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s = (uint8 *)(src+32);
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d = (uint8 *)(dst+32);
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xfer_data.dest = (uint32)d;
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xfer_data.src = (uint32)s;
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xfer_data.element_per_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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xfer_data.element_num = n;
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xfer_data.dir = ((((uint32)dst) < SRAM_BASE) || (((uint32)src) < SRAM_BASE)) ? DMA_XFER_DIR_M2D : DMA_XFER_DIR_M2M;
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xfer_data.src_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_addr_mode = DMA_XFER_MODE_INCREASE;
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xfer_data.dst_id = 0;
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xfer_data.src_id = 0;
|
||
|
|
xfer_data.irq_hdl = NULL;
|
||
|
|
xfer_data.endian = type;
|
||
|
|
addr = (uint32)s;
|
||
|
|
addr = addr&((0x7FFFFFFUL << 5));
|
||
|
|
s = (uint8*)addr;
|
||
|
|
addr = (uint32)d;
|
||
|
|
addr = addr&((0x7FFFFFFUL << 5));
|
||
|
|
d = (uint8*)addr;//&CACHE_CIR_INV_ADDR_Msk;
|
||
|
|
sys_dcache_clean_range((void *)s, (int32_t)s2-(int32_t)s); //cache->psram
|
||
|
|
sys_dcache_invalid_range((void *)d, (int32_t)d2-(int32_t)d); //psram cache invalid //最后一行可能没有无效化
|
||
|
|
|
||
|
|
((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, &xfer_data);
|
||
|
|
memcpy(d1, dma_buf, 32);
|
||
|
|
memcpy(d2, (void *)((uint32)dma_buf+32), 32);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data)
|
||
|
|
{
|
||
|
|
if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->xfer) {
|
||
|
|
return ((const struct dma_hal_ops *)dma->dev.ops)->xfer(dma, data);
|
||
|
|
}
|
||
|
|
return RET_ERR;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32 dma_status(struct dma_device *dma, uint32 ch)
|
||
|
|
{
|
||
|
|
if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->get_status) {
|
||
|
|
return ((const struct dma_hal_ops *)dma->dev.ops)->get_status(dma, ch);
|
||
|
|
}
|
||
|
|
return RET_ERR;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32 dma_stop(struct dma_device *dma, uint32 ch)
|
||
|
|
{
|
||
|
|
if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->stop) {
|
||
|
|
return ((const struct dma_hal_ops *)dma->dev.ops)->stop(dma, ch);
|
||
|
|
}
|
||
|
|
return RET_ERR;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2)
|
||
|
|
{
|
||
|
|
if (dma && ((const struct dma_hal_ops *)dma->dev.ops)->ioctl) {
|
||
|
|
return ((const struct dma_hal_ops *)dma->dev.ops)->ioctl(dma, cmd, param1, param2);
|
||
|
|
}
|
||
|
|
return RET_ERR;
|
||
|
|
}
|