312 lines
9.9 KiB
C
312 lines
9.9 KiB
C
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#ifndef _HGTIMER_V4_HW_H
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#define _HGTIMER_V4_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***** TIMERx CON Register *****/
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/*! Timer IR selection whether lsb first send (for TIMER1/2 only)
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*/
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#define LL_TIMER_CON_IR_TMR_FST_LSB_SEL (1UL << 29)
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/*! Timer IR function logic 0 PWM polarity selection (for TIMER1/2 only)
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*/
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#define LL_TIMER_CON_IR_ZERO_PWMPOL (1UL << 28)
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/*! Timer IR function logic 1 PWM polarity selection (for TIMER1/2 only)
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*/
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#define LL_TIMER_CON_IR_ONE_PWMPOL (1UL << 27)
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/*! Timer IR function enable (for TIMER1/2 only)
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*/
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#define LL_TIMER_CON_IR_EN (1UL << 26)
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/*! PWM polarity selection in TIMER module
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*/
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#define LL_TIMER_CON_PWMPOL (1UL << 25)
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/*! The polarity of capture event 1 is selected: 0 = rising edge, 1 = falling edge.
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*/
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#define LL_TIMER_CON_CAP1POL(n) ((n & 0x1) << 21)
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/*! When the capture event 1 occurs, the value of the CNT is automatically cleared.
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*/
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#define LL_TIMER_CON_CTRRST1 (1UL << 17)
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/*! The number of the Capture register:
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* 00 : Capture data store in CAP1
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* 01 : Capture data store in CAP1 CAP2
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* 10 : Capture data store in CAP1 CAP2 CAP3
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* 11 : Capture data store in CAP1 CAP2 CAP3 CAP4
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*/
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#define LL_TIMER_CON_CAP_CNT(n) (((n)&0x3) << 15)
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/*! Capture selection:
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* 00 : GPIO
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* 01 : GPIO OR
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* 10 : compare0 output
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* 11 : compare1 output
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*/
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#define LL_TIMER_CON_CAP_SEL(n) (((n)&0x3) << 13)
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/*! Output sync signal selection:
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* 00 : CNT value = PRD value
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* 01 : CNT value = CMP value
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* 10 : Output SYNCI value to SYNCO
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* 11 : PWM output is assigned to SYNCO
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*/
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#define LL_TIMER_CON_SYNCO_SEL(n) (((n)&0x3) << 11)
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/*! Synci polarity inversion:
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* 1 : Invert
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* 0 : not reversed
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*/
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#define LL_TIMER_CON_SYNCI_POL (1UL << 10)
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/*! Synci function selection
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* 00 : disable
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* 01 : kick start
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* 10 : reset
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* 11 : gating
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*/
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#define LL_TIMER_CON_SLAVE_MODE(n) (((n)&0x3) << 8)
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/*! Timer prescaler settings:
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* 000 : 0 frequency division
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* 001 : 2 frequency division
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* 010 : 4 frequency division
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* 011 : 8 frequency division
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* 100 : 16 frequency division
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* 101 : 32 frequency division
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* 110 : 64 frequency division
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* 111 : 128 frequency division
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*/
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#define LL_TIMER_CON_PSC(n) (((n)&0x7) << 5)
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/*! Timer counter source select bits:
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* 001 : Internal high speed RC
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* 010 : Internal low speed RC
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* 011 : External crystal oscillator divided by 2 clocks
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* 100 : timer inc pin rising
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* 101 : timer inc pin falling
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* 110 : timer inc pin rising and falling
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* Others : system clock
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*/
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#define LL_TIMER_CON_INC_SRC_SEL(n) (((n)&0x7) << 2)
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/*! Timer mode select bits:
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* 00 : timer counter mode
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* 01 : timer pwm mode
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* 10 : timer capture mode
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* Others : reservation
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*/
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#define LL_TIMER_CON_MODE_SEL(n) (((n)&0x3) << 0)
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/***** TIMERx EN Register *****/
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/*! TMR enable signal, active high.
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*/
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#define LL_TIMER_EN_TMREN (1UL << 0)
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/***** TIMERx IE Register *****/
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/*! Timer IR TX word done interrupt enable (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_WORD_DONE_IE (1UL << 11)
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/*! Timer IR TX done interrupt enable (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_DONE_IE (1UL << 10)
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/*! Dma buffer full interrupt enable.
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*/
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#define LL_TIMER_IE_DMA_FL_IE (1UL << 9)
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/*! Dma buffer half full interrupt enable.
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*/
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#define LL_TIMER_IE_DMA_HF_IE (1UL << 8)
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/*! The slave mode trigger mode or reset mode interrupt enable.
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*/
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#define LL_TIMER_IE_SLAVE_IE (1UL << 7)
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/*! When the CNT value is equal to the CMP value, the interrupt is enabled and is valid only in pwm mode.
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*/
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#define LL_TIMER_IE_CMP_IE (1UL << 6)
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/*! When the CNT value is equal to the PRD value, the interrupt is enabled and is valid only in the counter mode/PWM mode.
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*/
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#define LL_TIMER_IE_PRD_IE (1UL << 5)
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/*! When the CNT value overflows (16'hffff), the interrupt is enabled.
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*/
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#define LL_TIMER_IE_OVF_IE (1UL << 4)
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/*! When the capture event 1 occurs, the interrupt is enabled.
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@note: none this capture event interrupt
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*/
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#define LL_TIMER_IE_CAP1_IE (1UL << 0)
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/***** TIMERx CNT Register *****/
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/*! Count register.
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*/
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#define LL_TIMER_CNT(n) (((n)&0xFFFFFFFF) << 0)
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/***** TIMERx FLG Register *****/
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/*! Timer IR TX word done interrupt flag (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_WORD_DONE_FLG (1UL << 11)
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/*! Timer IR TX done interrupt flag (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_DONE_FLG (1UL << 10)
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/*! Dma buffer full sign.
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*/
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#define LL_TIMER_IE_DMA_FL_FLG (1UL << 9)
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/*! Dma buffer half full sign.
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*/
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#define LL_TIMER_IE_DMA_HF_FLG (1UL << 8)
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/*! The slave mode flag (reset or trigger only).
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*/
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#define LL_TIMER_IE_SLAVE_FLG (1UL << 7)
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/*! The CNT value is equal to the CMP value flag and is valid only in pwm mode.
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*/
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#define LL_TIMER_IE_CMP_FLG (1UL << 6)
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/*! The CNT value is equal to the PRD value flag and is valid only in counter mode/PWM mode.
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*/
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#define LL_TIMER_IE_PRD_FLG (1UL << 5)
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/*! CNT value overflow (16'hffff) flag.
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*/
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#define LL_TIMER_IE_OVF_FLG (1UL << 4)
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/*! Capture event 1 occurs.
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*/
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#define LL_TIMER_IE_CAP1_FLG (1UL << 0)
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/***** TIMERx CLR Register *****/
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/*! Timer IR TX word done interrupt clear (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_WORD_DONE_CLR (1UL << 11)
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/*! Timer IR TX done interrupt clear (for TIMER1/2 only)
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*/
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#define LL_TIMER_IE_IR_TX_DONE_CLR (1UL << 10)
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/*! Dma buffer full sign clear.
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*/
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#define LL_TIMER_IE_DMA_FL_CLR (1UL << 9)
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/*! Dma buffer half full sign clear.
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*/
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#define LL_TIMER_IE_DMA_HF_CLR (1UL << 8)
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/*! The slave mode flag (reset or trigger only) clear.
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*/
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#define LL_TIMER_IE_SLAVE_CLR (1UL << 7)
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/*! The CNT value is equal to the CMP value flag clear.
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*/
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#define LL_TIMER_IE_CMP_CLR (1UL << 6)
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/*! The CNT value is equal to the PRD value flag clear.
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*/
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#define LL_TIMER_IE_PRD_CLR (1UL << 5)
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/*! The CNT value overflow (16'hffff) flag is cleared.
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*/
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#define LL_TIMER_IE_OVF_CLR (1UL << 4)
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/*! Capture event 1 occurs flag clear.
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*/
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#define LL_TIMER_IE_CAP1_CLR (1UL << 0)
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/***** TIMERx CAP1/PR Register *****/
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/*! Capture mode : capture register 1
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* Timing mode/PWM mode: Count period register
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*/
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#define LL_TIMER_CMP1_PR(n) (((n)&0xFFFFFFFF) << 0)
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/***** TIMERx CAP2/CMP Register *****/
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/*! Capture mode : capture register 2
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* Timing mode/PWM mode: compare register
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*/
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#define LL_TIMER_CMP2_CMP(n) (((n)&0xFFFFFFFF) << 0)
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/***** TIMERx CAP3/PR_SD Register *****/
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/*! Capture mode : capture register 3
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* Timing mode/PWM mode: counting period shadow register
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*/
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#define LL_TIMER_CMP3_PR_SD(n) (((n)&0xFFFFFFFF) << 0)
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/***** TIMERx CAP4/CMP_SD Register *****/
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/*! Capture mode : capture register 4
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* Timing mode/PWM mode: Compare shadow registers
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*/
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#define LL_TIMER_CMP4_CMP_SD(n) (((n)&0xFFFFFFFF) << 0)
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/***** TIMERx DCCTL Register *****/
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/*! Dma mode selection
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* 0 : Single mode, after the specified dma length is completed, disable TMR.
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* 1 : Loop mode, after the dma length is specified, restart from the start address.
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*/
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#define LL_TIMER_DMA_LPBK (1UL << 1)
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/*! Dma enabled.
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*/
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#define LL_TIMER_DMA_EN (1UL << 0)
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/***** TIMERx DADR Register *****/
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/*! Dma starting address.
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*/
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#define LL_TIMER_DADR_STADR(n) (((n)&0xFFFF) << 0)
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/***** TIMERx DLEN Register *****/
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/*! Dma buffer length (32bit), if the buffer is n, the configuration is n-1;
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*/
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#define LL_TIMER_DLEN_LEN(n) (((n)&0xFFFF) << 0)
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/***** TIMERx DCNT Register *****/
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/*! The number of dma data is valid.
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*/
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#define LL_TIMER_DCNT_CNT(n) (((n)&0xFFFF) << 0)
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/***** TIMER ALLCON Register *****/
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/*! The timer3 sync count value is cleared.
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*/
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#define LL_TIMER_ALLCON_TMR3_SYNC (1UL << 11)
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/*! The timer2 sync count value is cleared.
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*/
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#define LL_TIMER_ALLCON_TMR2_SYNC (1UL << 10)
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/*! The timer1 sync count value is cleared.
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*/
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#define LL_TIMER_ALLCON_TMR1_SYNC (1UL << 9)
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/*! The timer0 sync count value is cleared.
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*/
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#define LL_TIMER_ALLCON_TMR0_SYNC (1UL << 8)
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/*! Timer3 starts counting.
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*/
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#define LL_TIMER_ALLCON_TMR3_KICK (1UL << 3)
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/*! Timer2 starts counting.
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*/
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#define LL_TIMER_ALLCON_TMR2_KICK (1UL << 2)
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/*! Timer1 starts counting.
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*/
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#define LL_TIMER_ALLCON_TMR1_KICK (1UL << 1)
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/*! Timer0 starts counting.
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*/
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#define LL_TIMER_ALLCON_TMR0_KICK (1UL << 0)
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/*! Configure the trigger path for the sync count of TIMER.
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*/
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#define LL_TIMER_ALLCON_SYNC_COUNT_ALL(n) (((n)&0x3F) << 8)
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/*! Configure the synchronous trigger path of TIMER.
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*/
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#define LL_TIMER_ALLCON_KICK_ALL(n) (((n)&0x3F) << 0)
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struct hgtimer_v4_hw {
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__IO uint32_t TMR_CON;
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__IO uint32_t TMR_EN;
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__IO uint32_t TMR_IE;
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__IO uint32_t TMR_CNT;
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__IO uint32_t TMR_FLG;
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__IO uint32_t TMR_CLR;
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__IO uint32_t TMR_CAP1;
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__IO uint32_t TMR_CAP2;
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__IO uint32_t TMR_CAP3;
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__IO uint32_t TMR_CAP4;
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/* The following registers only for timer1 & timer2 */
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__IO uint32_t TMR_DCTL;
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__IO uint32_t TMR_DADR;
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__IO uint32_t TMR_DLEN;
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__IO uint32_t TMR_DCNT;
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__IO uint32_t TMR_IR_BCNT;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HGTIMER_V4_HW_H */
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