374 lines
11 KiB
C
374 lines
11 KiB
C
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/**
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* @file hgpwm_v0.c
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* @author bxd
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* @brief pwm
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* @version
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* TXW80X; TXW81X
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* @date 2023-08-02
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*
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* @copyright Copyright (c) 2023
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*
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*/
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "osal/irq.h"
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#include "osal/string.h"
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#include "hal/timer_device.h"
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#include "hal/pwm.h"
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#include "dev/pwm/hgpwm_v0.h"
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/**********************************************************************************/
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/* LOW LAYER FUNCTION */
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/**********************************************************************************/
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static int32 hgpwm_v0_switch_hal_pwm_channel(enum pwm_channel param) {
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switch (param) {
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case (PWM_CHANNEL_0):
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return 0;
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break;
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case (PWM_CHANNEL_1):
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return 1;
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break;
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case (PWM_CHANNEL_2):
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return 2;
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break;
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case (PWM_CHANNEL_3):
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return 3;
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break;
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case (PWM_CHANNEL_4):
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return 4;
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break;
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case (PWM_CHANNEL_5):
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return 5;
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break;
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// case (PWM_CHANNEL_6):
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// return 6;
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// break;
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// case (PWM_CHANNEL_7):
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// return 7;
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// break;
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// case (PWM_CHANNEL_8):
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// return 8;
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// break;
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// case (PWM_CHANNEL_9):
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// return 9;
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// break;
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// case (PWM_CHANNEL_10):
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// return 10;
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// break;
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default:
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return -1;
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break;
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}
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}
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static int32 hgpwm_v0_config(struct hgpwm_v0 *dev, enum pwm_channel channel, struct hgpwm_v0_config *config) {
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struct hgpwm_v0_config *p_config = config;
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uint32 channel_to_reg = 0;
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int32 ret_val = RET_OK;
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/* Make sure the config struct pointer */
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if (!p_config) {
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return -EINVAL;
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}
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/* Make sure the channel */
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channel_to_reg = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_to_reg) {
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return -EINVAL;
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}
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/* Make sure the timer is attached */
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if ((dev->channel[channel_to_reg])) {
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ret_val = timer_device_ioctl((struct timer_device *)dev->channel[channel_to_reg], HGPWM_V0_FUNC_CMD_MASK, (uint32)p_config, 0);
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} else {
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ret_val = RET_ERR;
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}
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return ret_val;
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}
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/**********************************************************************************/
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/* ATTCH FUNCTION */
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/**********************************************************************************/
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static int32 hgpwm_v0_init(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (dev->opened[channel_num]) {
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return -EBUSY;
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}
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/* config pwm */
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config.period = period_sysclkpd_cnt;
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config.duty = h_duty_sysclkpd_cnt;
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config.func_cmd = HGPWM_V0_FUNC_CMD_INIT;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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dev->opened[channel_num] = 1;
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return ret_val;
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}
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static int32 hgpwm_v0_deinit(struct pwm_device *pwm, enum pwm_channel channel) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (!(dev->opened[channel_num])) {
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return RET_OK;
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}
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config.func_cmd = HGPWM_V0_FUNC_CMD_DEINIT;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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dev->opened[channel_num] = 0;
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return ret_val;
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}
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static int32 hgpwm_v0_start(struct pwm_device *pwm, enum pwm_channel channel) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (!(dev->opened[channel_num])) {
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return RET_ERR;
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}
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config.func_cmd = HGPWM_V0_FUNC_CMD_START;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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return ret_val;
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}
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static int32 hgpwm_v0_stop(struct pwm_device *pwm, enum pwm_channel channel) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (!(dev->opened[channel_num])) {
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return RET_OK;
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}
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config.func_cmd = HGPWM_V0_FUNC_CMD_STOP;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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return ret_val;
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}
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#ifdef CONFIG_SLEEP
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static int32 hgpwm_v0_suspend(struct pwm_device *pwm, enum pwm_channel channel)
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{
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (!(dev->opened[channel_num])) {
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return RET_OK;
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}
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config.func_cmd = HGPWM_V0_FUNC_CMD_SUSPEND;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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return ret_val;
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}
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static int32 hgpwm_v0_resume(struct pwm_device *pwm, enum pwm_channel channel)
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{
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 channel_num = 0;
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int32 ret_val = RET_OK;
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/* Make sure the channel */
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channel_num = hgpwm_v0_switch_hal_pwm_channel(channel);
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if ((-1) == channel_num) {
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return -EINVAL;
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}
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/* Make busy status */
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if (!(dev->opened[channel_num])) {
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return RET_OK;
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}
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config.func_cmd = HGPWM_V0_FUNC_CMD_RESUME;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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return ret_val;
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}
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#endif
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static int32 hgpwm_v0_ioctl(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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int32 ret_val = RET_OK;
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switch (ioctl_cmd) {
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case (PWM_IOCTL_CMD_SET_PERIOD_DUTY):
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config.func_cmd = HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY;
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config.period = param1;
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config.duty = param2;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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break;
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case (PWM_IOCTL_CMD_SET_SINGLE_INCREAM):
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config.func_cmd = HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM;
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config.period = param1;
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config.duty = param2;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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break;
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case (PWM_IOCTL_CMD_SET_INCREAM_DECREASE):
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config.func_cmd = HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE;
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config.period = param1;
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config.duty = param2;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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break;
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case (PWM_IOCTL_CMD_SET_PRESCALER):
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/*!
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* @brief: set prescaler
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* @param1: prescaler
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* @param2: NULL
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*/
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config.func_cmd = HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER;
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config.param1 = param1;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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break;
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case (PWM_IOCTL_CMD_SET_PERIOD_DUTY_IMMEDIATELY):
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/*!
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* @brief: set period and duty immediately
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* @param1: period
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* @param2: duty
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*/
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config.func_cmd = HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY;
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config.period = param1;
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config.duty = param2;
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ret_val = hgpwm_v0_config(dev, channel, &config);
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break;
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default:
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ret_val = -ENOTSUPP;
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break;
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}
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return ret_val;
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}
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static int32 hgpwm_v0_request_irq(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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switch (irq_flag) {
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case (PWM_IRQ_FLAG_COMPARE):
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config.func_cmd = HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE;
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config.irq_hdl = irq_hdl;
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config.irq_data = data;
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hgpwm_v0_config(dev, channel, &config);
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break;
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case (PWM_IRQ_FLAG_PERIOD):
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config.func_cmd = HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD;
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config.irq_hdl = irq_hdl;
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config.irq_data = data;
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hgpwm_v0_config(dev, channel, &config);
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break;
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}
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return RET_OK;
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}
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static int32 hgpwm_v0_release_irq(struct pwm_device *pwm, enum pwm_channel channel) {
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struct hgpwm_v0 *dev = (struct hgpwm_v0 *)pwm;
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struct hgpwm_v0_config config = {0};
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config.func_cmd = HGPWM_V0_FUNC_CMD_RELEASE_IRQ;
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config.irq_data = 0;
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config.irq_hdl = NULL;
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hgpwm_v0_config(dev, channel, &config);
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return RET_OK;
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}
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static const struct pwm_hal_ops pwm_v0_ops = {
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.init = hgpwm_v0_init,
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.deinit = hgpwm_v0_deinit,
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.start = hgpwm_v0_start,
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.stop = hgpwm_v0_stop,
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.ioctl = hgpwm_v0_ioctl,
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.request_irq = hgpwm_v0_request_irq,
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.release_irq = hgpwm_v0_release_irq,
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#ifdef CONFIG_SLEEP
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.ops.suspend = NULL,//hgpwm_v0_suspend,
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.ops.resume = NULL,//hgpwm_v0_resume,
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#endif
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};
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int32 hgpwm_v0_attach(uint32 dev_id, struct hgpwm_v0 *pwm) {
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uint32 i = 0;
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for (i=0; i<HGPWM_MAX_PWM_CHANNEL; i++) {
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pwm->opened[i] = 0;
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}
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pwm->dev.dev.ops = (const struct devobj_ops *)&pwm_v0_ops;
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dev_register(dev_id, (struct dev_obj *)pwm);
|
||
|
|
return RET_OK;
|
||
|
|
}
|