306 lines
9.9 KiB
C
306 lines
9.9 KiB
C
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#ifndef _HGI2C_V1_HW_H
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#define _HGI2C_V1_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup IIC MODULE REGISTER
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* @{
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*/
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/***** CON0(for IIC) Register *****/
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#define LL_IIC_CON0_SBC_IE(n) (((n)&0x01) << 30)
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#define LL_IIC_CON0_SBC_EN(n) (((n)&0x01) << 29)
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#define LL_IIC_CON0_ALERT_IE(n) (((n)&0x01) << 28)
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#define LL_IIC_CON0_NOSTRETCH_EN(n) (((n)&0x01) << 27)
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#define LL_IIC_CON0_SMBDEV_ADR_EN(n) (((n)&0x01) << 26)
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#define LL_IIC_CON0_SMBALERT_EN(n) (((n)&0x01) << 25)
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#define LL_IIC_CON0_SMBHOST_ADR_EN(n) (((n)&0x01) << 24)
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/*! IIC received NACK signal interrupt enable
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*/
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#define LL_IIC_CON0_STRONG_DRV_EN (1UL << 23)
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/*! IIC received NACK signal interrupt enable
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*/
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#define LL_IIC_CON0_RX_NACK_IE_EN (1UL << 22)
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/*! IIC arbitration loss interrupt enable
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*/
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#define LL_IIC_CON0_AL_IE_EN (1UL << 21)
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/*! IIC received STOP signal interrupt enable
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*/
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#define LL_IIC_CON0_STOP_IE_EN (1UL << 20)
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#define LL_IIC_CON0_ADR_MTH_IE(n) (((n)&0x01) << 19)
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#define LL_IIC_CON0_I2C_FILTER_MAX(n) (((n)&0x1F) << 14)
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#define LL_IIC_CON0_I2C_AL_EN(n) (((n)&0x01) << 13)
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/*! IIC slave broadcast interrupt enable
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*/
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#define LL_IIC_CON0_BROADCAST_IE_EN (1UL << 12)
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#define LL_IIC_CON0_ISP_CMD_LEN(n) (((n)&0x0F) << 8)
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#define LL_IIC_CON0_ISP_MODE_EN (1UL << 7)
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#define LL_IIC_CON0_TIMEOUTB_IE(n) (((n)&0x01) << 3)
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#define LL_IIC_CON0_TIMEOUTA_IE(n) (((n)&0x01) << 2)
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/*! The IIC responds to the NACK signal after receiving the data
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*/
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#define LL_IIC_CON0_TX_NACK (1UL << 1)
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/*! IIC slave address bit width
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*/
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#define LL_IIC_CON0_SLAVE_ADR_WIDTH(n) (((n)&0x01) << 0)
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/***** CON1(for IIC) Register *****/
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#define LL_IIC_CON1_PING_PONG_EN(n) ((n&0x1) << 12)
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#define LL_IIC_CON1_CLRBUFCNT_CLRSSP_EN(n) ((n&0x1) << 11)
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#define LL_IIC_CON1_RX_TIMEOUT_IE(n) ((n&0x1) << 10)
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/*! IIC DMA interrupt enable
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*/
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#define LL_IIC_CON1_DMA_IE_EN (1UL << 9)
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/*! IIC FIFO overflow interrupt enable
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*/
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#define LL_IIC_CON1_BUF_OV_IE_EN (1UL << 8)
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/*! IIC RX FIFO not empty interrupt enable
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*/
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#define LL_IIC_CON1_RX_BUF_NOT_EMPTY_IE_EN (1UL << 7)
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/*! IIC TX FIFO not full interrupt enable
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*/
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#define LL_IIC_CON1_TX_BUF_NOT_FULL_IE_EN (1UL << 6)
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/*! IIC transfers one frame interrupt enable
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*/
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#define LL_IIC_CON1_SSP_IE_EN (1UL << 5)
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/*! IIC DMA enable
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*/
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#define LL_IIC_CON1_DMA_EN (1UL << 4)
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/*! The IIC is set to the TX direction
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*/
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#define LL_IIC_CON1_TX_EN (1UL << 3)
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/*! IIC working mode
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*/
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#define LL_IIC_CON1_MODE(n) (((n)&0x01) << 2)
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/*! IIC module selet
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*/
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#define LL_IIC_CON1_IIC_SEL (1UL << 1)
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/*! SPI/IIC module enable
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*/
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#define LL_IIC_CON1_SSP_EN (1UL << 0)
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/***** SSP CMD DATA(for IIC) Register *****/
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/*! IIC master transfers START signal
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*/
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#define LL_IIC_CMD_DATA_START_BIT_EN (1UL << 8)
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/*! IIC master transfers STOP signal
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*/
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#define LL_IIC_CMD_DATA_STOP_BIT_EN (1UL << 9)
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/*! Write data
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*/
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#define LL_IIC_CMD_DATA_WRITE(n) (((n)&0xFF) << 0)
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/*! Read data
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*/
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#define LL_IIC_CMD_DATA_READ(n) (((n)>>0) & 0xFF)
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/***** BAUD(for IIC) Register *****/
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#define LL_IIC_TIMECON_PRESC(n) (((n)&0x0F) << 28)
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#define LL_IIC_TIMECON_SCLDEL(n) (((n)&0x0F) << 24)
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#define LL_IIC_TIMECON_SDADEL(n) (((n)&0x0F) << 20)
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#define LL_IIC_TIMECON_SCLH(n) (((n)&0x3FF) << 10)
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#define LL_IIC_TIMECON_SCLL(n) (((n)&0x3FF) << 0)
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/***** DMA Tx LEN(for IIC) Register *****/
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/*! Set DMA Tx length(12bit)
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*/
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#define LL_IIC_DMA_TX_LEN(n) (n)
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/***** DMA Tx CNT(for IIC) Register *****/
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/*! The length of the byte of the received data(12bit)
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*/
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#define LL_IIC_DMA_TX_CNT(n) (n)
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/***** DMA Tx STADR(for IIC) Register *****/
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/*! DMA Tx start address(13bit)
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*/
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#define LL_IIC_DMA_TX_STADR(n) (n)
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/***** DMA Rx LEN(for IIC) Register *****/
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/*! Set DMA Rx length(12bit)
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*/
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#define LL_IIC_DMA_RX_LEN(n) (n)
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/***** DMA Rx CNT(for IIC) Register *****/
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/*! The length of the byte of the received data(12bit)
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*/
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#define LL_IIC_DMA_RX_CNT(n) (n)
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/***** DMA Rx STADR(for IIC) Register *****/
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/*! DMA Rx start address(13bit)
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*/
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#define LL_IIC_DMA_RX_STADR(n) (n)
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/***** STA1(for IIC) Register *****/
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#define LL_IIC_STA1_HSYNC_PEND_CLR_BUF_CNT (1UL << 31)
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#define LL_IIC_STA1_HSYNC_PEND (1UL << 21)
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#define LL_IIC_STA1_VSYNC_PEND (1UL << 20)
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#define LL_IIC_STA1_DMA_PPBUF_SEL (1UL << 19)
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#define LL_IIC_STA1_RX_TIMEOUT_PEND (1UL << 18)
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#define LL_IIC_STA1_MODF (1UL << 17)
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#define LL_IIC_STA1_SLAVE_WRONG_CMD_PENDING (1UL << 16)
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#define LL_IIC_STA1_SLAVE_WIREMODE_CFG_PENDING (1UL << 15)
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#define LL_IIC_STA1_SLAVE_RDSTATUS_PENDING (1UL << 14)
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#define LL_IIC_STA1_SLAVE_RDDATA_PENDING (1UL << 13)
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#define LL_IIC_STA1_SLAVE_WRDATA_PENDING (1UL << 12)
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#define LL_IIC_STA1_CLEAR_BUF_CNT (1UL << 9)
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/*! Get how many bytes of valid data in the FIFO
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*/
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#define LL_IIC_STA1_BUF_CNT(n) (((n)& 0x07) )
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#define LL_IIC_STA1_MASTER_RX_BUSY_PENDING (1UL << 8)
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#define LL_IIC_STA1_SLAVE_CS_STATE (1UL << 7)
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#define LL_IIC_STA1_SSP_BUSY_PENDING (1UL << 6)
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#define LL_IIC_STA1_NSS_POS_PENDING (1UL << 5)
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#define LL_IIC_STA1_DMA_PENDING (1UL << 4)
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#define LL_IIC_STA1_BUF_OV_PENDING (1UL << 3)
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#define LL_IIC_STA1_BUF_EMPTY_PENDING (1UL << 2)
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#define LL_IIC_STA1_BUF_FULL_PENDING (1UL << 1)
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#define LL_IIC_STA1_DONE_PENDING (1UL << 0)
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/***** STA2(for IIC) Register *****/
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#define LL_IIC_STA2_STATE(n) ((n&0x07)<<16)
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#define LL_IIC_STA2_TIMEOUTB_PEND(n) ((n&0x01)<<13)
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#define LL_IIC_STA2_TIMEOUTA_PEND(n) ((n&0x01)<<12)
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#define LL_IIC_STA2_SBC_PEND(n) ((n&0x01)<<11)
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#define LL_IIC_STA2_ALERT_PEND(n) ((n&0x01)<<10)
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#define LL_IIC_STA2_I2C_AL(n) ((n&0x01)<<9)
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#define LL_IIC_STA2_RX_NACK(n) ((n&0x01)<<8)
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#define LL_IIC_STA2_STOP_PEND(n) ((n&0x01)<<7)
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#define LL_IIC_STA2_I2C_BUS_BUSY(n) ((n&0x01)<<6)
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#define LL_IIC_STA2_SLV_RW(n) ((n&0x01)<<5)
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#define LL_IIC_STA2_ADRMTHCODE(n) ((n&0x07)<<2)
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#define LL_IIC_STA2_SLV_ADDRED(n) ((n&0x01)<<1)
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#define LL_IIC_STA2_ADR_MTH_PEND(n) ((n&0x01)<<0)
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/***** OWNADRCON(for IIC) Register *****/
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#define LL_IIC_OWNADRCON_OWN_ADR2_MASK(n) ((n&0x07)<<24)
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#define LL_IIC_OWNADRCON_OWN_ADR2(n) ((n&0x7F)<<17)
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#define LL_IIC_OWNADRCON_OWN_ADR2_EN(n) ((n&0x01)<<16)
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#define LL_IIC_OWNADRCON_OWN_ADR1_S(n) ((n&0x01)<<11)
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#define LL_IIC_OWNADRCON_OWN_ADR1_EN(n) ((n&0x01)<<10)
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#define LL_IIC_OWNADRCON_OWN_ADR1(n) ((n&0x3FF)<<0)
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/***** RBUF(for IIC) Register *****/
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#define LL_IIC_RBUF(n) ((n))
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/***** TIMEOUTCON(for IIC) Register *****/
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#define LL_IIC_TIMEOUTCON_TIMEOUTB_EN(n) ((n&01)<<31)
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#define LL_IIC_TIMEOUTCON_TIMEOUTB(n) ((n&0xFFF)<<16)
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#define LL_IIC_TIMEOUTCON_TIMEOUTA_EN(n) ((n&01)<<15)
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#define LL_IIC_TIMEOUTCON_TIMEOUTA_S(n) ((n&01)<<12)
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#define LL_IIC_TIMEOUTCON_TIMEOUTA(n) ((n&0xFFF)<<0)
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/***** RX TIMEOUTCON(for IIC) Register *****/
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#define LL_IIC_RXTIMEOUTCON_RX_TIMEOUT(n) ((n&0x1ffffff7)<<1)
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#define LL_IIC_RXTIMEOUTCON_RX_TIMEOUT_EN(n) ((n&0x1)<<0)
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typedef enum {
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/*! IIC does not transmit signals other than ACK.
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*/
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LL_IIC_NONE_FLAG = 0,
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/*! IIC sends START signal
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*/
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LL_IIC_START_FLAG = 1,
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/*! IIC sends STOP signal
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*/
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LL_IIC_STOP_FLAG = 2,
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/*! IIC sends NACK signal
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*/
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LL_IIC_NACK_FLAG = 4,
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} TYPE_ENUM_LL_IIC_FLAG;
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/**
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* @brief IIC
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*/
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struct hgi2c_v1_hw {
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__IO uint32_t CON0;
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__IO uint32_t CON1;
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__IO uint32_t CMD_DATA;
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__IO uint32_t TIMECON;
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__IO uint32_t TDMALEN;
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__IO uint32_t RDMALEN;
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__IO uint32_t TDMACNT;
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__IO uint32_t RDMACNT;
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__IO uint32_t TSTADR;
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__IO uint32_t RSTADR;
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__IO uint32_t STA1;
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__IO uint32_t STA2;
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__IO uint32_t SLAVESTA;
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__IO uint32_t OWNADRCON;
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__IO uint32_t RBUF;
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__IO uint32_t TIMEOUTCON;
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__IO uint32_t RXTIMEOUTCON;
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__IO uint32_t RSTADR1;
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__IO uint32_t VSYNC_TCON;
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__IO uint32_t HSYNC_TCON;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HGI2C_V1_HW_H */
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