435 lines
13 KiB
C
435 lines
13 KiB
C
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "osal/irq.h"
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#include "osal/semaphore.h"
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#include "osal/mutex.h"
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#include "osal/string.h"
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#include "hal/dma.h"
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#include "dev/dma/hg_m2m_dma.h"
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#include "osal/sleep.h"
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#define DMA_LEN_THRESHOLD (2048)
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uint32_t in_disable_irq(void);
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static void hg_m2m0_dma_irq_handler(void *data)
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{
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struct mem_dma_dev *dma = (struct mem_dma_dev *)data;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dma->hw;
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hw->dma_ch[0].DMA_SAIE = 1;
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os_sema_up(&dma->done[0]);
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}
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static void hg_m2m1_dma_irq_handler(void *data)
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{
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struct mem_dma_dev *dma = (struct mem_dma_dev *)data;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dma->hw;
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hw->dma_ch[1].DMA_SAIE = 1;
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os_sema_up(&dma->done[1]);
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}
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#ifdef TXW82X
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static void hg_m2m2_dma_irq_handler(void *data)
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{
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struct mem_dma_dev *dma = (struct mem_dma_dev *)data;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dma->hw;
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hw->dma_ch[2].DMA_SAIE = 1;
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os_sema_up(&dma->done[2]);
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}
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#endif
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static inline int32 hg_m2m_dma_get_free_ch(struct mem_dma_dev *dev, uint8 ch_fix)
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{
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int32 ch = (ch_fix >= HG_M2M_DMA_NUM) ? (HG_M2M_DMA_NUM-1) : ch_fix;
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uint32 flags = disable_irq();
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for (; ch>=0; ) {
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if (!(dev->busy_flag & BIT(ch))){
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dev->busy_flag |= BIT(ch);
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break;
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}
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if (ch_fix < HG_M2M_DMA_NUM) {
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ch = -1;
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break;
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} else {
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ch--;
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}
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}
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enable_irq(flags);
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return ch;
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}
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static inline void hg_m2m_dma_free_ch(struct mem_dma_dev *dev, int32 ch)
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{
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uint32 flags = disable_irq();
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dev->busy_flag &= ~ BIT(ch);
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enable_irq(flags);
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}
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#define is_memset_same_val(n) ((((n) >> 0) & 0xff) == (((n) >> 8) & 0xff))
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static void hg_soft_memset(uint32 *dest, uint32 val, uint32 size)
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{
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uint32 i = 0;
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uint8 head_size = (uint32)dest % 4;
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uint8 tail_size = ((uint32)dest+size) % 4;
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uint32 c_size = ALIGN(size, 4) + ALIGN(head_size, 4);
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uint32 *p_dst = (uint32 *)((uint32)dest - head_size);
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uint8 *p_dst_bt = (uint8 *)dest;
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if (is_memset_same_val(val))
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{
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os_memset((void*)dest, (val & 0xff), size);
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} else {
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for (; i < c_size>>2; i++)
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*p_dst++ = val;
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for (i = head_size; i < (head_size << 1); i++)
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*p_dst_bt++ = val>>((i % 4)<<3);
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p_dst_bt = (uint8 *)((uint32)dest + size - tail_size);
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for (i = tail_size; i < (tail_size << 1); i++)
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*p_dst_bt++ = val>>((i % 4)<<3);
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}
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}
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const uint8 dma_element_size[4] = {1,2,4,8};
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static int32 hg_m2m_dma_xfer(struct dma_device *dma, struct dma_xfer_data *data)
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{
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int32 ch = -1;
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uint32 val = (data->src_addr_mode == DMA_XFER_MODE_RECYCLE) ? (*((uint32 *)data->src)) : (0);
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uint32 count = data->element_num * dma_element_size[data->element_per_width];
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static uint8 ch0_lock = 0;
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uint32 retry;
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uint32 addr_offset = 0;
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uint32 dma_cnt = 0;
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int32 ret = 0;
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struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dev->hw;
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retry = (__in_interrupt() || in_disable_irq()) ? 1 : (count >> (8+(2*dev->dma1_status)));
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if (!retry) retry = 1;
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if (data->element_per_width >= DMA_SLAVE_BUSWIDTH_UNDEFINED) {
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return -EBUSY;
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}
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/* get free channel */
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for ( ; (!dev->suspend) && (retry--); ) {
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if (data->dir != DMA_XFER_DIR_M2M) {
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uint32 flags = disable_irq();
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ch = hg_m2m_dma_get_free_ch(dev, 0);
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if (0 == ch)
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ch0_lock = 1;
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enable_irq(flags);
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} else {
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ch = hg_m2m_dma_get_free_ch(dev, ch0_lock ? (HG_M2M_DMA_NUM - 1) : HG_M2M_DMA_NUM);
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}
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if (ch >= 0) {
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break;
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}
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}
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if (ch < 0) {
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if (data->src_addr_mode == DMA_XFER_MODE_RECYCLE) {
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hg_soft_memset((void*)data->dest, val, count);
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} else if(data->src_addr_mode == DMA_XFER_MODE_INCREASE){
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os_memcpy((void*)data->dest, (void*)data->src, count);
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}
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return ch;
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}
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#ifdef TXW81X
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uint32 dst_addr = data->dest>>24;
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if (dst_addr == 0x38 || dst_addr == 0x08) {
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while(ll_sysctrl_dma2ahb_is_busy((ch) ? (DMA2AHB_BURST_CH_M2M1_WR) : (DMA2AHB_BURST_CH_M2M0_WR)));
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}
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#endif
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//sysctrl_m2m_dma_reset();
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#if defined(TXW81X)
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hw->dma_ch[ch].DMA_CON &= HG_M2M_DMA_CON_ENDIAN_RES;
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hw->dma_ch[ch].DMA_ISIZE = 0;
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#elif defined(TXW82X)
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hw->dma_ch[ch].DMA_CON = 0x00;
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hw->dma_ch[ch].DMA_CON |= HG_M2M_DMA_CON_ENDIAN_SET(data->endian);
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#else
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hw->dma_ch[ch].DMA_CON = 0x00;
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#endif
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hw->dma_ch[ch].DMA_DATA = val;
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while(count)
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{
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hw->dma_ch[ch].DMA_TADR = (uint32)data->dest + addr_offset;
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hw->dma_ch[ch].DMA_SADR = (uint32)data->src + addr_offset;
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dma_cnt = (count > (HG_M2M_DMA_MAX_LEN)) ? (HG_M2M_DMA_MAX_LEN) : (count);
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if ((!__in_interrupt()) && (!in_disable_irq()) && (dma_cnt > DMA_LEN_THRESHOLD)) {
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hw->dma_ch[ch].DMA_SAIE = 0x10001;
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os_sema_eat(&dev->done[ch]);
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} else {
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hw->dma_ch[ch].DMA_SAIE = 1;
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}
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hw->dma_ch[ch].DMA_DLEN = dma_cnt - 1;
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count -= dma_cnt;
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addr_offset += dma_cnt;
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if (data->src_addr_mode == DMA_XFER_MODE_RECYCLE) {
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hw->dma_ch[ch].DMA_CON |= (HG_M2M_DMA_CON_MEMSET | HG_M2M_DMA_CON_DTE);
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} else if(data->src_addr_mode == DMA_XFER_MODE_INCREASE){
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hw->dma_ch[ch].DMA_CON |= (HG_M2M_DMA_CON_MEMCPY | HG_M2M_DMA_CON_DTE);
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}
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if (hw->dma_ch[ch].DMA_SAIE & 0x10000) {
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ret = os_sema_down(&dev->done[ch], 50);
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if (!ret) {
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os_printf(KERN_ERR"hw_dma err: {%08x <--- %08x} len=%d\r\n", hw->dma_ch[ch].DMA_TADR, hw->dma_ch[ch].DMA_SADR, dma_cnt);
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}
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} else {
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while (hw->dma_ch[ch].DMA_CON & HG_M2M_DMA_CON_DTE) {
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}
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}
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}
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hw->dma_ch[ch].DMA_CON = 0x00;
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hg_m2m_dma_free_ch(dev, ch);
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if(ch && dev->dma1_mutex && !dev->dma1_status)
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{
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dev->dma1_status = true;
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hg_m2m_dma_get_free_ch(dev, ch);
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}
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return ch;
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}
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static int32 hg_m2m_dma_only_hw_xfer(struct dma_device *dma, struct dma_xfer_data *data)
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{
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int32 ch = -1;
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uint32 val = (data->src_addr_mode == DMA_XFER_MODE_RECYCLE) ? (*((uint32 *)data->src)) : (0);
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uint32 count = data->element_num * dma_element_size[data->element_per_width];
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static uint8 ch0_lock = 0;
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uint32 retry;
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uint32 addr_offset = 0;
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uint32 dma_cnt = 0;
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int32 ret = 0;
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struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dev->hw;
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retry = (__in_interrupt() || in_disable_irq()) ? 1 : (count >> (8+(2*dev->dma1_status)));
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if (!retry) retry = 1;
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if (data->element_per_width >= DMA_SLAVE_BUSWIDTH_UNDEFINED) {
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return -EBUSY;
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}
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/* get free channel */
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for ( ; (!dev->suspend) && (retry); ) {
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if (data->dir != DMA_XFER_DIR_M2M) {
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uint32 flags = disable_irq();
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ch = hg_m2m_dma_get_free_ch(dev, 0);
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if (0 == ch)
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ch0_lock = 1;
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enable_irq(flags);
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} else {
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ch = hg_m2m_dma_get_free_ch(dev, ch0_lock ? (HG_M2M_DMA_NUM - 1) : HG_M2M_DMA_NUM);
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}
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if (ch >= 0) {
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break;
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}
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os_sleep_ms(1);
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}
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#ifdef TXW81X
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uint32 dst_addr = data->dest>>24;
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if (dst_addr == 0x38 || dst_addr == 0x08) {
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while(ll_sysctrl_dma2ahb_is_busy((ch) ? (DMA2AHB_BURST_CH_M2M1_WR) : (DMA2AHB_BURST_CH_M2M0_WR)));
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}
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#endif
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//sysctrl_m2m_dma_reset();
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#if defined(TXW81X)
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hw->dma_ch[ch].DMA_CON &= HG_M2M_DMA_CON_ENDIAN_RES;
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hw->dma_ch[ch].DMA_ISIZE = 0;
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#elif defined(TXW82X)
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hw->dma_ch[ch].DMA_CON = 0x00;
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hw->dma_ch[ch].DMA_CON |= HG_M2M_DMA_CON_ENDIAN_SET(data->endian);
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#else
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hw->dma_ch[ch].DMA_CON = 0x00;
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#endif
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hw->dma_ch[ch].DMA_DATA = val;
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while(count)
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{
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hw->dma_ch[ch].DMA_TADR = (uint32)data->dest + addr_offset;
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hw->dma_ch[ch].DMA_SADR = (uint32)data->src + addr_offset;
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dma_cnt = (count > (HG_M2M_DMA_MAX_LEN)) ? (HG_M2M_DMA_MAX_LEN) : (count);
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if ((!__in_interrupt()) && (!in_disable_irq()) && (dma_cnt > DMA_LEN_THRESHOLD)) {
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hw->dma_ch[ch].DMA_SAIE = 0x10001;
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os_sema_eat(&dev->done[ch]);
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} else {
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hw->dma_ch[ch].DMA_SAIE = 1;
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}
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hw->dma_ch[ch].DMA_DLEN = dma_cnt - 1;
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count -= dma_cnt;
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addr_offset += dma_cnt;
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if (data->src_addr_mode == DMA_XFER_MODE_RECYCLE) {
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hw->dma_ch[ch].DMA_CON |= (HG_M2M_DMA_CON_MEMSET | HG_M2M_DMA_CON_DTE);
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} else if(data->src_addr_mode == DMA_XFER_MODE_INCREASE){
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hw->dma_ch[ch].DMA_CON |= (HG_M2M_DMA_CON_MEMCPY | HG_M2M_DMA_CON_DTE);
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}
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if (hw->dma_ch[ch].DMA_SAIE & 0x10000) {
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ret = os_sema_down(&dev->done[ch], 50);
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if (!ret) {
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os_printf(KERN_ERR"hw_dma err: {%08x <--- %08x} len=%d\r\n", hw->dma_ch[ch].DMA_TADR, hw->dma_ch[ch].DMA_SADR, dma_cnt);
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}
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} else {
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while (hw->dma_ch[ch].DMA_CON & HG_M2M_DMA_CON_DTE) {
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}
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}
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}
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hw->dma_ch[ch].DMA_CON = 0x00;
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hg_m2m_dma_free_ch(dev, ch);
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if(ch && dev->dma1_mutex && !dev->dma1_status)
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{
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dev->dma1_status = true;
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hg_m2m_dma_get_free_ch(dev, ch);
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}
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return ch;
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}
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static int32 hg_m2m_dma_get_status(struct dma_device *dma, uint32 chn)
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{
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struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dev->hw;
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if (hw->dma_ch[chn].DMA_CON & HG_M2M_DMA_CON_DTE) {
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return DMA_IN_PROGRESS;
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} else {
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return DMA_SUCCESS;
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}
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}
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static int32 hg_m2m_dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2)
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{
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int32 ret_val = RET_OK;
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switch (cmd)
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{
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#if (defined(TX81X) || defined(TXW82X))
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case DMA_IOCTL_CMD_ENDIAN:{
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struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
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struct mem_dma_hw *hw = (struct mem_dma_hw *)dev->hw;
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|
|
for (int i = 0; i < HG_M2M_DMA_NUM; i++)
|
||
|
|
hw->dma_ch[i].DMA_CON = ((hw->dma_ch[i].DMA_CON & (~HG_M2M_DMA_CON_ENDIAN_RES)) | HG_M2M_DMA_CON_ENDIAN_SET(param1));
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
case DMA_IOCTL_CMD_CHECK_DMA1_STATUS:{
|
||
|
|
struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
|
||
|
|
ret_val = dev->dma1_status;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
case DMA_IOCTL_CMD_DMA1_LOCK:{
|
||
|
|
struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
|
||
|
|
int32 ch = hg_m2m_dma_get_free_ch(dev, 1);
|
||
|
|
if(ch)
|
||
|
|
{
|
||
|
|
dev->dma1_status = true;
|
||
|
|
}else{
|
||
|
|
hg_m2m_dma_free_ch(dev, ch);
|
||
|
|
dev->dma1_status = false;
|
||
|
|
}
|
||
|
|
dev->dma1_mutex = true;
|
||
|
|
break;
|
||
|
|
};
|
||
|
|
|
||
|
|
case DMA_IOCTL_CMD_DMA1_UNLOCK:{
|
||
|
|
struct mem_dma_dev *dev = (struct mem_dma_dev *)dma;
|
||
|
|
hg_m2m_dma_free_ch(dev, 1);
|
||
|
|
dev->dma1_mutex = false;
|
||
|
|
dev->dma1_status = false;
|
||
|
|
break;
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
default:
|
||
|
|
ret_val = -ENOTSUPP;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return ret_val;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_SLEEP
|
||
|
|
int32 hg_m2m_dma_suspend(struct dev_obj *dev)
|
||
|
|
{
|
||
|
|
struct mem_dma_dev *dma = (struct mem_dma_dev *)dev;
|
||
|
|
|
||
|
|
if (dma->suspend) {
|
||
|
|
return -ENOTSUP;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* force all dma busy */
|
||
|
|
dma->suspend = 1;
|
||
|
|
|
||
|
|
for (int i = 0; i < HG_M2M_DMA_NUM; i++)
|
||
|
|
while (0 != hg_m2m_dma_get_free_ch(dma, i)) { os_sleep_ms(1); }
|
||
|
|
|
||
|
|
return RET_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32 hg_m2m_dma_resume(struct dev_obj *dev)
|
||
|
|
{
|
||
|
|
struct mem_dma_dev *dma = (struct mem_dma_dev *)dev;
|
||
|
|
|
||
|
|
if (!dma->suspend) {
|
||
|
|
return -ENOTSUP;
|
||
|
|
}
|
||
|
|
hg_m2m_dma_free_ch(dma, 0);
|
||
|
|
hg_m2m_dma_free_ch(dma, 1);
|
||
|
|
irq_enable(dma->irq_num);
|
||
|
|
irq_enable(dma->irq_num+1);
|
||
|
|
dma->suspend = 0;
|
||
|
|
|
||
|
|
return RET_OK;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
static const struct dma_hal_ops m2m_ops = {
|
||
|
|
.xfer = hg_m2m_dma_xfer,
|
||
|
|
.only_hw_xfer = hg_m2m_dma_only_hw_xfer,
|
||
|
|
.get_status = hg_m2m_dma_get_status,
|
||
|
|
.ioctl = hg_m2m_dma_ioctl,
|
||
|
|
#ifdef CONFIG_SLEEP
|
||
|
|
.ops.suspend = hg_m2m_dma_suspend,
|
||
|
|
.ops.resume = hg_m2m_dma_resume,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
__init int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma)
|
||
|
|
{
|
||
|
|
#ifdef TXW82X
|
||
|
|
void *irq_handler[] = {hg_m2m0_dma_irq_handler, hg_m2m1_dma_irq_handler, hg_m2m2_dma_irq_handler};
|
||
|
|
#else
|
||
|
|
void *irq_handler[] = {hg_m2m0_dma_irq_handler, hg_m2m1_dma_irq_handler};
|
||
|
|
#endif
|
||
|
|
p_dma->dev.dev.ops = (const struct devobj_ops *)&m2m_ops;
|
||
|
|
p_dma->busy_flag = 0;
|
||
|
|
p_dma->suspend = 0;
|
||
|
|
|
||
|
|
for (uint8 i = 0; i < HG_M2M_DMA_NUM; i++)
|
||
|
|
{
|
||
|
|
os_sema_init(&p_dma->done[i], 0);
|
||
|
|
p_dma->hw->dma_ch[i].DMA_CON = 0x00;
|
||
|
|
p_dma->hw->dma_ch[i].DMA_SAIE = HG_M2M_DMA_SAIE_TCP_PENDING;
|
||
|
|
irq_enable(p_dma->irq_num[i]);
|
||
|
|
request_irq(p_dma->irq_num[i], irq_handler[i], p_dma);
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_register(dev_id, (struct dev_obj *)p_dma);
|
||
|
|
return RET_OK;
|
||
|
|
}
|
||
|
|
|