76 lines
1.8 KiB
C
76 lines
1.8 KiB
C
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#ifndef _HG_CRC_HW_H_
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#define _HG_CRC_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum hg_crc_flags {
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HGCRC_FLAGS_SUSPEND = BIT(0),
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HGCRC_FLAGS_HOLD = BIT(1),
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};
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/***** CRC_CFG Register *****/
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/*! CRC interrupt enable
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*/
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#define LL_CRC_CFG_INT_EN (1UL << 0)
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/*! CRC shift bit direction
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*/
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#define LL_CRC_CFG_BIT_ORDER_LEFT (1UL << 1)
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#define LL_CRC_CFG_BIT_ORDER_RIGHT (0UL << 1)
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/*! CRC POLY width: 5/7/8/16/32
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*/
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#define LL_CRC_CFG_POLY_BITS(n) (((n)&0x3F) << 8)
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/*! CRC DMA data wait clock every time
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*/
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#define LL_CRC_CFG_DMAWAIT_CLOCK(n) (((n)&0x7) << 16)
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/*! CRC TCP mode enable
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*/
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#define LL_CRC_CFG_TCP_MODE_EN (1UL << 24)
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/***** CRC_KST Register *****/
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/*! CRC pending clear
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*/
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#define LL_CRC_KST_DMA_PENDING_CLR (1UL << 0)
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/***** CRC_STA Register *****/
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/*! CRC pending
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*/
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#define LL_CRC_STA_DMA_PENDING (1UL << 0)
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/***** CRC_INIT Register *****/
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/***** CRC_INV Register *****/
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/***** CRC_POLY Register *****/
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/***** CRC_DMA_ADDR Register *****/
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/***** CRC_DMA_LEN Register *****/
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/***** CRC_CRC_OUT Register *****/
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/**
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* @brief CRC
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*/
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struct hg_crc_hw {
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__IO uint32 CRC_CFG; // 0x0c
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__IO uint32 CRC_INIT; // 0x04
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__IO uint32 CRC_INV; // 0x08
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__IO uint32 CRC_POLY; // 0x0c
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__IO uint32 CRC_KST; // 0x10
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__IO uint32 CRC_STA; // 0x14
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uint32 RESERVED0;
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__IO uint32 DMA_ADDR; // 0x1c
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__IO uint32 DMA_LEN; // 0x20
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__IO uint32 CRC_OUT; // 0x24
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} ;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HG_CRC_H_ */
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