140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
|
|
#ifndef _E32_DEMO_H_
|
|||
|
|
#define _E32_DEMO_H_
|
|||
|
|
|
|||
|
|
#include "e32_hal.h"
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
OFF = 0x00,
|
|||
|
|
ON = 0x01,
|
|||
|
|
}on_off_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
RADIO_RATE_2400 = 0x02,
|
|||
|
|
RADIO_RATE_4800 = 0x03,
|
|||
|
|
RADIO_RATE_9600 = 0x04,
|
|||
|
|
RADIO_RATE_19200 = 0x05,
|
|||
|
|
RADIO_RATE_38400 = 0x06,
|
|||
|
|
RADIO_RATE_62500 = 0x07,
|
|||
|
|
}radio_rate_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
UART_8N1 = 0x00,
|
|||
|
|
UART_8O1 = 0x01,
|
|||
|
|
UART_8E1 = 0x02,
|
|||
|
|
}uart_parity_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
UART_RATE_1200 = 0x00,
|
|||
|
|
UART_RATE_2400 = 0x01,
|
|||
|
|
UART_RATE_4800 = 0x02,
|
|||
|
|
UART_RATE_9600 = 0x03,
|
|||
|
|
UART_RATE_19200 = 0x04 ,
|
|||
|
|
UART_RATE_38400 = 0x05,
|
|||
|
|
UART_RATE_57600 = 0x06,
|
|||
|
|
UART_RATE_115200= 0x07,
|
|||
|
|
}uart_rate_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
WOR_PERIOD_250MS = 0x00,
|
|||
|
|
WOR_PERIOD_500MS = 0x01,
|
|||
|
|
WOR_PERIOD_750MS = 0x02,
|
|||
|
|
WOR_PERIOD_1000MS = 0x03,
|
|||
|
|
WOR_PERIOD_1250MS = 0x04,
|
|||
|
|
WOR_PERIOD_1500MS = 0x05,
|
|||
|
|
WOR_PERIOD_1750MS = 0x06,
|
|||
|
|
WOR_PERIOD_2000MS = 0x07,
|
|||
|
|
}wor_period_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
TX_POWER_DBM_30 = 0x00,
|
|||
|
|
TX_POWER_DBM_27 = 0x01,
|
|||
|
|
TX_POWER_DBM_24 = 0x02,
|
|||
|
|
TX_POWER_DBM_21 = 0x03,
|
|||
|
|
}transmit_power_t;
|
|||
|
|
|
|||
|
|
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
/* 00H<30>ǹ̶<C7B9><CCB6><EFBFBD>HEAD<41><44><EFBFBD><EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
|
|||
|
|
/* ======== <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> 01H ======== */
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
uint8_t address_h; /* ģ<><C4A3><EFBFBD><EFBFBD>ַ (<28>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 01H<31><48>02H) <20><>ͬ<EFBFBD><CDAC>ַ<EFBFBD><D6B7>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD>ֱ<EFBFBD>ӻ<EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>(<28>㲥<EFBFBD><E3B2A5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>); 65535Ϊ<35>㲥<EFBFBD><E3B2A5>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA><EFBFBD><EFBFBD>Ϣ */
|
|||
|
|
}register_1;
|
|||
|
|
|
|||
|
|
/* ======== <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> 02H ======== */
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
uint8_t address_l;
|
|||
|
|
}register_2;
|
|||
|
|
|
|||
|
|
/* ======== <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> 03H ======== */
|
|||
|
|
union {
|
|||
|
|
uint8_t value;
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
radio_rate_t radio_rate : 3; /* <20><><EFBFBD>߿<EFBFBD><DFBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 03H Bit2-0) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Խ<EFBFBD>ߣ<EFBFBD><DFA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Խ<EFBFBD>죬<EFBFBD><ECA3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB>½<EFBFBD><C2BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊͨ<CEAA>ž<EFBFBD><C5BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
|||
|
|
uart_rate_t uart_baud_rate : 3; /* <20><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 03H Bit7-5) <20><><EFBFBD><EFBFBD>ģʽ(ģʽ2)ǿ<>ƹ̶<C6B9><CCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ9600<30><30><EFBFBD><EFBFBD><EFBFBD>ഫ<EFBFBD><E0B4AB>ģʽʱΪ<CAB1>û<EFBFBD><C3BB><EFBFBD><EFBFBD>ô<EFBFBD><C3B4>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
uart_parity_t uart_parity : 2; /* <20><><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 03H Bit4-3) */
|
|||
|
|
}field;
|
|||
|
|
}register_3;
|
|||
|
|
|
|||
|
|
/* ======== <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> 04H ======== */
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
uint8_t channel; /* <20>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 04H) <20><><EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>йأ<D0B9><D8A3>ز<EFBFBD>Ƶ<EFBFBD><C6B5> = <20>ŵ<EFBFBD>0<EFBFBD><30>ʼƵ<CABC><C6B5> + (1MHz x <20>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>) */
|
|||
|
|
}register_4;
|
|||
|
|
|
|||
|
|
/* ======== <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> 05H ======== */
|
|||
|
|
union {
|
|||
|
|
uint8_t value;
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
transmit_power_t tx_power : 2; /* <20><><EFBFBD>书<EFBFBD><E4B9A6> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 05H Bit1-0) <20><>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>Ĺ<EFBFBD><C4B9>ʷֵ<CAB7><D6B5><EFBFBD>һ<EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>Ҫ<EFBFBD>ο<EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ֲ<EFBFBD> */
|
|||
|
|
on_off_t packet_fec : 1; /* ǰ<><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FEC (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 05H Bit2 ) ˫<><CBAB>˫<EFBFBD>˱<EFBFBD><CBB1><EFBFBD>һ<EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>š<EFBFBD><C5A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><F3A3ACBE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ҳ<EFBFBD><D2B2><EFBFBD>ӳ<EFBFBD> */
|
|||
|
|
wor_period_t wake_on_radio_period : 3; /* <20><><EFBFBD>л<EFBFBD><D0BB><EFBFBD>WOR<4F><52><EFBFBD><EFBFBD> (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 05H Bit2-0) <20>շ<EFBFBD>˫<EFBFBD><CBAB><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׳<EFBFBD><D7B3><EFBFBD><EFBFBD><EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
on_off_t reserve : 1; /* <20><><EFBFBD><EFBFBD> IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ*/
|
|||
|
|
on_off_t specify_target : 1; /* ָ<><D6B8>Ŀ<EFBFBD>괫<EFBFBD>䣬Ҳ<E4A3AC>ж<EFBFBD><D0B6><EFBFBD>ģʽ (<28>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ: 05H Bit7 ) <20><><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD><C4B1><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>ŵ<EFBFBD> */
|
|||
|
|
}field;
|
|||
|
|
}register_5;
|
|||
|
|
|
|||
|
|
}e32_register_t;
|
|||
|
|
|
|||
|
|
typedef enum
|
|||
|
|
{
|
|||
|
|
REQUEST_CMD_CONFIG = 0x00,
|
|||
|
|
REQUEST_CMD_NAME ,
|
|||
|
|
REQUEST_CMD_VERSION ,
|
|||
|
|
}request_cmd_t;
|
|||
|
|
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
uint8_t address_h;
|
|||
|
|
uint8_t address_l;
|
|||
|
|
uint8_t channel;
|
|||
|
|
uint8_t data[237];//<2F><><EFBFBD>㴫<EFBFBD><E3B4AB>(ָ<><D6B8>Ŀ<EFBFBD><C4BF>)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2>ó<EFBFBD><C3B3><EFBFBD>237<33>ֽڣ<D6BD><DAA3><EFBFBD><EFBFBD><EFBFBD><F2B3ACB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݻᶪʧ
|
|||
|
|
}e32_specify_target_buffer_t;
|
|||
|
|
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
uint8_t command;
|
|||
|
|
uint8_t config[20];
|
|||
|
|
}e32_hex_cmd_buffer_t;
|
|||
|
|
|
|||
|
|
typedef union
|
|||
|
|
{
|
|||
|
|
uint8_t opt_buffer[1024];
|
|||
|
|
e32_hex_cmd_buffer_t hex_cmd;
|
|||
|
|
e32_specify_target_buffer_t target;
|
|||
|
|
}e32_opt_buffer_t;
|
|||
|
|
|
|||
|
|
#endif
|
|||
|
|
|