214 lines
6.7 KiB
C
214 lines
6.7 KiB
C
/*****************************************************************
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>file name : vco_clock_trim.c
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>author : IC lishanliao
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>create time : Mon 22 Nov 2021 02:44:34 PM CST
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>Decription : 通过vco时钟的trim，使vco clock接近29MHz，
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这样adc采样对应电压更准确
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*****************************************************************/
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#include "vad_mic.h"
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#include "voice_mic_data.h"
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static u8 vco_clock_calibrated = 0;
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#define VAD_EN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON0, 29, 1, x)
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#define VAD_ACM_10V_4_(x) SFR(P11_LPVAD->VAD_ACON0, 0, 4, x)
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#define VAD_LDO_IS_10V_2_(x) SFR(P11_LPVAD->VAD_ACON1, 0, 2, x)
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#define VAD_LDO_VS_10V_3_(x) SFR(P11_LPVAD->VAD_ACON1, 2, 3, x)
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#define VAD_BUF_EN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON0, 17, 1, x)
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#define VAD_BUF_IS_10V_2_(x) SFR(P11_LPVAD->VAD_ACON0, 18, 2, x)
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#define VAD_PGA_EN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON1, 22, 1, x)
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#define VAD_PGA_IS_10V_2_(x) SFR(P11_LPVAD->VAD_ACON1, 27, 2, x)
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#define VAD_PGA_GS_10V_4_(x) SFR(P11_LPVAD->VAD_ACON1, 23, 4, x)
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#define VAD_BUF2INN_EN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON0, 16, 1, x)
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#define VAD_ADC_EN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON0, 4, 1, x)
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#define VAD_ADC_RIN_10V_3_(x) SFR(P11_LPVAD->VAD_ACON0, 9, 3, x)
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#define VAD_ADC_RBS_10V_3_(x) SFR(P11_LPVAD->VAD_ACON0, 6, 3, x)
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#define VAD_ADC_TEN_10V_1_(x) SFR(P11_LPVAD->VAD_ACON0, 12, 1, x)
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#define VAD_VCON_TOE_10V_1_(x) SFR(P11_LPVAD->VAD_CON , 27, 1, x)
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#define VAD_VCOP_TOE_10V_1_(x) SFR(P11_LPVAD->VAD_CON , 28, 1, x)
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#define VAD_IREF1U_TOE_10V_1_(x) SFR(P11_LPVAD->VAD_ACON1, 30, 1, x)
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void vco_clock_test_mode_setup(void)
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{
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P11_LPVAD->VAD_ACON0 = 0;
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P11_LPVAD->VAD_ACON1 = 0;
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P11_LPVAD->VAD_CON = 0;
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SFR(JL_ADDA->ADDA_CON1, 1, 1, 1);//enable vad analog to ANA pad
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VAD_EN_10V_1_(1) ;
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VAD_ACM_10V_4_(7) ;
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VAD_LDO_VS_10V_3_(3) ;
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VAD_LDO_IS_10V_2_(2) ;
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VAD_BUF_EN_10V_1_(1) ;
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VAD_BUF_IS_10V_2_(2) ;
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VAD_PGA_EN_10V_1_(1) ;
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VAD_PGA_IS_10V_2_(2) ;
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VAD_PGA_GS_10V_4_(4) ;
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VAD_BUF2INN_EN_10V_1_(1);
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VAD_ADC_EN_10V_1_(1) ;
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VAD_ADC_RIN_10V_3_(5) ;
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VAD_ADC_RBS_10V_3_(5) ;
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VAD_VCON_TOE_10V_1_(1) ;
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VAD_VCOP_TOE_10V_1_(1) ;
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VAD_IREF1U_TOE_10V_1_(1);
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}
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/*
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void vco_clk2io_test(void)
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{
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//vad_vcon0->PA6
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//vad_vcop0->PA7
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SFR(JL_CLOCK->CLK_CON0, 24, 4, 15); //clk_out2_sel sel vad_vcon0
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SFR(JL_CLOCK->CLK_CON0, 28, 4, 15); //clk_out2_sel sel vad_vcop0
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SFR(JL_IOMC->OCH_CON0, 0, 5, 16); //
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SFR(JL_IOMC->OCH_CON0, 5, 9, 17);
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JL_OMAP->PA6_OUT = (0 << 0) | //input enable
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(1 << 1) | //output enable
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(0 << 2); //output signal select
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JL_OMAP->PA7_OUT = (0 << 0) | //input enable
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(1 << 1) | //output enable
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(1 << 2); //output signal select
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JL_PORTA->DIR &= ~BIT(6);
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JL_PORTA->DIR &= ~BIT(7);
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printf("============== start VCO_CLK_IO test =================");
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}
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*/
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void delay1us(u16 i)
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{
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int num = clk_get("sys") / 1000000 * i;
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while (num--) {
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asm("nop");
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}
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}
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#define GPC_FD_MUX_3_(x) SFR(JL_CLOCK->CLK_CON2,28,4,x)
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//osc clk mux 0:btosc24m 1:btosc48m 2:std24m
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// 3:rtc_osc 4:lrc_clk 5:pat_clk
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#define OSC_CLK_MUX_3_(x) SFR(JL_CLOCK->CLK_CON0,1,3,x)
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//0:lsb_clk 1:osc_clk 2:cap_mux_clk 3:clk_mux
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//4:gpc_fd(9:vad_vcon 10:vad_vcop) 5:ring_clk
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//6:pll_d1p0_mo 7:irflt_in
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#define GPCNT_CSS_3_(x) SFR(JL_GPCNT->CON,1,3,x)//count source select
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#define GPCNT_GSS_3_(x) SFR(JL_GPCNT->CON,12,3,x)//gate source select
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#define GPCNT_GTS_4_(x) SFR(JL_GPCNT->CON,8,4,x)//gate time select 32*2^n
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#define GPCNT_EN_1_(x) SFR(JL_GPCNT->CON,0,1,x)
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#define CLR_PND_1_(x) SFR(JL_GPCNT->CON,6,1,x)
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u32 get_gpcnt(u8 sel_p_n, u8 gs_clk, u8 cs_clk, u8 prd)
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{
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u32 gpcnt_n = 0;
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/*printf("start get cnt\r\n");*/
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GPCNT_EN_1_(0);
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if (sel_p_n == 0) {
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GPC_FD_MUX_3_(9);//9:vad_vcon 10:vad_vcop
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} else {
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GPC_FD_MUX_3_(10);//9:vad_vcon 10:vad_vcop
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}
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OSC_CLK_MUX_3_(gs_clk);
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GPCNT_CSS_3_(cs_clk);
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GPCNT_GSS_3_(1);
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GPCNT_GTS_4_(prd);//32*2^n
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GPCNT_EN_1_(1);
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CLR_PND_1_(1);
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delay1us(1000);
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asm("csync");
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asm("csync");
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asm("csync");
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while (!(JL_GPCNT->CON >> 7 & 0x01));
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asm("csync");
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asm("csync");
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asm("csync");
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gpcnt_n = JL_GPCNT->NUM;
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return gpcnt_n;
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}
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#define FCNT_N 10
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u32 get_avr_gpcnt(void)
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{
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u32 f_cnt = 0, i = 0, fc_num = 0, f_max = 0, f_min = 1000000;
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// delay_1000ms();
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for (i = 0; i < FCNT_N; i++) {
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//osc clk mux 0:btosc24m 1:btosc48m 2:std24m
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// 3:rtc_osc 4:lrc_clk 5:pat_clk
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// 32*2^(7)=4096
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f_cnt = get_gpcnt(1, 2, 4, 7); //32*2^n
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//f_cnt = get_gpcnt(1,0,4,7); //32*2^n
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//printf("===========get vco clk cnt=%d \r\r\n\n",f_cnt);
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fc_num = f_cnt + fc_num;
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if (f_max < f_cnt) {
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f_max = f_cnt;
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}
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if (f_min > f_cnt) {
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f_min = f_cnt;
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}
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wdt_clear();
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}
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//printf("===========get vco f_min clk cnt=%d \r\r\n\n",f_min);
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//printf("===========get vco f_max clk cnt=%d \r\r\n\n",f_max);
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f_cnt = (fc_num - f_max - f_min) / (FCNT_N - 2);
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return f_cnt;
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}
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#define VCO_TRIM_CNT 8
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#define VCO_TRIM_TAR 4949 // 24/32.99= 32*2^7/VCO_TRIM_TAR
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void vad_vco_clk_trim(void)
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{
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u32 gp_cnt[VCO_TRIM_CNT], gp_min, gp_ind;
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u8 i;
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os_time_dly(80); //500ms delay
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for (i = 0; i < VCO_TRIM_CNT; i++) {
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VAD_ADC_RIN_10V_3_(i) ;
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VAD_ADC_RBS_10V_3_(i) ;
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gp_cnt[i] = get_avr_gpcnt();
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printf("get vco clk average cnt[%d]=%d\n", i, gp_cnt[i]);
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}
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for (i = 0; i < VCO_TRIM_CNT; i++) {
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if (gp_cnt[i] > VCO_TRIM_TAR) {
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gp_cnt[i] = gp_cnt[i] - VCO_TRIM_TAR;
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} else {
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gp_cnt[i] = VCO_TRIM_TAR - gp_cnt[i];
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}
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if (i == 0) {
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gp_min = gp_cnt[i];
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gp_ind = i;
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} else if (gp_min > gp_cnt[i]) {
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gp_min = gp_cnt[i];
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gp_ind = i;
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}
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wdt_clear();
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}
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printf("set vco clk index=%d,res=%d\n", gp_ind, gp_min);
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/*VAD_ADC_RIN_10V_3_(gp_ind) ;*/
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/*VAD_ADC_RBS_10V_3_(gp_ind) ;*/
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struct vad_mic_platform_data *data = (struct vad_mic_platform_data *)(VAD_AVAD_CONFIG_BEGIN + sizeof(struct avad_config));
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data->mic_data.adc_rin = gp_ind;
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data->mic_data.adc_rbs = gp_ind;
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}
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void audio_vad_clock_trim(void)
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{
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if (vco_clock_calibrated) {
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return;
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}
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vco_clock_test_mode_setup();
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/*vco_clk2io_test();*/
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vad_vco_clk_trim();
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vco_clock_calibrated = 1;
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}
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