154 lines
3.3 KiB
C
154 lines
3.3 KiB
C
#ifndef _CPU_CLOCK_
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#define _CPU_CLOCK_
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#include "typedef.h"
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#include "clock_hw.h"
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#include "asm/clock_define.h"
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typedef int SYS_CLOCK_INPUT;
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typedef enum {
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SYS_ICLOCK_INPUT_BTOSC, //BTOSC 双脚(12-26M)
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SYS_ICLOCK_INPUT_RTOSCH,
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SYS_ICLOCK_INPUT_RTOSCL,
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SYS_ICLOCK_INPUT_PAT,
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} SYS_ICLOCK_INPUT;
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typedef enum {
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ALINK_CLOCK_12M288K, //160M div 13, 48k采样率类型
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ALINK_CLOCK_11M2896K, //192M div 17, 44.1k采样率类型
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} ALINK_INPUT_CLK_TYPE;
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typedef enum {
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TDM_CLOCK_12M288K, //160M div 13, 48k采样率类型
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TDM_CLOCK_11M2896K, //192M div 17, 44.1k采样率类型
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} TDM_INPUT_CLK_TYPE;
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/*
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* system enter critical and exit critical handle
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* */
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struct clock_critical_handler {
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void (*enter)();
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void (*exit)();
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};
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#define CLOCK_CRITICAL_HANDLE_REG(name, enter, exit) \
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const struct clock_critical_handler clock_##name \
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SEC_USED(.clock_critical_txt) = {enter, exit};
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extern struct clock_critical_handler clock_critical_handler_begin[];
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extern struct clock_critical_handler clock_critical_handler_end[];
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#define list_for_each_loop_clock_critical(h) \
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for (h=clock_critical_handler_begin; h<clock_critical_handler_end; h++)
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int clk_early_init(u8 sys_in, u32 input_freq, u32 out_freq);
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int clk_get(const char *name);
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int clk_set(const char *name, int clk);
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int clk_set_sys_lock(int clk, int lock_en);
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enum CLK_OUT_SOURCE {
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LRC_CLK_OUT,
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P33_RCLK_CLK_OUT,
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RC16M_CLK_OUT,
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RTC_OSC_CLK_OUT,
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BTOSC_24M_CLK_OUT,
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BTOSC_48M_CLK_OUT,
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STD_12M_CLK_OUT,
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STD_24M_CLK_OUT,
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STD_48M_CLK_OUT,
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HSB_CLK_OUT,
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LSB_CLK_OUT,
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PLL_96M_CLK_OUT,
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XXX_CLK_OUT_0,
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XXX_CLK_OUT_1,
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XXX_CLK_OUT_2,
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XXX_CLK_OUT_3,
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};
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enum XXX_CLK_OUT_0_1_SOURCE {
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SRC_CLK_OUT = 12,
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IMD_CLK_OUT,
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PSRAM_CLK_OUT,
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XOSC_CLK_OUT,
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};
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enum XXX_CLK_OUT_2_3_SOURCE {
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PLL_ALNK0_CLK_OUT = 12,
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RF_CLKO75M_CLK_OUT,
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DCDC_CLK_OUT,
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DPLL_CLK_OUT,
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};
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void clk_out(u8 gpio, enum CLK_OUT_SOURCE clk);
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void clock_dump(void);
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#define MHz (1000000L)
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enum sys_clk {
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SYS_24M = 24 * MHz,
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SYS_32M = 32 * MHz,
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SYS_48M = 48 * MHz,
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SYS_64M = 64 * MHz,
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SYS_76M = 76800000,
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SYS_80M = 80 * MHz,
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SYS_96M = 96 * MHz,
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SYS_120M = 120 * MHz,
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SYS_128M = 128 * MHz,
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SYS_160M = 160 * MHz,
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};
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enum clk_mode {
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CLOCK_MODE_ADAPTIVE = 0,
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CLOCK_MODE_USR,
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};
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//clk : SYS_48M / SYS_24M
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void sys_clk_set(enum sys_clk clk);
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void clk_voltage_init(u8 mode, u8 sys_dvdd);
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int xosc_hcs_trim(void);
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void clk_set_osc_cap(u8 sel_l, u8 sel_r);
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u32 clk_get_osc_cap();
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void audio_link_clock_sel(ALINK_INPUT_CLK_TYPE type);
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void tdm_clock_sel(TDM_INPUT_CLK_TYPE type);
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/**
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* @brief clock_set_sfc_max_freq
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* 使用前需要保证所使用的flash支持4bit 100Mhz 模式
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*
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* @param dual_max_freq for cmd 3BH BBH
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* @param quad_max_freq for cmd 6BH EBH
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*/
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void clock_set_sfc_max_freq(u32 dual_max_freq, u32 quad_max_freq);
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/**
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* @brief clock_set_lowest_voltage 设置dvdd工作的最低 工作电压
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*
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* @param dvdd_lev mic 工作时候 建议 SYSVDD_VOL_SEL_105V，关闭的时候设置为 SYSVDD_VOL_SEL_084V
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*/
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void clock_set_lowest_voltage(u32 dvdd_lev);
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/**
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* @brief clock_set_pll_target_frequency
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*
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* @param freq *Mhz 支持192或者240
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*/
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void clock_set_pll_target_frequency(u32 freq);
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u32 clock_get_pll_target_frequency(); //获取PLL_TARGET_FREQUENCY
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#endif
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