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chore: Remove tracked build artifacts

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lmx
2025-11-28 16:24:27 +08:00
parent 892ed9267b
commit 818e8c3778
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256
include_lib/driver/cpu/br28/asm/power/lp_ipc.h
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#ifndef __LP_IPC_H__
#define __LP_IPC_H__
//=================================消息格式========================================
//消息buf大小
#define MAX_POOL 128
//消息类型
#define NO_MSG 0xff
//获取消息返回值
enum {
MSG_NO_ERROR = 0,
MSG_NO_MSG = 0,
MSG_EVENT_EXIST = -1,
MSG_NOT_EVENT = -2,
MSG_EVENT_PARAM_ERROR = -3,
MSG_BUF_NOT_ENOUGH = -4,
MSG_CBUF_ERROR = -5,
};
//消息头格式
#define MSG_HEADER_BYTE_LEN 3
#define MSG_HEADER_BIT_LEN (MSG_HEADER_BYTE_LEN*8)
#define MSG_HEADER_ALL_BIT ((1L<<MSG_HEADER_BIT_LEN) - 1)
#define MSG_INDEX_BIT 7
#define MSG_ACK_BIT 1
#define MSG_TYPE_BIT_LEN 12
#define MSG_PARAM_BIT_LEN (MSG_HEADER_BYTE_LEN*8-MSG_TYPE_BIT_LEN-MSG_INDEX_BIT-MSG_ACK_BIT)
//=================================M2P===========================================
//M2P中断索引
enum {
M2P_LP_INDEX = 0,
M2P_PF_INDEX,
M2P_LLP_INDEX,
M2P_P33_INDEX,
M2P_SF_INDEX,
M2P_CTMU_INDEX,
M2P_CCMD_INDEX, //common cmd
M2P_VAD_INDEX,
M2P_USER_INDEX,
M2P_WDT_INDEX,
M2P_SYNC_INDEX,
M2P_APP_INDEX,
};
#define M2P_LRC_PRD M2P_MESSAGE_ACCESS(0x000)
#define M2P_WDVDD M2P_MESSAGE_ACCESS(0x001)
#define M2P_LRC_TMR_50us M2P_MESSAGE_ACCESS(0x002)
#define M2P_LRC_TMR_200us M2P_MESSAGE_ACCESS(0x003)
#define M2P_LRC_TMR_600us M2P_MESSAGE_ACCESS(0x004)
#define M2P_VDDIO_KEEP M2P_MESSAGE_ACCESS(0x005)
#define M2P_LRC_KEEP M2P_MESSAGE_ACCESS(0x006)
#define M2P_SYNC_CMD M2P_MESSAGE_ACCESS(0x007)
#define M2P_MESSAGE_VAD_CMD M2P_MESSAGE_ACCESS(0x008)
#define M2P_MESSAGE_VAD_CBUF_RPTR M2P_MESSAGE_ACCESS(0x009)
#define M2P_VDDIO_KEEP_TYPE M2P_MESSAGE_ACCESS(0x00a)
#define M2P_RCH_FEQ_H M2P_MESSAGE_ACCESS(0x00b)
#define M2P_MEM_CONTROL M2P_MESSAGE_ACCESS(0x00c)
#define M2P_BTOSC_KEEP M2P_MESSAGE_ACCESS(0x00d)
#define M2P_CTMU_KEEP M2P_MESSAGE_ACCESS(0x00e)
#define M2P_RTC_KEEP M2P_MESSAGE_ACCESS(0x00f)
#define M2P_WDT_SYNC M2P_MESSAGE_ACCESS(0x010)
#define M2P_LIGHT_PDOWN_DVDD_VOL M2P_MESSAGE_ACCESS(0x011)
#define M2P_PVDD_LEVEL_SLEEP_TRIM M2P_MESSAGE_ACCESS(0x012)
/*触摸所有通道配置*/
#define M2P_CTMU_CMD M2P_MESSAGE_ACCESS(0x18)
#define M2P_CTMU_MSG M2P_MESSAGE_ACCESS(0x19)
#define M2P_CTMU_PRD0 M2P_MESSAGE_ACCESS(0x1a)
#define M2P_CTMU_PRD1 M2P_MESSAGE_ACCESS(0x1b)
#define M2P_CTMU_CH_ENABLE M2P_MESSAGE_ACCESS(0x1c)
#define M2P_CTMU_CH_DEBUG M2P_MESSAGE_ACCESS(0x1d)
#define M2P_CTMU_CH_CFG M2P_MESSAGE_ACCESS(0x1e)
#define M2P_CTMU_CH_WAKEUP_EN M2P_MESSAGE_ACCESS(0x1f)
#define M2P_CTMU_EARTCH_CH M2P_MESSAGE_ACCESS(0x20)
#define M2P_CTMU_TIME_BASE M2P_MESSAGE_ACCESS(0x21)
#define M2P_CTMU_LONG_TIMEL M2P_MESSAGE_ACCESS(0x22)
#define M2P_CTMU_LONG_TIMEH M2P_MESSAGE_ACCESS(0x23)
#define M2P_CTMU_HOLD_TIMEL M2P_MESSAGE_ACCESS(0x24)
#define M2P_CTMU_HOLD_TIMEH M2P_MESSAGE_ACCESS(0x25)
#define M2P_CTMU_SOFTOFF_LONG_TIMEL M2P_MESSAGE_ACCESS(0x26)
#define M2P_CTMU_SOFTOFF_LONG_TIMEH M2P_MESSAGE_ACCESS(0x27)
#define M2P_CTMU_LONG_PRESS_RESET_TIME_VALUE_L M2P_MESSAGE_ACCESS(0x28)//长按复位
#define M2P_CTMU_LONG_PRESS_RESET_TIME_VALUE_H M2P_MESSAGE_ACCESS(0x29)//长按复位
#define M2P_CTMU_INEAR_VALUE_L M2P_MESSAGE_ACCESS(0x2a)
#define M2P_CTMU_INEAR_VALUE_H M2P_MESSAGE_ACCESS(0x2b)
#define M2P_CTMU_OUTEAR_VALUE_L M2P_MESSAGE_ACCESS(0x2c)
#define M2P_CTMU_OUTEAR_VALUE_H M2P_MESSAGE_ACCESS(0x2d)
#define M2P_CTMU_EARTCH_TRIM_VALUE_L M2P_MESSAGE_ACCESS(0x2e)
#define M2P_CTMU_EARTCH_TRIM_VALUE_H M2P_MESSAGE_ACCESS(0x2f)
#define M2P_MASSAGE_CTMU_CH0_CFG0L 0x30
#define M2P_MASSAGE_CTMU_CH0_CFG0H 0x31
#define M2P_MASSAGE_CTMU_CH0_CFG1L 0x32
#define M2P_MASSAGE_CTMU_CH0_CFG1H 0x33
#define M2P_MASSAGE_CTMU_CH0_CFG2L 0x34
#define M2P_MASSAGE_CTMU_CH0_CFG2H 0x35
#define M2P_CTMU_CH0_CFG0L M2P_MESSAGE_ACCESS(0x30)
#define M2P_CTMU_CH0_CFG0H M2P_MESSAGE_ACCESS(0x31)
#define M2P_CTMU_CH0_CFG1L M2P_MESSAGE_ACCESS(0x32)
#define M2P_CTMU_CH0_CFG1H M2P_MESSAGE_ACCESS(0x33)
#define M2P_CTMU_CH0_CFG2L M2P_MESSAGE_ACCESS(0x34)
#define M2P_CTMU_CH0_CFG2H M2P_MESSAGE_ACCESS(0x35)
#define M2P_CTMU_CH1_CFG0L M2P_MESSAGE_ACCESS(0x38)
#define M2P_CTMU_CH1_CFG0H M2P_MESSAGE_ACCESS(0x39)
#define M2P_CTMU_CH1_CFG1L M2P_MESSAGE_ACCESS(0x3a)
#define M2P_CTMU_CH1_CFG1H M2P_MESSAGE_ACCESS(0x3b)
#define M2P_CTMU_CH1_CFG2L M2P_MESSAGE_ACCESS(0x3c)
#define M2P_CTMU_CH1_CFG2H M2P_MESSAGE_ACCESS(0x3d)
#define M2P_CTMU_CH2_CFG0L M2P_MESSAGE_ACCESS(0x40)
#define M2P_CTMU_CH2_CFG0H M2P_MESSAGE_ACCESS(0x41)
#define M2P_CTMU_CH2_CFG1L M2P_MESSAGE_ACCESS(0x42)
#define M2P_CTMU_CH2_CFG1H M2P_MESSAGE_ACCESS(0x43)
#define M2P_CTMU_CH2_CFG2L M2P_MESSAGE_ACCESS(0x44)
#define M2P_CTMU_CH2_CFG2H M2P_MESSAGE_ACCESS(0x45)
#define M2P_CTMU_CH3_CFG0L M2P_MESSAGE_ACCESS(0x48)
#define M2P_CTMU_CH3_CFG0H M2P_MESSAGE_ACCESS(0x49)
#define M2P_CTMU_CH3_CFG1L M2P_MESSAGE_ACCESS(0x4a)
#define M2P_CTMU_CH3_CFG1H M2P_MESSAGE_ACCESS(0x4b)
#define M2P_CTMU_CH3_CFG2L M2P_MESSAGE_ACCESS(0x4c)
#define M2P_CTMU_CH3_CFG2H M2P_MESSAGE_ACCESS(0x4d)
#define M2P_CTMU_CH4_CFG0L M2P_MESSAGE_ACCESS(0x50)
#define M2P_CTMU_CH4_CFG0H M2P_MESSAGE_ACCESS(0x51)
#define M2P_CTMU_CH4_CFG1L M2P_MESSAGE_ACCESS(0x52)
#define M2P_CTMU_CH4_CFG1H M2P_MESSAGE_ACCESS(0x53)
#define M2P_CTMU_CH4_CFG2L M2P_MESSAGE_ACCESS(0x54)
#define M2P_CTMU_CH4_CFG2H M2P_MESSAGE_ACCESS(0x55)
#define M2P_RVD2PVDD_EN M2P_MESSAGE_ACCESS(0x56)
#define M2P_PVDD_EXTERN_DCDC M2P_MESSAGE_ACCESS(0x57)
#define M2P_USER_PEND (0x58)
#define M2P_USER_MSG_TYPE (0x59)
#define M2P_USER_MSG_LEN0 (0x5a)
#define M2P_USER_MSG_LEN1 (0x5b)
#define M2P_USER_ADDR0 (0x5c)
#define M2P_USER_ADDR1 (0x5d)
#define M2P_USER_ADDR2 (0x5e)
#define M2P_USER_ADDR3 (0x5f)
enum {
CLOSE_P33_INTERRUPT = 1,
OPEN_P33_INTERRUPT,
LOWPOWER_PREPARE,
M2P_SPIN_LOCK,
M2P_SPIN_UNLOCK,
P2M_SPIN_LOCK,
P2M_SPIN_UNLOCK,
M2P_WDT_CLEAR,
P2M_RESERVED_CMD = 0xFF,
};
//=================================P2M===========================================
//P2M中断索引
enum {
P2M_LP_INDEX = 0,
P2M_PF_INDEX,
P2M_LLP_INDEX,
P2M_WK_INDEX,
P2M_WDT_INDEX,
P2M_LP_INDEX2,
P2M_CTMU_INDEX,
P2M_CTMU_POWUP,
P2M_REPLY_CCMD_INDEX, //reply common cmd
P2M_VAD_INDEX,
P2M_USER_INDEX,
P2M_BANK_INDEX,
P2M_REPLY_SYNC_INDEX,
P2M_APP_INDEX,
};
#define P2M_WKUP_SRC P2M_MESSAGE_ACCESS(0x000)
#define P2M_WKUP_PND0 P2M_MESSAGE_ACCESS(0x001)
#define P2M_WKUP_PND1 P2M_MESSAGE_ACCESS(0x002)
#define P2M_REPLY_SYNC_CMD P2M_MESSAGE_ACCESS(0x003)
#define P2M_MESSAGE_VAD_CMD P2M_MESSAGE_ACCESS(0x004)
#define P2M_MESSAGE_VAD_CBUF_WPTR P2M_MESSAGE_ACCESS(0x005)
#define P2M_MESSAGE_BANK_ADR_L P2M_MESSAGE_ACCESS(0x006)
#define P2M_MESSAGE_BANK_ADR_H P2M_MESSAGE_ACCESS(0x007)
#define P2M_MESSAGE_BANK_INDEX P2M_MESSAGE_ACCESS(0x008)
#define P2M_MESSAGE_BANK_ACK P2M_MESSAGE_ACCESS(0x009)
#define P2M_P11_HEAP_BEGIN_ADDR_L P2M_MESSAGE_ACCESS(0x00A)
#define P2M_P11_HEAP_BEGIN_ADDR_H P2M_MESSAGE_ACCESS(0x00B)
#define P2M_P11_HEAP_SIZE_L P2M_MESSAGE_ACCESS(0x00C)
#define P2M_P11_HEAP_SIZE_H P2M_MESSAGE_ACCESS(0x00D)
#define P2M_CTMU_KEY_EVENT P2M_MESSAGE_ACCESS(0x010)
#define P2M_CTMU_KEY_CNT P2M_MESSAGE_ACCESS(0x011)
#define P2M_CTMU_WKUP_MSG P2M_MESSAGE_ACCESS(0x012)
#define P2M_CTMU_EARTCH_EVENT P2M_MESSAGE_ACCESS(0x013)
#define P2M_MASSAGE_CTMU_CH0_L_RES 0x014
#define P2M_MASSAGE_CTMU_CH0_H_RES 0x015
#define P2M_CTMU_CH0_L_RES P2M_MESSAGE_ACCESS(0x014)
#define P2M_CTMU_CH0_H_RES P2M_MESSAGE_ACCESS(0x015)
#define P2M_CTMU_CH1_L_RES P2M_MESSAGE_ACCESS(0x016)
#define P2M_CTMU_CH1_H_RES P2M_MESSAGE_ACCESS(0x017)
#define P2M_CTMU_CH2_L_RES P2M_MESSAGE_ACCESS(0x018)
#define P2M_CTMU_CH2_H_RES P2M_MESSAGE_ACCESS(0x019)
#define P2M_CTMU_CH3_L_RES P2M_MESSAGE_ACCESS(0x01a)
#define P2M_CTMU_CH3_H_RES P2M_MESSAGE_ACCESS(0x01b)
#define P2M_CTMU_CH4_L_RES P2M_MESSAGE_ACCESS(0x01c)
#define P2M_CTMU_CH4_H_RES P2M_MESSAGE_ACCESS(0x01d)
#define P2M_CTMU_EARTCH_L_IIR_VALUE P2M_MESSAGE_ACCESS(0x01e)
#define P2M_CTMU_EARTCH_H_IIR_VALUE P2M_MESSAGE_ACCESS(0x01f)
#define P2M_CTMU_EARTCH_L_TRIM_VALUE P2M_MESSAGE_ACCESS(0x020)
#define P2M_CTMU_EARTCH_H_TRIM_VALUE P2M_MESSAGE_ACCESS(0x021)
#define P2M_CTMU_EARTCH_L_DIFF_VALUE P2M_MESSAGE_ACCESS(0x022)
#define P2M_CTMU_EARTCH_H_DIFF_VALUE P2M_MESSAGE_ACCESS(0x023)
#define P2M_AWKUP_P_PND P2M_MESSAGE_ACCESS(0x024)
#define P2M_AWKUP_N_PND P2M_MESSAGE_ACCESS(0x025)
#define P2M_WKUP_RTC P2M_MESSAGE_ACCESS(0x026)
#define P2M_CBUF_ADDR0 P2M_MESSAGE_ACCESS(0x027)
#define P2M_CBUF_ADDR1 P2M_MESSAGE_ACCESS(0x028)
#define P2M_CBUF_ADDR2 P2M_MESSAGE_ACCESS(0x029)
#define P2M_CBUF_ADDR3 P2M_MESSAGE_ACCESS(0x02a)
#define P2M_CBUF1_ADDR0 P2M_MESSAGE_ACCESS(0x02b)
#define P2M_CBUF1_ADDR1 P2M_MESSAGE_ACCESS(0x02c)
#define P2M_CBUF1_ADDR2 P2M_MESSAGE_ACCESS(0x02d)
#define P2M_CBUF1_ADDR3 P2M_MESSAGE_ACCESS(0x02e)
#define P2M_USER_PEND (0x038)//传感器使用或者开放客户使用
#define P2M_USER_MSG_TYPE (0x039)
#define P2M_USER_MSG_LEN0 (0x03a)
#define P2M_USER_MSG_LEN1 (0x03b)
#define P2M_USER_ADDR0 (0x03c)
#define P2M_USER_ADDR1 (0x03d)
#define P2M_USER_ADDR2 (0x03e)
#define P2M_USER_ADDR3 (0x040)
#include "m2p_msg.h"
#include "p2m_msg.h"
void msys_to_p11_sync_cmd(u8 cmd);
void lp_ipc_init();
#endif

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include_lib/driver/cpu/br28/asm/power/m2p_msg.h
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#ifndef __M2P_MSG_H__
#define __M2P_MSG_H__
//m2p用户消息类型
enum {
M2P_MSG_ACK = BIT(0),
M2P_MSG_TEST = BIT(1),
M2P_MSG_COMMOM = BIT(2),
M2P_MSG_CTMU = BIT(3),
M2P_MSG_SENSOR = BIT(4),
M2P_MSG_VAD = BIT(5),
};
//测试
struct m2p_msg_test {
u8 dat;
};
//测试
struct m2p_msg_ack {
u8 dat;
};
//公共消息
struct m2p_msg_common {
u8 dat;
};
//触摸消息
struct m2p_msg_ctmu {
u8 dat;
};
//vad
struct m2p_msg_vad {
u8 dat;
};
//m2p用户消息格式
struct m2p_msg_head {
u16 type :
MSG_TYPE_BIT_LEN;
u16 len :
MSG_PARAM_BIT_LEN;
u8 index :
MSG_INDEX_BIT;
u8 ack :
MSG_ACK_BIT;
} __attribute__((packed));
struct m2p_msg {
struct m2p_msg_head head;
union {
struct m2p_msg_ack ack;
struct m2p_msg_test test;
struct m2p_msg_common com;
struct m2p_msg_ctmu ctmu;
struct m2p_msg_vad vad;
} u;
} __attribute__((packed));
//m2p用户消息对应处理
struct m2p_msg_handler {
u8 type;
void (*handler)(struct m2p_msg *);
} __attribute__((packed));
#define REGISTER_M2P_MSG_HANDLER(_type, fn, pri) \
const struct m2p_msg_handler _##fn SEC_USED(.m2p_msg_handler)= { \
.type = _type, \
.handler = fn, \
}
extern struct m2p_msg_handler m2p_msg_handler_begin[];
extern struct m2p_msg_handler m2p_msg_handler_end[];
#define list_for_each_m2p_msg_handler(p) \
for (p = m2p_msg_handler_begin; p < m2p_msg_handler_end; p++)
int m2p_get_msg(int len, struct m2p_msg *msg);
int m2p_post_msg(int len, struct m2p_msg *msg);
int m2p_post_sync_msg(int len, struct m2p_msg *msg, u8 abandon, int timeout);
void msys_to_p11_sys_cmd(u8 cmd);
#endif

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include_lib/driver/cpu/br28/asm/power/p11.h
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/*********************************************************************************************
* Filename : p11.h
* Description :
* Author : Bingquan
* Email : caibingquan@zh-jieli.com
* Last modifiled : 2019-12-09 10:21
* Copyright:(c)JIELI 2011-2019 @ , All Rights Reserved.
*********************************************************************************************/
#ifndef __P11_H__
#define __P11_H__
#include "p11_csfr.h"
#include "p11_sfr.h"
#include "p11_app.h"
#endif /* #ifndef __P11_H__ */

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include_lib/driver/cpu/br28/asm/power/p11_app.h
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/*********************************************************************************************
* Filename : p11_app.h
* Description : 本文件基于p11.h文件封装应用的接口
* Author : MoZhiYe
* Email : mozhiye@zh-jieli.com
* Last modifiled : 2021-04-19 09:00
* Copyright:(c)JIELI 2021-2029 @ , All Rights Reserved.
*********************************************************************************************/
#ifndef __P11_APP_H__
#define __P11_APP_H__
#include "p11.h"
/*
_______________ <-----P11 Message Acess End
| poweroff boot |
|_______________|
| m2p msg(0x40) |
|_______________|
| p2m msg(0x40) |
|_______________|<-----P11 Message Acess Begin
| |
| p11 use |
|_______________|__
*/
#define P11_RAM_BASE 0xF20000
#define P11_RAM_SIZE (0x8000)
#define P11_RAM_END (P11_RAM_BASE + P11_RAM_SIZE)
#define P11_POWEROFF_RAM_SIZE (0x14 + 0xc)
#define P11_POWEROFF_RAM_BEGIN (P11_RAM_END - P11_POWEROFF_RAM_SIZE)
#define P2M_MESSAGE_SIZE 0x40
#define M2P_MESSAGE_SIZE 0x60
#define M2P_MESSAGE_RAM_BEGIN (P11_POWEROFF_RAM_BEGIN - M2P_MESSAGE_SIZE)
#define P2M_MESSAGE_RAM_BEGIN (M2P_MESSAGE_RAM_BEGIN - P2M_MESSAGE_SIZE)
#define P11_MESSAGE_RAM_BEGIN (P2M_MESSAGE_RAM_BEGIN)
#define P11_RAM_ACCESS(x) (*(volatile u8 *)(x))
#define P2M_MESSAGE_ACCESS(x) P11_RAM_ACCESS(P2M_MESSAGE_RAM_BEGIN + x)
#define M2P_MESSAGE_ACCESS(x) P11_RAM_ACCESS(M2P_MESSAGE_RAM_BEGIN + x)
//==========================================================//
// P11_VAD_RAM //
//==========================================================//
//-------------------------- VAD CBUF-----------------------//
#define VAD_POINT_PER_FRAME (160)
#define VAD_FRAME_SIZE (160 * 2)
#define VAD_CBUF_FRAME_CNT (6)
#define VAD_CBUF_TAG_SIZE (0)
#define VAD_CBUF_FRAME_SIZE (VAD_FRAME_SIZE + VAD_CBUF_TAG_SIZE)
#define CONFIG_P11_CBUF_SIZE (VAD_CBUF_FRAME_SIZE * VAD_CBUF_FRAME_CNT)
#define VAD_CBUF_END (P11_MESSAGE_RAM_BEGIN - 0x20)
#define VAD_CBUF_BEGIN (VAD_CBUF_END - CONFIG_P11_CBUF_SIZE)
//------------------------ VAD CONFIG-----------------------//
#define CONFIG_P2M_AVAD_CONFIG_SIZE (20 * 4) //sizeof(int)
#define CONFIG_P2M_DVAD_CONFIG_SIZE (20 * 4) //sizeof(int)
#define CONFIG_VAD_CONFIG_SIZE (CONFIG_P2M_AVAD_CONFIG_SIZE + CONFIG_P2M_DVAD_CONFIG_SIZE)
#define VAD_AVAD_CONFIG_BEGIN (VAD_CBUF_BEGIN - CONFIG_P2M_AVAD_CONFIG_SIZE)
#define VAD_DVAD_CONFIG_BEGIN (VAD_AVAD_CONFIG_BEGIN - CONFIG_P2M_DVAD_CONFIG_SIZE)
#define P11_HEAP_BEGIN (P11_RAM_BASE + ((P2M_P11_HEAP_BEGIN_ADDR_H << 8) | P2M_P11_HEAP_BEGIN_ADDR_L))
#define P11_HEAP_SIZE ((P2M_P11_HEAP_SIZE_H << 8) | P2M_P11_HEAP_SIZE_L)
#define P11_RAM_PROTECT_END (P11_HEAP_BEGIN)
#define P11_PWR_CON P11_CLOCK->PWR_CON
/*
*------------------- P11_CLOCK->CLK_CON
*/
#define P11_CLK_CON0 P11_CLOCK->CLK_CON0
enum P11_SYS_CLK_TABLE {
P11_SYS_CLK_RC250K = 0,
P11_SYS_CLK_RC16M,
P11_SYS_CLK_LRC_OSC,
P11_SYS_CLK_BTOSC_24M,
P11_SYS_CLK_BTOSC_48M,
P11_SYS_CLK_PLL_SYS_CLK,
P11_SYS_CLK_CLK_X2,
};
//#define P11_SYS_CLK_SEL(x) SFR(P11_CLOCK->CLK_CON0, 0, 3, x)
#define P11_SYS_CLK_SEL(x) (P11_CLOCK->CLK_CON0 = x)
//p11 btosc use d2sh
#define CLOCK_KEEP(en) \
if(en){ \
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
P11_CLOCK->CLK_CON1 |= BIT(14); \
P11_CLOCK->CLK_CON1 |= (2<<15); \
}else{ \
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
P11_CLOCK->CLK_CON1 &= ~BIT(14); \
}
#define P11_P2M_CLK_CON0 P11_SYSTEM->P2M_CLK_CON0
#define P11_SYSTEM_CON0 P11_SYSTEM->P11_SYS_CON0
#define P11_SYSTEM_CON1 P11_SYSTEM->P11_SYS_CON1
#define P11_P11_SYS_CON0 P11_SYSTEM_CON0
#define P11_P11_SYS_CON1 P11_SYSTEM_CON1
#define P11_RST_SRC P11_CLOCK->RST_SRC
#define LED_CLK_SEL(x) P11_SYSTEM->P2M_CLK_CON0 = ((P11_SYSTEM->P2M_CLK_CON0 & ~0xe0) | (x) << 5)
#define GET_LED_CLK_SEL(x) (P11_SYSTEM->P2M_CLK_CON0 & 0xe0)
#define P11_WDT_CON P11_WDT->CON
#define P11_P2M_INT_IE P11_SYSTEM->P2M_INT_IE
#define P11_M2P_INT_IE P11_SYSTEM->M2P_INT_IE
#define P11_M2P_INT_SET P11_SYSTEM->M2P_INT_SET
#define P11_P2M_INT_SET P11_SYSTEM->P2M_INT_SET
#define P11_P2M_INT_CLR P11_SYSTEM->P2M_INT_CLR
#define P11_P2M_INT_PND P11_SYSTEM->P2M_INT_PND //?
#define P11_M2P_INT_PND P11_SYSTEM->M2P_INT_PND //?
#define P11_TMR0_CON0 P11_LPTMR0->CON0
#define P11_TMR0_CON1 P11_LPTMR0->CON1
#define P11_TMR0_CON2 P11_LPTMR0->CON2
#define P11_TMR0_CNT P11_LPTMR0->CNT
#define P11_TMR0_PRD P11_LPTMR0->PRD
#define P11_TMR0_RSC P11_LPTMR0->RSC
#define P11_TMR1_CON0 P11_LPTMR1->CON0
#define P11_TMR1_CON1 P11_LPTMR1->CON1
#define P11_TMR1_CON2 P11_LPTMR1->CON2
#define P11_TMR1_CNT P11_LPTMR1->CNT
#define P11_TMR1_PRD P11_LPTMR1->PRD
#define P11_TMR1_RSC P11_LPTMR1->RSC
#define P11_TMR2_CON0 P11_LPTMR2->CON0
#define P11_TMR2_CON1 P11_LPTMR2->CON1
#define P11_TMR2_CON2 P11_LPTMR2->CON2
#define P11_TMR2_CNT P11_LPTMR2->CNT
#define P11_TMR2_PRD P11_LPTMR2->PRD
#define P11_TMR2_RSC P11_LPTMR2->RSC
#define P11_TMR3_CON0 P11_LPTMR3->CON0
#define P11_TMR3_CON1 P11_LPTMR3->CON1
#define P11_TMR3_CON2 P11_LPTMR3->CON2
#define P11_TMR3_CNT P11_LPTMR3->CNT
#define P11_TMR3_PRD P11_LPTMR3->PRD
#define P11_TMR3_RSC P11_LPTMR3->RSC
#define GET_P11_SYS_RST_SRC() P11_RST_SRC
#define LP_PWR_IDLE(x) SFR(P11_PWR_CON, 0, 1, x)
#define LP_PWR_STANDBY(x) SFR(P11_PWR_CON, 1, 1, x)
#define LP_PWR_SLEEP(x) SFR(P11_PWR_CON, 2, 1, x)
#define LP_PWR_SSMODE(x) SFR(P11_PWR_CON, 3, 1, x)
#define LP_PWR_SOFT_RESET(x) SFR(P11_PWR_CON, 4, 1, x)
#define LP_PWR_INIT_FLAG() (P11_PWR_CON & BIT(5))
#define LP_PWR_RST_FLAG_CLR(x) SFR(P11_PWR_CON, 6, 1, x)
#define LP_PWR_RST_FLAG() (P11_PWR_CON & BIT(7))
#define P33_TEST_ENABLE() P11_P11_SYS_CON0 |= BIT(5)
#define P33_TEST_DISABLE() P11_P11_SYS_CON0 &= ~BIT(5)
#define P11_TX_DISABLE(x) P11_SYSTEM->P11_SYS_CON1 |= BIT(2)
#define P11_TX_ENABLE(x) P11_SYSTEM->P11_SYS_CON1 &= ~BIT(2)
#define MSYS_IO_LATCH_ENABLE() P11_SYSTEM->P11_SYS_CON1 |= BIT(7)
#define MSYS_IO_LATCH_DISABLE() P11_SYSTEM->P11_SYS_CON1 &= ~BIT(7)
#define LP_TMR0_EN(x) SFR(P11_TMR0_CON0, 0, 1, x)
#define LP_TMR0_CTU(x) SFR(P11_TMR0_CON0, 1, 1, x)
#define LP_TMR0_P11_WKUP_IE(x) SFR(P11_TMR0_CON0, 2, 1, x)
#define LP_TMR0_P11_TO_IE(x) SFR(P11_TMR0_CON0, 3, 1, x)
#define LP_TMR0_CLR_P11_WKUP(x) SFR(P11_TMR0_CON0, 4, 1, x)
#define LP_TMR0_P11_WKUP(x) (P11_TMR0_CON0 & BIT(5))
#define LP_TMR0_CLR_P11_TO(x) SFR(P11_TMR0_CON0, 6, 1, x)
#define LP_TMR0_P11_TO(x) (P11_TMR0_CON0 & BIT(7))
#define LP_TMR0_SW_KICK_START_EN(x) SFR(P11_TMR0_CON1, 0, 1, x)
#define LP_TMR0_HW_KICK_START_EN(x) SFR(P11_TMR0_CON1, 1, 1, x)
#define LP_TMR0_WKUP_IE(x) SFR(P11_TMR0_CON1, 2, 1, x)
#define LP_TMR0_TO_IE(x) SFR(P11_TMR0_CON1, 3, 1, x)
#define LP_TMR0_CLR_MSYS_WKUP(x) SFR(P11_TMR0_CON1, 4, 1, x)
#define LP_TMR0_MSYS_WKUP(x) (P11_TMR0_CON1 & BIT(5))
#define LP_TMR0_CLR_MSYS_TO(x) SFR(P11_TMR0_CON1, 6, 1, x)
#define LP_TMR0_MSYS_TO(x) (P11_TMR0_CON1 & BIT(7))
#define LP_TMR0_CLK_SEL(x) SFR(P11_TMR0_CON2, 0, 4, x)
#define LP_TMR0_CLK_DIV(x) SFR(P11_TMR0_CON2, 4, 4, x)
#define LP_TMR0_KST(x) SFR(P11_TMR0_CON2, 8, 1, x)
#define LP_TMR0_RUN() (P11_TMR0_CON2 & BIT(9))
#define P11_M2P_RESET_MASK(x) SFR(P11_P11_SYS_CON1 , 4, 1, x)
//MEM_PWR_CON
#define MEM_PWR_CPU_CON BIT(0)
#define MEM_PWR_RAM0_RAM3_CON BIT(1)
#define MEM_PWR_RAM4_RAM5_CON BIT(2)
#define MEM_PWR_RAM6_RAM7_CON BIT(3)
#define MEM_PWR_RAM8_RAM9_CON BIT(4)
#define MEM_PWR_PERIPH_CON BIT(5)
#define MEM_PWR_RAM_SET(a) (((1 << a) - 1) - 1)
#define LRC_Hz_DEFAULT (200 * 1000L)
#define LRC_CON0_INIT \
/* */ (0 << 7) |\
/* */ (0 << 6) |\
/*RC32K_RPPS_S1_33v */ (1 << 5) |\
/*RC32K_RPPS_S0_33v */ (0 << 4) |\
/* */ (0 << 3) |\
/* */ (0 << 2) |\
/*RC32K_RN_TRIM_33v */ (0 << 1) |\
/*RC32K_EN_33v */ (1 << 0)
#define LRC_CON1_INIT \
/* */ (0 << 7) |\
/*RC32K_CAP_S2_33v */ (1 << 6) |\
/*RC32K_CAP_S1_33v */ (0 << 5) |\
/*RC32K_CAP_S0_33v */ (0 << 4) |\
/* 2bit */ (0 << 2) |\
/*RC32K_RNPS_S1_33v */ (0 << 1) |\
/*RC32K_RNPS_S0_33v */ (1 << 0)
void wdt_isr(void);
u8 p11_run_query(void);
#endif /* #ifndef __P11_APP_H__ */

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include_lib/driver/cpu/br28/asm/power/p11_csfr.h
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//*********************************************************************************//
// Module name : csfr.h //
// Description : q32small core sfr define //
// By Designer : zequan_liu //
// Dat changed : //
//*********************************************************************************//
#ifndef __P11_Q32S_CSFR__
#define __P11_Q32S_CSFR__
#define __RW volatile // read write
#define __RO volatile const // only read
#define __WO volatile // only write
#define __u8 unsigned int // u8 to u32 special for struct
#define __u16 unsigned int // u16 to u32 special for struct
#define __u32 unsigned int
//---------------------------------------------//
// q32small define
//---------------------------------------------//
#ifdef PMU_SYSTEM
#define p11_q32s_sfr_base 0x00a000
#define p11_q32s_sfr_offset 0x000000 // multi_core used
#else
#define p11_q32s_sfr_base 0xf2a000
#define p11_q32s_sfr_offset 0x000000 // multi_core used
#endif
#define p11_q32s_cpu_base (p11_q32s_sfr_base + 0x00)
#define p11_q32s_mpu_base (p11_q32s_sfr_base + 0x80)
#define p11_q32s(n) ((JL_TypeDef_p11_q32s *)(p11_q32s_sfr_base + p11_q32s_sfr_offset*n))
#define p11_q32s_mpu(n) ((JL_TypeDef_p11_q32s_MPU *)(p11_q32s_mpu_base + p11_q32s_sfr_offset*n))
//---------------------------------------------//
// q32small core sfr
//---------------------------------------------//
typedef struct {
/* 00 */ __RO __u32 DR00;
/* 01 */ __RO __u32 DR01;
/* 02 */ __RO __u32 DR02;
/* 03 */ __RO __u32 DR03;
/* 04 */ __RO __u32 DR04;
/* 05 */ __RO __u32 DR05;
/* 06 */ __RO __u32 DR06;
/* 07 */ __RO __u32 DR07;
/* 08 */ __RO __u32 DR08;
/* 09 */ __RO __u32 DR09;
/* 0a */ __RO __u32 DR10;
/* 0b */ __RO __u32 DR11;
/* 0c */ __RO __u32 DR12;
/* 0d */ __RO __u32 DR13;
/* 0e */ __RO __u32 DR14;
/* 0f */ __RO __u32 DR15;
/* 10 */ __RO __u32 RETI;
/* 11 */ __RO __u32 RETE;
/* 12 */ __RO __u32 RETX;
/* 13 */ __RO __u32 RETS;
/* 14 */ __RO __u32 SR04;
/* 15 */ __RO __u32 PSR;
/* 16 */ __RO __u32 CNUM;
/* 17 */ __RO __u32 SR07;
/* 18 */ __RO __u32 SR08;
/* 19 */ __RO __u32 SR09;
/* 1a */ __RO __u32 SR10;
/* 1b */ __RO __u32 ICFG;
/* 1c */ __RO __u32 USP;
/* 1d */ __RO __u32 SSP;
/* 1e */ __RO __u32 SP;
/* 1f */ __RO __u32 PCRS;
/* 20 */ __RW __u32 BPCON;
/* 21 */ __RW __u32 BSP;
/* 22 */ __RW __u32 BP0;
/* 23 */ __RW __u32 BP1;
/* 24 */ __RW __u32 BP2;
/* 25 */ __RW __u32 BP3;
/* 26 */ __WO __u32 CMD_PAUSE;
/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
/* 30 */ __RW __u32 PMU_CON;
/* */ __RO __u32 REV_3b_30[0x3b - 0x30 - 1];
/* 3b */ __RW __u8 TTMR_CON;
/* 3c */ __RW __u32 TTMR_CNT;
/* 3d */ __RW __u32 TTMR_PRD;
/* 3e */ __RW __u32 BANK_CON;
/* 3f */ __RW __u32 BANK_NUM;
/* 40 */ __RW __u32 ICFG00;
/* 41 */ __RW __u32 ICFG01;
/* 42 */ __RW __u32 ICFG02;
/* 43 */ __RW __u32 ICFG03;
/* 44 */ __RW __u32 ICFG04;
/* 45 */ __RW __u32 ICFG05;
/* 46 */ __RW __u32 ICFG06;
/* 47 */ __RW __u32 ICFG07;
/* 48 */ __RW __u32 ICFG08;
/* 49 */ __RW __u32 ICFG09;
/* 4a */ __RW __u32 ICFG10;
/* 4b */ __RW __u32 ICFG11;
/* 4c */ __RW __u32 ICFG12;
/* 4d */ __RW __u32 ICFG13;
/* 4e */ __RW __u32 ICFG14;
/* 4f */ __RW __u32 ICFG15;
/* 50 */ __RW __u32 ICFG16;
/* 51 */ __RW __u32 ICFG17;
/* 52 */ __RW __u32 ICFG18;
/* 53 */ __RW __u32 ICFG19;
/* 54 */ __RW __u32 ICFG20;
/* 55 */ __RW __u32 ICFG21;
/* 56 */ __RW __u32 ICFG22;
/* 57 */ __RW __u32 ICFG23;
/* 58 */ __RW __u32 ICFG24;
/* 59 */ __RW __u32 ICFG25;
/* 5a */ __RW __u32 ICFG26;
/* 5b */ __RW __u32 ICFG27;
/* 5c */ __RW __u32 ICFG28;
/* 5d */ __RW __u32 ICFG29;
/* 5e */ __RW __u32 ICFG30;
/* 5f */ __RW __u32 ICFG31;
/* 60 */ __RO __u32 IPND0;
/* 61 */ __RO __u32 IPND1;
/* 62 */ __RO __u32 IPND2;
/* 63 */ __RO __u32 IPND3;
/* 64 */ __RO __u32 IPND4;
/* 65 */ __RO __u32 IPND5;
/* 66 */ __RO __u32 IPND6;
/* 67 */ __RO __u32 IPND7;
/* 68 */ __WO __u32 ILAT_SET;
/* 69 */ __WO __u32 ILAT_CLR;
/* 6a */ __RW __u32 IPMASK;
/* 6b */ __RW __u32 GIEMASK;
/* 6c */ __RW __u32 IWKUP_NUM;
/* */ __RO __u32 REV_70_6c[0x70 - 0x6c - 1];
/* 70 */ __RW __u32 ETM_CON;
/* 71 */ __RO __u32 ETM_PC0;
/* 72 */ __RO __u32 ETM_PC1;
/* 73 */ __RO __u32 ETM_PC2;
/* 74 */ __RO __u32 ETM_PC3;
/* 75 */ __RW __u32 WP0_ADRH;
/* 76 */ __RW __u32 WP0_ADRL;
/* 77 */ __RW __u32 WP0_DATH;
/* 78 */ __RW __u32 WP0_DATL;
/* 79 */ __RW __u32 WP0_PC;
/* */ __RO __u32 REV_80_79[0x80 - 0x79 - 1];
/* 80 */ __RW __u32 EMU_CON;
/* 81 */ __RW __u32 EMU_MSG;
/* 82 */ __RO __u32 EMU_SSP_H;
/* 83 */ __RO __u32 EMU_SSP_L;
/* 84 */ __RO __u32 EMU_USP_H;
/* 85 */ __RO __u32 EMU_USP_L;
} JL_TypeDef_p11_q32s;
#undef __RW
#undef __RO
#undef __WO
#undef __u8
#undef __u16
#undef __u32
#endif
//*********************************************************************************//
// //
// end of this module //
// //
//*********************************************************************************//

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include_lib/driver/cpu/br28/asm/power/p11_io_imap.h
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//===============================================================================//
//
// input IO define
//
//===============================================================================//
#define P11_PB0_IN 1
#define P11_PB1_IN 2
#define P11_PB2_IN 3
#define P11_PB3_IN 4
#define P11_PB4_IN 5
#define P11_PB5_IN 6
#define P11_PB6_IN 7
#define P11_PB7_IN 8
#define P11_PB8_IN 9
#define P11_PB9_IN 10
#define P11_PB10_IN 11
#define P11_PB11_IN 12
//===============================================================================//
//
// function input select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 P11_FI_GP_ICH0;
__RW __u8 P11_FI_GP_ICH1;
__RW __u8 P11_FI_GP_ICH2;
__RW __u8 P11_FI_UART0_RX;
__RW __u8 P11_FI_SPI_DI;
__RW __u8 P11_FI_IIC_SCL;
__RW __u8 P11_FI_IIC_SDA;
__RW __u8 P11_FI_DMIC_DAT;
} P11_IMAP_TypeDef;
#define P11_IMAP_BASE (p11_sfr_base + map_adr(0x16, 0x00))
#define P11_IMAP ((P11_IMAP_TypeDef *)P11_IMAP_BASE)

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include_lib/driver/cpu/br28/asm/power/p11_io_omap.h
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//===============================================================================//
//
// output function define
//
//===============================================================================//
#define P11_FO_GP_OCH0 ((0 << 2)|BIT(1))
#define P11_FO_GP_OCH1 ((1 << 2)|BIT(1))
#define P11_FO_GP_OCH2 ((2 << 2)|BIT(1))
#define P11_FO_UART0_TX ((3 << 2)|BIT(1)|BIT(0))
#define P11_FO_UART1_TX ((4 << 2)|BIT(1)|BIT(0))
#define P11_FO_SPI_CLK ((5 << 2)|BIT(1)|BIT(0))
#define P11_FO_SPI_DO ((6 << 2)|BIT(1)|BIT(0))
#define P11_FO_IIC_SCL ((7 << 2)|BIT(1)|BIT(0))
#define P11_FO_IIC_SDA ((8 << 2)|BIT(1)|BIT(0))
#define P11_FO_DMIC_CLK ((9 << 2)|BIT(1)|BIT(0))
//===============================================================================//
//
// IO output select sfr
//
//===============================================================================//
typedef struct {
__RW __u8 P11_PB0_OUT;
__RW __u8 P11_PB1_OUT;
__RW __u8 P11_PB2_OUT;
__RW __u8 P11_PB3_OUT;
__RW __u8 P11_PB4_OUT;
__RW __u8 P11_PB5_OUT;
__RW __u8 P11_PB6_OUT;
__RW __u8 P11_PB7_OUT;
__RW __u8 P11_PB8_OUT;
__RW __u8 P11_PB9_OUT;
__RW __u8 P11_PB10_OUT;
__RW __u8 P11_PB11_OUT;
} P11_OMAP_TypeDef;
#define P11_OMAP_BASE (p11_sfr_base + map_adr(0x15, 0x00))
#define P11_OMAP ((P11_OMAP_TypeDef *)P11_OMAP_BASE)

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include_lib/driver/cpu/br28/asm/power/p11_sfr.h
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#ifndef __P11__
#define __P11__
//===============================================================================//
//
// sfr define
//
//===============================================================================//
#ifdef PMU_SYSTEM
#define p11_base 0x000000
#define p11_ram_base p11_base
#define p11_sfr_base 0x00a000
#else
#define p11_base 0xf20000
#define p11_ram_base p11_base
#define p11_sfr_base 0xf2a000
#endif
#define __RW volatile // read write
#define __RO volatile const // only read
#define __WO volatile // only write
#define __u8 unsigned int // u8 to u32 special for struct
#define __u16 unsigned int // u16 to u32 special for struct
#define __u32 unsigned int
#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
#define __s16(x) short(x); short(reserved_1_##x)
#define __s32(x) int(x)
#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
//===============================================================================//
//
// sfr address define
//
//===============================================================================//
//............. 0x0000 - 0x03ff............ for cpu
// #include ../core/csfr.h
//............. 0x0400 - 0x04ff............ for clock
typedef struct {
__RW __u32 PWR_CON;
__RW __u32 RST_SRC;
__RW __u32 WKUP_EN;
__RW __u32 WKUP_SRC;
__RW __u32 SYS_DIV;
__RW __u32 CLK_CON0;
__RW __u32 CLK_CON1;
__RW __u32 CLK_CON2;
__RW __u32 CLK_CON3;
} P11_CLOCK_TypeDef;
#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
//............. 0x0500 - 0x05ff............ for memory control
typedef struct {
__RW __u32 MPC0;
__RW __u32 MPC1;
__RW __u32 MSC;
} P11_MEM_CTL_TypeDef;
#define P11_MEM_CTL_BASE (p11_sfr_base + map_adr(0x05, 0x00))
#define P11_MEM_CTL ((P11_MEM_CTL_TypeDef *)P11_MEM_CTL_BASE)
//............. 0x0600 - 0x06ff............ for system
typedef struct {
__RW __u32 P2M_INT_IE;
__RW __u32 P2M_INT_SET;
__RW __u32 P2M_INT_CLR;
__RO __u32 P2M_INT_PND;
__RW __u32 P2M_CLK_CON0;
__RW __u32 M2P_INT_IE;
__RW __u32 M2P_INT_SET;
__RW __u32 M2P_INT_CLR;
__RO __u32 M2P_INT_PND;
__RW __u32 P11_SYS_CON0;
__RW __u32 P11_SYS_CON1;
__RW __u32 MEM_PWR_CON;
} P11_SYSTEM_TypeDef;
#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
//............. 0x0800 - 0x08ff............ for watch dog
typedef struct {
__RW __u32 CON;
__RW __u32 KEY;
__RW __u32 DUMMY;
} P11_WDT_TypeDef;
#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
//............. 0x0900 - 0x0cff............ for lp timer
typedef struct {
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 CON2;
__RW __u32 PRD;
__RW __u32 RSC;
__RO __u32 CNT;
} P11_LPTMR_TypeDef;
#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
//............. 0x0d00 - 0x0dff............ for irflt
typedef struct {
__RW __u32 CON;
} P11_IRFLT_TypeDef;
#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
//............. 0x0e00 - 0x0eff............ for spi
typedef struct {
__RW __u32 CON;
__WO __u32 BAUD;
__RW __u32 BUF;
//__WO __u32 ADR;
//__WO __u32 CNT;
} P11_SPI_TypeDef;
#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
//............. 0x0f00 - 0x10ff............ for uart
typedef struct {
__RW __u16 CON0;
//__RW __u16 CON1;
__WO __u16 BAUD;
__RW __u8 BUF;
__RW __u32 OTCNT;
//__RW __u32 TXADR;
//__WO __u16 TXCNT;
//__RW __u32 RXSADR;
//__RW __u32 RXEADR;
//__RW __u32 RXCNT;
//__RO __u16 HRXCNT;
__RW __u16 CON2;
} P11_UART_TypeDef;
#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
//............. 0x1100 - 0x11ff............ for iic
typedef struct {
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 BAUD;
__RW __u32 BUF;
} P11_IIC_TypeDef;
#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
//............. 0x1200 - 0x12ff............ for port
typedef struct {
__RW __u32 OCH_CON0 ;
__RW __u32 ICH_CON0 ;
__RW __u32 P33_PORT ;
__RW __u32 PB_SEL ;
__RW __u32 PB_PU ;
__RW __u32 PB_PD ;
__RW __u32 PB_DIR ;
__RW __u32 PB_DIE ;
__RW __u32 PB_DIEH ;
__RW __u32 PB_OUT ;
__RO __u32 PB_IN ;
} P11_PORT_TypeDef;
#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
//............. 0x1300 - 0x13ff............ for lp ctmu
typedef struct {
__RW __u32 CON0;
__RW __u32 CON1;
__RW __u32 CON2;
__RW __u32 CON3;
__RW __u32 ANA0;
__RW __u32 ANA1;
__RW __u32 RES;
} P11_LPCTM_TypeDef;
#define P11_LPCTM_BASE (p11_sfr_base + map_adr(0x13, 0x00))
#define P11_LPCTM ((P11_LPCTM_TypeDef *)P11_LPCTM_BASE)
//............. 0x1400 - 0x14ff............ for lpvad
typedef struct {
__RW __u32 VAD_CON;
__RW __u32 VAD_ACON0;
__RW __u32 VAD_ACON1;
__RW __u32 AVAD_CON;
__RW __u32 AVAD_DATA;
__RW __u32 DVAD_CON0;
__RW __u32 DVAD_CON1;
__RW __u32 DMA_BADR;
__RW __u32 DMA_LEN;
__RW __u32 DMA_HPTR;
__RW __u32 DMA_SPTR;
__RW __u32 DMA_SPN;
__RW __u32 DMA_SHN;
} P11_LPVAD_TypeDef;
#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x14, 0x00))
#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
//............. 0x1500 - 0x16ff............ for crossbar
#include "p11_io_omap.h"
#include "p11_io_imap.h"
//............. 0x1700 - 0x18ff............ for gp timer
typedef struct {
__RW __u32 CON;
__RW __u32 CNT;
__RW __u32 PRD;
__RW __u32 PWM;
} P11_GPTMR_TypeDef;
#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x17, 0x00))
#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x00))
#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
#endif

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include_lib/driver/cpu/br28/asm/power/p2m_msg.h
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#ifndef __P2M_MSG_H__
#define __P2M_MSG_H__
//p2m用户消息实例
enum {
P2M_MSG_ACK = BIT(0),
P2M_MSG_TEST = BIT(1),
P2M_MSG_COMMOM = BIT(2),
P2M_MSG_CTMU = BIT(3),
P2M_MSG_SENSOR = BIT(4),
P2M_MSG_VAD = BIT(5),
};
//测试
struct p2m_msg_test {
u8 dat;
};
//测试
struct p2m_msg_ack {
u8 dat;
};
//公共消息
struct p2m_msg_common {
u8 dat;
};
//触摸消息
struct p2m_msg_ctmu {
u8 dat;
};
//vad
struct p2m_msg_vad {
u8 dat;
};
//p2m用户消息格式
struct p2m_msg_head {
u16 type :
MSG_TYPE_BIT_LEN;
u16 len :
MSG_PARAM_BIT_LEN;
u8 index :
MSG_INDEX_BIT;
u8 ack :
MSG_ACK_BIT;
} __attribute__((packed));
struct p2m_msg {
struct p2m_msg_head head;
union {
struct p2m_msg_ack ack;
struct p2m_msg_test test;
struct p2m_msg_common com;
struct p2m_msg_ctmu ctmu;
struct p2m_msg_vad vad;
} u;
} __attribute__((packed));
//p2m用户消息对应处理
struct p2m_msg_handler {
u8 type;
void (*handler)(struct p2m_msg *);
};
#define REGISTER_P2M_MSG_HANDLER(_type, fn, pri) \
const struct p2m_msg_handler _##fn sec(.p2m_msg_handler)= { \
.type = _type, \
.handler = fn, \
}
extern struct p2m_msg_handler p2m_msg_handler_begin[];
extern struct p2m_msg_handler p2m_msg_handler_end[];
#define list_for_each_p2m_msg_handler(p) \
for (p = p2m_msg_handler_begin; p < p2m_msg_handler_end; p++)
int p2m_get_msg(int len, struct p2m_msg *msg);
int p2m_post_msg(int len, struct p2m_msg *msg);
int p2m_post_sync_msg(int len, struct p2m_msg *msg, u8 abandon, int timeout);
#endif

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include_lib/driver/cpu/br28/asm/power/p33.h
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/*********************************************************************************************
* Filename : p33.h
* Description :
* Author : Bingquan
* Email : caibingquan@zh-jieli.com
* Last modifiled : 2019-12-09 10:42
* Copyright:(c)JIELI 2011-2019 @ , All Rights Reserved.
*********************************************************************************************/
#ifndef __P33_H__
#define __P33_H__
#include "p33_sfr.h"
#include "p33_app.h"
#include "p33_io_app.h"
#include "rtc_app.h"
#endif

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include_lib/driver/cpu/br28/asm/power/p33_app.h
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#ifndef __P33_APP_H__
#define __P33_APP_H__
//ROM
u8 p33_buf(u8 buf);
// void p33_xor_1byte(u16 addr, u8 data0);
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
// void p33_and_1byte(u16 addr, u8 data0);
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
//#define p33_and_1byte(addr, data0) addr &= (data0)
// void p33_or_1byte(u16 addr, u8 data0);
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
// #define p33_or_1byte(addr, data0) addr |= (data0)
// void p33_tx_1byte(u16 addr, u8 data0);
#define p33_tx_1byte(addr, data0) addr = data0
// u8 p33_rx_1byte(u16 addr);
#define p33_rx_1byte(addr) addr
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xff << (len))) << (start))) | \
(((data) & (~(0xff << (len)))) << (start)))
#define P33_CON_GET(sfr) sfr
#define P33_ANA_CHECK(reg) (((reg & reg##_MASK) == reg##_RV) ? 1:0)
#if 1
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
p33_or_1byte(reg, (data)); \
} else { \
p33_and_1byte(reg, ~(data)); \
} \
}
#else
#define p33_fast_access(reg, data, en) \
{ \
if (en) { \
reg |= (data); \
} else { \
reg &= ~(data); \
} \
}
#endif
//
//
// for p33_analog.doc
//
//
//
/************************P3_ANA_CON0*****************************/
#define VDD13TO12_SYS_EN(en) P33_CON_SET(P3_ANA_CON0, 0, 1, en)
#define VDD13TO12_RVD_EN(en) P33_CON_SET(P3_ANA_CON0, 1, 1, en)
#define LDO13_EN(en) P33_CON_SET(P3_ANA_CON0, 2, 1, en)
#define DCDC13_EN(en) P33_CON_SET(P3_ANA_CON0, 3, 1, en)
#define GET_DCDC13_EN() ((P33_CON_GET(P3_ANA_CON0) & BIT(3)) ? 1:0)
#define PVDD_EN(en) P33_CON_SET(P3_ANA_CON0, 4, 1, en)
#define MVIO_VBAT_EN(en) P33_CON_SET(P3_ANA_CON0, 5, 1, en)
#define MVIO_VPWR_EN(en) P33_CON_SET(P3_ANA_CON0, 6, 1, en)
#define MBG_EN(en) P33_CON_SET(P3_ANA_CON0, 7, 1, en)
#define P3_ANA_CON0_MASK 0b11110011
#define P3_ANA_CON0_RV 0b11110011
/************************P3_ANA_KEEP*****************************/
#define CLOSE_ANA_KEEP() P33_CON_SET(P3_ANA_KEEP, 0, 8, 0)
#define P3_ANA_KEEP_MASK 0b11111111
#define P3_ANA_KEEP_RV 0b00000000
/************************P3_ANA_KEEP1****************************/
#define VIO2_EN_KEEP(en) P33_CON_SET(P3_ANA_KEEP1, 0, 1, en)
#define P3_ANA_KEEP1_MASK 0b00000001
#define P3_ANA_KEEP1_RV 0b00000000
/**************************P3_ANA_CON1*********************************/
#define RVDD_BYPASS_EN(en) P33_CON_SET(P3_ANA_CON1, 0, 1, en)
#define WVDD_SHORT_RVDD(en) P33_CON_SET(P3_ANA_CON1, 1, 1, en)
#define WVDD_SHORT_SVDD(en) P33_CON_SET(P3_ANA_CON1, 2, 1, en)
#define WLDO06_EN(en) P33_CON_SET(P3_ANA_CON1, 3, 1, en)
#define WLDO06_OE(en) P33_CON_SET(P3_ANA_CON1, 4, 1, en)
#define EVD_EN(en) P33_CON_SET(P3_ANA_CON1, 5, 1, en)
#define EVD_SHORT_PB8(en) P33_CON_SET(P3_ANA_CON1, 6, 1, en)
#define PVD_SHORT_PB8(en) P33_CON_SET(P3_ANA_CON1, 7, 1, en)
#define P3_ANA_CON1_MASK 0b10011111
#define P3_ANA_CON1_RV 0b00000100
/************************P3_ANA_CON2*****************************/
#define VCM_DET_EN(en) P33_CON_SET(P3_ANA_CON2, 3, 1, en)
#define MVIO_VBAT_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 4, 1, en)
#define MVIO_VPWR_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 5, 1, en)
#define DCVD_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 6, 1, en)
#define CURRENT_LIMIT_DISABLE() (P3_ANA_CON2 &= ~(BIT(4) | BIT(5) | BIT(6)))
#define P3_ANA_CON2_MASK 0b01110000
#define P3_ANA_CON2_RV 0b01110000
/************************P3_ANA_CON3*****************************/
#define MVBG_SEL(en) P33_CON_SET(P3_ANA_CON3, 0, 4, en)
#define MVBG_GET() (P33_CON_GET(P3_ANA_CON3) & 0x0f)
#define WVBG_SEL(en) P33_CON_SET(P3_ANA_CON3, 4, 4, en)
#define P3_ANA_CON3_MASK 0b00000000
#define P3_ANA_CON3_RV 0b00000000
/************************P3_ANA_CON4*****************************/
#define PMU_DET_EN(en) P33_CON_SET(P3_ANA_CON4, 0, 1, en)
#define ADC_CHANNEL_SEL(ch) P33_CON_SET(P3_ANA_CON4, 1, 4, ch)
#define PMU_DET_BG_BUF_EN(en) P33_CON_SET(P3_ANA_CON4, 5, 1, en)
#define VBG_TEST_EN(en) P33_CON_SET(P3_ANA_CON4, 6, 1, en)
#define VBG_TEST_SEL(en) P33_CON_SET(P3_ANA_CON4, 7, 1, en)
#define P3_ANA_CON4_MASK 0b11100001
#define P3_ANA_CON4_RV 0b11100001
/************************P3_ANA_CON5*****************************/
//vddiom_lev
enum {
VDDIOM_VOL_20V = 0,
VDDIOM_VOL_22V,
VDDIOM_VOL_24V,
VDDIOM_VOL_26V,
VDDIOM_VOL_28V,
VDDIOM_VOL_30V, //default
VDDIOM_VOL_32V,
VDDIOM_VOL_34V,
};
#define VDDIOM_VOL_SEL(lev) P33_CON_SET(P3_ANA_CON5, 0, 3, lev)
#define GET_VDDIOM_VOL() (P33_CON_GET(P3_ANA_CON5) & 0x7)
//vddiow_lev
enum {
VDDIOW_VOL_20V = 0,
VDDIOW_VOL_22V,
VDDIOW_VOL_24V,
VDDIOW_VOL_26V,
VDDIOW_VOL_28V,
VDDIOW_VOL_30V,
VDDIOW_VOL_32V,
VDDIOW_VOL_34V,
};
#define VDDIOW_VOL_SEL(lev) P33_CON_SET(P3_ANA_CON5, 3, 3, lev)
#define GET_VDDIOW_VOL() (P33_CON_GET(P3_ANA_CON5)>>3 & 0x7)
#define VDDIO_HD_SEL(cur) P33_CON_SET(P3_ANA_CON5, 6, 2, cur)
#define P3_ANA_CON5_MASK 0b11000000
#define P3_ANA_CON5_RV 0b01000000
/************************P3_ANA_CON6*****************************/
#define VDC13_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON6, 0, 4, sel)
//Macro for VDC13_VOL_SEL
enum {
VDC13_VOL_SEL_100V = 0,
VDC13_VOL_SEL_105V,
VDC13_VOL_SEL_1075V,
VDC13_VOL_SEL_110V,
VDC13_VOL_SEL_1125V,
VDC13_VOL_SEL_115V,
VDC13_VOL_SEL_1175V,
VDC13_VOL_SEL_120V,
VDC13_VOL_SEL_1225V,
VDC13_VOL_SEL_125V,
VDC13_VOL_SEL_1275V,
VDC13_VOL_SEL_130V,
VDC13_VOL_SEL_1325V,
VDC13_VOL_SEL_135V,
VDC13_VOL_SEL_1375V,
VDC13_VOL_SEL_140V,
};
#define VD13_DEFAULT_VOL VDC13_VOL_SEL_125V
#define GET_VD13_VOL_SEL() (P33_CON_GET(P3_ANA_CON6) & 0xf)
#define VD13_HD_SEL(sel) P33_CON_SET(P3_ANA_CON6, 4, 2, sel)
#define VD13_CAP_EN(en) P33_CON_SET(P3_ANA_CON6, 6, 1, en)
#define VD13_DESHOT_EN(en) P33_CON_SET(P3_ANA_CON6, 7, 1, en)
#define P3_ANA_CON6_MASK 0b11111111
#define P3_ANA_CON6_RV 0b11011010
/************************P3_ANA_CON7*****************************/
#define BTDCDC_PFM_MODE(en) P33_CON_SET(P3_ANA_CON7, 0, 1, en)
#define GET_BTDCDC_PFM_MODE() (P33_CON_GET(P3_ANA_CON7) & BIT(0) ? 1 : 0)
#define BTDCDC_RAMP_SHORT(en) P33_CON_SET(P3_ANA_CON7, 1, 1, en)
#define BTDCDC_V17_TEST_OE(en) P33_CON_SET(P3_ANA_CON7, 2, 1, en);
#define BTDCDC_DUTY_SEL(sel) P33_CON_SET(P3_ANA_CON7, 3, 2, sel)
#define BTDCDC_OSC_SEL(sel) P33_CON_SET(P3_ANA_CON7, 5, 3, sel)
//Macro for BTDCDC_OSC_SEL
enum {
BTDCDC_OSC_SEL0520KHz = 0,
BTDCDC_OSC_SEL0762KHz,
BTDCDC_OSC_SEL0997KHz,
BTDCDC_OSC_SEL1220KHz,
BTDCDC_OSC_SEL1640KHz,
BTDCDC_OSC_SEL1840KHz,
BTDCDC_OSC_SEL2040KHz,
BTDCDC_OSC_SEL2220MHz,
};
#define P3_ANA_CON7_MASK 0b11111111
#define P3_ANA_CON7_RV 0b01001001
/************************P3_ANA_CON8*****************************/
#define BTDCDC_V21_RES_S(sel) P33_CON_SET(P3_ANA_CON8, 0, 2, sel)
#define BTDCDC_DT_S(sel) P33_CON_SET(P3_ANA_CON8, 2, 2, sel)
#define BTDCDC_ISENSE_HD(sel) P33_CON_SET(P3_ANA_CON8, 4, 2, sel)
#define BTDCDC_COMP_HD(sel) P33_CON_SET(P3_ANA_CON8, 6, 2, sel)
#define P3_ANA_CON8_MASK 0b11111111
#define P3_ANA_CON8_RV 0b01100110
/************************P3_ANA_CON9*****************************/
#define BTDCDC_NMOS_S(sel) P33_CON_SET(P3_ANA_CON9, 1, 3, sel)
#define BTDCDC_PMOS_S(sel) P33_CON_SET(P3_ANA_CON9, 5, 3, sel)
#define P3_ANA_CON9_MASK 0b11101110
#define P3_ANA_CON9_RV 0b01101110
/************************P3_ANA_CON10*****************************/
#define BTDCDC_OSC_TEST_OE(en) P33_CON_SET(P3_ANA_CON10, 7, 1, en)
#define BTDCDC_HD_BIAS_SEL(sel) P33_CON_SET(P3_ANA_CON10, 5, 2, sel)
#define BTDCDC_CLK_SEL(sel) P33_CON_SET(P3_ANA_CON10, 4, 1, sel)
#define GET_BTDCDC_CLK_SEL() (P33_CON_GET(P3_ANA_CON10) & BIT(4) ? 1 : 0)
#define BTDCDC_ZCD_RES(sel) P33_CON_SET(P3_ANA_CON10, 2, 2, sel)
#define BTDCDC_ZCD_EN(en) P33_CON_SET(P3_ANA_CON10, 0, 1, en)
#define P3_ANA_CON10_MASK 0b11111101
#define P3_ANA_CON10_RV 0b00110001
/************************P3_ANA_CON11*****************************/
#define SYSVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON11, 0, 4, sel)
//Macro for SYSVDD_VOL_SEL
enum {
SYSVDD_VOL_SEL_081V = 0,
SYSVDD_VOL_SEL_084V,
SYSVDD_VOL_SEL_087V,
SYSVDD_VOL_SEL_090V,
SYSVDD_VOL_SEL_093V,
SYSVDD_VOL_SEL_096V,
SYSVDD_VOL_SEL_099V,
SYSVDD_VOL_SEL_102V,
SYSVDD_VOL_SEL_105V,
SYSVDD_VOL_SEL_108V,
SYSVDD_VOL_SEL_111V,
SYSVDD_VOL_SEL_114V,
SYSVDD_VOL_SEL_117V,
SYSVDD_VOL_SEL_120V,
SYSVDD_VOL_SEL_123V,
SYSVDD_VOL_SEL_126V,
};
#define SYSVDD_DEFAULT_VOL SYSVDD_VOL_SEL_105V
#define GET_SYSVDD_VOL_SEL() (P33_CON_GET(P3_ANA_CON11) & 0xf)
#define SYSVDD_VOL_HD_SEL(sel) P33_CON_SET(P3_ANA_CON11, 4, 2, sel)
#define SYSVDD_CAP_EN(en) P33_CON_SET(P3_ANA_CON11, 6, 1, en)
#define P3_ANA_CON11_MASK 0b01110000
#define P3_ANA_CON11_RV 0b00010000
/************************P3_ANA_CON12*****************************/
#define RVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON12, 0, 4, sel)
//Macro for SYSVDD_VOL_SEL
enum {
RVDD_VOL_SEL_081V = 0,
RVDD_VOL_SEL_084V,
RVDD_VOL_SEL_087V,
RVDD_VOL_SEL_090V,
RVDD_VOL_SEL_093V,
RVDD_VOL_SEL_096V,
RVDD_VOL_SEL_099V,
RVDD_VOL_SEL_102V,
RVDD_VOL_SEL_105V,
RVDD_VOL_SEL_108V,
RVDD_VOL_SEL_111V,
RVDD_VOL_SEL_114V,
RVDD_VOL_SEL_117V,
RVDD_VOL_SEL_120V,
RVDD_VOL_SEL_123V,
RVDD_VOL_SEL_126V,
};
#define RVDD_DEFAULT_VOL RVDD_VOL_SEL_105V
#define GET_RVDD_VOL_SEL() (P33_CON_GET(P3_ANA_CON12) & 0xf)
#define RVDD_VOL_HD_SEL(en) P33_CON_SET(P3_ANA_CON12, 4, 2, en)
#define RVDD_CAP_EN(en) P33_CON_SET(P3_ANA_CON12, 6, 1, en)
#define P3_ANA_CON12_MASK 0b01110000
#define P3_ANA_CON12_RV 0b00010000
/************************P3_ANA_CON13*****************************/
#define WVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON13, 0, 4, sel)
//Macro for WVDD_VOL_SEL
enum {
WVDD_VOL_SEL_050V = 0,
WVDD_VOL_SEL_055V,
WVDD_VOL_SEL_060V,
WVDD_VOL_SEL_065V,
WVDD_VOL_SEL_070V,
WVDD_VOL_SEL_075V,
WVDD_VOL_SEL_080V,
WVDD_VOL_SEL_085V,
WVDD_VOL_SEL_090V,
WVDD_VOL_SEL_095V,
WVDD_VOL_SEL_100V,
WVDD_VOL_SEL_105V,
WVDD_VOL_SEL_110V,
WVDD_VOL_SEL_115V,
WVDD_VOL_SEL_120V,
WVDD_VOL_SEL_125V,
};
#define WVDD_VOL_MIN 500
#define VWDD_VOL_MAX 1250
#define WVDD_VOL_TRIM 800//mv
#define WVDD_VOL_STEP 50
#define WVDD_LEVEL_MAX 0xf
#define WVDD_LEVEL_ERR 0xff
#define WVDD_VOL_TRIM_LED 850
#define WVDD_LEVEL_DEFAULT ((WVDD_VOL_TRIM-WVDD_VOL_MIN)/WVDD_VOL_STEP + 2)
#define WVDD_LOAD_EN(en) P33_CON_SET(P3_ANA_CON13, 4, 1, en)
#define WVDDIO_FBRES_AUTO(en) P33_CON_SET(P3_ANA_CON13, 6, 1, en)
#define WVDDIO_FBRES_SEL_W(en) P33_CON_SET(P3_ANA_CON13, 7, 1, en)
#define P3_ANA_CON13_MASK 0b11110000
#define P3_ANA_CON13_RV 0b10000000
/************************P3_ANA_CON14*****************************/
#define RVD2PVD_SHORT_EN(en) P33_CON_SET(P3_ANA_CON14, 4, 1, en)
#define GET_RVD2PVD_SHORT_EN() (P33_CON_GET(P3_ANA_CON14) & BIT(4) ? 1:0)
#define PVD_DEUDSHT_EN(en) P33_CON_SET(P3_ANA_CON14, 3, 1, en)
#define GET_PVD_DEUDST_EN() ((P33_CON_GET(P3_ANA_CON14) & BIT(3)) ? 1:0)
#define PVD_HD_SEL(sel) P33_CON_SET(P3_ANA_CON14, 0, 3, sel)
#define GET_PVD_HD_SEL() (P33_CON_GET(P3_ANA_CON14) & 0x7)
#define P3_ANA_CON14_MASK 0b00011111
#define P3_ANA_CON14_RV 0b00000100
/************************P3_ANA_CON15*****************************/
#define EVD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON15, 0, 2, sel)
enum {
EVD_VOL_SEL_100V = 0,
EVD_VOL_SEL_105V,
EVD_VOL_SEL_110V,
EVD_VOL_SEL_115V,
};
#define EVD_HD_SEL(sel) P33_CON_SET(P3_ANA_CON15, 2, 2, sel)
#define EVD_CAP_EN(en) P33_CON_SET(P3_ANA_CON15, 4, 1, en)
#define P3_ANA_CON15_MASK 0b00001100
#define P3_ANA_CON15_RV 0b00000100
/************************P3_PVDD0_AUTO*****************************/
#define PVDD_LEVEL_LOW(sel) P33_CON_SET(P3_PVDD0_AUTO, 0, 4, sel)
#define GET_PVDD_LEVEL_LOW() (P33_CON_GET(P3_PVDD0_AUTO) & 0xf)
#define PVDD_LEVEL_AUTO(en) P33_CON_SET(P3_PVDD0_AUTO, 4, 1, en)
#define GET_PVDD_LEVEL_AUTO() ((P33_CON_GET(P3_PVDD0_AUTO) & BIT(4)) ? 1:0)
#define PVDD_AUTO_PRD(sel) P33_CON_SET(P3_PVDD0_AUTO, 5, 3, sel)
#define GET_PVDD_AUTO_PRD() ((P33_CON_GET(P3_PVDD0_AUTO) & (0x7<<5)) >> 5)
enum {
PVDD_VOL_SEL_050V = 0,
PVDD_VOL_SEL_055V,
PVDD_VOL_SEL_060V,
PVDD_VOL_SEL_065V,
PVDD_VOL_SEL_070V,
PVDD_VOL_SEL_075V,
PVDD_VOL_SEL_080V,
PVDD_VOL_SEL_085V,
PVDD_VOL_SEL_090V,
PVDD_VOL_SEL_095V,
PVDD_VOL_SEL_100V,
PVDD_VOL_SEL_105V,
PVDD_VOL_SEL_110V,
PVDD_VOL_SEL_115V,
PVDD_VOL_SEL_120V,
PVDD_VOL_SEL_125V,
};
#define PVDD_VOL_MIN 500
#define PVDD_VOL_MAX 1250
#define PVDD_VOL_STEP 50
#define PVDD_LEVEL_MAX 0xf
#define PVDD_LEVEL_ERR 0xff
#define PVDD_LEVEL_DEFAULT 0xc
#define PVDD_LEVEL_REF PVDD_VOL_SEL_115V
#define PVDD_VOL_REF 1150//mV
#define PVDD_VOL_CLOCK_SET 1200
#define PVDD_VOL_HIGH_NOW 1100
#ifdef CONFIG_WATCH_CASE_ENABLE
#define PVDD_LEVEL_SLEEP PVDD_VOL_SEL_090V
#define PVDD_VOL_SLEEP 900
#else
#define PVDD_LEVEL_SLEEP PVDD_VOL_SEL_095V
#define PVDD_VOL_SLEEP 950
#endif
#define P3_PVDD0_AUTO_MASK 0b11110000
#define P3_PVDD0_AUTO_RV 0b01110000
/************************P3_PVDD1_AUTO*****************************/
#define PVDD_LEVEL_HIGH_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 8, (sel<<4)|sel);
#define PVDD_LEVEL_HIGH(sel) P33_CON_SET(P3_PVDD1_AUTO, 4, 4, sel)
#define GET_PVDD_LEVEL_HIGH() ((P33_CON_GET(P3_PVDD1_AUTO) & 0xf0)>>4)
#define PVDD_LEVEL_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 4, sel)
#define GET_PVDD_LEVEL_NOW() (P33_CON_GET(P3_PVDD1_AUTO) & 0x0f)
#define P3_PVDD1_AUTO_MASK 0b00000000
#define P3_PVDD1_AUTO_RV 0b00000000
/************************P3_PVDD2_AUTO*****************************/
#define GET_PVDD_DRV_AUTO() (P33_CON_GET(P3_PVDD2_AUTO) & BIT(0))
#define P3_PVDD2_AUTO_MASK 0b00000001
#define P3_PVDD2_AUTO_RV 0b00000001
/************************P3_CHG_CON0*****************************/
#define CHARGE_EN(en) P33_CON_SET(P3_CHG_CON0, 0, 1, en)
#define CHGGO_EN(en) P33_CON_SET(P3_CHG_CON0, 1, 1, en)
#define IS_CHARGE_EN() ((P33_CON_GET(P3_CHG_CON0) & BIT(0)) ? 1: 0 )
#define CHG_HV_MODE(mode) P33_CON_SET(P3_CHG_CON0, 2, 1, mode)
#define CHG_TRICKLE_EN(en) P33_CON_SET(P3_CHG_CON0, 3, 1, en)
#define CHG_CCLOOP_EN(en) P33_CON_SET(P3_CHG_CON0, 4, 1, en)
#define CHG_VILOOP_EN(en) P33_CON_SET(P3_CHG_CON0, 5, 1, en)
#define CHG_VINLOOP_SLT(sel) P33_CON_SET(P3_CHG_CON0, 6, 1, sel)
#define CHG_SEL_CHG_FULL 0
#define CHG_SEL_VBAT_DET 1
#define CHG_SSEL(sel) P33_CON_SET(P3_CHG_CON0, 7, 1, sel)
#define P3_CHG_CON0_MASK 0
#define P3_CHG_CON0_RV 0
/************************P3_CHG_CON1*****************************/
#define CHARGE_FULL_V_SEL(a) P33_CON_SET(P3_CHG_CON1, 0, 4, a)
#define CHARGE_mA_SEL(a) P33_CON_SET(P3_CHG_CON1, 4, 4, a)
#define P3_CHG_CON1_MASK 0
#define P3_CHG_CON1_RV 0
/************************P3_CHG_CON2*****************************/
#define CHARGE_FULL_mA_SEL(a) P33_CON_SET(P3_CHG_CON2, 4, 3, a)
enum {
CHARGE_DET_VOL_365V,
CHARGE_DET_VOL_375V,
CHARGE_DET_VOL_385V,
CHARGE_DET_VOL_395V,
};
#define CHARGE_DET_VOL(a) P33_CON_SET(P3_CHG_CON2, 1, 2, a)
#define CHARGE_DET_EN(en) P33_CON_SET(P3_CHG_CON2, 0, 1, en)
#define P3_CHG_CON2_MASK 0
#define P3_CHG_CON2_RV 0
/************************P3_L5V_CON0*****************************/
#define L5V_LOAD_EN(a) P33_CON_SET(P3_L5V_CON0, 0, 1, a)
#define L5V_IO_MODE(a) P33_CON_SET(P3_L5V_CON0, 2, 1, a)
#define IS_L5V_LOAD_EN() ((P33_CON_GET(P3_L5V_CON0) & BIT(0)) ? 1: 0 )
#define GET_L5V_RES_DET_S_SEL() (P33_CON_GET(P3_L5V_CON1) & 0x03)
#define P3_L5V_CON0_MASK 0
#define P3_L5V_CON0_RV 0
/************************P3_L5V_CON1*****************************/
#define L5V_RES_DET_S_SEL(a) P33_CON_SET(P3_L5V_CON1, 0, 2, a)
#define P3_L5V_CON1_MASK 0
#define P3_L5V_CON1_RV 0
/************************P3_VLVD_CON*****************************/
#define P33_VLVD_EN(en) P33_CON_SET(P3_VLVD_CON, 0, 1, en)
#define GET_VLVD_EN() (P33_CON_GET(P3_VLVD_CON) & BIT(0))
#define P33_VLVD_PS(en) P33_CON_SET(P3_VLVD_CON, 1, 1, en)
#define P33_VLVD_OE(en) P33_CON_SET(P3_VLVD_CON, 2, 1, en)
#define GET_VLVD_OE() ((P33_CON_GET(P3_VLVD_CON) & BIT(2)) ? 1:0)
#define VLVD_SEL(lev) P33_CON_SET(P3_VLVD_CON, 3, 3, lev)
#define GET_VLVD_SEL() ((P33_CON_GET(P3_VLVD_CON) & (0x7<<3))>>3)
//Macro for VLVD_SEL
enum {
VLVD_SEL_18V = 0,
VLVD_SEL_19V,
VLVD_SEL_20V,
VLVD_SEL_21V,
VLVD_SEL_22V,
VLVD_SEL_23V,
VLVD_SEL_24V,
VLVD_SEL_25V,
};
#define VLVD_PND_CLR() P33_CON_SET(P3_VLVD_CON, 6, 1, 1)
#define VLVD_PND() ((P33_CON_GET(P3_VLVD_CON) & BIT(7)) ? 1 : 0)
#define P3_VLVD_CON_MASK 0
#define P3_VLVD_CON_RV 0
/************************P3_VLVD_FLT*****************************/
#define VLVD_FLT(sel) P33_CON_SET(P3_VLVD_FLT, 0, 2, sel);
#define P3_VLVD_FLT_MASK 0b00000011
#define P3_VLVD_FLT_RV 0b00000010
/************************P3_RST_CON0*****************************/
#define DPOR_MASK(en) P33_CON_SET(P3_RST_CON0, 0, 1, en)
#define VLVD_RST_EN(en) P33_CON_SET(P3_RST_CON0, 2, 1, en)
#define VLVD_WKUP_EN(en) P33_CON_SET(P3_RST_CON0, 3, 1, en)
#define PPOR_MASK(en) P33_CON_SET(P3_RST_CON0, 4, 1, en)
#define P11_TO_P33_RST_MASK(en) P33_CON_SET(P3_RST_CON0, 5, 1, en)
#define DVDDOK_OE(en) P33_CON_SET(P3_RST_CON0, 6, 1, en)
#define PVDDOK_OE(en) P33_CON_SET(P3_RST_CON0, 7, 1, en)
#define P3_RST_CON0_MASK 0b11111101
#define P3_RST_CON0_RV 0b00000100
/************************P3_LRC_CON0*****************************/
#define RC32K_EN(en) P33_CON_SET(P3_LRC_CON0, 0, 1, en)
#define RC32K_RN_TRIM(en) P33_CON_SET(P3_LRC_CON0, 1, 1, en)
#define RC32K_RPPS_SEL(sel) P33_CON_SET(P3_LRC_CON0, 4, 2, sel)
#define P3_LRC_CON0_MASK 0b00110011
#define P3_LRC_CON0_RV 0b00100001
/************************P3_LRC_CON1*****************************/
#define RC32K_PNPS_SEL(sel) P33_CON_SET(P3_LRC_CON1, 0, 2, sel)
#define RC32K_CAP_SEL(sel) P33_CON_SET(P3_LRC_CON1, 4, 3, sel)
#define CLOSE_LRC() P33_CON_SET(P3_LRC_CON0, 0, 8, 0);\
P33_CON_SET(P3_LRC_CON1, 0, 8, 0)
#define P3_LRC_CON1_MASK 0b01110011
#define P3_LRC_CON1_RV 0b01000001
/************************P3_CLK_CON0*****************************/
#define RC_250K_EN(a) P33_CON_SET(P3_CLK_CON0, 0, 1, a)
#define P3_CLK_CON0_MASK 0b00000001
#define P3_CLK_CON0_RV 0b00000000
/************************P3_VLD_KEEP*****************************/
#define RTC_WKUP_KEEP(a) P33_CON_SET(P3_VLD_KEEP, 1, 1, a)
#define P33_WKUP_P11_EN(a) P33_CON_SET(P3_VLD_KEEP, 2, 1, a)
#define P3_VLD_KEEP_MASK 0b00000110
#define P3_VLD_KEEP_RV 0b00000110
/************************P3_PMU_CON0*****************************/
#define GET_P33_SYS_POWER_FLAG() ((P33_CON_GET(P3_PMU_CON0) & BIT(7)) ? 1 : 0)
#define P33_SYS_POWERUP_CLEAR() P33_CON_SET(P3_PMU_CON0, 6, 1, 1);
#define P3_PMU_CON0_MASK 0b00000000
#define P3_PMU_CON0_RV 0b00000000
/************************P3_PMU_DBG_CON*****************************/
#define P3_PMU_DBG_CON_MASK 0b00000000
#define P3_PMU_DBG_CON_RV 0b00000000
/************************P3_IOV2_CON*****************************/
#define GET_IOV2_VOL() ((P33_CON_GET(P3_IOV2_CON) & (0x7<<3)) >> 3)
#define GET_IOV2_IFULL() ((P33_CON_GET(P3_IOV2_CON) & BIT(2)) ? 1:0)
#define GET_IOV2_BYPASS() ((P33_CON_GET(P3_IOV2_CON) & BIT(1)) ? 1:0)
#define GET_IOV2_EN() ((P33_CON_GET(P3_IOV2_CON) & BIT(0)) ? 1:0)
#define P3_IOV2_CON_MASK 0
#define P3_IOV2_CON_RV 0
/************************P3_RVD_CON*****************************/
#define RVDD_CMP_EN(en) P33_CON_SET(P3_RVD_CON, 4, 1, en)
#define PVDD_DCDC_LEV_SEL(sel) P33_CON_SET(P3_RVD_CON, 0, 4, sel)
#define GET_PVDD_DCDC_LEV_SEL() (P33_CON_GET(P3_RVD_CON) & 0xf)
#define P3_RVD_CON_MASK 0b00000000
#define P3_RVD_CON_RV 0b00000000
/************************P3_CHG_WKUP*****************************/
#define CHARGE_LEVEL_DETECT_EN(a) P33_CON_SET(P3_CHG_WKUP, 0, 1, a)
#define CHARGE_EDGE_DETECT_EN(a) P33_CON_SET(P3_CHG_WKUP, 1, 1, a)
#define CHARGE_WKUP_SOURCE_SEL(a) P33_CON_SET(P3_CHG_WKUP, 2, 2, a)
#define CHARGE_WKUP_EN(a) P33_CON_SET(P3_CHG_WKUP, 4, 1, a)
#define CHARGE_WKUP_EDGE_SEL(a) P33_CON_SET(P3_CHG_WKUP, 5, 1, a)
#define CHARGE_WKUP_PND_CLR() P33_CON_SET(P3_CHG_WKUP, 6, 1, 1)
/************************P3_AWKUP_LEVEL*****************************/
#define CHARGE_FULL_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(2)) ? 1: 0)
#define LVCMP_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(1)) ? 1: 0)
#define LDO5V_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(0)) ? 1: 0)
/************************P3_ANA_READ*****************************/
#define CHARGE_FULL_FLAG_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(0)) ? 1: 0 )
#define LVCMP_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(1)) ? 1: 0 )
#define LDO5V_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(2)) ? 1: 0 )
//
//
// for ANA_control.doc
//
//
//
/************************P3_LS_XX*****************************/
#define PVDD_ANA_LAT_EN(en) \
if(en){ \
P3_LS_P11 = 0x01; \
P3_LS_P11 = 0x03; \
}else{ \
P3_LS_P11 = 0x0; \
}
#define DVDD_ANA_LAT_EN(en) \
if(en){ \
P3_LS_IO_DLY = 0x1; \
P3_LS_IO_ROM = 0x1; \
P3_LS_ADC = 0x1; \
P3_LS_AUDIO = 0x1; \
P3_LS_RF = 0x1; \
P3_LS_PLL = 0x1; \
P3_LS_IO_DLY = 0x3; \
P3_LS_IO_ROM = 0x3; \
P3_LS_ADC = 0x3; \
P3_LS_AUDIO = 0x3; \
P3_LS_RF = 0x3; \
P3_LS_PLL = 0x3; \
}else{ \
P3_LS_IO_DLY = 0x0; \
P3_LS_IO_ROM = 0x0; \
P3_LS_ADC = 0x0; \
P3_LS_AUDIO = 0x0; \
P3_LS_RF = 0x0; \
P3_LS_PLL = 0x0;\
}
#define DVDD_ANA_ROM_LAT_EN(en) \
if(en){ \
P3_LS_IO_ROM = 1; \
P3_LS_PLL = 1; \
P3_LS_RF = 1; \
P3_LS_IO_ROM = 3; \
P3_LS_PLL = 3; \
P3_LS_RF = 3; \
}else{ \
P3_LS_IO_ROM = 0; \
P3_LS_PLL = 0; \
P3_LS_RF = 0; \
}
//
//
// for reset_source.doc
//
//
//
/************************P3_PR_PWR*****************************/
#define P3_SOFT_RESET() P33_CON_SET(P3_PR_PWR, 4, 2, 3)
/************************P3_IVS_CLR*****************************/
#define P33_SF_KICK_START() P33_CON_SET(P3_IVS_CLR, 0, 8, 0b10101000)
/************************P3_RST_SRC*****************************/
#define GET_P33_SYS_RST_SRC() P33_CON_GET(P3_RST_SRC)
#endif

140
include_lib/driver/cpu/br28/asm/power/p33_io_app.h
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@ -1,140 +0,0 @@
#ifndef __P33_IO_APP_H__
#define __P33_IO_APP_H__
/*******************************************************************/
/*
*-------------------P3_WKUP_DLY
*/
#define P3_WKUP_DLY_SET(val) P33_CON_SET(P3_WKUP_DLY, 0, 3, val)
/*******************************************************************/
/*
*-------------------P3_PCNT_CON
*/
#define PCNT_PND_CLR() P33_CON_SET(P3_PCNT_CON, 6, 1, 1)
/*******************************************************************/
/*
*-------------------P3_PCNT_SET
*/
#define SET_EXCEPTION_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xb)
#define SET_ASSERT_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xc)
#define SET_XOSC_RESUME_ERR_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xd)
#define SET_LPTMR_TIMEOUT_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xe)
#define SET_LVD_FLAG(en) P33_CON_SET(P3_PCNT_SET0, 7, 1, en)
#define GET_EXCEPTION_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xb) ? 1 : 0)
#define GET_ASSERT_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xc) ? 1 : 0)
#define GET_XOSC_RESUME_ERR_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xd) ? 1 : 0)
#define GET_LPTMR_TIMEOUT_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xe) ? 1 : 0)
#define GET_LVD_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x80) == 0x80) ? 1 : 0)
#define SOFT_RESET_FLAG_CLEAR() (P33_CON_SET(P3_PCNT_SET0, 0, 8, 0))
/*******************************************************************/
/*
*-------------------P3_WKUP_XX
*/
#define MAX_WAKEUP_PORT 12 //最大同时支持数字io输入个数
#define MAX_WAKEUP_ANA_PORT 3 //最大同时支持模拟io输入个数
typedef enum {
RISING_EDGE = 0,
FALLING_EDGE,
BOTH_EDGE,
} POWER_WKUP_EDGE;
typedef enum {
PORT_FLT_NULL = 0,
PORT_FLT_256us,
PORT_FLT_512us,
PORT_FLT_1ms,
PORT_FLT_2ms,
PORT_FLT_4ms,
PORT_FLT_8ms,
PORT_FLT_16ms,
} POWER_WKUP_FLT;
//en
#define P33_SET_WKUP_EN(data) P33_CON_SET(P3_WKUP_EN0, 0, 8, data & 0xff); \
P33_CON_SET(P3_WKUP_EN1, 0, 8, (data >> 8) & 0xff)
#define P33_OR_WKUP_EN(data) p33_fast_access(P3_WKUP_EN0, data & 0xff, 1); \
p33_fast_access(P3_WKUP_EN1, (data >> 8) & 0xff, 1)
#define P33_AND_WKUP_EN(data) p33_fast_access(P3_WKUP_EN0, data & 0xff, 0); \
p33_fast_access(P3_WKUP_EN1, (data >> 8) & 0xff, 0)
//edge
#define P33_SET_WKUP_EDGE(data) P33_CON_SET(P3_WKUP_EDGE0, 0, 8, data & 0xff); \
P33_CON_SET(P3_WKUP_EDGE1, 0, 8, (data >> 8) & 0xff)
#define P33_OR_WKUP_EDGE(data) p33_fast_access(P3_WKUP_EDGE0, data & 0xff, 1); \
p33_fast_access(P3_WKUP_EDGE1, (data >> 8) & 0xff, 1)
#define P33_AND_WKUP_EDGE(data) p33_fast_access(P3_WKUP_EDGE0, data & 0xff, 0); \
p33_fast_access(P3_WKUP_EDGE1, (data >> 8) & 0xff, 0)
//cpnd
#define P33_SET_WKUP_CPND(data) p33_fast_access(P3_WKUP_CPND0, data & 0xff, 1); \
p33_fast_access(P3_WKUP_CPND1, (data >> 8) & 0xff, 1)
//pnd
#define P33_GET_WKUP_PND() (P33_CON_GET(P3_WKUP_PND0) | (P33_CON_GET(P3_WKUP_PND1)<<8))
//akwup_en
#define P33_SET_AWKUP_EN(data) P33_CON_SET(P3_AWKUP_EN, 0, 8, data & 0xff)
#define P33_OR_AWKUP_EN(data) p33_fast_access(P3_AWKUP_EN, data & 0xff, 1)
//awkup_p_pnd
#define P33_GET_AWKUP_P_PND() (P33_CON_GET(P3_AWKUP_P_PND))
//awkup_n_pnd
#define P33_GET_AWKUP_N_PND() (P33_CON_GET(P3_AWKUP_N_PND))
//awkup_p_cpnd
#define P33_SET_AWKUP_P_CPND(data) p33_fast_access(P3_AWKUP_P_CPND, data & 0xff, 1)
//awkup_n_cpnd
#define P33_SET_AWKUP_N_CPND(data) p33_fast_access(P3_AWKUP_N_CPND, data & 0xff, 1)
//awkup_p_ie
#define P33_SET_AWKUP_P_IE(data) P33_CON_SET(P3_AWKUP_P_IE, 0, 8, data & 0xff)
#define P33_OR_AWKUP_P_IE(data) p33_fast_access(P3_AWKUP_P_IE, data & 0xff, 1)
#define P33_AND_AWKUP_P_IE(data) p33_fast_access(P3_AWKUP_P_IE, data & 0xff, 0)
//awkup_n_ie
#define P33_SET_AWAKEUP_N_IE(data) P33_CON_SET(P3_AWKUP_N_IE, 0, 8, data & 0xff)
#define P33_OR_AWKUP_N_IE(data) p33_fast_access(P3_AWKUP_N_IE, data & 0xff, 1)
#define P33_AND_AWKUP_N_IE(data) p33_fast_access(P3_AWKUP_N_IE, data & 0xff, 0)
#define CLEAN_GPIO_WAKEUP_PENDING() P33_SET_AWKUP_P_CPND(0xff); \
P33_SET_AWKUP_N_CPND(0xff); \
P33_SET_WKUP_CPND(0xffff);
#define CLEAN_P33_WKUP_PENDING() P33_SET_AWKUP_P_CPND(0xff); \
P33_SET_AWKUP_N_CPND(0xff); \
P33_SET_WKUP_CPND(0xffff); \
VLVD_PND_CLR(); \
PCNT_PND_CLR()
enum {
P3_WKUP_SRC_PCNT_OVF = 0,
P3_WKUP_SRC_PORT_EDGE,
P3_WKUP_SRC_ANA_EDGE,
P3_WKUP_SRC_VDDIO_LVD = 4,
};
#define P33_GET_WKUP_SRC() P33_CON_GET(P3_WKUP_SRC)
#endif

249
include_lib/driver/cpu/br28/asm/power/p33_sfr.h
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@ -1,249 +0,0 @@
#ifndef __BR28_P33__
#define __BR28_P33__
////////////////////////////////
#ifdef PMU_SYSTEM
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
#else
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
#endif
#ifdef PMU_SYSTEM
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
#else
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
#endif
//===========
//===============================================================================//
//
//
//
//===============================================================================//
//............. 0x0000 - 0x000f............
#define P3_IOV2_CON P33_ACCESS(0x00)
//............. 0x0010 - 0x001f............ for analog others
#define P3_OSL_CON P33_ACCESS(0x10)
#define P3_VLVD_CON P33_ACCESS(0x11)
#define P3_RST_SRC P33_ACCESS(0x12)
#define P3_LRC_CON0 P33_ACCESS(0x13)
#define P3_LRC_CON1 P33_ACCESS(0x14)
#define P3_RST_CON0 P33_ACCESS(0x15)
#define P3_ANA_KEEP P33_ACCESS(0x16)
#define P3_VLD_KEEP P33_ACCESS(0x17)
#define P3_CLK_CON0 P33_ACCESS(0x18)
#define P3_ANA_READ P33_ACCESS(0x19)
#define P3_CHG_CON0 P33_ACCESS(0x1a)
#define P3_CHG_CON1 P33_ACCESS(0x1b)
#define P3_CHG_CON2 P33_ACCESS(0x1c)
#define P3_CHG_CON3 P33_ACCESS(0x1d)
//............. 0x0020 - 0x002f............ for PWM LED
//#define P3_PWM_CON0 P33_ACCESS(0x20)
//#define P3_PWM_CON1 P33_ACCESS(0x21)
//#define P3_PWM_CON2 P33_ACCESS(0x22)
//#define P3_PWM_CON3 P33_ACCESS(0x23)
//#define P3_PWM_BRI_PRDL P33_ACCESS(0x24)
//#define P3_PWM_BRI_PRDH P33_ACCESS(0x25)
//#define P3_PWM_BRI_DUTY0L P33_ACCESS(0x26)
//#define P3_PWM_BRI_DUTY0H P33_ACCESS(0x27)
//#define P3_PWM_BRI_DUTY1L P33_ACCESS(0x28)
//#define P3_PWM_BRI_DUTY1H P33_ACCESS(0x29)
//#define P3_PWM_PRD_DIVL P33_ACCESS(0x2a)
//#define P3_PWM_DUTY0 P33_ACCESS(0x2b)
//#define P3_PWM_DUTY1 P33_ACCESS(0x2c)
//#define P3_PWM_DUTY2 P33_ACCESS(0x2d)
//#define P3_PWM_DUTY3 P33_ACCESS(0x2e)
//#define P3_PWM_CNT_RD P33_ACCESS(0x2f)
//............. 0x0030 - 0x003f............ for PMU manager
#define P3_PMU_CON0 P33_ACCESS(0x30)
#define P3_SFLAG0 P33_ACCESS(0x38)
#define P3_SFLAG1 P33_ACCESS(0x39)
#define P3_SFLAG2 P33_ACCESS(0x3a)
#define P3_SFLAG3 P33_ACCESS(0x3b)
//#define P3_SFLAG4 P33_ACCESS(0x3c)
//#define P3_SFLAG5 P33_ACCESS(0x3d)
//#define P3_SFLAG6 P33_ACCESS(0x3e)
//#define P3_SFLAG7 P33_ACCESS(0x3f)
//............. 0x0040 - 0x004f............ for
#define P3_IVS_RD P33_ACCESS(0x40)
#define P3_IVS_SET P33_ACCESS(0x41)
#define P3_IVS_CLR P33_ACCESS(0x42)
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
#define P3_WKUP_DLY P33_ACCESS(0x45)
#define P3_VLVD_FLT P33_ACCESS(0x46)
#define P3_PINR_CON1 P33_ACCESS(0x47)
#define P3_PINR_CON P33_ACCESS(0x48)
#define P3_PCNT_CON P33_ACCESS(0x49)
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
#define P3_PVDD2_AUTO P33_ACCESS(0x4e)
//............. 0x0050 - 0x005f............ for port wake up
#define P3_WKUP_EN0 P33_ACCESS(0x50)
#define P3_WKUP_EN1 P33_ACCESS(0x51)
#define P3_WKUP_EDGE0 P33_ACCESS(0x52)
#define P3_WKUP_EDGE1 P33_ACCESS(0x53)
#define P3_WKUP_LEVEL0 P33_ACCESS(0x54)
#define P3_WKUP_LEVEL1 P33_ACCESS(0x55)
#define P3_WKUP_PND0 P33_ACCESS(0x56)
#define P3_WKUP_PND1 P33_ACCESS(0x57)
#define P3_WKUP_CPND0 P33_ACCESS(0x58)
#define P3_WKUP_CPND1 P33_ACCESS(0x59)
//............. 0x0060 - 0x006f............ for
#define P3_AWKUP_EN P33_ACCESS(0x60)
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
#define P3_AWKUP_INSEL P33_ACCESS(0x64)
#define P3_AWKUP_P_PND P33_ACCESS(0x65)
#define P3_AWKUP_N_PND P33_ACCESS(0x66)
#define P3_AWKUP_P_CPND P33_ACCESS(0x67)
#define P3_AWKUP_N_CPND P33_ACCESS(0x68)
//............. 0x0070 - 0x007f............ for power gate
//#define P3_PGDR_CON0 P33_ACCESS(0x70)
//#define P3_PGDR_CON1 P33_ACCESS(0x71)
#define P3_PGSD_CON P33_ACCESS(0x72)
//#define P3_PGFS_CON P33_ACCESS(0x73)
//............. 0x0080 - 0x008f............ for
#define P3_AWKUP_FLT0 P33_ACCESS(0x80)
#define P3_AWKUP_FLT1 P33_ACCESS(0x81)
#define P3_AWKUP_FLT2 P33_ACCESS(0x82)
#define P3_APORT_SEL0 P33_ACCESS(0x88)
#define P3_APORT_SEL1 P33_ACCESS(0x89)
#define P3_APORT_SEL2 P33_ACCESS(0x8a)
//............. 0x0090 - 0x009f............ for analog control
#define P3_ANA_CON0 P33_ACCESS(0x90)
#define P3_ANA_CON1 P33_ACCESS(0x91)
#define P3_ANA_CON2 P33_ACCESS(0x92)
#define P3_ANA_CON3 P33_ACCESS(0x93)
#define P3_ANA_CON4 P33_ACCESS(0x94)
#define P3_ANA_CON5 P33_ACCESS(0x95)
#define P3_ANA_CON6 P33_ACCESS(0x96)
#define P3_ANA_CON7 P33_ACCESS(0x97)
#define P3_ANA_CON8 P33_ACCESS(0x98)
#define P3_ANA_CON9 P33_ACCESS(0x99)
#define P3_ANA_CON10 P33_ACCESS(0x9a)
#define P3_ANA_CON11 P33_ACCESS(0x9b)
#define P3_ANA_CON12 P33_ACCESS(0x9c)
#define P3_ANA_CON13 P33_ACCESS(0x9d)
#define P3_ANA_CON14 P33_ACCESS(0x9e)
#define P3_ANA_CON15 P33_ACCESS(0x9f)
//............. 0x00a0 - 0x00af............
#define P3_PR_PWR P33_ACCESS(0xa0)
#define P3_L5V_CON0 P33_ACCESS(0xa1)
#define P3_L5V_CON1 P33_ACCESS(0xa2)
#define P3_LS_P11 P33_ACCESS(0xa4)
#define P3_RVD_CON P33_ACCESS(0xa7)
#define P3_WKUP_SRC P33_ACCESS(0xa8)
#define P3_PMU_DBG_CON P33_ACCESS(0xaa)
#define P3_ANA_KEEP1 P33_ACCESS(0xab)
//............. 0x00b0 - 0x00bf............ for EFUSE
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
#define P3_EFUSE_RDAT P33_ACCESS(0xb2)
#define P3_FUNC_EN P33_ACCESS(0xb8)
//............. 0x00c0 - 0x00cf............ for port input select
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
#define P3_PORT_SEL8 P33_ACCESS(0xc8)
#define P3_PORT_SEL9 P33_ACCESS(0xc9)
#define P3_PORT_SEL10 P33_ACCESS(0xca)
#define P3_PORT_SEL11 P33_ACCESS(0xcb)
#define P3_PORT_SEL12 P33_ACCESS(0xcc)
#define P3_PORT_SEL13 P33_ACCESS(0xcd)
#define P3_PORT_SEL14 P33_ACCESS(0xce)
#define P3_PORT_SEL15 P33_ACCESS(0xcf)
//............. 0x00d0 - 0x00df............
#define P3_LS_IO_DLY P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
#define P3_LS_ADC P33_ACCESS(0xd2)
#define P3_LS_AUDIO P33_ACCESS(0xd3)
#define P3_LS_RF P33_ACCESS(0xd4)
#define P3_LS_PLL P33_ACCESS(0xd5)
//===============================================================================//
//
// p33 rtcvdd
//
//===============================================================================//
//#define RTC_SFR_BEGIN 0x1000
//............. 0x0080 - 0x008f............ for RTC
#define R3_ALM_CON RTC_ACCESS((0x80))
#define R3_RTC_CON0 RTC_ACCESS((0x84))
#define R3_RTC_CON1 RTC_ACCESS((0x85))
#define R3_RTC_DAT0 RTC_ACCESS((0x86))
#define R3_RTC_DAT1 RTC_ACCESS((0x87))
#define R3_RTC_DAT2 RTC_ACCESS((0x88))
#define R3_RTC_DAT3 RTC_ACCESS((0x89))
#define R3_RTC_DAT4 RTC_ACCESS((0x8a))
#define R3_ALM_DAT0 RTC_ACCESS((0x8b))
#define R3_ALM_DAT1 RTC_ACCESS((0x8c))
#define R3_ALM_DAT2 RTC_ACCESS((0x8d))
#define R3_ALM_DAT3 RTC_ACCESS((0x8e))
#define R3_ALM_DAT4 RTC_ACCESS((0x8f))
//............. 0x0090 - 0x009f............ for PORT control
#define R3_WKUP_EN RTC_ACCESS((0x90))
#define R3_WKUP_EDGE RTC_ACCESS((0x91))
#define R3_WKUP_CPND RTC_ACCESS((0x92))
#define R3_WKUP_PND RTC_ACCESS((0x93))
#define R3_WKUP_FLEN RTC_ACCESS((0x94))
#define R3_PORT_FLT RTC_ACCESS((0x95))
#define R3_PR_IN RTC_ACCESS((0x98))
#define R3_PR_OUT RTC_ACCESS((0x99))
#define R3_PR_DIR RTC_ACCESS((0x9a))
#define R3_PR_DIE RTC_ACCESS((0x9b))
#define R3_PR_PU RTC_ACCESS((0x9c))
#define R3_PR_PD RTC_ACCESS((0x9d))
#define R3_PR_HD RTC_ACCESS((0x9e))
//............. 0x00a0 - 0x00af............ for system
#define R3_TIME_CON RTC_ACCESS((0xa0))
#define R3_TIME_CPND RTC_ACCESS((0xa1))
#define R3_TIME_PND RTC_ACCESS((0xa2))
#define R3_ADC_CON RTC_ACCESS((0xa4))
#define R3_OSL_CON RTC_ACCESS((0xa5))
#define R3_WKUP_SRC RTC_ACCESS((0xa8))
#define R3_RST_SRC RTC_ACCESS((0xa9))
#define R3_RST_CON RTC_ACCESS((0xab))
#define R3_CLK_CON RTC_ACCESS((0xac))
#endif

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include_lib/driver/cpu/br28/asm/power/power_api.h
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#ifndef __POWER_API_H__
#define __POWER_API_H__
#define PMU_NEW_FLOW 0
#define TRIM_WVDD BIT(0)
#define TRIM_PVDD BIT(1)
#define TRIM_IOVDD BIT(2)
//=========================电源参数配置==================================
struct low_power_param {
u8 config; //低功耗使能，蓝牙&&系统空闲可进入低功耗
u8 osc_type; //低功耗晶振类型，btosc/lrc
u32 btosc_hz; //蓝牙晶振频率
//vddiow_lev不需要配置，sleep、softoff模式会保持电压，除非配置使用nkeep_vddio(功耗相差不大)
u8 vddiom_lev; //vddiom
u8 vddiow_lev; //vddiow
u8 nkeep_vddio; //softoff模式下不保持vddio
u32 osc_delay_us; //低功耗晶振起振延时，为预留配置。
u8 rtc_clk; //rtc时钟源，softoff模式根据此配置是否保持住相应时钟
u8 lpctmu_en; //低功耗触摸，softoff模式根据此配置是否保持住该模块
u8 mem_init_con; //初始化ram电源
u8 mem_lowpower_con; //低功耗ram电源
u8 rvdd2pvdd; //低功耗外接dcdc
u8 pvdd_dcdc_port;
u8 lptmr_flow; //低功耗参数由用户配置
u32 t1;
u32 t2;
u32 t3_lrc;
u32 t4_lrc;
u32 t3_btosc;
u32 t4_btosc;
u8 flash_pg; //iomc: 外置flash power gate
u8 btosc_disable;
u8 delay_us;
u8 vddio_keep_type_pd; //sleep keep vddio使用类型
u8 vddio_keep_type_sf; //soff keep vddio使用类型
};
//config
#define SLEEP_EN BIT(0)
#define DEEP_SLEEP_EN BIT(1)
enum {
VDDIO_KEEP_TYPE_TRIM = 0,//vddio keep使用trim值：默认
VDDIO_KEEP_TYPE_PG, //vddio keep使用 mvvdio：功耗代价100ua
};
//osc_type
enum {
OSC_TYPE_LRC = 0,
OSC_TYPE_BT_OSC,
};
//DCVDD电源模式
enum {
PWR_LDO15,
PWR_DCDC15,
};
//PVDD电源模式
enum PVDD_MODE {
PWR_PVDD_LDO,
PWR_PVDD_DCDC,
};
//==============================软关机参数配置============================
//软关机会复位寄存器，该参数为传给rom配置的参数。
struct soft_flag0_t {
u8 wdt_dis: 1;
u8 poweroff: 1;
u8 is_port_b: 1;
u8 lvd_en: 1;
u8 pmu_en: 1;
u8 iov2_ldomode: 1;
u8 res: 2;
};
struct soft_flag1_t {
u8 usbdp: 2;
u8 usbdm: 2;
u8 uart_key_port: 1;
u8 ldoin: 3;
};
struct soft_flag2_t {
u8 pg2: 4;
u8 pg3: 4;
};
struct soft_flag3_t {
u8 pg4: 4;
u8 res: 4;
};
struct soft_flag4_t {
u8 fast_boot: 1;
u8 flash_stable_delay_sel: 2;
u8 res: 5;
};
struct soft_flag5_t {
u8 mvddio: 3;
u8 wvbg: 4;
u8 res: 1;
};
struct boot_soft_flag_t {
union {
struct soft_flag0_t boot_ctrl;
u8 value;
} flag0;
union {
struct soft_flag1_t misc;
u8 value;
} flag1;
union {
struct soft_flag2_t pg2_pg3;
u8 value;
} flag2;
union {
struct soft_flag3_t pg4_res;
u8 value;
} flag3;
union {
struct soft_flag4_t fast_boot_ctrl;
u8 value;
} flag4;
union {
struct soft_flag5_t level;
u8 value;
} flag5;
};
enum soft_flag_io_stage {
SOFTFLAG_HIGH_RESISTANCE,
SOFTFLAG_PU,
SOFTFLAG_PD,
SOFTFLAG_OUT0,
SOFTFLAG_OUT0_HD0,
SOFTFLAG_OUT0_HD,
SOFTFLAG_OUT0_HD0_HD,
SOFTFLAG_OUT1,
SOFTFLAG_OUT1_HD0,
SOFTFLAG_OUT1_HD,
SOFTFLAG_OUT1_HD0_HD,
};
//==============================电源接口============================
#define AT_VOLATILE_RAM_CODE_POWER AT(.power_driver.text.cache.L1)
#define AT_VOLATILE_CACHE_CODE_POWER AT(.power_driver.text.cache.L2)
void power_set_mode(u8 mode);
void power_set_pvdd_mode(enum PVDD_MODE mode);
u8 get_pvdd_dcdc_cfg();
void power_init(const struct low_power_param *param);
void power_keep_dacvdd_en(u8 en);
void sdpg_config(int enable);
void p11_init(void);
u8 get_wvdd_trim_level();
u8 get_pvdd_level();
u8 get_pvdd_trim_level();
u8 get_miovdd_trim_level();
u8 get_wiovdd_trim_level();
void store_pmu_trim_value_to_vm(u8 wvdd_level, u8 pvdd_level, u8 miovdd_lev, u8 wiovdd_lev);
u8 load_pmu_trim_value_from_vm();
void volatage_trim_init();
//==============================sleep接口============================
//注意：所有接口在临界区被调用，请勿使用阻塞操作
//sleep模式介绍
//1.所有数字模块停止，包括cpu、periph、audio、rf等
//2.所有模拟模块停止，包括pll、btosc、rc等
//3.只保留pmu模块
//light_sleep: 不切电源域
//normal_sleep: dvdd低电
//deepsleep：dvdd掉电
//----------------低功耗线程查询是否满足低功耗状态, 被动等待------------
struct low_power_operation {
const char *name;
u32(*get_timeout)(void *priv);
void (*suspend_probe)(void *priv);
void (*suspend_post)(void *priv, u32 usec);
void (*resume)(void *priv, u32 usec);
void (*resume_post)(void *priv, u32 usec);
};
enum LOW_POWER_LEVEL {
LOW_POWER_MODE_LIGHT_SLEEP = 1,
LOW_POWER_MODE_SLEEP,
LOW_POWER_MODE_DEEP_SLEEP,
};
typedef u8(*idle_handler_t)(void);
typedef enum LOW_POWER_LEVEL(*level_handler_t)(void);
typedef u8(*idle_handler_t)(void);
struct lp_target {
char *name;
level_handler_t level;
idle_handler_t is_idle;
};
#define REGISTER_LP_TARGET(target) \
const struct lp_target target sec(.lp_target)
extern const struct lp_target lp_target_begin[];
extern const struct lp_target lp_target_end[];
#define list_for_each_lp_target(p) \
for (p = lp_target_begin; p < lp_target_end; p++)
//--------------低功耗线程请求进入低功耗, 主动发出------------
struct lp_request {
char *name;
u8(*request_enter)(u32 timeout);
u8(*request_exit)(u32 timeout);
};
#define REGISTER_LP_REQUEST(target) \
const struct lp_request target sec(.lp_request)
extern const struct lp_request lp_request_begin[];
extern const struct lp_request lp_request_end[];
#define list_for_each_lp_request(p) \
for (p = lp_request_begin; p < lp_request_end; p++)
//-----------------------深度睡眠处理--------------------------
struct deepsleep_target {
char *name;
u8(*enter)(void);
u8(*exit)(void);
};
#define DEEPSLEEP_TARGET_REGISTER(target) \
const struct deepsleep_target target sec(.deepsleep_target)
extern const struct deepsleep_target deepsleep_target_begin[];
extern const struct deepsleep_target deepsleep_target_end[];
#define list_for_each_deepsleep_target(p) \
for (p = deepsleep_target_begin; p < deepsleep_target_end; p++)
#define NEW_BASEBAND_COMPENSATION 0
u32 __tus_carry(u32 x);
#define power_is_poweroff_post() 0
void *low_power_get(void *priv, const struct low_power_operation *ops);
void low_power_put(void *priv);
void low_power_sys_request(void *priv);
void *low_power_sys_get(void *priv, const struct low_power_operation *ops);
void low_power_sys_put(void *priv);
u8 is_low_power_mode(enum LOW_POWER_LEVEL level);
u8 low_power_sys_is_idle(void);
s32 low_power_trace_drift(u32 usec);
void low_power_reset_osc_type(u8 type);
u8 low_power_get_default_osc_type(void);
u8 low_power_get_osc_type(void);
void low_power_on(void);
void low_power_request(void);
u8 low_power_sys_request_enter(u32 timeout);
u8 low_power_sys_request_exit(u32 timeout);
u32 get_rch_hz();
void cap_rch_enable();
void cap_rch_disable();
//==============================soft接口============================
void power_set_soft_poweroff();
void power_set_soft_poweroff_advance();
void mask_softflag_config(const struct boot_soft_flag_t *softflag);
void power_set_callback(u8 mode, void (*powerdown_enter)(u8 step), void (*powerdown_exit)(u32), void (*soft_poweroff_enter)(void));
#endif

8
include_lib/driver/cpu/br28/asm/power/power_compat.h
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#ifndef __POWER_COMPAT_H__
#define __POWER_COMPAT_H__
//compatibility
#endif

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include_lib/driver/cpu/br28/asm/power/power_port.h
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#ifndef __POWER_PORT_H__
#define __POWER_PORT_H__
#define NO_CONFIG_PORT (-1)
enum {
PORTA_GROUP = 0,
PORTB_GROUP,
PORTC_GROUP,
PORTD_GROUP,
PORTE_GROUP,
PORTG_GROUP,
PORTP_GROUP,
};
struct gpio_value {
u16 gpioa;
u16 gpiob;
u16 gpioc;
u16 gpiod;
u16 gpioe;
u16 gpiog;
u16 gpiop;
u16 gpiousb;
};
#define _PORT(p) JL_PORT##p
#define SPI_PORT(p) _PORT(p)
// | func\port | A | B | C |
// |-----------|------|------|------|
// | CS | PD3 | PG4 | PC3 |
// | CLK | PD0 | PD0 | PC1 |
// | DO(D0) | PD1 | PD1 | PC2 |
// | DI(D1) | PD2 | PG3 | PC4 |
// | WP(D2) | PD5 | PG2 | PC5 |
// | HOLD(D3) | PD6 | PD6 | PC0 |
#define PORT_SPI0_PWRA D
#define SPI0_PWRA 4
#define PORT_SPI0_CSA D
#define SPI0_CSA 3
#define PORT_SPI0_CLKA D
#define SPI0_CLKA 0
#define PORT_SPI0_DOA D
#define SPI0_DOA 1
#define PORT_SPI0_DIA D
#define SPI0_DIA 2
#define PORT_SPI0_D2A D
#define SPI0_D2A 5
#define PORT_SPI0_D3A D
#define SPI0_D3A 6
#define SPI0_PWR_A IO_PORTD_04
#define SPI0_CS_A IO_PORTD_03
#define SPI0_CLK_A IO_PORTD_00
#define SPI0_DO_D0_A IO_PORTD_01
#define SPI0_DI_D1_A IO_PORTD_02
#define SPI0_WP_D2_A IO_PORTD_05
#define SPI0_HOLD_D3_A IO_PORTD_06
////////////////////////////////////////////////////////////////////////////////
#define PORT_SPI0_PWRB D
#define SPI0_PWRB 4
#define PORT_SPI0_CSB G
#define SPI0_CSB 4
#define PORT_SPI0_CLKB D
#define SPI0_CLKB 0
#define PORT_SPI0_DOB D
#define SPI0_DOB 1
#define PORT_SPI0_DIB G
#define SPI0_DIB 3
#define PORT_SPI0_D2B G
#define SPI0_D2B 2
#define PORT_SPI0_D3B D
#define SPI0_D3B 6
#define SPI0_PWR_B IO_PORTD_04
#define SPI0_CS_B IO_PORTG_04
#define SPI0_CLK_B IO_PORTD_00
#define SPI0_DO_D0_B IO_PORTD_01
#define SPI0_DI_D1_B IO_PORTG_03
#define SPI0_WP_D2_B IO_PORTG_02
#define SPI0_HOLD_D3_B IO_PORTD_06
////////////////////////////////////////////////////////////////////////////////
#define PORT_SPI0_PWRC C
#define SPI0_PWRC 8
#define PORT_SPI0_CSC C
#define SPI0_CSC 3
#define PORT_SPI0_CLKC C
#define SPI0_CLKC 1
#define PORT_SPI0_DOC C
#define SPI0_DOC 2
#define PORT_SPI0_DIC C
#define SPI0_DIC 4
#define PORT_SPI0_D2C C
#define SPI0_D2C 5
#define PORT_SPI0_D3C C
#define SPI0_D3C 0
#define SPI0_PWR_C IO_PORTC_08
#define SPI0_CS_C IO_PORTC_03
#define SPI0_CLK_C IO_PORTC_01
#define SPI0_DO_D0_C IO_PORTC_02
#define SPI0_DI_D1_C IO_PORTC_04
#define SPI0_WP_D2_C IO_PORTC_05
#define SPI0_HOLD_D3_C IO_PORTC_00
////////////////////////////////////////////////////////////////////////
#define PSRAM_D0A IO_PORTE_00
#define PSRAM_D1A IO_PORTE_01
#define PSRAM_D2A IO_PORTE_02
#define PSRAM_D3A IO_PORTE_05
u32 get_sfc_port(void);
u8 get_sfc_bit_mode();
u8 get_sfc1_bit_mode();
void port_init(void);
void port_protect(u16 *port_group, u32 port_num);
u8 WSIG_to_PANA(u8 wsig);
u8 PANA_to_WSIG(u8 iomap);
void soff_gpio_protect(u32 gpio);
void board_set_soft_poweroff_common(void *priv);
void sleep_gpio_protect(u32 gpio);
void sleep_enter_callback_common(void *priv);
void sleep_exit_callback_common(void *priv);
#endif

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include_lib/driver/cpu/br28/asm/power/power_reset.h
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#ifndef __POWER_RESET_H__
#define __POWER_RESET_H__
/*
*复位原因包括两种
1.系统复位源: p33 p11 主系统
2.自定义复位源：断言、异常等
*/
enum RST_REASON {
/*主系统*/
MSYS_P11_RST, //P11复位
MSYS_DVDD_POR_RST, //DVDD上电
MSYS_SOFT_RST, //主系统软件复位
MSYS_P2M_RST, //低功耗唤醒复位(softoff advance && deepsleep)
MSYS_POWER_RETURN, //主系统未被复位
/*P11*/
P11_PVDD_POR_RST, //pvdd上电
P11_IVS_RST, //低功耗唤醒复位(softoff legacy)
P11_P33_RST, //p33复位
P11_WDT_RST, //看门狗复位
P11_SOFT_RST, //软件复位
P11_MSYS_RST, //主系统复位P11
P11_POWER_RETURN, //P11系统未被复位
/*P33*/
P33_VDDIO_POR_RST, //vddio上电复位(电池/vpwr供电)
P33_VDDIO_LVD_RST, //vddio低压复位、上电复位(电池/vpwr供电)
P33_VCM_RST, //vcm高电平短接复位
P33_PPINR_RST, //数字io输入长按复位
P33_P11_RST, //p11系统复位p33，rset_mask=0
P33_SOFT_RST, //p33软件复位，一般软件复位指此系统复位源，所有系统会直接复位。
P33_PPINR1_RST, //模拟io输入长按复位，包括charge_full、vatch、ldoint、vabt_det
P33_POWER_RETURN, //p33系统未被复位。
//SUB
P33_EXCEPTION_SOFT_RST, //异常软件复位
P33_ASSERT_SOFT_RST, //断言软件复位
P33_XOSC_RESUME_ERR_RST, //快速起振恢复失败软件复位
P33_LPTMR_TIMEOUT_RST, //LPTMR软件复位
};
void power_reset_close();
void reset_source_dump(void);
void p33_soft_reset(void);
void set_reset_source_value(enum RST_REASON index);
u32 get_reset_source_value(void);
u8 is_reset_source(enum RST_REASON index);
int cpu_reset_by_soft();
#endif

74
include_lib/driver/cpu/br28/asm/power/power_wakeup.h
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@ -1,74 +0,0 @@
#ifndef __POWER_WAKEUP_H__
#define __POWER_WAKEUP_H__
enum WAKEUP_REASON {
//WAKEUP
PWR_WK_REASON_PLUSE_CNT_OVERFLOW, //pcnt唤醒复位
PWR_WK_REASON_P11, //P11唤醒复位
PWR_WK_REASON_LPCTMU, //触摸唤醒复位
PWR_WK_REASON_PORT_EDGE, //数字io输入边沿唤醒复位
PWR_WK_REASON_ANA_EDGE, //模拟io输入边沿唤醒复位
PWR_WK_REASON_VDDIO_LVD, //vddio lvd唤醒复位
PWR_WK_REASON_EDGE_INDEX0, //p33 index0 io唤醒复位
PWR_WK_REASON_EDGE_INDEX1, //p33 index1 io唤醒复位
PWR_WK_REASON_EDGE_INDEX2, //p33 index2 io唤醒复位
PWR_WK_REASON_EDGE_INDEX3, //p33 index3 io唤醒复位
PWR_WK_REASON_EDGE_INDEX4, //p33 index4 io唤醒复位
PWR_WK_REASON_EDGE_INDEX5, //p33 index5 io唤醒复位
PWR_WK_REASON_EDGE_INDEX6, //p33 index6 io唤醒复位
PWR_WK_REASON_EDGE_INDEX7, //p33 index7 io唤醒复位
PWR_WK_REASON_EDGE_INDEX8, //p33 index8 io唤醒复位
PWR_WK_REASON_EDGE_INDEX9, //p33 index9 io唤醒复位
PWR_WK_REASON_EDGE_INDEX10, //p33 index10 io唤醒复位
PWR_WK_REASON_EDGE_INDEX11, //p33 index11 io唤醒复位
PWR_ANA_WK_REASON_FALLINIG_EDGE_LDOIN, //LDO5V上升沿唤醒复位
PWR_ANA_WK_REASON_RISING_EDGE_LDOIN, //LDO5V下降沿唤醒复位
PWR_ANA_WK_REASON_FALLING_EDGE_VBATCH, //VBATCH上升降沿唤醒复位
PWR_ANA_WK_REASON_RISING_EDGE_VBATCH, //VBATCH下降沿唤醒复位
PWR_RTC_WK_REASON_ALM, //RTC闹钟唤醒复位
PWR_RTC_WK_REASON_256HZ, //RTC 256Hz时基唤醒复位
PWR_RTC_WK_REASON_64HZ, //RTC 64Hz时基唤醒复位
PWR_RTC_WK_REASON_2HZ, //RTC 2Hz时基唤醒复位
PWR_RTC_WK_REASON_1HZ, //RTC 1Hz时基唤醒复位
};
//=========================唤醒参数配置==================================
struct port_wakeup {
u8 iomap; //唤醒io
u8 pullup_down_enable; //上下拉是否使能
POWER_WKUP_EDGE edge; //唤醒边沿条件
POWER_WKUP_FLT filter; //滤波参数，数字io输入没有滤波可配制
};
struct wakeup_param {
//数字io输入
const struct port_wakeup *port[MAX_WAKEUP_PORT];
//模拟io输入
const struct port_wakeup *aport[MAX_WAKEUP_ANA_PORT];
};
//=========================唤醒接口==================================
void power_wakeup_index_enable(u8 index, u8 enable);
void power_wakeup_gpio_enable(u8 gpio, u8 enable);
void power_wakeup_gpio_edge(u8 gpio, POWER_WKUP_EDGE edge);
void power_awakeup_index_enable(u8 index, u8 enable);
void power_awakeup_gpio_enable(u8 gpio, u8 enable);
void power_awakeup_gpio_edge(u8 gpio, POWER_WKUP_EDGE edge);
void power_wakeup_set_callback(void (*wakeup_callback)(u8 index, u8 gpio));
void power_awakeup_set_callback(void (*wakeup_callback)(u8 index, u8 gpio, POWER_WKUP_EDGE edge));
void port_edge_wkup_set_callback_by_index(u8 index, void (*wakeup_callback)(u8 index, u8 gpio));
void aport_edge_wkup_set_callback_by_index(u8 index, void (*wakeup_callback)(u8 index, u8 gpio, POWER_WKUP_EDGE edge));
void power_wakeup_init(const struct wakeup_param *param);
u8 is_wakeup_source(enum WAKEUP_REASON index);
void power_wakeup_reason_dump();
u8 is_ldo5v_wakeup(void);
#endif

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include_lib/driver/cpu/br28/asm/power/rtc_app.h
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#ifndef __RTC_APP_H__
#define __RTC_APP_H__
enum {
R3_WKUP_SRC_ALM = 0,
R3_WKUP_SRC_256HZ = 4,
R3_WKUP_SRC_64HZ,
R3_WKUP_SRC_2HZ,
R3_WKUP_SRC_1HZ,
};
/************************R3_ALM_CON*****************************/
#define ALM_ALMOUT(a) P33_CON_SET(R3_ALM_CON, 7, 1, a)
#define ALM_CLK_SEL(a) P33_CON_SET(R3_ALM_CON, 2, 3, a)
#define ALM_ALMEN(a) P33_CON_SET(R3_ALM_CON, 0, 1, a)
//Macro for CLK_SEL
enum {
CLK_SEL_32K = 1,
CLK_SEL_12M,
CLK_SEL_24M,
CLK_SEL_LRC,
};
/************************R3_RTC_CON0*****************************/
#define RTC_ALM_RDEN(a) P33_CON_SET(R3_RTC_CON0, 5, 1, a)
#define RTC_RTC_RDEN(a) P33_CON_SET(R3_RTC_CON0, 4, 1, a)
#define RTC_ALM_WREN(a) P33_CON_SET(R3_RTC_CON0, 1, 1, a)
#define RTC_RTC_WREN(a) P33_CON_SET(R3_RTC_CON0, 0, 1, a)
/************************R3_OSL_CON*****************************/
#define OSL_X32XS(a) P33_CON_SET(R3_OSL_CON, 4, 2, a)
#define OSL_X32TS(a) P33_CON_SET(R3_OSL_CON, 2, 1, a)
#define OSL_X32OS(a) P33_CON_SET(R3_OSL_CON, 1, 1, a)
#define OSL_X32ES(a) P33_CON_SET(R3_OSL_CON, 0, 1, a)
/************************R3_TIME_CPND*****************************/
#define TIME_256HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 0, 1, a)
#define TIME_64HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 1, 1, a)
#define TIME_2HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 2, 1, a)
#define TIME_1HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 3, 1, a)
#endif