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This commit is contained in:
119
include_lib/driver/cpu/br28/asm/adc_api.h
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119
include_lib/driver/cpu/br28/asm/adc_api.h
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#ifndef __ADC_API_H__
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#define __ADC_API_H__
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//AD channel define
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#define AD_CH_PA0 (0x0)
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#define AD_CH_PA5 (0x1)
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#define AD_CH_PA6 (0x2)
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#define AD_CH_PA8 (0x3)
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#define AD_CH_PC4 (0x4)
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#define AD_CH_PC5 (0x5)
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#define AD_CH_PB1 (0x6)
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#define AD_CH_PB2 (0x7)
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#define AD_CH_PB5 (0x8)
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#define AD_CH_PB9 (0x9)
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#define AD_CH_DP (0xa)
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#define AD_CH_DM (0xb)
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#define AD_CH_PG0 (0xc)
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#define AD_CH_PG1 (0xd)
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#define AD_CH_PG5 (0xe)
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#define AD_CH_PG7 (0xf)
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#define AD_CH_BT (0x10)
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#define AD_CH_PMU (0x11)
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#define AD_CH_AUDIO (0x12)
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#define AD_CH_LPCTM (0x13)
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#define AD_CH_X32K (0x14)
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#define AD_CH_PLL1 (0x15)
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#define ADC_PMU_CH_VBG (0x0<<16)//MVBG/WVBG
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#define ADC_PMU_CH_VSW (0x1<<16)
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#define ADC_PMU_CH_PROGI (0x2<<16)
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#define ADC_PMU_CH_PROGF (0x3<<16)
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#define ADC_PMU_CH_VTEMP (0x4<<16)
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#define ADC_PMU_CH_VPWR (0x5<<16) //1/4vpwr
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#define ADC_PMU_CH_VBAT (0x6<<16) //1/4vbat
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// #define ADC_PMU_CH_VBAT_2 (0x7<<16)
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#define ADC_PMU_CH_VB17 (0x8<<16)
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#define ADC_PMU_CH_IOVDD2 (0x9<<16)
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#define ADC_PMU_CH_VDC15 (0xa<<16)
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#define ADC_PMU_CH_DVDD (0xb<<16)
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#define ADC_PMU_CH_RVDD (0xc<<16)
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#define ADC_PMU_CH_TWVDD (0xd<<16)
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#define ADC_PMU_CH_PVDD (0xe<<16)
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#define ADC_PMU_CH_EVDD (0xf<<16)
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#define AD_CH_PMU_VBG (AD_CH_PMU | ADC_PMU_CH_VBG)
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#define AD_CH_VDC15 (AD_CH_PMU | ADC_PMU_CH_VDC15)
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#define AD_CH_SYSVDD (AD_CH_PMU | ADC_PMU_CH_DVDD)
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#define AD_CH_DTEMP (AD_CH_PMU | ADC_PMU_CH_VTEMP)
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#define AD_CH_VBAT (AD_CH_PMU | ADC_PMU_CH_VBAT)
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#define AD_CH_LDO5V (AD_CH_PMU | ADC_PMU_CH_VPWR)
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#define AD_CH_WVDD (AD_CH_PMU | ADC_PMU_CH_TWVDD)
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#define AD_CH_PVDD (AD_CH_PMU | ADC_PMU_CH_PVDD)
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#define AD_CH_LDOREF AD_CH_PMU_VBG
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// #define AD_CH_BT_VBG (AD_CH_BT | (0x8<<11)) //WLA_CON0[14:11]= 0b1000
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// #define AD_CH_LDOREF AD_CH_BT_VBG
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// #define AD_CH_PMU_VBG (AD_CH_PMU | ADC_PMU_CH_VBG)
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// #define AD_CH_VDC13 (AD_CH_PMU | ADC_PMU_CH_VDC13)
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// #define AD_CH_SYSVDD (AD_CH_PMU | ADC_PMU_CH_SYSVDD)
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// #define AD_CH_DTEMP (AD_CH_PMU | ADC_PMU_CH_DTEMP)
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// #define AD_CH_VBAT (AD_CH_PMU | ADC_PMU_CH_VBAT)
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// #define AD_CH_LDO5V (AD_CH_PMU | ADC_PMU_CH_LDO5V)
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// #define AD_CH_WVDD (AD_CH_PMU | ADC_PMU_CH_WVDD)
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#define AD_AUDIO_VADADC ((BIT(0))<<16)
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#define AD_AUDIO_VCM ((BIT(1))<<16)
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#define AD_AUDIO_VBGLDO ((BIT(2))<<16)
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#define AD_AUDIO_HPVDD ((BIT(3))<<16)
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#define AD_AUDIO_RN ((BIT(4))<<16)
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#define AD_AUDIO_RP ((BIT(5))<<16)
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#define AD_AUDIO_LN ((BIT(6))<<16)
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#define AD_AUDIO_LP ((BIT(7))<<16)
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#define AD_AUDIO_DACVDD ((BIT(8))<<16)
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#define AD_CH_AUDIO_VADADC (AD_CH_AUDIO | AD_AUDIO_VADADC)
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#define AD_CH_AUDIO_VCM (AD_CH_AUDIO | AD_AUDIO_VCM)
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#define AD_CH_AUDIO_VBGLDO (AD_CH_AUDIO | AD_AUDIO_VBGLDO)
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#define AD_CH_AUDIO_HPVDD (AD_CH_AUDIO | AD_AUDIO_HPVDD)
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#define AD_CH_AUDIO_RN (AD_CH_AUDIO | AD_AUDIO_RN)
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#define AD_CH_AUDIO_RP (AD_CH_AUDIO | AD_AUDIO_RP)
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#define AD_CH_AUDIO_LN (AD_CH_AUDIO | AD_AUDIO_LN)
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#define AD_CH_AUDIO_LP (AD_CH_AUDIO | AD_AUDIO_LP)
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#define AD_CH_AUDIO_DACVDD (AD_CH_AUDIO | AD_AUDIO_DACVDD)
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#define ADC_MAX_CH 10
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extern void adc_init();
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extern void adc_vbg_init();
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//p33 define
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extern void adc_pmu_ch_select(u32 ch);
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extern void adc_pmu_detect_en(u32 ch);
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extern void adc_vdc13_save();
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extern void adc_vdc13_restore();
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//
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u32 adc_get_value(u32 ch);
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u32 adc_add_sample_ch(u32 ch);
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u32 adc_remove_sample_ch(u32 ch);
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u32 adc_get_voltage(u32 ch);
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u32 adc_check_vbat_lowpower();
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u32 adc_set_sample_freq(u32 ch, u32 ms);
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u32 adc_sample(u32 ch);
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int get_hpvdd_voltage(void);
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u32 get_vdd_voltage(u32 ch);
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u32 get_vddio_voltage();
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#endif
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1277
include_lib/driver/cpu/br28/asm/br28.h
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1277
include_lib/driver/cpu/br28/asm/br28.h
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File diff suppressed because it is too large
Load Diff
101
include_lib/driver/cpu/br28/asm/cache.h
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101
include_lib/driver/cpu/br28/asm/cache.h
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@ -0,0 +1,101 @@
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//*********************************************************************************//
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// Module name : cache.h //
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// Description : q32DSP cache control head file //
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// By Designer : zequan_liu //
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// Dat changed : //
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//*********************************************************************************//
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#ifndef __Q32DSP_CACHE__
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#define __Q32DSP_CACHE__
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//#include "generic/typedef.h"
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#if 0
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//------------------------------------------------------//
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// icache function
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//------------------------------------------------------//
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void IcuEnable(void);
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void IcuDisable(void);
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void IcuInitial(void);
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//void IcuFlushAll(void);
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void IcuFlushinvAll(void);
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//void IcuFlushRegion(int *beg, int len); // note len!=0
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void IcuFlushinvRegion(int *beg, int len); // note len!=0
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void IcuUnlockAll(void);
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void IcuUnlockRegion(int *beg, int len); // note len!=0
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void IcuPfetchRegion(int *beg, int len); // note len!=0
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void IcuLockRegion(int *beg, int len); // note len!=0
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void IcuReportEnable(void);
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void IcuReportDisable(void);
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void IcuReportPrintf(void);
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void IcuReportClear(void);
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void IcuEmuEnable(void);
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void IcuEmuDisable(void);
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void IcuEmuMessage(void);
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#define WAIT_ICACHE_IDLE do{asm volatile("csync"); \
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while(!(q32DSP_icu(core_num())->CON & BIT(31)));} while(0);
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//------------------------------------------------------//
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// dcache function
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//------------------------------------------------------//
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void DcuEnable(void);
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void DcuDisable(void);
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void DcuInitial(void);
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//void DcuFlushAll(void);
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void DcuFlushinvAll(void);
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//void DcuFlushRegion(int *beg, int len); // note len!=0
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void DcuFlushinvRegion(int *beg, int len); // note len!=0
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void DcuUnlockAll(void);
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void DcuUnlockRegion(int *beg, int len); // note len!=0
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void DcuPfetchRegion(int *beg, int len); // note len!=0
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void DcuLockRegion(int *beg, int len); // note len!=0
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void DcuReportEnable(void);
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void DcuReportDisable(void);
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void DcuReportPrintf(void);
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void DcuReportClear(void);
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void DcuEmuEnable(void);
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void DcuEmuDisable(void);
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void DcuEmuMessage(void);
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#define WAIT_DCACHE_IDLE do{asm volatile("csync"); while(!(JL_DCU->CON & BIT(31)));} while(0);
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#endif
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void flush_dcache(void *ptr, int len);
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void flushinv_dcache(void *ptr, int len);
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void IcuEnable(void);
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void DcuEnable(void);
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void IcuWaitIdle(void);
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void DcuWaitIdle(void);
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void IcuDisable(void);
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void DcuDisable(void);
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void IcuFlushinvAll(void);
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void IcuUnlockAll(void);
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void IcuFlushinvRegion(int *beg, int len);
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void IcuUnlockRegion(int *beg, int len);
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void IcuLockRegion(int *beg, int len);
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void IcuPfetchRegion(int *beg, int len);
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void DcuFlushinvAll(void);
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void DcuFlushinvRegion(int *beg, int len);
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void DcuPfetchRegion(int *beg, int len);
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void IcuInitial(void);
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void DcuInitial(void);
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#define WAIT_DCACHE_IDLE do {DcuWaitIdle();} while(0);
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#define WAIT_ICACHE_IDLE do {IcuWaitIdle();} while(0);
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//#define WAIT_DCACHE_IDLE do{asm volatile("csync"); while(!(JL_DCU->CON & BIT(31)));} while(0);
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#endif /* #ifndef __Q32DSP_CACHE__ */
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//*********************************************************************************//
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// //
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// end of this module //
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// //
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//*********************************************************************************//
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169
include_lib/driver/cpu/br28/asm/charge.h
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169
include_lib/driver/cpu/br28/asm/charge.h
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@ -0,0 +1,169 @@
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#ifndef _CHARGE_H_
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#define _CHARGE_H_
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#include "typedef.h"
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#include "device.h"
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/*------充满电电压选择 4.041V-4.534V-------*/
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//低压压电池配置0~15
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#define CHARGE_FULL_V_4041 0
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#define CHARGE_FULL_V_4061 1
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#define CHARGE_FULL_V_4081 2
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#define CHARGE_FULL_V_4101 3
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#define CHARGE_FULL_V_4119 4
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#define CHARGE_FULL_V_4139 5
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#define CHARGE_FULL_V_4159 6
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#define CHARGE_FULL_V_4179 7
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#define CHARGE_FULL_V_4199 8
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#define CHARGE_FULL_V_4219 9
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#define CHARGE_FULL_V_4238 10
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#define CHARGE_FULL_V_4258 11
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#define CHARGE_FULL_V_4278 12
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#define CHARGE_FULL_V_4298 13
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#define CHARGE_FULL_V_4318 14
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#define CHARGE_FULL_V_4338 15
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//高压电池配置16~31
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#define CHARGE_FULL_V_4237 16
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#define CHARGE_FULL_V_4257 17
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#define CHARGE_FULL_V_4275 18
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#define CHARGE_FULL_V_4295 19
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#define CHARGE_FULL_V_4315 20
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#define CHARGE_FULL_V_4335 21
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#define CHARGE_FULL_V_4354 22
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#define CHARGE_FULL_V_4374 23
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#define CHARGE_FULL_V_4394 24
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#define CHARGE_FULL_V_4414 25
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#define CHARGE_FULL_V_4434 26
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#define CHARGE_FULL_V_4454 27
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#define CHARGE_FULL_V_4474 28
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#define CHARGE_FULL_V_4494 29
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#define CHARGE_FULL_V_4514 30
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#define CHARGE_FULL_V_4534 31
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#define CHARGE_FULL_V_MAX 32
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/*****************************************/
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/*充满电电流选择 2mA-30mA*/
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#define CHARGE_FULL_mA_2 0
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#define CHARGE_FULL_mA_5 1
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#define CHARGE_FULL_mA_7 2
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#define CHARGE_FULL_mA_10 3
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#define CHARGE_FULL_mA_15 4
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#define CHARGE_FULL_mA_20 5
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#define CHARGE_FULL_mA_25 6
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#define CHARGE_FULL_mA_30 7
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/*
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充电电流选择
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恒流：20-220mA
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*/
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#define CHARGE_mA_15 0
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#define CHARGE_mA_20 1
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#define CHARGE_mA_25 2
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#define CHARGE_mA_30 3
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#define CHARGE_mA_35 4
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#define CHARGE_mA_40 5
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#define CHARGE_mA_50 6
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#define CHARGE_mA_60 7
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#define CHARGE_mA_80 8
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#define CHARGE_mA_100 9
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#define CHARGE_mA_120 10
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#define CHARGE_mA_140 11
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#define CHARGE_mA_160 12
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#define CHARGE_mA_200 13
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#define CHARGE_mA_250 14
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#define CHARGE_mA_300 15
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#define CHARGE_mA_1P5 (BIT(4)|CHARGE_mA_15)
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#define CHARGE_mA_2 (BIT(4)|CHARGE_mA_20)
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#define CHARGE_mA_2P5 (BIT(4)|CHARGE_mA_25)
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#define CHARGE_mA_3 (BIT(4)|CHARGE_mA_30)
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#define CHARGE_mA_3P5 (BIT(4)|CHARGE_mA_35)
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#define CHARGE_mA_4 (BIT(4)|CHARGE_mA_40)
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#define CHARGE_mA_5 (BIT(4)|CHARGE_mA_50)
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#define CHARGE_mA_6 (BIT(4)|CHARGE_mA_60)
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#define CHARGE_mA_8 (BIT(4)|CHARGE_mA_80)
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#define CHARGE_mA_10 (BIT(4)|CHARGE_mA_100)
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#define CHARGE_mA_12 (BIT(4)|CHARGE_mA_120)
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#define CHARGE_mA_14 (BIT(4)|CHARGE_mA_140)
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#define CHARGE_mA_16 (BIT(4)|CHARGE_mA_160)
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/*
|
||||
充电口下拉选择
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||||
电阻 50k ~ 200k
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||||
*/
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||||
#define CHARGE_PULLDOWN_50K 0
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#define CHARGE_PULLDOWN_100K 1
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#define CHARGE_PULLDOWN_150K 2
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#define CHARGE_PULLDOWN_200K 3
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||||
|
||||
|
||||
#define CHARGE_CCVOL_V 300 //涓流充电向恒流充电的转换点
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||||
|
||||
#define DEVICE_EVENT_FROM_CHARGE (('C' << 24) | ('H' << 16) | ('G' << 8) | '\0')
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||||
|
||||
struct charge_platform_data {
|
||||
u8 charge_en; //内置充电使能
|
||||
u8 charge_poweron_en; //开机充电使能
|
||||
u8 charge_full_V; //充满电电压大小
|
||||
u8 charge_full_mA; //充满电电流大小
|
||||
u8 charge_mA; //恒流充电电流大小
|
||||
u8 charge_trickle_mA; //涓流充电电流大小
|
||||
u8 ldo5v_pulldown_en; //下拉使能位
|
||||
u8 ldo5v_pulldown_lvl; //ldo5v的下拉电阻配置项,若充电舱需要更大的负载才能检测到插入时，请将该变量置为对应阻值
|
||||
u8 ldo5v_pulldown_keep; //下拉电阻在softoff时是否保持,ldo5v_pulldown_en=1时有效
|
||||
u16 ldo5v_off_filter; //ldo5v拔出过滤值，过滤时间 = (filter*2 + 20)ms,ldoin<0.6V且时间大于过滤时间才认为拔出,对于充满直接从5V掉到0V的充电仓，该值必须设置成0，对于充满由5V先掉到0V之后再升压到xV的充电仓，需要根据实际情况设置该值大小
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||||
u16 ldo5v_on_filter; //ldo5v>vbat插入过滤值,电压的过滤时间 = (filter*2)ms
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||||
u16 ldo5v_keep_filter; //1V<ldo5v<vbat维持电压过滤值,过滤时间= (filter*2)ms
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||||
u16 charge_full_filter; //充满过滤值,连续检测充满信号恒为1才认为充满,过滤时间 = (filter*2)ms
|
||||
};
|
||||
|
||||
#define CHARGE_PLATFORM_DATA_BEGIN(data) \
|
||||
struct charge_platform_data data = {
|
||||
|
||||
#define CHARGE_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
CHARGE_FULL_33V = 0, //充满标记位
|
||||
TERMA_33V, //模拟测试信号
|
||||
VBGOK_33V, //模拟测试信号
|
||||
CICHARGE_33V, //涓流转恒流信号
|
||||
};
|
||||
|
||||
enum {
|
||||
CHARGE_EVENT_CHARGE_START,
|
||||
CHARGE_EVENT_CHARGE_CLOSE,
|
||||
CHARGE_EVENT_CHARGE_FULL,
|
||||
CHARGE_EVENT_LDO5V_KEEP,
|
||||
CHARGE_EVENT_LDO5V_IN,
|
||||
CHARGE_EVENT_LDO5V_OFF,
|
||||
CHARGE_EVENT_USB_CHARGE_IN,
|
||||
CHARGE_EVENT_USB_CHARGE_OFF,
|
||||
};
|
||||
|
||||
|
||||
extern void set_charge_event_flag(u8 flag);
|
||||
extern void set_charge_online_flag(u8 flag);
|
||||
extern void set_charge_event_flag(u8 flag);
|
||||
extern u8 get_charge_online_flag(void);
|
||||
extern u8 get_charge_poweron_en(void);
|
||||
extern void set_charge_poweron_en(u32 onOff);
|
||||
extern void charge_start(void);
|
||||
extern void charge_close(void);
|
||||
extern u8 get_charge_mA_config(void);
|
||||
extern void set_charge_mA(u8 charge_mA);
|
||||
extern u8 get_ldo5v_pulldown_en(void);
|
||||
extern u8 get_ldo5v_pulldown_res(void);
|
||||
extern u8 get_ldo5v_online_hw(void);
|
||||
extern u8 get_lvcmp_det(void);
|
||||
extern void charge_check_and_set_pinr(u8 mode);
|
||||
extern u16 get_charge_full_value(void);
|
||||
extern void charge_module_stop(void);
|
||||
extern void charge_module_restart(void);
|
||||
extern void ldoin_wakeup_isr(void);
|
||||
extern void charge_wakeup_isr(void);
|
||||
extern int charge_init(const struct dev_node *node, void *arg);
|
||||
extern const struct device_operations charge_dev_ops;
|
||||
extern void charge_set_ldo5v_detect_stop(u8 stop);
|
||||
|
||||
#endif //_CHARGE_H_
|
||||
74
include_lib/driver/cpu/br28/asm/chargestore.h
Normal file
74
include_lib/driver/cpu/br28/asm/chargestore.h
Normal file
@ -0,0 +1,74 @@
|
||||
#ifndef __BR28_CHARGESTORE_H__
|
||||
#define __BR28_CHARGESTORE_H__
|
||||
|
||||
enum {
|
||||
CMD_COMPLETE,
|
||||
CMD_RECVDATA,
|
||||
};
|
||||
|
||||
enum {
|
||||
MODE_RECVDATA,
|
||||
MODE_SENDDATA,
|
||||
};
|
||||
|
||||
enum {
|
||||
TYPE_NORMAL,
|
||||
TYPE_F95,
|
||||
};
|
||||
|
||||
#define LDOIN_BIND_IO IO_PORTP_00
|
||||
|
||||
struct chargestore_platform_data {
|
||||
u32 baudrate;
|
||||
u32 io_port;
|
||||
u8 uart_irq;
|
||||
void (*init)(const struct chargestore_platform_data *);
|
||||
void (*open)(u8 mode);
|
||||
void (*close)(void);
|
||||
void (*write)(u8 *, u8);
|
||||
};
|
||||
|
||||
struct chargestore_data_handler {
|
||||
int (*data_cb)(u8 *buf, u8 len);
|
||||
};
|
||||
|
||||
#define CHARGESTORE_HANDLE_REG(name, data_callback) \
|
||||
const struct chargestore_data_handler chargestore_##name \
|
||||
SEC_USED(.chargestore_callback_txt) = {data_callback};
|
||||
|
||||
extern struct chargestore_data_handler chargestore_handler_begin[];
|
||||
extern struct chargestore_data_handler chargestore_handler_end[];
|
||||
|
||||
#define list_for_each_loop_chargestore(h) \
|
||||
for (h=chargestore_handler_begin; h<chargestore_handler_end; h++)
|
||||
|
||||
|
||||
#define CHARGESTORE_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct chargestore_platform_data data = {
|
||||
|
||||
#define CHARGESTORE_PLATFORM_DATA_END() \
|
||||
.baudrate = 9600, \
|
||||
.init = chargestore_init, \
|
||||
.open = chargestore_open, \
|
||||
.close = chargestore_close, \
|
||||
.write = chargestore_write, \
|
||||
};
|
||||
|
||||
extern void chargestore_open(u8 mode);
|
||||
extern void chargestore_close(void);
|
||||
extern void chargestore_write(u8 *data, u8 len);
|
||||
extern void chargestore_init(const struct chargestore_platform_data *);
|
||||
extern void chargestore_set_update_ram(void);
|
||||
extern u8 chargestore_get_det_level(u8 chip_type);
|
||||
|
||||
//app层使用的接口
|
||||
extern void chargestore_api_close(void);
|
||||
extern int chargestore_api_write(u8 *buf, u8 len);
|
||||
extern void chargestore_api_init(const struct chargestore_platform_data *arg);
|
||||
extern void chargestore_api_wait_complete(void);
|
||||
extern void chargestore_api_set_timeout(u16 timeout);
|
||||
extern void chargestore_api_stop(void);
|
||||
extern void chargestore_api_restart(void);
|
||||
extern u8 chargestore_api_crc8(u8 *ptr, u8 len);
|
||||
|
||||
#endif
|
||||
153
include_lib/driver/cpu/br28/asm/clock.h
Normal file
153
include_lib/driver/cpu/br28/asm/clock.h
Normal file
@ -0,0 +1,153 @@
|
||||
#ifndef _CPU_CLOCK_
|
||||
#define _CPU_CLOCK_
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#include "clock_hw.h"
|
||||
#include "asm/clock_define.h"
|
||||
|
||||
|
||||
typedef int SYS_CLOCK_INPUT;
|
||||
|
||||
typedef enum {
|
||||
SYS_ICLOCK_INPUT_BTOSC, //BTOSC 双脚(12-26M)
|
||||
SYS_ICLOCK_INPUT_RTOSCH,
|
||||
SYS_ICLOCK_INPUT_RTOSCL,
|
||||
SYS_ICLOCK_INPUT_PAT,
|
||||
} SYS_ICLOCK_INPUT;
|
||||
|
||||
typedef enum {
|
||||
ALINK_CLOCK_12M288K, //160M div 13, 48k采样率类型
|
||||
ALINK_CLOCK_11M2896K, //192M div 17, 44.1k采样率类型
|
||||
} ALINK_INPUT_CLK_TYPE;
|
||||
|
||||
typedef enum {
|
||||
TDM_CLOCK_12M288K, //160M div 13, 48k采样率类型
|
||||
TDM_CLOCK_11M2896K, //192M div 17, 44.1k采样率类型
|
||||
} TDM_INPUT_CLK_TYPE;
|
||||
|
||||
|
||||
/*
|
||||
* system enter critical and exit critical handle
|
||||
* */
|
||||
struct clock_critical_handler {
|
||||
void (*enter)();
|
||||
void (*exit)();
|
||||
};
|
||||
|
||||
#define CLOCK_CRITICAL_HANDLE_REG(name, enter, exit) \
|
||||
const struct clock_critical_handler clock_##name \
|
||||
SEC_USED(.clock_critical_txt) = {enter, exit};
|
||||
|
||||
extern struct clock_critical_handler clock_critical_handler_begin[];
|
||||
extern struct clock_critical_handler clock_critical_handler_end[];
|
||||
|
||||
#define list_for_each_loop_clock_critical(h) \
|
||||
for (h=clock_critical_handler_begin; h<clock_critical_handler_end; h++)
|
||||
|
||||
|
||||
int clk_early_init(u8 sys_in, u32 input_freq, u32 out_freq);
|
||||
|
||||
int clk_get(const char *name);
|
||||
|
||||
int clk_set(const char *name, int clk);
|
||||
|
||||
int clk_set_sys_lock(int clk, int lock_en);
|
||||
|
||||
enum CLK_OUT_SOURCE {
|
||||
LRC_CLK_OUT,
|
||||
P33_RCLK_CLK_OUT,
|
||||
RC16M_CLK_OUT,
|
||||
RTC_OSC_CLK_OUT,
|
||||
BTOSC_24M_CLK_OUT,
|
||||
BTOSC_48M_CLK_OUT,
|
||||
STD_12M_CLK_OUT,
|
||||
STD_24M_CLK_OUT,
|
||||
STD_48M_CLK_OUT,
|
||||
HSB_CLK_OUT,
|
||||
LSB_CLK_OUT,
|
||||
PLL_96M_CLK_OUT,
|
||||
XXX_CLK_OUT_0,
|
||||
XXX_CLK_OUT_1,
|
||||
XXX_CLK_OUT_2,
|
||||
XXX_CLK_OUT_3,
|
||||
};
|
||||
|
||||
enum XXX_CLK_OUT_0_1_SOURCE {
|
||||
SRC_CLK_OUT = 12,
|
||||
IMD_CLK_OUT,
|
||||
PSRAM_CLK_OUT,
|
||||
XOSC_CLK_OUT,
|
||||
};
|
||||
|
||||
enum XXX_CLK_OUT_2_3_SOURCE {
|
||||
PLL_ALNK0_CLK_OUT = 12,
|
||||
RF_CLKO75M_CLK_OUT,
|
||||
DCDC_CLK_OUT,
|
||||
DPLL_CLK_OUT,
|
||||
};
|
||||
|
||||
void clk_out(u8 gpio, enum CLK_OUT_SOURCE clk);
|
||||
|
||||
void clock_dump(void);
|
||||
|
||||
#define MHz (1000000L)
|
||||
enum sys_clk {
|
||||
SYS_24M = 24 * MHz,
|
||||
SYS_32M = 32 * MHz,
|
||||
SYS_48M = 48 * MHz,
|
||||
SYS_64M = 64 * MHz,
|
||||
SYS_76M = 76800000,
|
||||
SYS_80M = 80 * MHz,
|
||||
SYS_96M = 96 * MHz,
|
||||
SYS_120M = 120 * MHz,
|
||||
SYS_128M = 128 * MHz,
|
||||
SYS_160M = 160 * MHz,
|
||||
};
|
||||
|
||||
enum clk_mode {
|
||||
CLOCK_MODE_ADAPTIVE = 0,
|
||||
CLOCK_MODE_USR,
|
||||
};
|
||||
|
||||
//clk : SYS_48M / SYS_24M
|
||||
void sys_clk_set(enum sys_clk clk);
|
||||
|
||||
void clk_voltage_init(u8 mode, u8 sys_dvdd);
|
||||
|
||||
int xosc_hcs_trim(void);
|
||||
|
||||
void clk_set_osc_cap(u8 sel_l, u8 sel_r);
|
||||
|
||||
u32 clk_get_osc_cap();
|
||||
|
||||
void audio_link_clock_sel(ALINK_INPUT_CLK_TYPE type);
|
||||
|
||||
void tdm_clock_sel(TDM_INPUT_CLK_TYPE type);
|
||||
|
||||
/**
|
||||
* @brief clock_set_sfc_max_freq
|
||||
* 使用前需要保证所使用的flash支持4bit 100Mhz 模式
|
||||
*
|
||||
* @param dual_max_freq for cmd 3BH BBH
|
||||
* @param quad_max_freq for cmd 6BH EBH
|
||||
*/
|
||||
void clock_set_sfc_max_freq(u32 dual_max_freq, u32 quad_max_freq);
|
||||
/**
|
||||
* @brief clock_set_lowest_voltage 设置dvdd工作的最低 工作电压
|
||||
*
|
||||
* @param dvdd_lev mic 工作时候 建议 SYSVDD_VOL_SEL_105V，关闭的时候设置为 SYSVDD_VOL_SEL_084V
|
||||
*/
|
||||
void clock_set_lowest_voltage(u32 dvdd_lev);
|
||||
|
||||
|
||||
/**
|
||||
* @brief clock_set_pll_target_frequency
|
||||
*
|
||||
* @param freq *Mhz 支持192或者240
|
||||
*/
|
||||
void clock_set_pll_target_frequency(u32 freq);
|
||||
|
||||
u32 clock_get_pll_target_frequency(); //获取PLL_TARGET_FREQUENCY
|
||||
#endif
|
||||
|
||||
30
include_lib/driver/cpu/br28/asm/clock_define.h
Normal file
30
include_lib/driver/cpu/br28/asm/clock_define.h
Normal file
@ -0,0 +1,30 @@
|
||||
|
||||
|
||||
#ifndef _CPU_CLOCK_DEFINE__
|
||||
#define _CPU_CLOCK_DEFINE__
|
||||
|
||||
///原生时钟源作系统时钟源
|
||||
#define SYS_CLOCK_INPUT_RC 0
|
||||
#define SYS_CLOCK_INPUT_BT_OSC 1 //BTOSC 双脚(12-26M)
|
||||
#define SYS_CLOCK_INPUT_RTOSCH 2
|
||||
#define SYS_CLOCK_INPUT_RTOSCL 3
|
||||
#define SYS_CLOCK_INPUT_PAT 4
|
||||
|
||||
///衍生时钟源作系统时钟源
|
||||
#define SYS_CLOCK_INPUT_PLL_BT_OSC 5
|
||||
#define SYS_CLOCK_INPUT_PLL_RTOSCH 6
|
||||
#define SYS_CLOCK_INPUT_PLL_PAT 7
|
||||
#define SYS_CLOCK_INPUT_PLL_RCL 8
|
||||
|
||||
///VAD时钟源
|
||||
#define VAD_CLOCK_USE_BTOSC 0 //DVAD、ANALOG使用BTOSC
|
||||
#define VAD_CLOCK_USE_RC_AND_BTOSC 1 //DVAD使用RC、BTOSC直连ANALOG
|
||||
#define VAD_CLOCK_USE_PMU_STD12M 2 //DVAD使用BTOSC通过PMU配置的STD12M
|
||||
#define VAD_CLOCK_USE_LRC 3 //DVAD使用LRC
|
||||
|
||||
//ANC时钟源
|
||||
#define ANC_CLOCK_USE_CLOSE 0 //ANC关闭，无需保持相关时钟
|
||||
#define ANC_CLOCK_USE_BTOSC 1 //ANC使用BTOSCX2时钟
|
||||
#define ANC_CLOCK_USE_PLL 2 //ANC使用PLL时钟
|
||||
#endif
|
||||
|
||||
404
include_lib/driver/cpu/br28/asm/clock_hw.h
Normal file
404
include_lib/driver/cpu/br28/asm/clock_hw.h
Normal file
@ -0,0 +1,404 @@
|
||||
#ifndef __CLOCK_HW_H__
|
||||
#define __CLOCK_HW_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#define RC_EN(x) SFR(JL_CLOCK->CLK_CON0, 0, 1, x)
|
||||
#define RCH_EN(x) SFR(JL_CLOCK->CLK_CON0, 0, 1, x)
|
||||
//for MACRO - RCH_EN
|
||||
enum {
|
||||
RCH_EN_250K = 0,
|
||||
RCH_EN_16M,
|
||||
};
|
||||
|
||||
#define OSC_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON0, 1, 3, x)
|
||||
//for MACRO - OSC_CLOCK_IN
|
||||
enum {
|
||||
OSC_CLOCK_IN_BT_OSC = 0,
|
||||
OSC_CLOCK_IN_BT_OSC_X2,
|
||||
OSC_CLOCK_IN_STD_24M,
|
||||
OSC_CLOCK_IN_RTC_OSC,
|
||||
OSC_CLOCK_IN_LRC_CLK,
|
||||
OSC_CLOCK_IN_PAT,
|
||||
};
|
||||
#define PLL_96M_SEL_END 6
|
||||
#define PLL_96M_SEL_GET() ((JL_CLOCK->CLK_CON0 >> 4) & 0xF)
|
||||
#define PLL_96M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 4, 4, x)
|
||||
enum {
|
||||
PLL_96M_SEL_NULL = 0,
|
||||
|
||||
PLL_96M_SEL_7DIV2, //f5
|
||||
PLL_96M_SEL_5DIV2, //f4
|
||||
PLL_96M_SEL_4DIV2, //f3
|
||||
PLL_96M_SEL_3DIV2, //f2
|
||||
PLL_96M_SEL_1DIV1, //f1
|
||||
|
||||
|
||||
|
||||
PLL1_96M_SEL_7DIV2, //f5
|
||||
PLL1_96M_SEL_5DIV2, //f4
|
||||
PLL1_96M_SEL_4DIV2, //f3
|
||||
PLL1_96M_SEL_3DIV2, //f2
|
||||
PLL1_96M_SEL_1DIV1, //f1
|
||||
|
||||
};
|
||||
|
||||
#define PLL_48M_SEL_GET() ((JL_CLOCK->CLK_CON0 & BIT(8)) >> 8)
|
||||
#define PLL_48M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 8, 1, x)
|
||||
enum {
|
||||
PLL_48M_SEL_DIV2 = 0,
|
||||
PLL_48M_SEL_DIV1,
|
||||
};
|
||||
|
||||
#define STD_48M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 9, 1, x)
|
||||
#define PLL_48M_TO_STD_48M 0
|
||||
#define BTOSCX2_TO_STD_48M 1
|
||||
|
||||
#define STD_48M_SEL_GET() ((JL_CLOCK->CLK_CON0 & BIT(9)) >> 9)
|
||||
|
||||
#define STD_24M_SEL(x) SFR(JL_CLOCK->CLK_CON0, 10, 1, x)
|
||||
#define STD_48M_DIV2_TO_STD_24M 0
|
||||
#define BTOSC_TO_STD_24M 1
|
||||
|
||||
|
||||
|
||||
#define PLL_SYS_SEL(x) SFR(JL_CLOCK->CLK_CON1, 0, 4, x)
|
||||
#define PLL_SYS_SEL_GET() ((JL_CLOCK->CLK_CON1 & 0xF))
|
||||
|
||||
#define PLL_SYS_SEL_END 6
|
||||
//for MACRO - PLL_SYS_SEL
|
||||
enum {
|
||||
PLL_SYS_SEL_NULL = 0,
|
||||
PLL_SYS_SEL_7DIV2, //f5
|
||||
PLL_SYS_SEL_5DIV2, //f4
|
||||
PLL_SYS_SEL_4DIV2, //f3
|
||||
PLL_SYS_SEL_3DIV2, //f2
|
||||
PLL_SYS_SEL_1DIV1, //f1
|
||||
|
||||
|
||||
PLL1_SYS_SEL_7DIV2, //f5
|
||||
PLL1_SYS_SEL_5DIV2, //f4
|
||||
PLL1_SYS_SEL_4DIV2, //f3
|
||||
PLL1_SYS_SEL_3DIV2, //f2
|
||||
PLL1_SYS_SEL_1DIV1, //f1
|
||||
|
||||
};
|
||||
|
||||
#define PLL_SYS_DIV(x) SFR(JL_CLOCK->CLK_CON1, 4, 4, x)
|
||||
//for MACRO - PLL_SYS_DIV
|
||||
enum {
|
||||
PLL_SYS_DIV1 = 0,
|
||||
PLL_SYS_DIV3,
|
||||
PLL_SYS_DIV5,
|
||||
PLL_SYS_DIV7,
|
||||
|
||||
PLL_SYS_DIV1X2 = 4,
|
||||
PLL_SYS_DIV3X2,
|
||||
PLL_SYS_DIV5X2,
|
||||
PLL_SYS_DIV7X2,
|
||||
|
||||
PLL_SYS_DIV1X4 = 8,
|
||||
PLL_SYS_DIV3X4,
|
||||
PLL_SYS_DIV5X4,
|
||||
PLL_SYS_DIV7X4,
|
||||
|
||||
PLL_SYS_DIV1X8 = 12,
|
||||
PLL_SYS_DIV3X8,
|
||||
PLL_SYS_DIV5X8,
|
||||
PLL_SYS_DIV7X8,
|
||||
};
|
||||
#define MAIN_CLOCK_SEL(x) SFR(JL_CLOCK->CLK_CON1, 8, 3, x); \
|
||||
asm("csync")
|
||||
|
||||
//for MACRO - CLOCK_IN
|
||||
enum {
|
||||
MAIN_CLOCK_IN_RC_250K = 0,
|
||||
MAIN_CLOCK_IN_PAT,
|
||||
MAIN_CLOCK_IN_RTC_OSC,
|
||||
MAIN_CLOCK_IN_RC,
|
||||
MAIN_CLOCK_IN_BTOSC,
|
||||
MAIN_CLOCK_IN_BTOSC_X2,
|
||||
MAIN_CLOCK_IN_PLL,
|
||||
MAIN_CLOCK_IN_RTOSC_L, //keep to fix make
|
||||
};
|
||||
|
||||
|
||||
#define SFR_MODE(x) SFR(JL_CLOCK->CLK_CON1, 11, 1, x)
|
||||
enum {
|
||||
SFR_CLOCK_IDLE = 0,
|
||||
SFR_CLOCK_ALWAYS_ON,
|
||||
};
|
||||
|
||||
|
||||
#define BT_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON1, 14, 2, x)
|
||||
//for MACRO - BT_CLOCK_IN
|
||||
enum {
|
||||
BT_CLOCK_IN_PLL48M = 0,
|
||||
BT_CLOCK_IN_HSB,
|
||||
BT_CLOCK_IN_LSB,
|
||||
BT_CLOCK_IN_DISABLE,
|
||||
};
|
||||
|
||||
#define PLL_ALNK0_SEL(x) SFR(JL_CLOCK->CLK_CON2, 0, 3, x)
|
||||
#define PLL_ALNK0_DIV(x) SFR(JL_CLOCK->CLK_CON2, 3, 2, x)
|
||||
|
||||
#define PLL_ALNK_EN(x) SFR(JL_CLOCK->CLK_CON2, 6, 1, x)
|
||||
#define PLL_ALNK_SEL(x) SFR(JL_CLOCK->CLK_CON2, 7, 1, x)
|
||||
//for MACRO - PLL_ALNK_SEL
|
||||
enum {
|
||||
PLL_ALNK_192M_DIV17 = 0,
|
||||
PLL_ALNK_480M_DIV39,
|
||||
};
|
||||
|
||||
#define USB_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 8, 2, x)
|
||||
//for MACRO - USB_CLOCK_IN
|
||||
enum {
|
||||
USB_CLOCK_IN_PLL48M = 0,
|
||||
USB_CLOCK_IN_OSC,
|
||||
USB_CLOCK_IN_LSB,
|
||||
USB_CLOCK_IN_DISABLE,
|
||||
};
|
||||
|
||||
#define UART_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 10, 2, x)
|
||||
//for MACRO - UART_CLOCK_IN
|
||||
enum {
|
||||
UART_CLOCK_IN_PLL24M = 0,
|
||||
UART_CLOCK_IN_OSC,
|
||||
UART_CLOCK_IN_LSB,
|
||||
UART_CLOCK_IN_DISABLE,
|
||||
};
|
||||
|
||||
#define PLL_FM_SEL(x) SFR(JL_CLOCK->CLK_CON2, 12, 2, x)
|
||||
//for MACRO - PLL_APC_SEL
|
||||
enum {
|
||||
PLL_APC_SEL_PLL192M = 0,
|
||||
PLL_APC_SEL_PLL137M,
|
||||
PLL_APC_SEL_PLL107M,
|
||||
PLL_APC_SEL_DISABLE,
|
||||
};
|
||||
|
||||
#define PLL_FM_DIV(x) SFR(JL_CLOCK->CLK_CON2, 14, 4, x)
|
||||
//for MACRO - PLL_APC_DIV
|
||||
enum {
|
||||
PLL_FM_DIV1 = 0,
|
||||
PLL_FM_DIV3,
|
||||
PLL_FM_DIV5,
|
||||
PLL_FM_DIV7,
|
||||
|
||||
PLL_FM_DIV1X2 = 4,
|
||||
PLL_FM_DIV3X2,
|
||||
PLL_FM_DIV5X2,
|
||||
PLL_FM_DIV7X2,
|
||||
|
||||
PLL_FM_DIV1X4 = 8,
|
||||
PLL_FM_DIV3X4,
|
||||
PLL_FM_DIV5X4,
|
||||
PLL_FM_DIV7X4,
|
||||
|
||||
PLL_FM_DIV1X8 = 12,
|
||||
PLL_FM_DIV3X8,
|
||||
PLL_FM_DIV5X8,
|
||||
PLL_FM_DIV7X8,
|
||||
};
|
||||
#define GPCNT_CLOCK_IN(x) SFR(JL_CLOCK->CLK_CON2, 28, 4, x)
|
||||
//for MACRO - DAC_CLOCK_IN
|
||||
enum {
|
||||
GPCNT_CLOCK_IN_NULL = 0,
|
||||
GPCNT_CLOCK_IN_SRC,
|
||||
GPCNT_CLOCK_IN_ORG,
|
||||
GPCNT_CLOCK_IN_HSB,
|
||||
GPCNT_CLOCK_IN_XOSC_FSCK,
|
||||
GPCNT_CLOCK_IN_BTOSC_48M,
|
||||
GPCNT_CLOCK_IN_WL,
|
||||
GPCNT_CLOCK_IN_USB,
|
||||
GPCNT_CLOCK_IN_PMU_ANA,
|
||||
GPCNT_CLOCK_IN_VAD_VCON0,
|
||||
GPCNT_CLOCK_IN_VAD_VCOP0,
|
||||
GPCNT_CLOCK_IN_RC_16M,
|
||||
GPCNT_CLOCK_IN_P33_RC_250k,
|
||||
GPCNT_CLOCK_IN_LRC,
|
||||
GPCNT_CLOCK_IN_DPLL_OUT,
|
||||
GPCNT_CLOCK_IN_RTC_OSC,
|
||||
};
|
||||
|
||||
#define PLL_IMD_SEL_GET( ) ((JL_CLOCK->CLK_CON3 >> 8) & 0xF)
|
||||
#define PLL_IMD_SEL(x) SFR(JL_CLOCK->CLK_CON3, 8, 4, x)
|
||||
#define PLL_IMD_DIV(x) SFR(JL_CLOCK->CLK_CON3, 12, 4, x)
|
||||
|
||||
#define PLL_TDM_SEL_GET(x) ((JL_CLOCK->CLK_CON3 >> 24) & 0x7)
|
||||
#define PLL_TDM_SEL(x) SFR(JL_CLOCK->CLK_CON3, 24, 3, x)
|
||||
#define PLL_TDM_DIV(x) SFR(JL_CLOCK->CLK_CON3, 27, 2, x)
|
||||
|
||||
|
||||
#define PLL_EN(x) SFR(JL_PLL0->CON0, 0, 1, (x))
|
||||
#define PLL_REST(x) SFR(JL_PLL0->CON0, 1, 1, (x))
|
||||
#define PLL_MODE(x) SFR(JL_PLL0->CON0, 2, 1, (x))
|
||||
#define PLL_PFDS(x) SFR(JL_PLL0->CON0, 3, 2, (x))
|
||||
#define PLL_ICPS(x) SFR(JL_PLL0->CON0, 5, 3, (x))
|
||||
#define PLL_LPFR2(x) SFR(JL_PLL0->CON0, 8, 3, (x))
|
||||
#define PLL_IVCO(x) SFR(JL_PLL0->CON0, 11, 3, (x))
|
||||
#define PLL_LDO12A(x) SFR(JL_PLL0->CON0, 14, 3, (x))
|
||||
#define PLL_LDO12D(x) SFR(JL_PLL0->CON0, 17, 3, (x))
|
||||
#define PLL_LDO_BYPASS(x) SFR(JL_PLL0->CON0, 20, 1, (x))
|
||||
#define PLL_TSEL(x) SFR(JL_PLL0->CON0, 21, 2, x)
|
||||
#define PLL_TEST(x) SFR(JL_PLL0->CON0, 23, 1, x)
|
||||
#define PLL_VBG_TR(x) SFR(JL_PLL0->CON0, 27, 4, (x))
|
||||
|
||||
|
||||
|
||||
//REFDS
|
||||
#define PLL_DIVn(x) SFR(JL_PLL0->CON1, 0, 7, x)
|
||||
#define PLL_REF_SEL0(x) SFR(JL_PLL0->CON1, 7, 2, x)
|
||||
//for MACRO - PLL_RSEL0
|
||||
enum {
|
||||
PLL_RSEL_RCLK = 0, //
|
||||
PLL_RSEL_RCH,
|
||||
PLL_RSEL_DPLL_CLK,
|
||||
PLL_RSEL_PAT_CLK,
|
||||
};
|
||||
|
||||
#define PLL_REF_SEL1(x) SFR(JL_PLL0->CON1, 9, 1, x)
|
||||
//for MACRO - PLL_REF_SEL1
|
||||
enum {
|
||||
PLL_REF_SEL_BTOSC_DIFF = 0, //btosc_DIFF
|
||||
PLL_REF_SEL_RCLK,
|
||||
};
|
||||
|
||||
|
||||
#define PLL_DIVn_EN(x) SFR(JL_PLL0->CON1, 10, 2, x)
|
||||
//for MACRO - PLL_DIVn_EN
|
||||
enum {
|
||||
PLL_DIVn_EN_X2 = 0,
|
||||
PLL_DIVn_DIS_DIV1,
|
||||
PLL_DIVn_EN_DIVn,
|
||||
};
|
||||
|
||||
#define PLL_FBDS(x) SFR(JL_PLL0->CON2, 0, 12, x)
|
||||
|
||||
#define PLL_CLK_1DIV1_OE(x) SFR(JL_PLL0->CON3, 0, 1, x) //f1
|
||||
#define PLL_CLK_3DIV2_OE(x) SFR(JL_PLL0->CON3, 1, 1, x) //f2
|
||||
#define PLL_CLK_4DIV2_OE(x) SFR(JL_PLL0->CON3, 2, 1, x) //f3
|
||||
#define PLL_CLK_5DIV2_OE(x) SFR(JL_PLL0->CON3, 3, 1, x) //f4
|
||||
#define PLL_CLK_7DIV2_OE(x) SFR(JL_PLL0->CON3, 4, 1, x) //f5
|
||||
|
||||
#define PLL_CLK_EN(x) SFR(JL_PLL0->CON3, 9, 1, x)
|
||||
|
||||
|
||||
#define PLL1_EN(x) SFR(JL_PLL1->CON0, 0, 1, (x))
|
||||
#define PLL1_REST(x) SFR(JL_PLL1->CON0, 1, 1, (x))
|
||||
#define PLL1_MODE(x) SFR(JL_PLL1->CON0, 2, 1, (x))
|
||||
#define PLL1_PFDS(x) SFR(JL_PLL1->CON0, 3, 2, (x))
|
||||
#define PLL1_ICPS(x) SFR(JL_PLL1->CON0, 5, 3, (x))
|
||||
#define PLL1_LPFR2(x) SFR(JL_PLL1->CON0, 8, 3, (x))
|
||||
#define PLL1_IVCO(x) SFR(JL_PLL1->CON0, 11, 3, (x))
|
||||
#define PLL1_LDO12A(x) SFR(JL_PLL1->CON0, 14, 3, (x))
|
||||
#define PLL1_LDO12D(x) SFR(JL_PLL1->CON0, 17, 3, (x))
|
||||
#define PLL1_LDO_BYPASS(x) SFR(JL_PLL1->CON0, 20, 1, (x))
|
||||
#define PLL1_TSEL(x) SFR(JL_PLL1->CON0, 21, 2, x)
|
||||
#define PLL1_TEST(x) SFR(JL_PLL1->CON0, 23, 1, x)
|
||||
#define PLL1_VBG_TR(x) SFR(JL_PLL1->CON0, 27, 4, (x))
|
||||
|
||||
#define PLL1_DIVn(x) SFR(JL_PLL1->CON1, 0, 7, x)
|
||||
#define PLL1_REF_SEL0(x) SFR(JL_PLL1->CON1, 7, 2, x)
|
||||
#define PLL1_REF_SEL1(x) SFR(JL_PLL1->CON1, 9, 1, x)
|
||||
#define PLL1_DIVn_EN(x) SFR(JL_PLL1->CON1, 10, 2, x)
|
||||
|
||||
#define PLL1_FBDS(x) SFR(JL_PLL1->CON2, 0, 12, x)
|
||||
|
||||
#define PLL1_CLK_1DIV1_OE(x) SFR(JL_PLL1->CON3, 0, 1, x) //f1
|
||||
#define PLL1_CLK_3DIV2_OE(x) SFR(JL_PLL1->CON3, 1, 1, x) //f2
|
||||
#define PLL1_CLK_4DIV2_OE(x) SFR(JL_PLL1->CON3, 2, 1, x) //f3
|
||||
#define PLL1_CLK_5DIV2_OE(x) SFR(JL_PLL1->CON3, 3, 1, x) //f4
|
||||
#define PLL1_CLK_7DIV2_OE(x) SFR(JL_PLL1->CON3, 4, 1, x) //f5
|
||||
#define PLL1_CLK_EN(x) SFR(JL_PLL1->CON3, 9, 1, x)
|
||||
|
||||
|
||||
#define HSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 0, 8, x)
|
||||
#define LSB_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 8, 3, x)
|
||||
#define SFC_CLK_DIV(x) SFR(JL_CLOCK->SYS_DIV, 12, 3, x)
|
||||
|
||||
/********************************************************************************/
|
||||
#define GPCNT_EN(x) SFR(JL_GPCNT->CON, 0, 1, x)
|
||||
#define GPCNT_CSS(x) SFR(JL_GPCNT->CON, 1, 3, x)
|
||||
//for MACRO - GPCNT_CSS
|
||||
enum {
|
||||
GPCNT_CSS_LSB = 0,
|
||||
GPCNT_CSS_OSC,
|
||||
GPCNT_CSS_INPUT_CH2,
|
||||
GPCNT_CSS_INPUT_CH3,
|
||||
GPCNT_CSS_CLOCK_IN,
|
||||
GPCNT_CSS_RING,
|
||||
GPCNT_CSS_PLL,
|
||||
GPCNT_CSS_INTPUT_CH1,
|
||||
};
|
||||
|
||||
#define GPCNT_CLR_PEND(x) SFR(JL_GPCNT->CON, 6, 1, x)
|
||||
#define GPCNT_GTS(x) SFR(JL_GPCNT->CON, 8, 4, x)
|
||||
|
||||
#define GPCNT_GSS(x) SFR(JL_GPCNT->CON, 12, 3, x)
|
||||
//for MACRO - GPCNT_CSS
|
||||
enum {
|
||||
GPCNT_GSS_LSB = 0,
|
||||
GPCNT_GSS_OSC,
|
||||
GPCNT_GSS_INPUT_CH14, //iomap con1[27:24]
|
||||
GPCNT_GSS_INPUT_CH15, //iomap con1[31:28]
|
||||
GPCNT_GSS_CLOCK_IN, //CLK_CON2[31:28]
|
||||
GPCNT_GSS_RING,
|
||||
GPCNT_GSS_PLL,
|
||||
GPCNT_GSS_INPUT_CH13, //iomap con1[23:20]
|
||||
};
|
||||
|
||||
//wla_con16 xosc
|
||||
#define XOSC_BGTR_10v_4(x) ((x&0xf)<<15)
|
||||
|
||||
//wla_con8 xosc
|
||||
#define XOSC_EN_10v_1(x) ((x&0x1)<<0)
|
||||
#define XOSCLDO_PAS_10v_1(x) ((x&0x1)<<1)
|
||||
#define XOSCLDO_S_10v_3(x) ((x&0x7)<<2)
|
||||
#define XOSC_CPTEST_EN_10v_1(x) ((x&0x1)<<5)
|
||||
#define XOSC_HCS_10v_5(x) ((x&0x1f)<<6)
|
||||
#define XOSC_CLS_10v_4(x) ((x&0xf)<<11)
|
||||
#define XOSC_CRS_10v_4(x) ((x&0xf)<<15)
|
||||
#define XOSC_BT_HDS_10v_2(x) ((x&0x3)<<19)
|
||||
#define XOSC_ANATEST_EN_10v_1(x) ((x&0x1)<<21)
|
||||
#define XOSC_ANATEST_S_10v_3(x) ((x&0x7)<<22)
|
||||
#define XOSC_BT_OE_10v_1(x) ((x&0x1)<<25)
|
||||
#define XOSC_SYS1_OE_10v_1(x) ((x&0x1)<<26)
|
||||
#define XOSC_CORE48M_OE_10v_1(x) ((x&0x1)<<27)
|
||||
#define XOSC_CORE48M_S_10v_3(x) ((x&0x7)<<28)
|
||||
#define XOSC_FSCK_OE_10v_1(x) ((x&0x1)<<31)
|
||||
|
||||
//wla_con9 xosc
|
||||
#define XOSC_FTCS_10v_3(x) ((x&0x7)<<0)
|
||||
#define XOSC_FTOE_10v_1(x) ((x&0x1)<<3)
|
||||
#define XOSC_FTIS_10v_5(x) ((x&0x1f)<<4)
|
||||
#define XOSC_CORE24M_OE_10v_1(x) ((x&0x1)<<9)
|
||||
#define XOSC_CMP_MODE_10v_1(x) ((x&0x1)<<10)
|
||||
#define XOSC_FTEN_10v_1(x) ((x&0x1)<<11)
|
||||
#define XOSC_PMU_HDS_10v_2(x) ((x&0x3)<<12)
|
||||
#define XOSC_PMU_OE_10v_1(x) ((x&0x1)<<14)
|
||||
#define XOSC_SYS1_HDS_10v_2(x) ((x&0x3)<<15)
|
||||
#define XOSC_DAC_HDS_10v_2(x) ((x&0x3)<<17)
|
||||
#define XOSC_DAC_OE_10v_1(x) ((x&0x1)<<19)
|
||||
#define XOSC_LFSREN_10v_1(x) ((x&0x1)<<20)
|
||||
|
||||
//wla_con10
|
||||
//PLL
|
||||
#define XOSC_ADET_EN_10v_1(x) ((x&0x1)<<0)
|
||||
#define XOSC_ADET_S_10v_2(x) ((x&0x3)<<1)
|
||||
#define XOSC_VAD_DIVS_10v_4(x) ((x&0xf)<<3)
|
||||
#define XOSC_SYS0_HDS_10v_2(x) ((x&0x3)<<7)
|
||||
#define XOSC_SYS0_OE_10v_1(x) ((x&0x1)<<9)
|
||||
#define XOSC_VAD_HDS_10v_2(x) ((x&0x3)<<10)
|
||||
#define XOSC_VAD_OE_10v_1(x) ((x&0x1)<<12)
|
||||
|
||||
//wla_con21
|
||||
#define WLA_RD_MUX_4(x) ((x&0xf)<<0)
|
||||
|
||||
//wla_con30
|
||||
#define XOSC_ADET_GET_RESULT() ((JL_WLA->WLA_CON30 >> 4) & 1)
|
||||
|
||||
|
||||
//CORE
|
||||
#define ROM_MULTI_CYCLE(x) SFR(JL_CMNG->CON0,3,2,(x))
|
||||
#endif
|
||||
380
include_lib/driver/cpu/br28/asm/cpu.h
Normal file
380
include_lib/driver/cpu/br28/asm/cpu.h
Normal file
@ -0,0 +1,380 @@
|
||||
|
||||
#ifndef ASM_CPU_H
|
||||
#define ASM_CPU_H
|
||||
|
||||
|
||||
#include "br28.h"
|
||||
#include "csfr.h"
|
||||
#include "cache.h"
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef unsigned char u8, bool, BOOL;
|
||||
typedef char s8;
|
||||
typedef unsigned short u16;
|
||||
typedef signed short s16;
|
||||
typedef unsigned int u32;
|
||||
typedef signed int s32;
|
||||
typedef unsigned long long u64;
|
||||
typedef u32 FOURCC;
|
||||
typedef long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define ___trig __asm__ volatile ("trigger")
|
||||
|
||||
|
||||
#ifndef BIG_ENDIAN
|
||||
#define BIG_ENDIAN 0x3021
|
||||
#endif
|
||||
#ifndef LITTLE_ENDIAN
|
||||
#define LITTLE_ENDIAN 0x4576
|
||||
#endif
|
||||
#define CPU_ENDIAN LITTLE_ENDIAN
|
||||
|
||||
#ifdef BT_DUT_INTERFERE
|
||||
#define CPU_CORE_NUM 1 //dut interfere
|
||||
#else
|
||||
#define CPU_CORE_NUM 2 //sdk
|
||||
#endif
|
||||
|
||||
#define OS_CORE_AFFINITY_ENABLE 1
|
||||
|
||||
extern const int CONFIG_CPU_UNMASK_IRQ_ENABLE;
|
||||
|
||||
///屏蔽的优先级, < N的优先级不可以响应
|
||||
#define CPU_IRQ_IPMASK_LEVEL 6
|
||||
|
||||
#define CPU_TASK_CLR(a)
|
||||
#define CPU_TASK_SW(a) \
|
||||
do { \
|
||||
q32DSP(a)->ILAT_SET |= BIT(3-a); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define CPU_INT_NESTING 2
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#if CPU_CORE_NUM > 1
|
||||
__attribute__((always_inline))
|
||||
static int current_cpu_id()
|
||||
{
|
||||
unsigned id;
|
||||
asm volatile("%0 = cnum" : "=r"(id) ::);
|
||||
return id ;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static int core_num(void)
|
||||
{
|
||||
u32 num;
|
||||
asm volatile("%0 = cnum" : "=r"(num) :);
|
||||
return num;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int current_cpu_id()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int core_num(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int cpu_in_irq()
|
||||
{
|
||||
int flag;
|
||||
__asm__ volatile("%0 = icfg" : "=r"(flag));
|
||||
return flag & 0xff;
|
||||
}
|
||||
|
||||
extern int __cpu_irq_disabled(void);
|
||||
static inline int cpu_irq_disabled()
|
||||
{
|
||||
if (CONFIG_CPU_UNMASK_IRQ_ENABLE) {
|
||||
return __cpu_irq_disabled();
|
||||
} else {
|
||||
int flag;
|
||||
__asm__ volatile("%0 = icfg" : "=r"(flag));
|
||||
return ((flag & 0x300) != 0x300);
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
static inline int data_sat_s16(int ind)
|
||||
{
|
||||
if (ind > 32767) {
|
||||
ind = 32767;
|
||||
} else if (ind < -32768) {
|
||||
ind = -32768;
|
||||
}
|
||||
return ind;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int data_sat_s16(int ind)
|
||||
{
|
||||
__asm__ volatile(
|
||||
" %0 = sat16(%0)(s) \t\n"
|
||||
: "=&r"(ind)
|
||||
: "0"(ind)
|
||||
:);
|
||||
return ind;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static inline u32 reverse_u32(u32 data32)
|
||||
{
|
||||
#if 0
|
||||
u8 *dataptr = (u8 *)(&data32);
|
||||
data32 = (((u32)dataptr[0] << 24) | ((u32)dataptr[1] << 16) | ((u32)dataptr[2] << 8) | (u32)dataptr[3]);
|
||||
#else
|
||||
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(data32) : "0"(data32) :);
|
||||
#endif
|
||||
return data32;
|
||||
}
|
||||
|
||||
static inline u32 reverse_u16(u16 data16)
|
||||
{
|
||||
u32 retv;
|
||||
#if 0
|
||||
u8 *dataptr = (u8 *)(&data16);
|
||||
retv = (((u32)dataptr[0] << 8) | ((u32)dataptr[1]));
|
||||
#else
|
||||
retv = ((u32)data16) << 16;
|
||||
__asm__ volatile("%0 = rev8(%0) \t\n" : "=&r"(retv) : "0"(retv) :);
|
||||
#endif
|
||||
return retv;
|
||||
}
|
||||
|
||||
static inline u32 rand32()
|
||||
{
|
||||
return JL_RAND->R64L;
|
||||
}
|
||||
|
||||
#define __asm_sine(s64, precision) \
|
||||
({ \
|
||||
u64 ret; \
|
||||
u8 sel = 0; \
|
||||
__asm__ volatile ("%0 = copex(%1) (%2)" : "=r"(ret) : "r"(s64), "i"(sel)); \
|
||||
ret = ret>>32; \
|
||||
ret;\
|
||||
})
|
||||
|
||||
void p33_soft_reset(void);
|
||||
static inline void cpu_reset(void)
|
||||
{
|
||||
// JL_CLOCK->PWR_CON |= (1 << 4);
|
||||
p33_soft_reset();
|
||||
}
|
||||
|
||||
#define __asm_csync() \
|
||||
do { \
|
||||
asm volatile("csync;"); \
|
||||
} while (0)
|
||||
|
||||
#include "asm/irq.h"
|
||||
#include "generic/printf.h"
|
||||
#include "system/generic/log.h"
|
||||
|
||||
|
||||
#define arch_atomic_read(v) \
|
||||
({ \
|
||||
__asm_csync(); \
|
||||
(*(volatile int *)&(v)->counter); \
|
||||
})
|
||||
#if 0
|
||||
extern volatile int cpu_lock_cnt[];
|
||||
extern volatile int irq_lock_cnt[];
|
||||
|
||||
|
||||
static inline void local_irq_disable()
|
||||
{
|
||||
__builtin_pi32v2_cli();
|
||||
irq_lock_cnt[current_cpu_id()]++;
|
||||
}
|
||||
|
||||
|
||||
static inline void local_irq_enable()
|
||||
{
|
||||
if (--irq_lock_cnt[current_cpu_id()] == 0) {
|
||||
__builtin_pi32v2_sti();
|
||||
}
|
||||
}
|
||||
#else
|
||||
|
||||
extern void __local_irq_disable() ;
|
||||
|
||||
extern void __local_irq_enable() ;
|
||||
|
||||
extern void local_irq_disable();
|
||||
extern void local_irq_enable();
|
||||
|
||||
#endif
|
||||
|
||||
#if(0 )
|
||||
|
||||
#define arch_spin_trylock(lock) \
|
||||
do { \
|
||||
__asm_csync(); \
|
||||
while ((lock)->rwlock); \
|
||||
(lock)->rwlock = 1; \
|
||||
}while(0)
|
||||
|
||||
#define arch_spin_lock(lock) \
|
||||
do { \
|
||||
int ret = false; \
|
||||
__asm_csync(); \
|
||||
if (!(lock)->rwlock) { \
|
||||
ret = true; \
|
||||
(lock)->rwlock = 1; \
|
||||
} \
|
||||
if (ret) \
|
||||
break; \
|
||||
}while(1)
|
||||
|
||||
#define arch_spin_unlock(lock) \
|
||||
do { \
|
||||
(lock)->rwlock = 0; \
|
||||
}while(0)
|
||||
|
||||
#else
|
||||
|
||||
|
||||
|
||||
static inline void q32DSP_testset(u8 volatile *ptr)
|
||||
{
|
||||
asm volatile(
|
||||
" 1: \n\t "
|
||||
" testset b[%0] \n\t "
|
||||
" ifeq goto 1b \n\t "
|
||||
:
|
||||
: "p"(ptr)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void q32DSP_testclr(u8 volatile *ptr)
|
||||
{
|
||||
asm volatile(
|
||||
" b[%0] = %1 \n\t "
|
||||
:
|
||||
: "p"(ptr), "r"(0)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
#define arch_spin_trylock(lock) \
|
||||
do { \
|
||||
q32DSP_testset((u8 *)(&lock->rwlock));\
|
||||
}while(0)
|
||||
|
||||
|
||||
#define arch_spin_lock(lock) arch_spin_trylock(lock)
|
||||
|
||||
#define arch_spin_unlock(lock) \
|
||||
do{ \
|
||||
q32DSP_testclr((u8 *)(&lock->rwlock)) ;\
|
||||
}while(0)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#if 1 // CPU_CORE_NUM >1
|
||||
|
||||
extern volatile int cpu_lock_cnt[];
|
||||
extern volatile int irq_lock_cnt[];
|
||||
#if 0
|
||||
#define CPU_SR_ALLOC() \
|
||||
// int flags
|
||||
|
||||
|
||||
|
||||
|
||||
#define CPU_CRITICAL_ENTER() \
|
||||
do { extern u8 volatile cpulock;\
|
||||
local_irq_disable(); \
|
||||
if(cpu_lock_cnt[current_cpu_id()]++ == 0) \
|
||||
q32DSP_testset(&cpulock);\
|
||||
__asm_csync(); \
|
||||
}while(0)
|
||||
|
||||
// asm volatile("lockset;");
|
||||
|
||||
#define CPU_CRITICAL_EXIT() \
|
||||
do {extern u8 volatile cpulock; \
|
||||
if (--cpu_lock_cnt[current_cpu_id()] == 0) \
|
||||
q32DSP_testclr(&cpulock);\
|
||||
local_irq_enable();\
|
||||
}while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define CPU_SR_ALLOC() \
|
||||
// int flags
|
||||
|
||||
#define CPU_CRITICAL_ENTER() \
|
||||
do { \
|
||||
local_irq_disable(); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define CPU_CRITICAL_EXIT() \
|
||||
do { \
|
||||
local_irq_enable(); \
|
||||
}while(0)
|
||||
|
||||
// asm volatile("lockclr;");
|
||||
#else
|
||||
|
||||
|
||||
#define CPU_SR_ALLOC() \
|
||||
// int flags
|
||||
|
||||
#define CPU_CRITICAL_ENTER() \
|
||||
do { \
|
||||
local_irq_disable(); \
|
||||
__asm_csync(); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define CPU_CRITICAL_EXIT() \
|
||||
do { \
|
||||
local_irq_enable(); \
|
||||
}while(0)
|
||||
|
||||
#endif
|
||||
|
||||
extern void cpu_assert_debug();
|
||||
extern const int config_asser;
|
||||
#define ASSERT(a,...) \
|
||||
do { \
|
||||
if(config_asser){\
|
||||
if(!(a)){ \
|
||||
printf("cpu %d file:%s, line:%d",current_cpu_id(), __FILE__, __LINE__); \
|
||||
printf("ASSERT-FAILD: "#a" "__VA_ARGS__); \
|
||||
cpu_assert_debug(); \
|
||||
} \
|
||||
}else {\
|
||||
if(!(a)){ \
|
||||
cpu_reset(); \
|
||||
}\
|
||||
}\
|
||||
}while(0);
|
||||
|
||||
|
||||
|
||||
#endif //__ASSEMBLY__
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
35
include_lib/driver/cpu/br28/asm/crc16.h
Normal file
35
include_lib/driver/cpu/br28/asm/crc16.h
Normal file
@ -0,0 +1,35 @@
|
||||
#ifndef __CPU_CRC16_H__
|
||||
#define __CPU_CRC16_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
|
||||
u16 CRC16(const void *ptr, u32 len);
|
||||
|
||||
/* i_val: CRC校验初值 */
|
||||
u16 CRC16_with_initval(const void *ptr, u32 len, u16 i_val);
|
||||
|
||||
u16 CRC16_with_code(const void *ptr, u32 len, u16 code);
|
||||
|
||||
void spi_crc16_set(u16 crc);
|
||||
u16 spi_crc16_get(void);
|
||||
|
||||
void CrcDecode(void *buf, u16 len);
|
||||
|
||||
u16 get_page_efuse(u32 page, u32 delay_cnt);
|
||||
void init_enc_key(u8 cmd);
|
||||
u32 get_sfc_enc_key(void);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
406
include_lib/driver/cpu/br28/asm/csfr.h
Normal file
406
include_lib/driver/cpu/br28/asm/csfr.h
Normal file
@ -0,0 +1,406 @@
|
||||
//*********************************************************************************//
|
||||
// Module name : csfr.h //
|
||||
// Description : q32DSP core sfr define //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#ifndef __Q32DSP_CSFR__
|
||||
#define __Q32DSP_CSFR__
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define csfr_base 0xff0000
|
||||
|
||||
//*********************************************************************************
|
||||
//
|
||||
// hcore_sfr
|
||||
//
|
||||
//*********************************************************************************
|
||||
|
||||
//............. 0x0000 - 0x00ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
} JL_CMNG_TypeDef;
|
||||
|
||||
#define JL_CMNG_BASE (csfr_base + map_adr(0x00, 0x00))
|
||||
#define JL_CMNG ((JL_CMNG_TypeDef *)JL_CMNG_BASE)
|
||||
|
||||
//............. 0x0100 - 0x01ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 KEY;
|
||||
} JL_SDTAP_TypeDef;
|
||||
|
||||
#define JL_SDTAP_BASE (csfr_base + map_adr(0x01, 0x00))
|
||||
#define JL_SDTAP ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)
|
||||
|
||||
//............. 0x0200 - 0x02ff............
|
||||
typedef struct {
|
||||
__RW __u32 WREN;
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 CON3;
|
||||
__RW __u32 MSG0;
|
||||
__RW __u32 MSG1;
|
||||
__RW __u32 MSG2;
|
||||
__RW __u32 MSG3;
|
||||
__RO __u32 ID;
|
||||
} JL_CEMU_TypeDef;
|
||||
|
||||
#define JL_CEMU_BASE (csfr_base + map_adr(0x02, 0x00))
|
||||
#define JL_CEMU ((JL_CEMU_TypeDef *)JL_CEMU_BASE)
|
||||
|
||||
//............. 0x0300 - 0x03ff............
|
||||
#define MPU_INV (1<<31)
|
||||
#define MPU_PWEN (1<<16)
|
||||
#define MPU_PREN (1<<8)
|
||||
#define MPU_PEN (MPU_PWEN | MPU_PREN)
|
||||
#define MPU_XEN (1<<2)
|
||||
#define MPU_WEN (1<<1)
|
||||
#define MPU_REN (1<<0)
|
||||
|
||||
#define MPU_IDx_cfg(n, id) (id<<(n*8))
|
||||
#define MPU_IDx_pen(n, pr, pw) ((pr<<(9+n)) | (pw<<(17+n)))
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON[15]; // 0-7 used in br28
|
||||
__RO __u32 REV0;
|
||||
__RW __u32 CID[15]; // 0-7 used in br28
|
||||
__RO __u32 REV1;
|
||||
__RW __u32 BEG[15]; // 0-7 used in br28
|
||||
__RO __u32 REV2;
|
||||
__RW __u32 END[15]; // 0-7 used in br28
|
||||
__RW __u32 WREN;
|
||||
} JL_MPU_TypeDef;
|
||||
|
||||
#define JL_MPU_BASE (csfr_base + map_adr(0x03, 0x00))
|
||||
#define JL_MPU ((JL_MPU_TypeDef *)JL_MPU_BASE)
|
||||
|
||||
//............. 0x0400 - 0x04ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 TLB1_BEG;
|
||||
__RW __u32 TLB1_END;
|
||||
} JL_MMU_TypeDef;
|
||||
|
||||
#define JL_MMU_BASE (csfr_base + map_adr(0x04, 0x00))
|
||||
#define JL_MMU ((JL_MMU_TypeDef *)JL_MMU_BASE)
|
||||
|
||||
typedef struct {
|
||||
short page: 15;
|
||||
short vld: 1;
|
||||
} JL_MMU_TLB1_TypeDef;
|
||||
|
||||
#define JL_MMU_TLB1 ((JL_MMU_TLB1_TypeDef *)(JL_MMU->TLB1_BEG))
|
||||
|
||||
//............. 0x0500 - 0x05ff............
|
||||
//#define JL_TypeDef_L1P JL_TypeDef_q32DSP_ICU
|
||||
#define JL_TypeDef_L1P JL_TypeDef_q32DSP_DCU
|
||||
#define JL_L1P_BASE (csfr_base + map_adr(0x05, 0x00))
|
||||
#define JL_L1P ((JL_TypeDef_L1P *)JL_L1P_BASE)
|
||||
|
||||
//............. 0x0600 - 0x06ff............
|
||||
#define JL_TypeDef_L2I JL_TypeDef_q32DSP_ICU
|
||||
#define JL_L2I_BASE (csfr_base + map_adr(0x06, 0x00))
|
||||
#define JL_L2I ((JL_TypeDef_L2I *)JL_L2I_BASE)
|
||||
|
||||
//............. 0x0700 - 0x07ff............
|
||||
#define JL_TypeDef_L2D JL_TypeDef_q32DSP_DCU
|
||||
#define JL_L2D_BASE (csfr_base + map_adr(0x07, 0x00))
|
||||
#define JL_L2D ((JL_TypeDef_L2D *)JL_L2D_BASE)
|
||||
|
||||
//............. 0x0800 - 0x08ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 SEL;
|
||||
__RW __u32 DP;
|
||||
__RW __u32 DAT_VLD0;
|
||||
__RW __u32 DAT_VLD1;
|
||||
__RW __u32 DAT_VLD2;
|
||||
__RW __u32 DAT_VLD3;
|
||||
__RW __u32 ROM_CRC;
|
||||
} JL_MBIST_TypeDef;
|
||||
|
||||
#define JL_MBIST_BASE (csfr_base + map_adr(0x08, 0x00))
|
||||
#define JL_MBIST ((JL_MBIST_TypeDef *)JL_MBIST_BASE)
|
||||
|
||||
//............. 0x0900 - 0x09ff............
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 CADR;
|
||||
__RW __u32 ACC0L;
|
||||
__RW __u32 ACC0H;
|
||||
__RW __u32 ACC1L;
|
||||
__RW __u32 ACC1H;
|
||||
__RW __u32 CONST;
|
||||
__RW __u32 TEST1;
|
||||
} JL_FFT_TypeDef;
|
||||
|
||||
#define JL_FFT_BASE (csfr_base + map_adr(0x09, 0x00))
|
||||
#define JL_FFT ((JL_FFT_TypeDef *)JL_FFT_BASE)
|
||||
|
||||
|
||||
//*********************************************************************************
|
||||
//
|
||||
// q32DSP_sfr
|
||||
//
|
||||
//*********************************************************************************
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP define
|
||||
//---------------------------------------------//
|
||||
|
||||
#define q32DSP_sfr_offset 0x000800
|
||||
#define q32DSP_sfr_base (csfr_base + 0xe000)
|
||||
|
||||
#define q32DSP_cpu_base (q32DSP_sfr_base + 0x0000)
|
||||
#define q32DSP_icu_base (q32DSP_sfr_base + 0x0400)
|
||||
#define q32DSP_dcu_base (q32DSP_sfr_base + 0x0500)
|
||||
|
||||
#define q32DSP(n) ((JL_TypeDef_q32DSP *)(q32DSP_sfr_base + q32DSP_sfr_offset*n))
|
||||
#define q32DSP_icu(n) ((JL_TypeDef_q32DSP_ICU *)(q32DSP_icu_base + q32DSP_sfr_offset*n))
|
||||
#define q32DSP_dcu(n) ((JL_TypeDef_q32DSP_DCU *)(q32DSP_dcu_base + q32DSP_sfr_offset*n))
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP core sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
/* 00 */ __RO __u32 DR00;
|
||||
/* 01 */ __RO __u32 DR01;
|
||||
/* 02 */ __RO __u32 DR02;
|
||||
/* 03 */ __RO __u32 DR03;
|
||||
/* 04 */ __RO __u32 DR04;
|
||||
/* 05 */ __RO __u32 DR05;
|
||||
/* 06 */ __RO __u32 DR06;
|
||||
/* 07 */ __RO __u32 DR07;
|
||||
/* 08 */ __RO __u32 DR08;
|
||||
/* 09 */ __RO __u32 DR09;
|
||||
/* 0a */ __RO __u32 DR10;
|
||||
/* 0b */ __RO __u32 DR11;
|
||||
/* 0c */ __RO __u32 DR12;
|
||||
/* 0d */ __RO __u32 DR13;
|
||||
/* 0e */ __RO __u32 DR14;
|
||||
/* 0f */ __RO __u32 DR15;
|
||||
|
||||
/* 10 */ __RO __u32 RETI;
|
||||
/* 11 */ __RO __u32 RETE;
|
||||
/* 12 */ __RO __u32 RETX;
|
||||
/* 13 */ __RO __u32 RETS;
|
||||
/* 14 */ __RO __u32 SR04;
|
||||
/* 15 */ __RO __u32 PSR;
|
||||
/* 16 */ __RO __u32 CNUM;
|
||||
/* 17 */ __RO __u32 SR07;
|
||||
/* 18 */ __RO __u32 SR08;
|
||||
/* 19 */ __RO __u32 SR09;
|
||||
/* 1a */ __RO __u32 SR10;
|
||||
/* 1b */ __RO __u32 ICFG;
|
||||
/* 1c */ __RO __u32 USP;
|
||||
/* 1d */ __RO __u32 SSP;
|
||||
/* 1e */ __RO __u32 SP;
|
||||
/* 1f */ __RO __u32 PCRS;
|
||||
|
||||
/* 20 */ __RW __u32 BPCON;
|
||||
/* 21 */ __RW __u32 BSP;
|
||||
/* 22 */ __RW __u32 BP0;
|
||||
/* 23 */ __RW __u32 BP1;
|
||||
/* 24 */ __RW __u32 BP2;
|
||||
/* 25 */ __RW __u32 BP3;
|
||||
/* 26 */ __WO __u32 CMD_PAUSE;
|
||||
/* 27 */ __RW __u32 BP4;
|
||||
/* 28 */ __RW __u32 BP5;
|
||||
/* 29 */ __RW __u32 BP6;
|
||||
/* 2a */ __RW __u32 BP7;
|
||||
/* */ __RO __u32 REV2a[0x30 - 0x2a - 1];
|
||||
|
||||
/* 30 */ __RW __u32 PMU_CON0;
|
||||
/* 31 */ __RW __u32 PMU_CON1;
|
||||
/* */ __RO __u32 REV30[0x3b - 0x31 - 1];
|
||||
/* 3b */ __RW __u8 TTMR_CON;
|
||||
/* 3c */ __RW __u32 TTMR_CNT;
|
||||
/* 3d */ __RW __u32 TTMR_PRD;
|
||||
/* 3e */ __RW __u32 BANK_CON;
|
||||
/* 3f */ __RW __u32 BANK_NUM;
|
||||
|
||||
/* 40 */ __RW __u32 ICFG00;
|
||||
/* 41 */ __RW __u32 ICFG01;
|
||||
/* 42 */ __RW __u32 ICFG02;
|
||||
/* 43 */ __RW __u32 ICFG03;
|
||||
/* 44 */ __RW __u32 ICFG04;
|
||||
/* 45 */ __RW __u32 ICFG05;
|
||||
/* 46 */ __RW __u32 ICFG06;
|
||||
/* 47 */ __RW __u32 ICFG07;
|
||||
/* 48 */ __RW __u32 ICFG08;
|
||||
/* 49 */ __RW __u32 ICFG09;
|
||||
/* 4a */ __RW __u32 ICFG10;
|
||||
/* 4b */ __RW __u32 ICFG11;
|
||||
/* 4c */ __RW __u32 ICFG12;
|
||||
/* 4d */ __RW __u32 ICFG13;
|
||||
/* 4e */ __RW __u32 ICFG14;
|
||||
/* 4f */ __RW __u32 ICFG15;
|
||||
|
||||
/* 50 */ __RW __u32 ICFG16;
|
||||
/* 51 */ __RW __u32 ICFG17;
|
||||
/* 52 */ __RW __u32 ICFG18;
|
||||
/* 53 */ __RW __u32 ICFG19;
|
||||
/* 54 */ __RW __u32 ICFG20;
|
||||
/* 55 */ __RW __u32 ICFG21;
|
||||
/* 56 */ __RW __u32 ICFG22;
|
||||
/* 57 */ __RW __u32 ICFG23;
|
||||
/* 58 */ __RW __u32 ICFG24;
|
||||
/* 59 */ __RW __u32 ICFG25;
|
||||
/* 5a */ __RW __u32 ICFG26;
|
||||
/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
||||
/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
||||
|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV6a[0x70 - 0x6c - 1];
|
||||
|
||||
/* 70 */ __RW __u32 ETM_CON;
|
||||
/* 71 */ __RO __u32 ETM_PC0;
|
||||
/* 72 */ __RO __u32 ETM_PC1;
|
||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RW __u32 WP0_PC;
|
||||
/* */ __RO __u32 REV79[0x80 - 0x79 - 1];
|
||||
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RW __u32 EMU_SSP_H;
|
||||
/* 83 */ __RW __u32 EMU_SSP_L;
|
||||
/* 84 */ __RW __u32 EMU_USP_H;
|
||||
/* 85 */ __RW __u32 EMU_USP_L;
|
||||
/* 86 */ __RW __u32 LIM_PC0_H;
|
||||
/* 87 */ __RW __u32 LIM_PC0_L;
|
||||
/* 88 */ __RW __u32 LIM_PC1_H;
|
||||
/* 89 */ __RW __u32 LIM_PC1_L;
|
||||
/* 8a */ __RW __u32 LIM_PC2_H;
|
||||
/* 8b */ __RW __u32 LIM_PC2_L;
|
||||
/* */ __RO __u32 REV8b[0x90 - 0x8b - 1];
|
||||
|
||||
/* 90 */ __RW __u32 ESU_CON;
|
||||
/* 91 */ __RO __u32 CNT_CHIT;
|
||||
/* 92 */ __RO __u32 CNT_CMIS;
|
||||
/* 93 */ __RO __u32 CNT_FILL;
|
||||
/* 94 */ __RO __u32 CNT_IHIT;
|
||||
/* 95 */ __RO __u32 CNT_IMIS;
|
||||
/* 96 */ __RO __u32 CNT_RHIT;
|
||||
/* 97 */ __RO __u32 CNT_RMIS;
|
||||
/* 98 */ __RO __u32 CNT_WHIT;
|
||||
/* 99 */ __RO __u32 CNT_WMIS;
|
||||
} JL_TypeDef_q32DSP;
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP icache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CMD_CON;
|
||||
__RW __u32 CMD_BEG;
|
||||
__RW __u32 CMD_END;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 MBIST_CON;
|
||||
} JL_TypeDef_q32DSP_ICU;
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32DSP dcache sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 EMU_CON;
|
||||
__RW __u32 EMU_MSG;
|
||||
__RW __u32 EMU_ID;
|
||||
__RW __u32 CNT_WACK;
|
||||
__RW __u32 CNT_WNAK;
|
||||
__RW __u32 CNT_RACK;
|
||||
__RW __u32 CNT_RNAK;
|
||||
__RW __u32 MBIST_CON;
|
||||
__RO __u32 REV0[0x10 - 0x8 - 1];
|
||||
__RW __u32 CMD_CON[4];
|
||||
__RW __u32 CMD_BEG[4];
|
||||
__RW __u32 CMD_END[4];
|
||||
__RO __u32 REV1[0x20 - 0x1b - 1];
|
||||
__WO __u32 CMO[32];
|
||||
} JL_TypeDef_q32DSP_DCU;
|
||||
|
||||
typedef struct _CPU_REGS {
|
||||
unsigned int reti;
|
||||
unsigned int rets;
|
||||
unsigned int psr;
|
||||
unsigned int r0;
|
||||
unsigned int r1;
|
||||
unsigned int r2;
|
||||
unsigned int r3;
|
||||
unsigned int r4;
|
||||
unsigned int r5;
|
||||
unsigned int r6;
|
||||
unsigned int r7;
|
||||
unsigned int r8;
|
||||
unsigned int r9;
|
||||
unsigned int r10;
|
||||
unsigned int r11;
|
||||
unsigned int r12;
|
||||
unsigned int r13;
|
||||
unsigned int r14;
|
||||
unsigned int r15;
|
||||
} CPU_REGS;
|
||||
|
||||
|
||||
#define TICK_CON (q32DSP(0)->TTMR_CON)
|
||||
#define TICK_PRD (q32DSP(0)->TTMR_PRD)
|
||||
#define TICK_CNT (q32DSP(0)->TTMR_CNT)
|
||||
|
||||
#define SOFT_CLEAR_PENDING (q32DSP(0)->ILAT_CLR)
|
||||
|
||||
#define CPU_MSG (q32DSP(0)->EMU_MSG)
|
||||
#define CPU_CON (q32DSP(0)->EMU_CON)
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
#endif
|
||||
45
include_lib/driver/cpu/br28/asm/ctmu.h
Normal file
45
include_lib/driver/cpu/br28/asm/ctmu.h
Normal file
@ -0,0 +1,45 @@
|
||||
#ifndef _CTMU_DRV_H_
|
||||
#define _CTMU_DRV_H_
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
#define CTMU_KEY_CH_MAX 3
|
||||
|
||||
typedef struct _CTMU_KEY_VAR {
|
||||
s32 touch_release_buf[CTMU_KEY_CH_MAX]; //按键释放值滤波器buffer
|
||||
u16 touch_cnt_buf[CTMU_KEY_CH_MAX]; //按键计数值滤波器buffer
|
||||
s16 FLT1CFG1; //滤波器1配置参数1
|
||||
s16 FLT1CFG2; //滤波器1配置参数2, 等于(-RELEASECFG0)<<FLT1CFG0
|
||||
s16 PRESSCFG; //按下判决门限
|
||||
s16 RELEASECFG0; //释放判决门限0
|
||||
s16 RELEASECFG1; //释放判决门限1
|
||||
s8 FLT0CFG; //滤波器0配置参数(0/1/2/3)
|
||||
s8 FLT1CFG0; //滤波器1配置参数0
|
||||
u16 touch_key_state; //按键状态标志，随时可能被中断改写，按键处理程序需要将此标志复制出来再行处理
|
||||
u8 touch_init_cnt[CTMU_KEY_CH_MAX]; //初始化计数器，非0时进行初始化
|
||||
} sCTMU_KEY_VAR;
|
||||
|
||||
|
||||
struct ctmu_key_port {
|
||||
u8 port; //触摸按键IO
|
||||
u8 key_value; //按键返回值
|
||||
};
|
||||
|
||||
struct ctmu_touch_key_platform_data {
|
||||
u8 num; //触摸按键个数
|
||||
s16 press_cfg; //按下判决门限
|
||||
s16 release_cfg0; //释放判决门限0
|
||||
s16 release_cfg1; //释放判决门限1
|
||||
const struct ctmu_key_port *port_list;
|
||||
};
|
||||
|
||||
/* =========== ctmu API ============= */
|
||||
//ctmu 初始化
|
||||
int ctmu_init(void *_data);
|
||||
|
||||
//获取plcnt按键状态
|
||||
u8 get_ctmu_value(void);
|
||||
|
||||
|
||||
#endif /* #ifndef _CTMU_DRV_H_ */
|
||||
|
||||
87
include_lib/driver/cpu/br28/asm/debug.h
Normal file
87
include_lib/driver/cpu/br28/asm/debug.h
Normal file
@ -0,0 +1,87 @@
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief 异常检测模块初始化
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void debug_init();
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief 异常分析函数
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void exception_analyze();
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief 根据设备名获取设备ID
|
||||
*
|
||||
* @param name: 设备名称, 如:"DBG_SPI0"
|
||||
*
|
||||
* @return: 设备ID
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
u32 get_dev_id(char *name);
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief Memory权限保护设置
|
||||
*
|
||||
* @param idx: 保护框索引, 范围: 0 ~ 7, 目前系统默认使用0和3, 用户可用1, 2, 4, 5, 6, 7
|
||||
* @param begin: Memory开始地址
|
||||
* @param end: Memory结束地址
|
||||
* @param inv: 0: 保护框内, 1: 保护框外
|
||||
* @param format: "Cxwr0rw1rw2rw3rw", CPU:外设0:外设1:外设2:外设3,
|
||||
* @param ...: 外设ID号索引, 如: DBG_EQ, 见debug.h
|
||||
|
||||
* @example1: 设置内存保护框1, 保护地址为0x200 ~ 0x400 - 1, 令该地址只可以FFT和EQ设备访问:
|
||||
mpu_set(1, 0x200, 0x400 - 1, 0, "0rw1rw", get_dev_id("DBG_FFT"), get_dev_id("DBG_EQ"));
|
||||
* @example2: 设置内存保护框2, 保护地址为0x200 ~ 0x400 - 1, 令该地址只可以cpu读写和EQ设备访问:
|
||||
mpu_set(2, 0x200, 0x400 - 1, 0, "Crw0rw", get_dev_id("DBG_EQ"));
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_set(int idx, u32 begin, u32 end, u32 inv, const char *format, ...);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief 取消指定框的mpu保护
|
||||
*
|
||||
* @param idx: 保护框索引号
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_disable_by_index(u8 idx);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief :取消所有保护框mpu保护
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void mpu_diasble(void);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief flash PC范围设置为Flash外区域, 调用该接口后调用flash里的函数将触发异常
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void flash_pc_limit_disable();
|
||||
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
/**
|
||||
* @brief flash PC范围限制恢复为flash代码区域, 调用该接口后可调用flash里的函数
|
||||
*/
|
||||
/* ---------------------------------------------------------------------------- */
|
||||
void flash_pc_limit_enable();
|
||||
|
||||
|
||||
#endif /* #ifndef __DEBUG_H__ */
|
||||
|
||||
|
||||
33
include_lib/driver/cpu/br28/asm/efuse.h
Normal file
33
include_lib/driver/cpu/br28/asm/efuse.h
Normal file
@ -0,0 +1,33 @@
|
||||
#ifndef __EFUSE_H__
|
||||
#define __EFUSE_H__
|
||||
|
||||
|
||||
void efuse_init();
|
||||
u16 get_chip_id();
|
||||
u16 get_vbat_trim();
|
||||
u16 get_vbat_trim_435();
|
||||
u16 get_vbg_trim();
|
||||
u8 get_sysdvdd_trim();
|
||||
u32 get_chip_version();
|
||||
/* struct lrc_config_t { */
|
||||
/* u16 lrc_ws_inc; //from uboot */
|
||||
/* u16 lrc_ws_init; //from uboot */
|
||||
/* u16 btosc_ws_inc; //from uboot */
|
||||
/* u16 btosc_ws_init; //from uboot */
|
||||
/* u8 lrc_change_mode; //from uboot */
|
||||
/* }; */
|
||||
u16 get_lrc_ws_inc(); //from uboot
|
||||
u16 get_lrc_ws_init(); //from uboot
|
||||
u16 get_btosc_ws_inc(); //from uboot
|
||||
u16 get_btosc_ws_init(); //from uboot
|
||||
u8 get_lrc_change_mode(); //from uboot
|
||||
u8 get_wvdd_level_trim();
|
||||
|
||||
u32 get_boot_flag();
|
||||
void set_boot_flag(u32 flag);
|
||||
|
||||
u8 get_btvbg_xosc_trim();
|
||||
|
||||
u8 get_vad_vbg_trim();
|
||||
|
||||
#endif /*EFUSE_H*/
|
||||
825
include_lib/driver/cpu/br28/asm/gpio.h
Normal file
825
include_lib/driver/cpu/br28/asm/gpio.h
Normal file
@ -0,0 +1,825 @@
|
||||
/**
|
||||
* @file gpio.h
|
||||
* @brief
|
||||
* @author @zh-jieli.com
|
||||
* @version 1.0.0
|
||||
* @date 2018-10-11
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
#define IO_GROUP_NUM 16
|
||||
|
||||
|
||||
#define IO_PORTA_00 (IO_GROUP_NUM * 0 + 0)
|
||||
#define IO_PORTA_01 (IO_GROUP_NUM * 0 + 1)
|
||||
#define IO_PORTA_02 (IO_GROUP_NUM * 0 + 2)
|
||||
#define IO_PORTA_03 (IO_GROUP_NUM * 0 + 3)
|
||||
#define IO_PORTA_04 (IO_GROUP_NUM * 0 + 4)
|
||||
#define IO_PORTA_05 (IO_GROUP_NUM * 0 + 5)
|
||||
#define IO_PORTA_06 (IO_GROUP_NUM * 0 + 6)
|
||||
#define IO_PORTA_07 (IO_GROUP_NUM * 0 + 7)
|
||||
#define IO_PORTA_08 (IO_GROUP_NUM * 0 + 8)
|
||||
#define IO_PORTA_09 (IO_GROUP_NUM * 0 + 9)
|
||||
#define IO_PORTA_10 (IO_GROUP_NUM * 0 + 10)
|
||||
#define IO_PORTA_11 (IO_GROUP_NUM * 0 + 11)
|
||||
#define IO_PORTA_12 (IO_GROUP_NUM * 0 + 12)
|
||||
#define IO_PORTA_13 (IO_GROUP_NUM * 0 + 13)
|
||||
#define IO_PORTA_14 (IO_GROUP_NUM * 0 + 14)
|
||||
#define IO_PORTA_15 (IO_GROUP_NUM * 0 + 15)
|
||||
|
||||
#define IO_PORTB_00 (IO_GROUP_NUM * 1 + 0)
|
||||
#define IO_PORTB_01 (IO_GROUP_NUM * 1 + 1)
|
||||
#define IO_PORTB_02 (IO_GROUP_NUM * 1 + 2)
|
||||
#define IO_PORTB_03 (IO_GROUP_NUM * 1 + 3)
|
||||
#define IO_PORTB_04 (IO_GROUP_NUM * 1 + 4)
|
||||
#define IO_PORTB_05 (IO_GROUP_NUM * 1 + 5)
|
||||
#define IO_PORTB_06 (IO_GROUP_NUM * 1 + 6)
|
||||
#define IO_PORTB_07 (IO_GROUP_NUM * 1 + 7)
|
||||
#define IO_PORTB_08 (IO_GROUP_NUM * 1 + 8)
|
||||
#define IO_PORTB_09 (IO_GROUP_NUM * 1 + 9)
|
||||
#define IO_PORTB_10 (IO_GROUP_NUM * 1 + 10)
|
||||
#define IO_PORTB_11 (IO_GROUP_NUM * 1 + 11)
|
||||
|
||||
#define IO_PORTC_00 (IO_GROUP_NUM * 2 + 0)
|
||||
#define IO_PORTC_01 (IO_GROUP_NUM * 2 + 1)
|
||||
#define IO_PORTC_02 (IO_GROUP_NUM * 2 + 2)
|
||||
#define IO_PORTC_03 (IO_GROUP_NUM * 2 + 3)
|
||||
#define IO_PORTC_04 (IO_GROUP_NUM * 2 + 4)
|
||||
#define IO_PORTC_05 (IO_GROUP_NUM * 2 + 5)
|
||||
#define IO_PORTC_06 (IO_GROUP_NUM * 2 + 6)
|
||||
#define IO_PORTC_07 (IO_GROUP_NUM * 2 + 7)
|
||||
#define IO_PORTC_08 (IO_GROUP_NUM * 2 + 8)
|
||||
|
||||
#define IO_PORTD_00 (IO_GROUP_NUM * 3 + 0)
|
||||
#define IO_PORTD_01 (IO_GROUP_NUM * 3 + 1)
|
||||
#define IO_PORTD_02 (IO_GROUP_NUM * 3 + 2)
|
||||
#define IO_PORTD_03 (IO_GROUP_NUM * 3 + 3)
|
||||
#define IO_PORTD_04 (IO_GROUP_NUM * 3 + 4)
|
||||
#define IO_PORTD_05 (IO_GROUP_NUM * 3 + 5)
|
||||
#define IO_PORTD_06 (IO_GROUP_NUM * 3 + 6)
|
||||
|
||||
#define IO_PORTE_00 (IO_GROUP_NUM * 4 + 0)
|
||||
#define IO_PORTE_01 (IO_GROUP_NUM * 4 + 1)
|
||||
#define IO_PORTE_02 (IO_GROUP_NUM * 4 + 2)
|
||||
#define IO_PORTE_03 (IO_GROUP_NUM * 4 + 3)
|
||||
#define IO_PORTE_04 (IO_GROUP_NUM * 4 + 4)
|
||||
#define IO_PORTE_05 (IO_GROUP_NUM * 4 + 5)
|
||||
#define IO_PORTE_06 (IO_GROUP_NUM * 4 + 6)
|
||||
|
||||
#define IO_PORTG_00 (IO_GROUP_NUM * 5 + 0)
|
||||
#define IO_PORTG_01 (IO_GROUP_NUM * 5 + 1)
|
||||
#define IO_PORTG_02 (IO_GROUP_NUM * 5 + 2)
|
||||
#define IO_PORTG_03 (IO_GROUP_NUM * 5 + 3)
|
||||
#define IO_PORTG_04 (IO_GROUP_NUM * 5 + 4)
|
||||
#define IO_PORTG_05 (IO_GROUP_NUM * 5 + 5)
|
||||
#define IO_PORTG_06 (IO_GROUP_NUM * 5 + 6)
|
||||
#define IO_PORTG_07 (IO_GROUP_NUM * 5 + 7)
|
||||
#define IO_PORTG_08 (IO_GROUP_NUM * 5 + 8)
|
||||
|
||||
#define IO_PORTP_00 (IO_GROUP_NUM * 6 + 0)
|
||||
|
||||
#define IO_MAX_NUM (IO_PORTP_00 + 1)
|
||||
|
||||
#define IO_PORT_PR_00 (IO_MAX_NUM + 0)
|
||||
#define IO_PORT_PR_01 (IO_MAX_NUM + 1)
|
||||
#define IO_PORT_PR_02 (IO_MAX_NUM + 2)
|
||||
#define IO_PORT_PR_03 (IO_MAX_NUM + 3)
|
||||
#define IO_PORT_PR_04 (IO_MAX_NUM + 4)
|
||||
|
||||
#define USB_IO_OFFSET 5
|
||||
#define IO_PORT_DP (IO_MAX_NUM + USB_IO_OFFSET)
|
||||
#define IO_PORT_DM (IO_MAX_NUM + USB_IO_OFFSET + 1)
|
||||
|
||||
#define P33_IO_OFFSET 7
|
||||
#define IO_CHGFL_DET (IO_MAX_NUM + P33_IO_OFFSET + 0)
|
||||
#define IO_VBGOK_DET (IO_MAX_NUM + P33_IO_OFFSET + 1)
|
||||
#define IO_VBTCH_DET (IO_MAX_NUM + P33_IO_OFFSET + 2)
|
||||
#define IO_LDOIN_DET (IO_MAX_NUM + P33_IO_OFFSET + 3)
|
||||
|
||||
#define IO_PORT_MAX (IO_PORT_DM + 1)
|
||||
|
||||
#define GPIOA (IO_GROUP_NUM * 0)
|
||||
#define GPIOB (IO_GROUP_NUM * 1)
|
||||
#define GPIOC (IO_GROUP_NUM * 2)
|
||||
#define GPIOD (IO_GROUP_NUM * 3)
|
||||
#define GPIOE (IO_GROUP_NUM * 4)
|
||||
#define GPIOG (IO_GROUP_NUM * 5)
|
||||
#define GPIOP (IO_GROUP_NUM * 6)
|
||||
#define GPIOR (IO_MAX_NUM)
|
||||
#define GPIOUSB (IO_MAX_NUM + USB_IO_OFFSET)
|
||||
#define GPIOP33 (IO_MAX_NUM + P33_IO_OFFSET)
|
||||
|
||||
enum {
|
||||
INPUT_CH0,
|
||||
INPUT_CH1,
|
||||
INPUT_CH2,
|
||||
INPUT_CH3,
|
||||
};
|
||||
|
||||
enum {
|
||||
LOW_POWER_FREE = 0,
|
||||
LOW_POWER_KEEP = 1,
|
||||
};
|
||||
enum gpio_op_mode {
|
||||
GPIO_SET = 1,
|
||||
GPIO_AND,
|
||||
GPIO_OR,
|
||||
GPIO_XOR,
|
||||
};
|
||||
enum gpio_direction {
|
||||
GPIO_OUT = 0,
|
||||
GPIO_IN = 1,
|
||||
};
|
||||
struct gpio_reg {
|
||||
volatile unsigned int out;
|
||||
volatile unsigned int in;
|
||||
volatile unsigned int dir;
|
||||
volatile unsigned int die;
|
||||
volatile unsigned int pu;
|
||||
volatile unsigned int pd;
|
||||
volatile unsigned int hd0;
|
||||
volatile unsigned int hd;
|
||||
volatile unsigned int dieh;
|
||||
};
|
||||
|
||||
struct gpio_platform_data {
|
||||
unsigned int gpio;
|
||||
};
|
||||
|
||||
#define GPIO_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct gpio_platform_data data = { \
|
||||
|
||||
|
||||
#define GPIO_PLATFORM_DATA_END() \
|
||||
};
|
||||
#if 0
|
||||
#define IO_DEBUG_0(i,x) {JL_PORT##i->DIR &= ~BIT(x), JL_PORT##i->OUT &= ~BIT(x);}
|
||||
#define IO_DEBUG_1(i,x) {JL_PORT##i->DIR &= ~BIT(x), JL_PORT##i->OUT |= BIT(x);}
|
||||
#define IO_DEBUG_TOGGLE(i,x) {JL_PORT##i->DIR &= ~BIT(x), JL_PORT##i->OUT ^= BIT(x);}
|
||||
|
||||
|
||||
#else
|
||||
#define IO_DEBUG_0(i,x) {}
|
||||
#define IO_DEBUG_1(i,x) {}
|
||||
#define IO_DEBUG_TOGGLE(i,x) {}
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @brief usb_iomode
|
||||
*
|
||||
* @param enable 1，使能；0，关闭
|
||||
*/
|
||||
void usb_iomode(u32 enable);
|
||||
/**
|
||||
* @brief gpio_direction_input
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param dir 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_direction(u32 gpio, u32 dir);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_direction_input
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1, 0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_output_value(u32 gpio, u32 dir);
|
||||
|
||||
/**
|
||||
* @brief gpio_dir
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_dir(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_direction_output
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1；0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_direction_output(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_out
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，输入；0，输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_out(u32 gpio, u32 start, u32 len, u32 dat);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pull_up
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，上拉；0，不上拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_pull_up(u32 gpio, int value);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pu
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，上拉；0，不上拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_pu(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pull_down
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，下拉；0，不下拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_pull_down(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_pd
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，下拉；0，不下拉
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_pd(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_hd0
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，增强输出；0，不增强输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_hd0(u32 gpio, u32 value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_hd
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，增强输出；0，不增强输出
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_hd(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_die
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_set_die(u32 gpio, int value);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_dieh
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_dieh(u32 gpio, u32 value);
|
||||
|
||||
/**
|
||||
* @brief gpio_die
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_die(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_dieh
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
* @param start [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param len [0-15]，GPIOR[0-3]，GPIOUSB[0-1]
|
||||
* @param dat 1，IO普通输入；0，IO模拟输入
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_dieh(u32 gpio, u32 start, u32 len, u32 dat, enum gpio_op_mode op);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_output_channle
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param clk 参考枚举CHx_UTx_TX，如CH0_UT0_TX
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_output_channle(u32 gpio, u32 clk);
|
||||
|
||||
/**
|
||||
* @brief gpio_read
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int gpio_read(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_in
|
||||
*
|
||||
* @param gpio [GPIOA GPIOB GPIOC GPIOD GPIOR GPIOUSB]
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_in(u32 gpio);
|
||||
/**
|
||||
* @brief gpio_write
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
* @param value 1，输出1；0，输出0
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_write(u32 gpio, u32 value);
|
||||
|
||||
/**
|
||||
* @brief gpio_wakeup0 use IN_CHNL0_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_wakeup0(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_irflt_in use IN_CHNL1_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_irflt_in(u32 gpio);
|
||||
|
||||
/**
|
||||
* @brief gpio_cap_mux use IN_CHNL2_SEL
|
||||
*
|
||||
* @param gpio 参考宏IO_PORTx_xx，如IO_PORTA_00
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_cap_mux(u32 gpio);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_uart_rx_input
|
||||
*
|
||||
* @param gpio
|
||||
* @param ut
|
||||
* @param ch
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_uart_rx_input(u32 gpio, u32 ut, u32 ch);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart0(void);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart1(void);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_close_uart2(void);
|
||||
|
||||
/**
|
||||
* @brief gpio_set_uart0
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PA5_TX|PA6_RX|
|
||||
* |1|PB7_TX|PB8_RX|
|
||||
* |2|PA7_TX|PA8_RX|
|
||||
* |3|预留|预留|
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart0(u32 ch);
|
||||
/**
|
||||
* @brief gpio_set_uart1
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PB5_TX|PB6_RX|
|
||||
* |1|预留|预留|
|
||||
* |2|PA1_TX|PA2_RX|
|
||||
* |3|USBDP |USBDM |
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart1(u32 ch);
|
||||
/**
|
||||
* @brief gpio_set_uart2
|
||||
*
|
||||
* @param ch 0:3 选择对应IO br22
|
||||
* |ch|tx|rx|
|
||||
* |- |- |- |
|
||||
* |0|PA3_TX|PA4_RX|
|
||||
* |1|预留|预留|
|
||||
* |2|预留|预留|
|
||||
* |3|PA9_TX|PA10_RX|
|
||||
* |-1|关闭对应的IO口串口功能|no|
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_set_uart2(u32 ch);
|
||||
|
||||
enum {
|
||||
IRFLT_LSB,
|
||||
IRFLT_RC,
|
||||
IRFLT_OSC,
|
||||
IRFLT_PLL48M,
|
||||
};
|
||||
enum {
|
||||
IRFLT_DIV1,
|
||||
IRFLT_DIV2,
|
||||
IRFLT_DIV4,
|
||||
IRFLT_DIV8,
|
||||
IRFLT_DIV16,
|
||||
IRFLT_DIV32,
|
||||
IRFLT_DIV64,
|
||||
IRFLT_DIV128,
|
||||
IRFLT_DIV256,
|
||||
IRFLT_DIV512,
|
||||
IRFLT_DIV1024,
|
||||
IRFLT_DIV2048,
|
||||
IRFLT_DIV4096,
|
||||
IRFLT_DIV8192,
|
||||
IRFLT_DIV16384,
|
||||
IRFLT_DIV32768,
|
||||
};
|
||||
/* u32 irflt_config(u32 osc, u32 div); */
|
||||
|
||||
/**
|
||||
* @brief gpio_irflt_to_timer
|
||||
*
|
||||
* @param t: [0-3]
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 gpio_irflt_to_timer(u32 t);
|
||||
|
||||
|
||||
u32 get_gpio(const char *p);
|
||||
|
||||
|
||||
//===================================================//
|
||||
// BR30 Crossbar API
|
||||
//===================================================//
|
||||
enum PFI_TABLE {
|
||||
PFI_GP_ICH0 = ((u32)(&(JL_IMAP->FI_GP_ICH0))),
|
||||
PFI_GP_ICH1 = ((u32)(&(JL_IMAP->FI_GP_ICH1))),
|
||||
PFI_GP_ICH2 = ((u32)(&(JL_IMAP->FI_GP_ICH2))),
|
||||
PFI_GP_ICH3 = ((u32)(&(JL_IMAP->FI_GP_ICH3))),
|
||||
PFI_GP_ICH4 = ((u32)(&(JL_IMAP->FI_GP_ICH4))),
|
||||
PFI_GP_ICH5 = ((u32)(&(JL_IMAP->FI_GP_ICH5))),
|
||||
PFI_GP_ICH6 = ((u32)(&(JL_IMAP->FI_GP_ICH6))),
|
||||
PFI_GP_ICH7 = ((u32)(&(JL_IMAP->FI_GP_ICH7))),
|
||||
PFI_GP_ICH8 = ((u32)(&(JL_IMAP->FI_GP_ICH8))),
|
||||
PFI_GP_ICH9 = ((u32)(&(JL_IMAP->FI_GP_ICH9))),
|
||||
PFI_GP_ICH10 = ((u32)(&(JL_IMAP->FI_GP_ICH10))),
|
||||
PFI_GP_ICH11 = ((u32)(&(JL_IMAP->FI_GP_ICH11))),
|
||||
PFI_GP_ICH12 = ((u32)(&(JL_IMAP->FI_GP_ICH12))),
|
||||
PFI_GP_ICH13 = ((u32)(&(JL_IMAP->FI_GP_ICH13))),
|
||||
PFI_SPI0_CLK = ((u32)(&(JL_IMAP->FI_SPI0_CLK))),
|
||||
PFI_SPI0_DA0 = ((u32)(&(JL_IMAP->FI_SPI0_DA0))),
|
||||
PFI_SPI0_DA1 = ((u32)(&(JL_IMAP->FI_SPI0_DA1))),
|
||||
PFI_SPI0_DA2 = ((u32)(&(JL_IMAP->FI_SPI0_DA2))),
|
||||
PFI_SPI0_DA3 = ((u32)(&(JL_IMAP->FI_SPI0_DA3))),
|
||||
PFI_SPI1_CLK = ((u32)(&(JL_IMAP->FI_SPI1_CLK))),
|
||||
PFI_SPI1_DA0 = ((u32)(&(JL_IMAP->FI_SPI1_DA0))),
|
||||
PFI_SPI1_DA1 = ((u32)(&(JL_IMAP->FI_SPI1_DA1))),
|
||||
PFI_SPI1_DA2 = ((u32)(&(JL_IMAP->FI_SPI1_DA2))),
|
||||
PFI_SPI1_DA3 = ((u32)(&(JL_IMAP->FI_SPI1_DA3))),
|
||||
PFI_SPI2_CLK = ((u32)(&(JL_IMAP->FI_SPI2_CLK))),
|
||||
PFI_SPI2_DA0 = ((u32)(&(JL_IMAP->FI_SPI2_DA0))),
|
||||
PFI_SPI2_DA1 = ((u32)(&(JL_IMAP->FI_SPI2_DA1))),
|
||||
PFI_SPI2_DA2 = ((u32)(&(JL_IMAP->FI_SPI2_DA2))),
|
||||
PFI_SPI2_DA3 = ((u32)(&(JL_IMAP->FI_SPI2_DA3))),
|
||||
PFI_SD0_CMD = ((u32)(&(JL_IMAP->FI_SD0_CMD))),
|
||||
PFI_SD0_DA0 = ((u32)(&(JL_IMAP->FI_SD0_DA0))),
|
||||
PFI_SD0_DA1 = ((u32)(&(JL_IMAP->FI_SD0_DA1))),
|
||||
PFI_SD0_DA2 = ((u32)(&(JL_IMAP->FI_SD0_DA2))),
|
||||
PFI_SD0_DA3 = ((u32)(&(JL_IMAP->FI_SD0_DA3))),
|
||||
PFI_IIC_SCL = ((u32)(&(JL_IMAP->FI_IIC_SCL))),
|
||||
PFI_IIC_SDA = ((u32)(&(JL_IMAP->FI_IIC_SDA))),
|
||||
PFI_UART0_RX = ((u32)(&(JL_IMAP->FI_UART0_RX))),
|
||||
PFI_UART1_RX = ((u32)(&(JL_IMAP->FI_UART1_RX))),
|
||||
PFI_UART1_CTS = ((u32)(&(JL_IMAP->FI_UART1_CTS))),
|
||||
PFI_UART2_RX = ((u32)(&(JL_IMAP->FI_UART2_RX))),
|
||||
PFI_TDM_S_WCK = ((u32)(&(JL_IMAP->FI_TDM_S_WCK))),
|
||||
PFI_TDM_S_BCK = ((u32)(&(JL_IMAP->FI_TDM_S_BCK))),
|
||||
PFI_TDM_M_DA = ((u32)(&(JL_IMAP->FI_TDM_M_DA))),
|
||||
PFI_RDEC0_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT0))),
|
||||
PFI_RDEC0_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC0_DAT1))),
|
||||
PFI_RDEC1_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT0))),
|
||||
PFI_RDEC1_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC1_DAT1))),
|
||||
PFI_RDEC2_DAT0 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT0))),
|
||||
PFI_RDEC2_DAT1 = ((u32)(&(JL_IMAP->FI_RDEC2_DAT1))),
|
||||
PFI_ALNK0_MCLK = ((u32)(&(JL_IMAP->FI_ALNK0_MCLK))),
|
||||
PFI_ALNK0_LRCK = ((u32)(&(JL_IMAP->FI_ALNK0_LRCK))),
|
||||
PFI_ALNK0_SCLK = ((u32)(&(JL_IMAP->FI_ALNK0_SCLK))),
|
||||
PFI_ALNK0_DAT0 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT0))),
|
||||
PFI_ALNK0_DAT1 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT1))),
|
||||
PFI_ALNK0_DAT2 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT2))),
|
||||
PFI_ALNK0_DAT3 = ((u32)(&(JL_IMAP->FI_ALNK0_DAT3))),
|
||||
PFI_PLNK_DAT0 = ((u32)(&(JL_IMAP->FI_PLNK_DAT0))),
|
||||
PFI_PLNK_DAT1 = ((u32)(&(JL_IMAP->FI_PLNK_DAT1))),
|
||||
PFI_CHAIN_IN0 = ((u32)(&(JL_IMAP->FI_CHAIN_IN0))),
|
||||
PFI_CHAIN_IN1 = ((u32)(&(JL_IMAP->FI_CHAIN_IN1))),
|
||||
PFI_CHAIN_IN2 = ((u32)(&(JL_IMAP->FI_CHAIN_IN2))),
|
||||
PFI_CHAIN_IN3 = ((u32)(&(JL_IMAP->FI_CHAIN_IN3))),
|
||||
PFI_CHAIN_RST = ((u32)(&(JL_IMAP->FI_CHAIN_RST))),
|
||||
PFI_TOTAl = ((u32)(&(JL_IMAP->FI_TOTAL))),
|
||||
};
|
||||
|
||||
enum OUTPUT_CH_SIGNAL {
|
||||
OUTPUT_CH_SIGNAL_MC_PWM0_H = 0,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM0_L,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM1_H,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM1_L,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM2_H,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM2_L,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM3_H,
|
||||
OUTPUT_CH_SIGNAL_MC_PWM3_L,
|
||||
OUTPUT_CH_SIGNAL_TIMER0_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER1_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER2_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER3_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER4_PWM,
|
||||
OUTPUT_CH_SIGNAL_TIMER5_PWM,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT0,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT1,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT2,
|
||||
OUTPUT_CH_SIGNAL_CLOCK_OUT3,
|
||||
};
|
||||
|
||||
enum INPUT_CH_TYPE {
|
||||
INPUT_CH_TYPE_GP_ICH = 0,
|
||||
INPUT_CH_TYPE_TIME0_PWM = 14,
|
||||
INPUT_CH_TYPE_TIME1_PWM,
|
||||
};
|
||||
|
||||
enum INPUT_CH_SIGNAL {
|
||||
//ICH_CON0
|
||||
INPUT_CH_SIGNAL_TIMER0_CIN = 0,
|
||||
INPUT_CH_SIGNAL_TIMER0_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER1_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER1_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER2_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER2_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER3_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER3_CAPTURE,
|
||||
|
||||
//ICH_CON1
|
||||
INPUT_CH_SIGNAL_TIMER4_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER4_CAPTURE,
|
||||
INPUT_CH_SIGNAL_TIMER5_CIN,
|
||||
INPUT_CH_SIGNAL_TIMER5_CAPTURE,
|
||||
INPUT_CH_SIGNAL_WAKEUP,
|
||||
INPUT_CH_SIGNAL_IRFLT,
|
||||
INPUT_CH_SIGNAL_CAP,
|
||||
INPUT_CH_SIGNAL_CLK_PIN,
|
||||
|
||||
//ICH_CON2
|
||||
INPUT_CH_SIGNAL_WLC_EXT_ACT,
|
||||
INPUT_CH_SIGNAL_LCD_TE,
|
||||
INPUT_CH_SIGNAL_MC_CKPIN0,
|
||||
INPUT_CH_SIGNAL_MC_CKPIN1,
|
||||
INPUT_CH_SIGNAL_MC_CKPIN2,
|
||||
INPUT_CH_SIGNAL_MC_CKPIN3,
|
||||
INPUT_CH_SIGNAL_MC_FPIN0,
|
||||
INPUT_CH_SIGNAL_MC_FPIN1,
|
||||
|
||||
//ICH_CON3
|
||||
INPUT_CH_SIGNAL_MC_FPIN2,
|
||||
INPUT_CH_SIGNAL_MC_FPIN3,
|
||||
INPUT_CH_SIGNAL_RESERVE0,
|
||||
INPUT_CH_SIGNAL_RESERVE1,
|
||||
INPUT_CH_SIGNAL_RESERVE2,
|
||||
INPUT_CH_SIGNAL_RESERVE3,
|
||||
INPUT_CH_SIGNAL_RESERVE4,
|
||||
INPUT_CH_SIGNAL_RESERVE5,
|
||||
};
|
||||
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 获取某IO的输出映射寄存器
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
|
||||
//@return:
|
||||
// 输出映射寄存器地址; 如&(JL_OMAP->PA0_OUT)
|
||||
//=================================================================================//
|
||||
u32 *gpio2crossbar_outreg(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 获取某IO的输入映射序号
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口; 如IO_PORTA_00
|
||||
//@return:
|
||||
// 输出映射序号; 如PA0_IN
|
||||
//=================================================================================//
|
||||
u32 gpio2crossbar_inport(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输出设置 API, 将指定IO口设置为某个外设的输出
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口;
|
||||
// fun_index: 需要输出到指定IO口的外设信号, 可以输出外设信号列表请查看io_omap.h文件;
|
||||
// dir_ctl: IO口方向由外设控制使能, 常设为1;
|
||||
// data_ctl: IO口电平状态由外设控制使能, 常设为1;
|
||||
// low_power_mode: 低功耗状态是否保持io功能;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note: 所映射的IO需要在设置IO状态为输出配置;
|
||||
//@example: 将UART0的Tx信号输出到IO_PORTA_05口:
|
||||
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
|
||||
// gpio_set_fun_output_port(IO_PORTA_05, FO_UART0_TX, 1, 1); //将UART0的Tx信号输出到IO_PORTA_05口
|
||||
//=================================================================================//
|
||||
int gpio_set_fun_output_port(u32 gpio, u32 fun_index, u8 dir_ctl, u8 data_ctl, u8 low_power_mode);
|
||||
|
||||
u32 gpio_get_ompap_low_power_mode(u32 offset);
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note:
|
||||
//@example: 将IO_PORTA_05口被某一外设控制状态释放:
|
||||
// gpio_disable_fun_output_port(IO_PORTA_05);
|
||||
//=================================================================================//
|
||||
int gpio_disable_fun_output_port(u32 gpio);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输入设置 API, 将某个外设的输入设置为从某个IO输入
|
||||
//@input:
|
||||
// gpio: 需要输入外设信号的IO口;
|
||||
// pfun: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
|
||||
// low_power_mode: 低功耗状态是否保持io功能;
|
||||
//@return:
|
||||
// 1)0: 执行正确;
|
||||
// 2)-EINVAL: 传参出错;
|
||||
//@note: 所映射的IO需要在设置IO状态为输入配置;
|
||||
//@example: 将UART0的Rx信号设置为IO_PORTA_05口输入:
|
||||
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
|
||||
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
|
||||
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
|
||||
// gpio_set_fun_input_port(IO_PORTA_05, PFI_UART0_RX); //将UART0的Rx信号设置为IO_PORTA_05口输入
|
||||
//=================================================================================//
|
||||
int gpio_set_fun_input_port(u32 gpio, enum PFI_TABLE pfun, u32 low_power_mode);
|
||||
u32 gpio_get_impap_low_power_mode(u32 offset);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: CrossBar 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
|
||||
//@input:
|
||||
// pfun: 需要释放由某个IO口输入的外设信号, 外设信号列表请查看gpio.h文件enum PFI_TABLE枚举项;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将外设信号PFI_UART0_RX释放由某个IO输入:
|
||||
// gpio_disable_fun_input_port(PFI_UART0_RX);
|
||||
//=================================================================================//
|
||||
int gpio_disable_fun_input_port(enum PFI_TABLE pfun);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Output Channel输出设置 API, 将指定IO口设置为某个外设的输出
|
||||
//@input:
|
||||
// gpio: 需要输出外设信号的IO口;
|
||||
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要输出到指定IO口的外设信号, 可以输出的外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;
|
||||
//@return: 默认为0, 出错内部触发ASSERT;
|
||||
//@note: 所映射的IO需要在设置IO状态为输出配置;
|
||||
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H的Tx信号输出到IO_PORTA_05口:
|
||||
// gpio_direction_output(IO_PORTA_05, 1); //设置IO为输出状态
|
||||
// gpio_och_sel_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H); //将OUTPUT_CH_SIGNAL_MC_PWM0_H信号输出到IO_PORTA_05口
|
||||
//=================================================================================//
|
||||
int gpio_och_sel_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Output Channel 输出设置 API, 将指定IO释放外设控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要释放外设控制IO口, 释放后变为普通IO模式;
|
||||
// signal: 将enum OUTPUT_CH_SIGNAL列表中需要取消输出的外设信号, 外设信号列表请查看gpio.h文件的enum OUTPUT_CH_SIGNAL枚举项;;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将OUTPUT_CH_SIGNAL_MC_PWM0_H取消输出IO_PORTA_05:
|
||||
// gpio_och_disable_output_signal(IO_PORTA_05, OUTPUT_CH_SIGNAL_MC_PWM0_H);
|
||||
//=================================================================================//
|
||||
int gpio_och_disable_output_signal(u32 gpio, enum OUTPUT_CH_SIGNAL signal);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Input Channel 输入设置 API, 将某个外设的输入设置为从某个IO输入
|
||||
//@input:
|
||||
// gpio: 需要输入外设信号的IO口;
|
||||
// signal: 需要从指定IO输入的外设信号, 可以输入的外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
|
||||
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
|
||||
//@return: 默认为0, 出错内部触发ASSERT;
|
||||
//@note: 所映射的IO需要在设置IO状态为输入配置;
|
||||
//@example: 将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入:
|
||||
// gpio_set_die(IO_PORTA_05, 1); //数字输入使能
|
||||
// gpio_set_pull_up(IO_PORTA_05, 1); //上拉输入使能
|
||||
// gpio_direction_input(IO_PORTA_05); //设置IO为输入状态
|
||||
// gpio_ich_sel_iutput_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH); //将INPUT_CH_SIGNAL_TIMER0_CIN信号设置为IO_PORTA_05口输入
|
||||
//=================================================================================//
|
||||
int gpio_ich_sel_iutput_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: Input Channel 输入设置 API, 将某个外设信号释放IO口控制, 变为普通IO;
|
||||
//@input:
|
||||
// gpio: 需要取消输入外设信号的IO口;
|
||||
// signal: 需要取消输入的外设信号, 外设信号列表请查看gpio.h文件enum INPUT_CH_SIGNAL枚举项;
|
||||
// type: INPUT_CH 类型, 常设为INPUT_CH_TYPE_GP_ICH;
|
||||
//@return: 默认为0, 无出错处理;
|
||||
//@note:
|
||||
//@example: 将外设信号INPUT_CH_SIGNAL_TIMER0_CIN释放由某个IO输入:
|
||||
// gpio_ich_disable_iutput_signal(IO_PORTA_05, INPUT_CH_SIGNAL_TIMER0_CIN, INPUT_CH_TYPE_GP_ICH);
|
||||
//=================================================================================//
|
||||
int gpio_ich_disable_iutput_signal(u32 gpio, enum INPUT_CH_SIGNAL signal, enum INPUT_CH_TYPE type);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_longpress_pin0_reset_config
|
||||
*
|
||||
* @param pin 任意GPIO
|
||||
* @param level 0(下降沿触发) 1(上升沿触发)
|
||||
* @param time 0(disable) 1 2 4 8 16单位为秒
|
||||
*/
|
||||
void gpio_longpress_pin0_reset_config(u32 pin, u32 level, u32 time);
|
||||
|
||||
|
||||
/**
|
||||
* @brief gpio_longpress_pin1_reset_config
|
||||
*
|
||||
* @param pin IO_LDOIN_DET IO_VBTCH_DET
|
||||
* @param level 0(下降沿触发) 1(上升沿触发)
|
||||
* @param time 0(disable) 1 2 4 8 16单位为秒
|
||||
*/
|
||||
void gpio_longpress_pin1_reset_config(u32 pin, u32 level, u32 time);
|
||||
|
||||
|
||||
/**
|
||||
* @brief get_sfc_port 获取当前code flash的端口
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
u32 get_sfc_port(void);
|
||||
#endif /*GPIO_H*/
|
||||
178
include_lib/driver/cpu/br28/asm/hwi.h
Normal file
178
include_lib/driver/cpu/br28/asm/hwi.h
Normal file
@ -0,0 +1,178 @@
|
||||
#ifndef HWI_H
|
||||
#define HWI_H
|
||||
|
||||
//=================================================
|
||||
#define IRQ_EMUEXCPT_IDX 0 //0
|
||||
#define IRQ_EXCEPTION_IDX 1 //0
|
||||
#define IRQ_SYSCALL_IDX 2 //0
|
||||
#define IRQ_TICK_TMR_IDX 3 //0
|
||||
#define IRQ_TIME0_IDX 4 //0
|
||||
#define IRQ_TIME1_IDX 5 //0
|
||||
#define IRQ_TIME2_IDX 6 //0
|
||||
#define IRQ_TIME3_IDX 7 //0
|
||||
#define IRQ_TIME4_IDX 8 //0
|
||||
#define IRQ_TIME5_IDX 9 //0
|
||||
|
||||
#define IRQ_UART0_IDX 12 //0
|
||||
#define IRQ_UART1_IDX 13 //0
|
||||
#define IRQ_UART2_IDX 14 //0
|
||||
|
||||
#define IRQ_SPI0_IDX 16 //0
|
||||
#define IRQ_SPI1_IDX 17 //0
|
||||
#define IRQ_SPI2_IDX 18 //0
|
||||
|
||||
#define IRQ_SD0_IDX 20 //0
|
||||
|
||||
#define IRQ_IIC_IDX 24 //0
|
||||
|
||||
#define IRQ_USB_SOF_IDX 28 //1
|
||||
#define IRQ_USB_CTRL_IDX 29 //1
|
||||
|
||||
#define IRQ_P2M_IDX 32 //0
|
||||
#define IRQ_LP_TIMER0_IDX 33
|
||||
#define IRQ_LP_TIMER1_IDX 34
|
||||
#define IRQ_LP_TIMER2_IDX 35
|
||||
#define IRQ_LP_TIMER3_IDX 36
|
||||
|
||||
#define IRQ_PORT_IDX 38 //0
|
||||
#define IRQ_GPADC_IDX 39 //0
|
||||
#define IRQ_CTM_IDX 40
|
||||
#define IRQ_PWM_LED_IDX 41 //1
|
||||
#define IRQ_OSA_IDX 42
|
||||
#define IRQ_LRCT_IDX 43 //1
|
||||
#define IRQ_GPC_IDX 44 //1
|
||||
#define IRQ_FMTX_IDX 45 //1
|
||||
#define IRQ_TDM_IDX 46 //1
|
||||
#define IRQ_RDEC0_IDX 47 //1
|
||||
#define IRQ_SBC_IDX 48 //1
|
||||
#define IRQ_AES_IDX 49
|
||||
#define IRQ_RDEC1_IDX 50 //1
|
||||
#define IRQ_RDEC2_IDX 51 //1
|
||||
#define IRQ_MCPWM_CHX_IDX 52
|
||||
#define IRQ_MCPWM_TMR_IDX 53
|
||||
|
||||
#define IRQ_ANC_IDX 67
|
||||
#define IRQ_AUDIO_IDX 68 //1
|
||||
#define IRQ_ALINK0_IDX 69 //1
|
||||
#define IRQ_PDM_LINK_IDX 70 //1
|
||||
|
||||
#define IRQ_BT_CLKN_IDX 76 //2
|
||||
#define IRQ_BT_DBG_IDX 77 //1
|
||||
#define IRQ_BLE_RX_IDX 78 //2
|
||||
#define IRQ_BLE_EVENT_IDX 79 //1
|
||||
|
||||
#define IRQ_BT_TIMEBASE_IDX 80 //1
|
||||
#define IRQ_WL_LOFC_IDX 81 //2
|
||||
#define IRQ_BREDR_IDX 82 //2
|
||||
|
||||
#define IRQ_SYNC_IDX 88 //2
|
||||
#define IRQ_SRC_SYNC_IDX 89 //1
|
||||
#define IRQ_SRC_IDX 90 //1
|
||||
#define IRQ_EQ_IDX 91 //1
|
||||
#define IRQ_DCP_IDX 93 //1
|
||||
|
||||
#define IRQ_IMG_CP_IDX 103 //1
|
||||
#define IRQ_IMD_IDX 104 //1
|
||||
#define IRQ_IMB_IDX 105 //1
|
||||
#define IRQ_JPG_IDX 106 //1
|
||||
|
||||
#define IRQ_FFT_IDX 116 //1
|
||||
|
||||
#define IRQ_SOFT0_IDX 124
|
||||
#define IRQ_SOFT1_IDX 125
|
||||
#define IRQ_SOFT2_IDX 126
|
||||
#define IRQ_SOFT3_IDX 127
|
||||
|
||||
#define MAX_IRQ_ENTRY_NUM 128
|
||||
|
||||
//=================================================
|
||||
|
||||
//=================================================
|
||||
|
||||
void interrupt_init();
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief 中断注册函数
|
||||
*
|
||||
* @param index 中断号
|
||||
* @param priority 优先级，范围0-6可用
|
||||
* @param handler 中断服务函数
|
||||
* @param cpu_id 相应中断服务函数的CPU
|
||||
*/
|
||||
/* ----------------------------------------------------------------------------*/
|
||||
void request_irq(u8 index, u8 priority, void (*handler)(void), u8 cpu_id);
|
||||
|
||||
void unrequest_irq(u8 index);
|
||||
|
||||
void reg_set_ip(unsigned char index, unsigned char priority, u8 cpu_id);
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief 设置不可屏蔽中断（不可屏蔽中断不区分优先级）
|
||||
* cpu多核同步默认使用0，其他使用1。
|
||||
*
|
||||
* @param index 中断号
|
||||
* @param priority 不可屏蔽优先级，范围 0、1 （CPU_IRQ_IPMASK_LEVEL == 6）
|
||||
* @param cpu_id 相应中断服务函数的CPU
|
||||
*/
|
||||
/* ----------------------------------------------------------------------------*/
|
||||
void irq_unmask_set(u8 index, u8 priority, u8 cpu_id);
|
||||
|
||||
void bit_clr_ie(unsigned char index);
|
||||
void bit_set_ie(unsigned char index);
|
||||
bool irq_read(u32 index);
|
||||
|
||||
#define irq_disable(x) bit_clr_ie(x)
|
||||
#define irq_enable(x) bit_set_ie(x)
|
||||
|
||||
void unmask_enter_critical(void);
|
||||
void unmask_exit_critical(void);
|
||||
//---------------------------------------------//
|
||||
// low power waiting
|
||||
//---------------------------------------------//
|
||||
__attribute__((always_inline))
|
||||
static void lp_waiting(int *ptr, int pnd, int cpd, char inum)
|
||||
{
|
||||
q32DSP(core_num())->IWKUP_NUM = inum;
|
||||
while (!(*ptr & pnd)) {
|
||||
asm volatile("idle");
|
||||
}
|
||||
*ptr |= cpd;
|
||||
}
|
||||
|
||||
//---------------------------------------------//
|
||||
// interrupt cli/sti
|
||||
//---------------------------------------------//
|
||||
|
||||
static inline int int_cli(void)
|
||||
{
|
||||
int msg;
|
||||
asm volatile("cli %0" : "=r"(msg) :);
|
||||
return msg;
|
||||
}
|
||||
|
||||
static inline void int_sti(int msg)
|
||||
{
|
||||
asm volatile("sti %0" :: "r"(msg));
|
||||
}
|
||||
|
||||
#ifdef IRQ_TIME_COUNT_EN
|
||||
void irq_handler_enter(int irq);
|
||||
|
||||
void irq_handler_exit(int irq);
|
||||
|
||||
void irq_handler_times_dump();
|
||||
#else
|
||||
|
||||
#define irq_handler_enter(irq) do { }while(0)
|
||||
#define irq_handler_exit(irq) do { }while(0)
|
||||
#define irq_handler_times_dump() do { }while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
82
include_lib/driver/cpu/br28/asm/iic_hw.h
Normal file
82
include_lib/driver/cpu/br28/asm/iic_hw.h
Normal file
@ -0,0 +1,82 @@
|
||||
#ifndef _IIC_HW_H_
|
||||
#define _IIC_HW_H_
|
||||
|
||||
#include "system/generic/typedef.h"
|
||||
|
||||
#define IIC_HW_NUM 1
|
||||
#define IIC_PORT_GROUP_NUM 4
|
||||
|
||||
#define iic_enable(reg) (reg->CON0 |= BIT(0))
|
||||
#define iic_disable(reg) (reg->CON0 &= ~BIT(0))
|
||||
#define iic_role_host(reg) (reg->CON0 &= ~BIT(1))
|
||||
#define iic_role_slave(reg) (reg->CON0 |= BIT(1))
|
||||
#define iic_cfg_done(reg) (reg->CON0 |= BIT(2))
|
||||
#define iic_dir_out(reg) (reg->CON0 &= ~BIT(3))
|
||||
#define iic_dir_in(reg) (reg->CON0 |= BIT(3))
|
||||
#define iic_preset_end(reg) (reg->CON0 |= BIT(4))
|
||||
#define iic_preset_restart(reg) (reg->CON0 |= BIT(5))
|
||||
#define iic_recv_ack(reg) (reg->CON0 &= ~BIT(6))
|
||||
#define iic_recv_nack(reg) (reg->CON0 |= BIT(6))
|
||||
#define iic_send_is_ack(reg) (!(reg->CON0 & BIT(7)))
|
||||
#define iic_isel_direct(reg) (reg->CON0 &= ~BIT(9))
|
||||
#define iic_isel_filter(reg) (reg->CON0 |= BIT(9))
|
||||
#define iic_si_mode_en(reg) (reg->CON1 |= BIT(13))
|
||||
#define iic_si_mode_dis(reg) (reg->CON1 &= ~BIT(13))
|
||||
|
||||
#define iic_set_ie(reg) (reg->CON0 |= BIT(8))
|
||||
#define iic_clr_ie(reg) (reg->CON0 &= ~BIT(8))
|
||||
#define iic_pnd(reg) (reg->CON0 & BIT(15))
|
||||
#define iic_pnd_clr(reg) (reg->CON0 |= BIT(14))
|
||||
|
||||
#define iic_set_end_ie(reg) (reg->CON0 |= BIT(10))
|
||||
#define iic_clr_end_ie(reg) (reg->CON0 &= BIT(10))
|
||||
#define iic_end_pnd(reg) (reg->CON0 & BIT(13))
|
||||
#define iic_end_pnd_clr(reg) (reg->CON0 |= BIT(12))
|
||||
|
||||
#define iic_start_pnd(reg) (reg->CON1 & BIT(15))
|
||||
#define iic_start_pnd_clr(reg) (reg->CON1 |= BIT(14))
|
||||
|
||||
#define iic_baud_reg(reg) (reg->BAUD)
|
||||
#define iic_buf_reg(reg) (reg->BUF)
|
||||
|
||||
|
||||
typedef const int hw_iic_dev;
|
||||
|
||||
enum {IIC_MASTER, IIC_SLAVE};
|
||||
|
||||
struct hw_iic_config {
|
||||
u8 port[2];
|
||||
u32 baudrate;
|
||||
u8 hdrive;
|
||||
u8 io_filter;
|
||||
u8 io_pu;
|
||||
u8 role;
|
||||
};
|
||||
|
||||
extern const struct hw_iic_config hw_iic_cfg[];
|
||||
|
||||
int hw_iic_init(hw_iic_dev iic);
|
||||
void hw_iic_uninit(hw_iic_dev iic);
|
||||
void hw_iic_suspend(hw_iic_dev iic);
|
||||
void hw_iic_resume(hw_iic_dev iic);
|
||||
void hw_iic_start(hw_iic_dev iic);
|
||||
void hw_iic_stop(hw_iic_dev iic);
|
||||
u8 hw_iic_tx_byte(hw_iic_dev iic, u8 byte);
|
||||
u8 hw_iic_rx_byte(hw_iic_dev iic, u8 ack);
|
||||
int hw_iic_read_buf(hw_iic_dev iic, void *buf, int len);
|
||||
int hw_iic_write_buf(hw_iic_dev iic, const void *buf, int len);
|
||||
int hw_iic_set_baud(hw_iic_dev iic, u32 baud);
|
||||
|
||||
void hw_iic_set_ie(hw_iic_dev iic, u8 en);
|
||||
u8 hw_iic_get_pnd(hw_iic_dev iic);
|
||||
void hw_iic_clr_pnd(hw_iic_dev iic);
|
||||
void hw_iic_set_end_ie(hw_iic_dev iic, u8 en);
|
||||
u8 hw_iic_get_end_pnd(hw_iic_dev iic);
|
||||
void hw_iic_clr_end_pnd(hw_iic_dev iic);
|
||||
void hw_iic_slave_set_addr(hw_iic_dev iic, u8 addr, u8 addr_ack);
|
||||
void hw_iic_slave_rx_prepare(hw_iic_dev iic, u8 ack);
|
||||
u8 hw_iic_slave_rx_byte(hw_iic_dev iic, bool *is_start_addr);
|
||||
void hw_iic_slave_tx_byte(hw_iic_dev iic, u8 byte);
|
||||
u8 hw_iic_slave_tx_check_ack(hw_iic_dev iic);
|
||||
|
||||
#endif
|
||||
28
include_lib/driver/cpu/br28/asm/iic_soft.h
Normal file
28
include_lib/driver/cpu/br28/asm/iic_soft.h
Normal file
@ -0,0 +1,28 @@
|
||||
#ifndef _IIC_SOFT_H_
|
||||
#define _IIC_SOFT_H_
|
||||
|
||||
#include "generic/typedef.h"
|
||||
|
||||
typedef const int soft_iic_dev;
|
||||
|
||||
struct soft_iic_config {
|
||||
int scl;
|
||||
int sda;
|
||||
u32 delay;
|
||||
u8 io_pu;
|
||||
};
|
||||
|
||||
extern const struct soft_iic_config soft_iic_cfg[];
|
||||
|
||||
int soft_iic_init(soft_iic_dev iic);
|
||||
void soft_iic_uninit(soft_iic_dev iic);
|
||||
void soft_iic_suspend(soft_iic_dev iic);
|
||||
void soft_iic_resume(soft_iic_dev iic);
|
||||
void soft_iic_start(soft_iic_dev iic);
|
||||
void soft_iic_stop(soft_iic_dev iic);
|
||||
u8 soft_iic_tx_byte(soft_iic_dev iic, u8 byte);
|
||||
u8 soft_iic_rx_byte(soft_iic_dev iic, u8 ack);
|
||||
int soft_iic_read_buf(soft_iic_dev iic, void *buf, int len);
|
||||
int soft_iic_write_buf(soft_iic_dev iic, const void *buf, int len);
|
||||
#endif
|
||||
|
||||
48
include_lib/driver/cpu/br28/asm/iis.h
Normal file
48
include_lib/driver/cpu/br28/asm/iis.h
Normal file
@ -0,0 +1,48 @@
|
||||
#ifndef __IIS_H__
|
||||
#define __IIS_H__
|
||||
|
||||
#include "generic/typedef.h"
|
||||
|
||||
|
||||
#define ALINK_SEL(module, reg) (((JL_ALNK_TypeDef *)(((u8 *)JL_ALNK0)))->reg)
|
||||
|
||||
#define ALNK_CON_RESET(module) do {ALINK_SEL(module, CON0) = 0; ALINK_SEL(module, CON1) = 0; ALINK_SEL(module, CON2) = 0; ALINK_SEL(module, CON3) = 0;} while(0)
|
||||
#define ALNK_HWPTR_RESET(module) do {ALINK_SEL(module, HWPTR0) = 0; ALINK_SEL(module, HWPTR1) = 0; ALINK_SEL(module, HWPTR2) = 0; ALINK_SEL(module, HWPTR3) = 0;} while(0)
|
||||
#define ALNK_SWPTR_RESET(module) do {ALINK_SEL(module, SWPTR0) = 0; ALINK_SEL(module, SWPTR1) = 0; ALINK_SEL(module, SWPTR2) = 0; ALINK_SEL(module, SWPTR3) = 0;} while(0)
|
||||
#define ALNK_SHN_RESET(module) do {ALINK_SEL(module, SHN0) = 0; ALINK_SEL(module, SHN1) = 0; ALINK_SEL(module, SHN2) = 0; ALINK_SEL(module, SHN3) = 0;} while(0)
|
||||
#define ALNK_ADR_RESET(module) do {ALINK_SEL(module, ADR0) = 0; ALINK_SEL(module, ADR1) = 0; ALINK_SEL(module, ADR2) = 0; ALINK_SEL(module, ADR3) = 0;} while(0)
|
||||
#define ALNK_PNS_RESET(module) do {ALINK_SEL(module, PNS) = 0;} while(0)
|
||||
|
||||
#define ALINK_DA2BTSRC_SEL(module, x) SFR(ALINK_SEL(module, CON0), 0, 2, x)
|
||||
#define ALINK_DMA_MODE_SEL(module, x) SFR(ALINK_SEL(module, CON0), 2, 1, x)
|
||||
#define ALINK_DSPE(module, x) SFR(ALINK_SEL(module, CON0), 6, 1, x)
|
||||
#define ALINK_SOE(module, x) SFR(ALINK_SEL(module, CON0), 7, 1, x)
|
||||
#define ALINK_MOE(module, x) SFR(ALINK_SEL(module, CON0), 8, 1, x)
|
||||
#define F32_EN(module, x) SFR(ALINK_SEL(module, CON0), 9, 1, x)
|
||||
#define SCLKINV(module, x) SFR(ALINK_SEL(module, CON0),10, 1, x)
|
||||
#define ALINK_EN(module, x) SFR(ALINK_SEL(module, CON0),11, 1, x)
|
||||
#define ALINK_24BIT_MODE(module) (ALINK_SEL(module, CON1) |= (BIT(2) | BIT(6) | BIT(10) | BIT(14)))
|
||||
#define ALINK_16BIT_MODE(module) (ALINK_SEL(module, CON1) &= (~(BIT(2) | BIT(6) | BIT(10) | BIT(14))))
|
||||
|
||||
|
||||
#define ALINK_CHx_DIR_MODE(module, ch, x) SFR(ALINK_SEL(module, CON1), 3 + 4 * ch, 1, x)
|
||||
#define ALINK_CHx_MODE_SEL(module, ch, x) SFR(ALINK_SEL(module, CON1), 4 * ch, 2, x)
|
||||
#define ALINK_CHx_CLOSE(module, ch) SFR(ALINK_SEL(module, CON1), 4 * ch, 2, 0)
|
||||
|
||||
|
||||
#define ALINK_CLR_ALL_PND(module) (ALINK_SEL(module, CON2) |= BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
#define ALINK_CLR_CHx_PND(module, ch) (ALINK_SEL(module, CON2) |= BIT(ch))
|
||||
#define ALINK_CHx_IE(module, ch, x) SFR(ALINK_SEL(module, CON2), ch + 12, 1, x)
|
||||
|
||||
#define ALINK_MSRC(module, x) SFR(ALINK_SEL(module, CON3), 0, 2, x)
|
||||
#define ALINK_MDIV(module, x) SFR(ALINK_SEL(module, CON3), 2, 3, x)
|
||||
#define ALINK_LRDIV(module, x) SFR(ALINK_SEL(module, CON3), 5, 3, x)
|
||||
|
||||
#define ALINK_OPNS(module) (ALINK_SEL(module, PNS) >> 16)
|
||||
#define ALINK_IPNS(module) (ALINK_SEL(module, PNS) & 0xffff)
|
||||
#define ALINK_OPNS_SET(module, x) SFR(ALINK_SEL(module, PNS), 16, 16, x)
|
||||
#define ALINK_IPNS_SET(module, x) SFR(ALINK_SEL(module, PNS), 0, 16, x)
|
||||
|
||||
#define ALINK_LEN_SET(module, x) (ALINK_SEL(module, LEN) = x)
|
||||
#define ALINK_FIFO_LEN(module) (ALINK_SEL(module, LEN))
|
||||
#endif
|
||||
31
include_lib/driver/cpu/br28/asm/includes.h
Normal file
31
include_lib/driver/cpu/br28/asm/includes.h
Normal file
@ -0,0 +1,31 @@
|
||||
#ifndef ASM_INCLUDES_H
|
||||
#define ASM_INCLUDES_H
|
||||
|
||||
#include "asm/cpu.h"
|
||||
#include "asm/crc16.h"
|
||||
#include "asm/clock.h"
|
||||
#include "asm/uart.h"
|
||||
#include "asm/uart_dev.h"
|
||||
#include "asm/gpio.h"
|
||||
#include "asm/spiflash.h"
|
||||
#include "asm/csfr.h"
|
||||
#include "asm/power_interface.h"
|
||||
#include "asm/efuse.h"
|
||||
#include "asm/wdt.h"
|
||||
#include "asm/debug.h"
|
||||
#include "asm/power/p33.h"
|
||||
#include "asm/timer.h"
|
||||
#include "asm/rtc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
131
include_lib/driver/cpu/br28/asm/io_imap.h
Normal file
131
include_lib/driver/cpu/br28/asm/io_imap.h
Normal file
@ -0,0 +1,131 @@
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define PA0_IN 1
|
||||
#define PA1_IN 2
|
||||
#define PA2_IN 3
|
||||
#define PA3_IN 4
|
||||
#define PA4_IN 5
|
||||
#define PA5_IN 6
|
||||
#define PA6_IN 7
|
||||
#define PA7_IN 8
|
||||
#define PA8_IN 9
|
||||
#define PA9_IN 10
|
||||
#define PA10_IN 11
|
||||
#define PA11_IN 12
|
||||
#define PA12_IN 13
|
||||
#define PA13_IN 14
|
||||
#define PA14_IN 15
|
||||
#define PA15_IN 16
|
||||
#define PB0_IN 17
|
||||
#define PB1_IN 18
|
||||
#define PB2_IN 19
|
||||
#define PB3_IN 20
|
||||
#define PB4_IN 21
|
||||
#define PB5_IN 22
|
||||
#define PB6_IN 23
|
||||
#define PB7_IN 24
|
||||
#define PB8_IN 25
|
||||
#define PB9_IN 26
|
||||
#define PB10_IN 27
|
||||
#define PB11_IN 28
|
||||
#define PC0_IN 29
|
||||
#define PC1_IN 30
|
||||
#define PC2_IN 31
|
||||
#define PC3_IN 32
|
||||
#define PC4_IN 33
|
||||
#define PC5_IN 34
|
||||
#define PC6_IN 35
|
||||
#define PC7_IN 36
|
||||
#define PC8_IN 37
|
||||
#define PG0_IN 38
|
||||
#define PG1_IN 39
|
||||
#define PG2_IN 40
|
||||
#define PG3_IN 41
|
||||
#define PG4_IN 42
|
||||
#define PG5_IN 43
|
||||
#define PG6_IN 44
|
||||
#define PG7_IN 45
|
||||
#define PG8_IN 46
|
||||
#define USBDP_IN 47
|
||||
#define USBDM_IN 48
|
||||
#define PP0_IN 49
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 FI_GP_ICH0;
|
||||
__RW __u8 FI_GP_ICH1;
|
||||
__RW __u8 FI_GP_ICH2;
|
||||
__RW __u8 FI_GP_ICH3;
|
||||
__RW __u8 FI_GP_ICH4;
|
||||
__RW __u8 FI_GP_ICH5;
|
||||
__RW __u8 FI_GP_ICH6;
|
||||
__RW __u8 FI_GP_ICH7;
|
||||
__RW __u8 FI_GP_ICH8;
|
||||
__RW __u8 FI_GP_ICH9;
|
||||
__RW __u8 FI_GP_ICH10;
|
||||
__RW __u8 FI_GP_ICH11;
|
||||
__RW __u8 FI_GP_ICH12;
|
||||
__RW __u8 FI_GP_ICH13;
|
||||
__RW __u8 FI_SPI0_CLK;
|
||||
__RW __u8 FI_SPI0_DA0;
|
||||
__RW __u8 FI_SPI0_DA1;
|
||||
__RW __u8 FI_SPI0_DA2;
|
||||
__RW __u8 FI_SPI0_DA3;
|
||||
__RW __u8 FI_SPI1_CLK;
|
||||
__RW __u8 FI_SPI1_DA0;
|
||||
__RW __u8 FI_SPI1_DA1;
|
||||
__RW __u8 FI_SPI1_DA2;
|
||||
__RW __u8 FI_SPI1_DA3;
|
||||
__RW __u8 FI_SPI2_CLK;
|
||||
__RW __u8 FI_SPI2_DA0;
|
||||
__RW __u8 FI_SPI2_DA1;
|
||||
__RW __u8 FI_SPI2_DA2;
|
||||
__RW __u8 FI_SPI2_DA3;
|
||||
__RW __u8 FI_SD0_CMD;
|
||||
__RW __u8 FI_SD0_DA0;
|
||||
__RW __u8 FI_SD0_DA1;
|
||||
__RW __u8 FI_SD0_DA2;
|
||||
__RW __u8 FI_SD0_DA3;
|
||||
__RW __u8 FI_IIC_SCL;
|
||||
__RW __u8 FI_IIC_SDA;
|
||||
__RW __u8 FI_UART0_RX;
|
||||
__RW __u8 FI_UART1_RX;
|
||||
__RW __u8 FI_UART1_CTS;
|
||||
__RW __u8 FI_UART2_RX;
|
||||
__RW __u8 FI_TDM_S_WCK;
|
||||
__RW __u8 FI_TDM_S_BCK;
|
||||
__RW __u8 FI_TDM_M_DA;
|
||||
__RW __u8 FI_RDEC0_DAT0;
|
||||
__RW __u8 FI_RDEC0_DAT1;
|
||||
__RW __u8 FI_RDEC1_DAT0;
|
||||
__RW __u8 FI_RDEC1_DAT1;
|
||||
__RW __u8 FI_RDEC2_DAT0;
|
||||
__RW __u8 FI_RDEC2_DAT1;
|
||||
__RW __u8 FI_ALNK0_MCLK;
|
||||
__RW __u8 FI_ALNK0_LRCK;
|
||||
__RW __u8 FI_ALNK0_SCLK;
|
||||
__RW __u8 FI_ALNK0_DAT0;
|
||||
__RW __u8 FI_ALNK0_DAT1;
|
||||
__RW __u8 FI_ALNK0_DAT2;
|
||||
__RW __u8 FI_ALNK0_DAT3;
|
||||
__RW __u8 FI_PLNK_DAT0;
|
||||
__RW __u8 FI_PLNK_DAT1;
|
||||
__RW __u8 FI_CHAIN_IN0;
|
||||
__RW __u8 FI_CHAIN_IN1;
|
||||
__RW __u8 FI_CHAIN_IN2;
|
||||
__RW __u8 FI_CHAIN_IN3;
|
||||
__RW __u8 FI_CHAIN_RST;
|
||||
__RW __u8 FI_TOTAL;
|
||||
} JL_IMAP_TypeDef;
|
||||
|
||||
#define JL_IMAP_BASE (ls_base + map_adr(0x5c, 0x00))
|
||||
#define JL_IMAP ((JL_IMAP_TypeDef *)JL_IMAP_BASE)
|
||||
130
include_lib/driver/cpu/br28/asm/io_omap.h
Normal file
130
include_lib/driver/cpu/br28/asm/io_omap.h
Normal file
@ -0,0 +1,130 @@
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define FO_GP_OCH3 ((3 << 2)|BIT(1))
|
||||
#define FO_GP_OCH4 ((4 << 2)|BIT(1))
|
||||
#define FO_GP_OCH5 ((5 << 2)|BIT(1))
|
||||
#define FO_GP_OCH6 ((6 << 2)|BIT(1))
|
||||
#define FO_GP_OCH7 ((7 << 2)|BIT(1))
|
||||
#define FO_GP_OCH8 ((8 << 2)|BIT(1))
|
||||
#define FO_GP_OCH9 ((9 << 2)|BIT(1))
|
||||
#define FO_GP_OCH10 ((10 << 2)|BIT(1))
|
||||
#define FO_GP_OCH11 ((11 << 2)|BIT(1))
|
||||
#define FO_GP_OCH12 ((12 << 2)|BIT(1))
|
||||
#define FO_GP_OCH13 ((13 << 2)|BIT(1))
|
||||
#define FO_GP_OCH14 ((14 << 2)|BIT(1))
|
||||
#define FO_GP_OCH15 ((15 << 2)|BIT(1))
|
||||
#define FO_SPI0_CLK ((16 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI0_DA0 ((17 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI0_DA1 ((18 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI0_DA2 ((19 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI0_DA3 ((20 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_CLK ((21 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA0 ((22 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA1 ((23 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA2 ((24 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI1_DA3 ((25 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_CLK ((26 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA0 ((27 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA1 ((28 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA2 ((29 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SPI2_DA3 ((30 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_CLK ((31 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_CMD ((32 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA0 ((33 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA1 ((34 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA2 ((35 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_SD0_DA3 ((36 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC_SCL ((37 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_IIC_SDA ((38 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART0_TX ((39 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART1_TX ((40 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART1_RTS ((41 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_UART2_TX ((42 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_TDM_M_MCK ((43 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_TDM_M_WCK ((44 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_TDM_M_BCK ((45 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_TDM_S_DA ((46 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_MCLK ((47 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_LRCK ((48 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_SCLK ((49 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_DAT0 ((50 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_DAT1 ((51 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_DAT2 ((52 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_ALNK0_DAT3 ((53 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_PLNK_SCLK ((54 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_WL_ANT_ID0 ((55 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_WL_ANT_ID1 ((56 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_WL_ANT_ID2 ((57 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_WL_ANT_ID3 ((58 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT0 ((59 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT1 ((60 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT2 ((61 << 2)|BIT(1)|BIT(0))
|
||||
#define FO_CHAIN_OUT3 ((62 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 PA0_OUT;
|
||||
__RW __u8 PA1_OUT;
|
||||
__RW __u8 PA2_OUT;
|
||||
__RW __u8 PA3_OUT;
|
||||
__RW __u8 PA4_OUT;
|
||||
__RW __u8 PA5_OUT;
|
||||
__RW __u8 PA6_OUT;
|
||||
__RW __u8 PA7_OUT;
|
||||
__RW __u8 PA8_OUT;
|
||||
__RW __u8 PA9_OUT;
|
||||
__RW __u8 PA10_OUT;
|
||||
__RW __u8 PA11_OUT;
|
||||
__RW __u8 PA12_OUT;
|
||||
__RW __u8 PA13_OUT;
|
||||
__RW __u8 PA14_OUT;
|
||||
__RW __u8 PA15_OUT;
|
||||
__RW __u8 PB0_OUT;
|
||||
__RW __u8 PB1_OUT;
|
||||
__RW __u8 PB2_OUT;
|
||||
__RW __u8 PB3_OUT;
|
||||
__RW __u8 PB4_OUT;
|
||||
__RW __u8 PB5_OUT;
|
||||
__RW __u8 PB6_OUT;
|
||||
__RW __u8 PB7_OUT;
|
||||
__RW __u8 PB8_OUT;
|
||||
__RW __u8 PB9_OUT;
|
||||
__RW __u8 PB10_OUT;
|
||||
__RW __u8 PB11_OUT;
|
||||
__RW __u8 PC0_OUT;
|
||||
__RW __u8 PC1_OUT;
|
||||
__RW __u8 PC2_OUT;
|
||||
__RW __u8 PC3_OUT;
|
||||
__RW __u8 PC4_OUT;
|
||||
__RW __u8 PC5_OUT;
|
||||
__RW __u8 PC6_OUT;
|
||||
__RW __u8 PC7_OUT;
|
||||
__RW __u8 PC8_OUT;
|
||||
__RW __u8 PG0_OUT;
|
||||
__RW __u8 PG1_OUT;
|
||||
__RW __u8 PG2_OUT;
|
||||
__RW __u8 PG3_OUT;
|
||||
__RW __u8 PG4_OUT;
|
||||
__RW __u8 PG5_OUT;
|
||||
__RW __u8 PG6_OUT;
|
||||
__RW __u8 PG7_OUT;
|
||||
__RW __u8 PG8_OUT;
|
||||
__RW __u8 USBDP_OUT;
|
||||
__RW __u8 USBDM_OUT;
|
||||
__RW __u8 PP0_OUT;
|
||||
} JL_OMAP_TypeDef;
|
||||
|
||||
#define JL_OMAP_BASE (ls_base + map_adr(0x58, 0x00))
|
||||
#define JL_OMAP ((JL_OMAP_TypeDef *)JL_OMAP_BASE)
|
||||
231
include_lib/driver/cpu/br28/asm/irflt.h
Normal file
231
include_lib/driver/cpu/br28/asm/irflt.h
Normal file
@ -0,0 +1,231 @@
|
||||
#ifndef __KEY_DRV_IR_H__
|
||||
#define __KEY_DRV_IR_H__
|
||||
|
||||
#define IR_PORTA(x) (0x00 + x)
|
||||
#define IR_PORTB(x) (0x10 + x)
|
||||
#define IR_PORTC(x) (0x20 + x)
|
||||
#define IR_PORTD(x) (0x30 + x)
|
||||
#define IR_USBDP (0x3d)
|
||||
#define IR_USBDM (0x3e)
|
||||
|
||||
#define IR_IO IR_PORTA(9)
|
||||
|
||||
/*ir key define*/
|
||||
#define IR_00 0
|
||||
#define IR_01 1
|
||||
#define IR_02 2
|
||||
#define IR_03 3
|
||||
#define IR_04 4
|
||||
#define IR_05 5
|
||||
#define IR_06 6
|
||||
#define IR_07 7
|
||||
#define IR_08 8
|
||||
#define IR_09 9
|
||||
#define IR_10 10
|
||||
#define IR_11 11
|
||||
#define IR_12 12
|
||||
#define IR_13 13
|
||||
#define IR_14 14
|
||||
#define IR_15 15
|
||||
#define IR_16 16
|
||||
#define IR_17 17
|
||||
#define IR_18 18
|
||||
#define IR_19 19
|
||||
#define IR_20 20
|
||||
#define IR_21 21
|
||||
#define IR_22 22
|
||||
|
||||
//////////////////////////////////
|
||||
#define NKEY_00 0xff
|
||||
#define NKEY_01 0xff
|
||||
#define NKEY_02 0xff
|
||||
#define NKEY_03 0xff
|
||||
#define NKEY_04 0xff
|
||||
#define NKEY_05 0xff
|
||||
#define NKEY_06 0xff
|
||||
#define NKEY_07 0xff
|
||||
#define NKEY_08 0xff
|
||||
#define NKEY_09 0xff
|
||||
#define NKEY_0A 0xff
|
||||
#define NKEY_0B 0xff
|
||||
#define NKEY_0C 0xff
|
||||
#define NKEY_0D 0xff
|
||||
#define NKEY_0E 0xff
|
||||
#define NKEY_0F 0xff
|
||||
#define NKEY_10 0xff
|
||||
#define NKEY_11 0xff
|
||||
#define NKEY_12 0xff
|
||||
#define NKEY_13 0xff
|
||||
#define NKEY_14 0xff
|
||||
#define NKEY_15 0xff
|
||||
#define NKEY_16 0xff
|
||||
#define NKEY_17 0xff
|
||||
#define NKEY_18 0xff
|
||||
#define NKEY_19 0xff
|
||||
#define NKEY_1A 0xff
|
||||
#define NKEY_1B 0xff
|
||||
#define NKEY_1C 0xff
|
||||
#define NKEY_1D 0xff
|
||||
#define NKEY_1E 0xff
|
||||
#define NKEY_1F 0xff
|
||||
#define NKEY_20 0xff
|
||||
#define NKEY_21 0xff
|
||||
#define NKEY_22 0xff
|
||||
#define NKEY_23 0xff
|
||||
#define NKEY_24 0xff
|
||||
#define NKEY_25 0xff
|
||||
#define NKEY_26 0xff
|
||||
#define NKEY_27 0xff
|
||||
#define NKEY_28 0xff
|
||||
#define NKEY_29 0xff
|
||||
#define NKEY_2A 0xff
|
||||
#define NKEY_2B 0xff
|
||||
#define NKEY_2C 0xff
|
||||
#define NKEY_2D 0xff
|
||||
#define NKEY_2E 0xff
|
||||
#define NKEY_2F 0xff
|
||||
#define NKEY_30 0xff
|
||||
#define NKEY_31 0xff
|
||||
#define NKEY_32 0xff
|
||||
#define NKEY_33 0xff
|
||||
#define NKEY_34 0xff
|
||||
#define NKEY_35 0xff
|
||||
#define NKEY_36 0xff
|
||||
#define NKEY_37 0xff
|
||||
#define NKEY_38 0xff
|
||||
#define NKEY_39 0xff
|
||||
#define NKEY_3A 0xff
|
||||
#define NKEY_3B 0xff
|
||||
#define NKEY_3C 0xff
|
||||
#define NKEY_3D 0xff
|
||||
#define NKEY_3E 0xff
|
||||
#define NKEY_3F 0xff
|
||||
#define NKEY_40 0xff
|
||||
#define NKEY_41 0xff
|
||||
#define NKEY_42 0xff
|
||||
#define NKEY_43 0xff
|
||||
#define NKEY_44 0xff
|
||||
#define NKEY_45 0xff
|
||||
#define NKEY_46 0xff
|
||||
#define NKEY_47 0xff
|
||||
#define NKEY_48 0xff
|
||||
#define NKEY_49 0xff
|
||||
#define NKEY_4A 0xff
|
||||
#define NKEY_4B 0xff
|
||||
#define NKEY_4C 0xff
|
||||
#define NKEY_4D 0xff
|
||||
#define NKEY_4E 0xff
|
||||
#define NKEY_4F 0xff
|
||||
#define NKEY_50 0xff
|
||||
#define NKEY_51 0xff
|
||||
#define NKEY_52 0xff
|
||||
#define NKEY_53 0xff
|
||||
#define NKEY_54 0xff
|
||||
#define NKEY_55 0xff
|
||||
#define NKEY_56 0xff
|
||||
#define NKEY_57 0xff
|
||||
#define NKEY_58 0xff
|
||||
#define NKEY_59 0xff
|
||||
#define NKEY_5A 0xff
|
||||
#define NKEY_5B 0xff
|
||||
#define NKEY_5C 0xff
|
||||
#define NKEY_5D 0xff
|
||||
#define NKEY_5E 0xff
|
||||
#define NKEY_5F 0xff
|
||||
#define NKEY_60 0xff
|
||||
#define NKEY_61 0xff
|
||||
#define NKEY_62 0xff
|
||||
#define NKEY_63 0xff
|
||||
#define NKEY_64 0xff
|
||||
#define NKEY_65 0xff
|
||||
#define NKEY_66 0xff
|
||||
#define NKEY_67 0xff
|
||||
#define NKEY_68 0xff
|
||||
#define NKEY_69 0xff
|
||||
#define NKEY_6A 0xff
|
||||
#define NKEY_6B 0xff
|
||||
#define NKEY_6C 0xff
|
||||
#define NKEY_6D 0xff
|
||||
#define NKEY_6E 0xff
|
||||
#define NKEY_6F 0xff
|
||||
#define NKEY_70 0xff
|
||||
#define NKEY_71 0xff
|
||||
#define NKEY_72 0xff
|
||||
#define NKEY_73 0xff
|
||||
#define NKEY_74 0xff
|
||||
#define NKEY_75 0xff
|
||||
#define NKEY_76 0xff
|
||||
#define NKEY_77 0xff
|
||||
#define NKEY_78 0xff
|
||||
#define NKEY_79 0xff
|
||||
#define NKEY_7A 0xff
|
||||
#define NKEY_7B 0xff
|
||||
#define NKEY_7C 0xff
|
||||
#define NKEY_7D 0xff
|
||||
#define NKEY_7E 0xff
|
||||
#define NKEY_7F 0xff
|
||||
#define NKEY_80 0xff
|
||||
#define NKEY_81 0xff
|
||||
#define NKEY_82 0xff
|
||||
#define NKEY_83 0xff
|
||||
#define NKEY_84 0xff
|
||||
#define NKEY_85 0xff
|
||||
#define NKEY_86 0xff
|
||||
#define NKEY_87 0xff
|
||||
#define NKEY_88 0xff
|
||||
#define NKEY_89 0xff
|
||||
#define NKEY_8A 0xff
|
||||
#define NKEY_8B 0xff
|
||||
#define NKEY_8C 0xff
|
||||
#define NKEY_8D 0xff
|
||||
#define NKEY_8E 0xff
|
||||
#define NKEY_8F 0xff
|
||||
#define NKEY_90 0xff
|
||||
#define NKEY_91 0xff
|
||||
#define NKEY_92 0xff
|
||||
#define NKEY_93 0xff
|
||||
#define NKEY_94 0xff
|
||||
#define NKEY_95 0xff
|
||||
|
||||
|
||||
typedef struct _IR_CODE {
|
||||
u16 wData; //<键值
|
||||
u16 wUserCode; //<用户码
|
||||
u16 timer_pad;
|
||||
u8 bState; //<接收状态
|
||||
u8 boverflow; //<红外信号超时
|
||||
} IR_CODE;
|
||||
|
||||
enum timer_sel {
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
TIMER5,
|
||||
};
|
||||
|
||||
struct irflt_platform_data {
|
||||
u8 irflt_io;
|
||||
u8 timer;
|
||||
};
|
||||
|
||||
#define IRFLT_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct irflt_platform_data data = {
|
||||
|
||||
#define IRFLT_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
extern const struct device_operations irflt_dev_ops;
|
||||
|
||||
void set_ir_clk(void);
|
||||
void ir_input_io_sel(u8 port);
|
||||
void ir_output_timer_sel();
|
||||
void ir_timeout_set(void);
|
||||
void irflt_config();
|
||||
void log_irflt_info();
|
||||
u8 get_irflt_value(void);
|
||||
|
||||
#endif
|
||||
|
||||
20
include_lib/driver/cpu/br28/asm/irq.h
Normal file
20
include_lib/driver/cpu/br28/asm/irq.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef CPU_IRQ_H
|
||||
#define CPU_IRQ_H
|
||||
|
||||
|
||||
#include "asm/hwi.h"
|
||||
|
||||
#ifdef CONFIG_HWI_DEBUG
|
||||
#define ___interrupt
|
||||
#else
|
||||
#define ___interrupt __attribute__((interrupt("")))
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
20
include_lib/driver/cpu/br28/asm/lp_touch_key_alog.h
Normal file
20
include_lib/driver/cpu/br28/asm/lp_touch_key_alog.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef __LP_TOUCH_KEY_ALOG_H__
|
||||
#define __LP_TOUCH_KEY_ALOG_H__
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
void TouchAlgo_Init(u8 ch, u16 min, u16 max);
|
||||
void TouchAlgo_Update(u8 ch, u16 x);
|
||||
void TouchAlgo_Reset(u8 ch, u16 min, u16 max);
|
||||
|
||||
u16 TouchAlgo_GetRange(u8 ch, u8 *valid);
|
||||
void TouchAlgo_SetRange(u8 ch, u16 range);
|
||||
|
||||
s32 TouchAlgo_GetSigma(u8 ch);
|
||||
void TouchAlgo_SetSigma(u8 ch, s32 sigma);
|
||||
|
||||
|
||||
#endif /*LP_TOUCH_KEY_ALOG_H*/
|
||||
|
||||
157
include_lib/driver/cpu/br28/asm/lp_touch_key_api.h
Normal file
157
include_lib/driver/cpu/br28/asm/lp_touch_key_api.h
Normal file
@ -0,0 +1,157 @@
|
||||
#ifndef _LP_TOUCH_KEY_API_
|
||||
#define _LP_TOUCH_KEY_API_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "asm/lp_touch_key_hw.h"
|
||||
|
||||
|
||||
/**************************************************USER配置************************************************************************/
|
||||
//长按开机时间:
|
||||
#define CFG_M2P_CTMU_SOFTOFF_LONG_TIME 1000 //单位: ms
|
||||
|
||||
//触摸按键长按复位时间配置
|
||||
#define CTMU_RESET_TIME_CONFIG 8000 //长按复位时间(ms), 配置为0关闭
|
||||
|
||||
//debug
|
||||
#define CFG_CH0_DEBUG_ENABLE 0
|
||||
#define CFG_CH1_DEBUG_ENABLE 0
|
||||
#define CFG_CH2_DEBUG_ENABLE 0
|
||||
#define CFG_CH3_DEBUG_ENABLE 0
|
||||
#define CFG_CH4_DEBUG_ENABLE 0
|
||||
|
||||
#define CFG_CHx_DEBUG_ENABLE ((CFG_CH4_DEBUG_ENABLE<<4) | (CFG_CH3_DEBUG_ENABLE<<3) | (CFG_CH2_DEBUG_ENABLE<<2) | (CFG_CH1_DEBUG_ENABLE<<1) | (CFG_CH0_DEBUG_ENABLE))
|
||||
|
||||
#define CFG_DISABLE_KEY_EVENT 0
|
||||
|
||||
#define TWS_BT_SEND_KEY_CH_RES_DATA_ENABLE 0
|
||||
|
||||
#define TWS_BT_SEND_EARTCH_RES_DATA_ENABLE 0
|
||||
|
||||
#define TWS_BT_SEND_EVENT_ENABLE 0
|
||||
|
||||
|
||||
#if TWS_BT_SEND_KEY_CH_RES_DATA_ENABLE
|
||||
#if !CFG_CHx_DEBUG_ENABLE
|
||||
#undef CFG_CHx_DEBUG_ENABLE
|
||||
#define CFG_CHx_DEBUG_ENABLE 0b11111
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#if (CFG_CH0_DEBUG_ENABLE || CFG_CH1_DEBUG_ENABLE || CFG_CH2_DEBUG_ENABLE || CFG_CH3_DEBUG_ENABLE || CFG_CH4_DEBUG_ENABLE)
|
||||
#if !CFG_DISABLE_KEY_EVENT
|
||||
#undef CFG_DISABLE_KEY_EVENT
|
||||
#define CFG_DISABLE_KEY_EVENT 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#define ERATCH_KEY_MSG_LOCK_TIME 3000 //ms 入耳检测状态发生改变时，多长时间内不能发送按键消息
|
||||
|
||||
|
||||
/*************************************************** Lpctmu API **********************************************************/
|
||||
#define LP_CTMU_CHANNEL_SIZE 5
|
||||
|
||||
enum LP_TOUCH_SOFTOFF_MODE {
|
||||
LP_TOUCH_SOFTOFF_MODE_LEGACY = 0, //普通关机
|
||||
LP_TOUCH_SOFTOFF_MODE_ADVANCE = 1, //带触摸关机
|
||||
};
|
||||
|
||||
enum ctmu_key_event {
|
||||
CTMU_KEY_NULL,
|
||||
CTMU_KEY_SHORT_CLICK,
|
||||
CTMU_KEY_LONG_CLICK,
|
||||
CTMU_KEY_HOLD_CLICK,
|
||||
};
|
||||
|
||||
|
||||
enum {
|
||||
TOUCH_KEY_EVENT_SLIDE_UP,
|
||||
TOUCH_KEY_EVENT_SLIDE_DOWN,
|
||||
TOUCH_KEY_EVENT_SLIDE_LEFT,
|
||||
TOUCH_KEY_EVENT_SLIDE_RIGHT,
|
||||
TOUCH_KEY_EVENT_MAX,
|
||||
};
|
||||
|
||||
|
||||
struct ctmu_ch_cfg {
|
||||
u8 enable;
|
||||
u8 wakeup_enable;
|
||||
u8 key_value;
|
||||
u8 port;
|
||||
u8 sensitivity;
|
||||
};
|
||||
|
||||
struct lp_touch_key_platform_data {
|
||||
u8 slide_mode_en;
|
||||
u8 slide_mode_key_value;
|
||||
u8 eartch_en;
|
||||
u8 eartch_ch;
|
||||
u8 eartch_ref_ch;
|
||||
u16 eartch_soft_inear_val;
|
||||
u16 eartch_soft_outear_val;
|
||||
struct ctmu_ch_cfg ch[LP_CTMU_CHANNEL_SIZE];
|
||||
};
|
||||
|
||||
enum ch1_event_list {
|
||||
EAR_IN,
|
||||
EAR_OUT,
|
||||
};
|
||||
|
||||
enum {
|
||||
EPD_IN,
|
||||
EPD_OUT,
|
||||
EPD_STATE_NO_CHANCE
|
||||
};
|
||||
|
||||
struct ch_ana_cfg {
|
||||
u8 isel;
|
||||
u8 vhsel;
|
||||
u8 vlsel;
|
||||
};
|
||||
|
||||
struct ch_adjust_table {
|
||||
u16 cfg0;
|
||||
u16 cfg1;
|
||||
u16 cfg2;
|
||||
};
|
||||
|
||||
struct ctmu_key {
|
||||
u8 init;
|
||||
u8 softoff_mode;
|
||||
u8 slide_dir;
|
||||
u8 click_cnt[LP_CTMU_CHANNEL_SIZE];
|
||||
u8 last_key[LP_CTMU_CHANNEL_SIZE];
|
||||
u16 short_timer[LP_CTMU_CHANNEL_SIZE];
|
||||
|
||||
u8 key_ch_msg_lock;
|
||||
u16 key_ch_msg_lock_timer;
|
||||
|
||||
u8 eartch_inear_ok;
|
||||
u8 eartch_last_state;
|
||||
u8 eartch_trim_flag;
|
||||
u16 eartch_trim_value;
|
||||
|
||||
const struct lp_touch_key_platform_data *config;
|
||||
};
|
||||
|
||||
extern struct ctmu_key _ctmu_key;
|
||||
|
||||
|
||||
void lp_touch_key_init(const struct lp_touch_key_platform_data *config);
|
||||
|
||||
u8 lp_touch_key_power_on_status();
|
||||
|
||||
void lp_touch_key_disable(void);
|
||||
|
||||
void lp_touch_key_enable(void);
|
||||
|
||||
u8 lp_touch_key_alog_range_display(u8 *display_buf);
|
||||
|
||||
void lp_touch_key_send_cmd(enum CTMU_M2P_CMD cmd);
|
||||
|
||||
void set_lpkey_active(u8 set);
|
||||
|
||||
u8 lp_touch_key_alog_range_display(u8 *display_buf);
|
||||
|
||||
#endif /* #ifndef _LP_TOUCH_KEY_API_ */
|
||||
148
include_lib/driver/cpu/br28/asm/lp_touch_key_hw.h
Normal file
148
include_lib/driver/cpu/br28/asm/lp_touch_key_hw.h
Normal file
@ -0,0 +1,148 @@
|
||||
#ifndef _LP_TOUCH_KEY_HW_H_
|
||||
#define _LP_TOUCH_KEY_HW_H_
|
||||
|
||||
/**************************************************************P11 通讯定义*****************************************************************/
|
||||
|
||||
enum CTMU_P2M_EVENT {
|
||||
CTMU_P2M_CH0_RES_EVENT = 0x50,
|
||||
CTMU_P2M_CH0_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH0_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH0_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH0_FALLING_EVENT,
|
||||
CTMU_P2M_CH0_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH1_RES_EVENT = 0x58,
|
||||
CTMU_P2M_CH1_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH1_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH1_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH1_FALLING_EVENT,
|
||||
CTMU_P2M_CH1_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH2_RES_EVENT = 0x60,
|
||||
CTMU_P2M_CH2_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH2_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH2_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH2_FALLING_EVENT,
|
||||
CTMU_P2M_CH2_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH3_RES_EVENT = 0x68,
|
||||
CTMU_P2M_CH3_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH3_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH3_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH3_FALLING_EVENT,
|
||||
CTMU_P2M_CH3_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_CH4_RES_EVENT = 0x70,
|
||||
CTMU_P2M_CH4_SHORT_KEY_EVENT,
|
||||
CTMU_P2M_CH4_LONG_KEY_EVENT,
|
||||
CTMU_P2M_CH4_HOLD_KEY_EVENT,
|
||||
CTMU_P2M_CH4_FALLING_EVENT,
|
||||
CTMU_P2M_CH4_RAISING_EVENT,
|
||||
|
||||
CTMU_P2M_EARTCH_IN_EVENT = 0x78,
|
||||
CTMU_P2M_EARTCH_OUT_EVENT,
|
||||
};
|
||||
|
||||
enum CTMU_M2P_CMD {
|
||||
CTMU_M2P_INIT = 0x50,
|
||||
CTMU_M2P_DISABLE, //模块关闭
|
||||
CTMU_M2P_ENABLE, //模块使能
|
||||
CTMU_M2P_CH0_ENABLE, //通道0打开
|
||||
CTMU_M2P_CH0_DISABLE, //通道0关闭
|
||||
CTMU_M2P_CH1_ENABLE, //通道1打开
|
||||
CTMU_M2P_CH1_DISABLE, //通道1关闭
|
||||
CTMU_M2P_CH2_ENABLE, //通道2打开
|
||||
CTMU_M2P_CH2_DISABLE, //通道2关闭
|
||||
CTMU_M2P_CH3_ENABLE, //通道3打开
|
||||
CTMU_M2P_CH3_DISABLE, //通道3关闭
|
||||
CTMU_M2P_CH4_ENABLE, //通道4打开
|
||||
CTMU_M2P_CH4_DISABLE, //通道4关闭
|
||||
CTMU_M2P_UPDATE_BASE_TIME, //更新时基参数
|
||||
CTMU_M2P_CHARGE_ENTER_MODE, //进仓充电模式
|
||||
CTMU_M2P_CHARGE_EXIT_MODE, //退出充电模式
|
||||
CTMU_M2P_RESET_ALGO, //单独复位触摸算法
|
||||
};
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// P11: P2M_MESSAGE_CTMU_WKUP_MSG
|
||||
// MSYS: P2M_CTMU_CTMU_WKUP_MSG
|
||||
// 消息列表
|
||||
// 作用: 与主系统同步消息, 缓解异步问题
|
||||
/////////////////////////////////////////////////
|
||||
#define P2M_MESSAGE_POWER_ON_FLAG BIT(0) //lpctmu长按开机标志, 0: 非长按开机, 1: 长按开机, P11/MSYS清0, P11置位, 主系统查询
|
||||
#define P2M_MESSAGE_SYNC_FLAG BIT(1) //主系统清0, P11置位, 主系统查询置位, 解决异步问题
|
||||
#define P2M_MESSAGE_KEY_ACTIVE_FLAG BIT(2) //lpctmu按键状态, 1: 按键按下, 0: 按键抬起, P11清0, P11置位, 主系统查询
|
||||
#define P2M_MESSAGE_INIT_MODE_FLAG BIT(3) //lpctmu初始化模式, 0: 普通初始化(复位硬件,复位算法,初始化定时器), 1: 连续工作初始化(恢复定时器工作), 主系统清0, 主系统置位, P11查询
|
||||
#define P2M_MESSAGE_RESET_ALGO_FLAG BIT(4) //主系统清0, P11置位, 主系统查询置位，用于内置触摸算法的复位
|
||||
|
||||
|
||||
//=======================================================================//
|
||||
// LPCTMU ANA0 //
|
||||
//=======================================================================//
|
||||
//------------------- 上限电压配置: P11_LPCTM->ANA0[7:6]
|
||||
/*
|
||||
上限电压表:
|
||||
0: 0.65V
|
||||
1: 0.70V
|
||||
2: 0.75V
|
||||
3: 0.80V
|
||||
*/
|
||||
enum LPCTM_VH_TABLE {
|
||||
LPCTMU_VH_065V = (0 << 6),
|
||||
LPCTMU_VH_070V = (1 << 6),
|
||||
LPCTMU_VH_075V = (2 << 6),
|
||||
LPCTMU_VH_080V = (3 << 6),
|
||||
};
|
||||
|
||||
//------------------- 下限电压配置: P11_LPCTM->ANA0[5:4]
|
||||
/*
|
||||
下限电压表:
|
||||
0: 0.20V
|
||||
1: 0.25V
|
||||
2: 0.30V
|
||||
3: 0.35V
|
||||
*/
|
||||
enum LPCTM_VL_TABLE {
|
||||
LPCTMU_VL_020V = (0 << 4),
|
||||
LPCTMU_VL_025V = (1 << 4),
|
||||
LPCTMU_VL_030V = (2 << 4),
|
||||
LPCTMU_VL_035V = (3 << 4),
|
||||
};
|
||||
|
||||
//------------------- 充放电电流配置: P11_LPCTM->ANA0[3:1]
|
||||
/*
|
||||
充放电电流表:
|
||||
0: 3.6 uA
|
||||
1: 7.2 uA
|
||||
2: 10.8 uA
|
||||
3: 14.4 uA
|
||||
4: 18.2 uA
|
||||
5: 21.6 uA
|
||||
6: 25.2 uA
|
||||
7: 28.8 uA
|
||||
*/
|
||||
enum LPCTM_ISEL_TABLE {
|
||||
LPCTMU_ISEL_036UA = (0 << 1),
|
||||
LPCTMU_ISEL_072UA = (1 << 1),
|
||||
LPCTMU_ISEL_108UA = (2 << 1),
|
||||
LPCTMU_ISEL_144UA = (3 << 1),
|
||||
LPCTMU_ISEL_180UA = (4 << 1),
|
||||
LPCTMU_ISEL_216UA = (5 << 1),
|
||||
LPCTMU_ISEL_252UA = (6 << 1),
|
||||
LPCTMU_ISEL_288UA = (7 << 1)
|
||||
};
|
||||
|
||||
u8 get_lpctmu_ana_level(void);
|
||||
|
||||
#define LPCTMU_ANA0_CONFIG(x) (P11_LPCTM->ANA0 = x)
|
||||
|
||||
/**********************************************************算法流程配置**********************************************************************************/
|
||||
#define CTMU_SAMPLE_RATE_PRD 20 //kick start采样周期, 单位: ms
|
||||
|
||||
#define CTMU_SHORT_CLICK_DELAY_TIME 400 //单击事件后等待下一次单击时间(ms)
|
||||
#define CTMU_HOLD_CLICK_DELAY_TIME 200 //long事件产生后, 发hold事件间隔(ms)
|
||||
#define CTMU_LONG_KEY_DELAY_TIME 2000 //从按下到产生long事件的时间(ms)
|
||||
|
||||
#endif /* #ifndef _LP_TOUCH_KEY_HW_H_ */
|
||||
|
||||
|
||||
29
include_lib/driver/cpu/br28/asm/lp_touch_key_tool.h
Normal file
29
include_lib/driver/cpu/br28/asm/lp_touch_key_tool.h
Normal file
@ -0,0 +1,29 @@
|
||||
#ifndef __LP_TOUCH_KEY_TOOL__
|
||||
#define __LP_TOUCH_KEY_TOOL__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
enum {
|
||||
BT_KEY_CH_RES_MSG,
|
||||
BT_EARTCH_RES_MSG,
|
||||
BT_EVENT_HW_MSG,
|
||||
BT_EVENT_SW_MSG,
|
||||
BT_EVENT_VDDIO,
|
||||
};
|
||||
|
||||
//tws
|
||||
void lpctmu_tws_send_event_data(int msg, int type);
|
||||
void lpctmu_tws_send_res_data(int data1, int data2, int data3, int data4, int data5, int type);
|
||||
|
||||
//spp
|
||||
int lp_touch_key_online_debug_init(void);
|
||||
int lp_touch_key_online_debug_send(u8 ch, u16 val);
|
||||
int lp_touch_key_online_debug_key_event_handle(u8 ch_index, struct sys_event *event);
|
||||
|
||||
//testbox
|
||||
u8 lp_touch_key_testbox_remote_test(u8 ch, u8 event);
|
||||
void lp_touch_key_testbox_inear_trim(u8 flag);
|
||||
|
||||
#endif
|
||||
|
||||
74
include_lib/driver/cpu/br28/asm/mcpwm.h
Normal file
74
include_lib/driver/cpu/br28/asm/mcpwm.h
Normal file
@ -0,0 +1,74 @@
|
||||
#ifndef _MCPWM_H_
|
||||
#define _MCPWM_H_
|
||||
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
|
||||
/* 对齐方式选择 */
|
||||
typedef enum {
|
||||
pwm_edge_aligned, ///< 边沿对齐模式
|
||||
pwm_center_aligned, ///< 中心对齐模式
|
||||
} pwm_aligned_mode_type;
|
||||
|
||||
/* pwm通道选择 */
|
||||
typedef enum {
|
||||
pwm_ch0,
|
||||
pwm_ch1,
|
||||
pwm_ch2,
|
||||
pwm_ch3,
|
||||
pwm_ch_max,
|
||||
} pwm_ch_num_type;
|
||||
|
||||
/* MCPWM TIMER寄存器 */
|
||||
typedef struct _pwm_timer_reg {
|
||||
volatile u32 tmr_con;
|
||||
volatile u32 tmr_cnt;
|
||||
volatile u32 tmr_pr;
|
||||
} PWM_TIMER_REG;
|
||||
|
||||
/* MCPWM通道寄存器 */
|
||||
typedef struct _pwm_ch_reg {
|
||||
volatile u32 ch_con0;
|
||||
volatile u32 ch_con1;
|
||||
volatile u32 ch_cmph;
|
||||
volatile u32 ch_cmpl;
|
||||
} PWM_CH_REG;
|
||||
|
||||
/* 初始化要用的参数结构体 */
|
||||
struct pwm_platform_data {
|
||||
pwm_aligned_mode_type pwm_aligned_mode; ///< PWM对齐方式选择
|
||||
pwm_ch_num_type pwm_ch_num; ///< 选择pwm通道号
|
||||
u32 frequency; ///< 初始共同频率，CH0, CH, CH2,,,,,,
|
||||
u16 duty; ///< 初始占空比，0~10000 对应 0%~100% 。每个通道可以有不同的占空比。互补模式的占空比体现在高引脚的波形上。
|
||||
u8 h_pin; ///< 一个通道的H引脚。
|
||||
u8 l_pin; ///< 一个通道的L引脚，不需要则填-1
|
||||
u8 complementary_en; ///< 该通道的两个引脚输出的波形。0: 同步， 1: 互补，互补波形的占空比体现在H引脚上
|
||||
};
|
||||
|
||||
|
||||
|
||||
void mcpwm_set_frequency(pwm_ch_num_type ch, pwm_aligned_mode_type align, u32 frequency);
|
||||
void mcpwm_set_duty(pwm_ch_num_type pwm_ch, u16 duty);
|
||||
void mctimer_ch_open_or_close(pwm_ch_num_type pwm_ch, u8 enable);
|
||||
void mcpwm_ch_open_or_close(pwm_ch_num_type pwm_ch, u8 enable);
|
||||
void mcpwm_open(pwm_ch_num_type pwm_ch);
|
||||
void mcpwm_close(pwm_ch_num_type pwm_ch);
|
||||
void mcpwm_init(struct pwm_platform_data *arg);
|
||||
void mcpwm_test(void);
|
||||
|
||||
|
||||
void set_io_ext_interrupt_cbfun(void (*cbfun)(u8 index));
|
||||
void io_ext_interrupt_init(u8 index, u8 port, u8 trigger_mode);
|
||||
void io_ext_interrupt_close(u8 index, u8 port);
|
||||
void io_ext_interrupt_test(void);
|
||||
|
||||
|
||||
void timer_pwm_init(JL_TIMER_TypeDef *JL_TIMERx, u32 pwm_io, u32 fre, u32 duty);
|
||||
void set_timer_pwm_duty(JL_TIMER_TypeDef *JL_TIMERx, u32 duty);
|
||||
void timer_pwm_test(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
29
include_lib/driver/cpu/br28/asm/plcnt.h
Normal file
29
include_lib/driver/cpu/br28/asm/plcnt.h
Normal file
@ -0,0 +1,29 @@
|
||||
#ifndef _PLCNT_DRV_H_
|
||||
#define _PLCNT_DRV_H_
|
||||
|
||||
|
||||
#define PLCNT_KEY_CH_MAX 3
|
||||
|
||||
struct touch_key_port {
|
||||
u16 press_delta; //按下判决的阈值
|
||||
u8 port; //触摸按键IO
|
||||
u8 key_value; //按键返回值
|
||||
};
|
||||
|
||||
struct touch_key_platform_data {
|
||||
u8 num; //触摸按键个数
|
||||
const struct touch_key_port *port_list;
|
||||
};
|
||||
|
||||
|
||||
/* =========== pclcnt API ============= */
|
||||
//plcnt 初始化
|
||||
int plcnt_init(void *_data);
|
||||
|
||||
//获取plcnt按键状态
|
||||
u8 get_plcnt_value(void);
|
||||
|
||||
|
||||
#endif /* _PLCNT_DRV_H_ */
|
||||
|
||||
|
||||
256
include_lib/driver/cpu/br28/asm/power/lp_ipc.h
Normal file
256
include_lib/driver/cpu/br28/asm/power/lp_ipc.h
Normal file
@ -0,0 +1,256 @@
|
||||
#ifndef __LP_IPC_H__
|
||||
#define __LP_IPC_H__
|
||||
|
||||
//=================================消息格式========================================
|
||||
|
||||
//消息buf大小
|
||||
#define MAX_POOL 128
|
||||
|
||||
//消息类型
|
||||
#define NO_MSG 0xff
|
||||
|
||||
//获取消息返回值
|
||||
enum {
|
||||
MSG_NO_ERROR = 0,
|
||||
MSG_NO_MSG = 0,
|
||||
MSG_EVENT_EXIST = -1,
|
||||
MSG_NOT_EVENT = -2,
|
||||
MSG_EVENT_PARAM_ERROR = -3,
|
||||
MSG_BUF_NOT_ENOUGH = -4,
|
||||
MSG_CBUF_ERROR = -5,
|
||||
};
|
||||
|
||||
//消息头格式
|
||||
#define MSG_HEADER_BYTE_LEN 3
|
||||
#define MSG_HEADER_BIT_LEN (MSG_HEADER_BYTE_LEN*8)
|
||||
#define MSG_HEADER_ALL_BIT ((1L<<MSG_HEADER_BIT_LEN) - 1)
|
||||
|
||||
#define MSG_INDEX_BIT 7
|
||||
#define MSG_ACK_BIT 1
|
||||
|
||||
#define MSG_TYPE_BIT_LEN 12
|
||||
#define MSG_PARAM_BIT_LEN (MSG_HEADER_BYTE_LEN*8-MSG_TYPE_BIT_LEN-MSG_INDEX_BIT-MSG_ACK_BIT)
|
||||
|
||||
//=================================M2P===========================================
|
||||
//M2P中断索引
|
||||
enum {
|
||||
M2P_LP_INDEX = 0,
|
||||
M2P_PF_INDEX,
|
||||
M2P_LLP_INDEX,
|
||||
M2P_P33_INDEX,
|
||||
M2P_SF_INDEX,
|
||||
M2P_CTMU_INDEX,
|
||||
M2P_CCMD_INDEX, //common cmd
|
||||
M2P_VAD_INDEX,
|
||||
M2P_USER_INDEX,
|
||||
M2P_WDT_INDEX,
|
||||
M2P_SYNC_INDEX,
|
||||
M2P_APP_INDEX,
|
||||
};
|
||||
|
||||
#define M2P_LRC_PRD M2P_MESSAGE_ACCESS(0x000)
|
||||
#define M2P_WDVDD M2P_MESSAGE_ACCESS(0x001)
|
||||
#define M2P_LRC_TMR_50us M2P_MESSAGE_ACCESS(0x002)
|
||||
#define M2P_LRC_TMR_200us M2P_MESSAGE_ACCESS(0x003)
|
||||
#define M2P_LRC_TMR_600us M2P_MESSAGE_ACCESS(0x004)
|
||||
#define M2P_VDDIO_KEEP M2P_MESSAGE_ACCESS(0x005)
|
||||
#define M2P_LRC_KEEP M2P_MESSAGE_ACCESS(0x006)
|
||||
#define M2P_SYNC_CMD M2P_MESSAGE_ACCESS(0x007)
|
||||
#define M2P_MESSAGE_VAD_CMD M2P_MESSAGE_ACCESS(0x008)
|
||||
#define M2P_MESSAGE_VAD_CBUF_RPTR M2P_MESSAGE_ACCESS(0x009)
|
||||
#define M2P_VDDIO_KEEP_TYPE M2P_MESSAGE_ACCESS(0x00a)
|
||||
#define M2P_RCH_FEQ_H M2P_MESSAGE_ACCESS(0x00b)
|
||||
#define M2P_MEM_CONTROL M2P_MESSAGE_ACCESS(0x00c)
|
||||
#define M2P_BTOSC_KEEP M2P_MESSAGE_ACCESS(0x00d)
|
||||
#define M2P_CTMU_KEEP M2P_MESSAGE_ACCESS(0x00e)
|
||||
#define M2P_RTC_KEEP M2P_MESSAGE_ACCESS(0x00f)
|
||||
#define M2P_WDT_SYNC M2P_MESSAGE_ACCESS(0x010)
|
||||
#define M2P_LIGHT_PDOWN_DVDD_VOL M2P_MESSAGE_ACCESS(0x011)
|
||||
#define M2P_PVDD_LEVEL_SLEEP_TRIM M2P_MESSAGE_ACCESS(0x012)
|
||||
|
||||
|
||||
/*触摸所有通道配置*/
|
||||
#define M2P_CTMU_CMD M2P_MESSAGE_ACCESS(0x18)
|
||||
#define M2P_CTMU_MSG M2P_MESSAGE_ACCESS(0x19)
|
||||
#define M2P_CTMU_PRD0 M2P_MESSAGE_ACCESS(0x1a)
|
||||
#define M2P_CTMU_PRD1 M2P_MESSAGE_ACCESS(0x1b)
|
||||
#define M2P_CTMU_CH_ENABLE M2P_MESSAGE_ACCESS(0x1c)
|
||||
#define M2P_CTMU_CH_DEBUG M2P_MESSAGE_ACCESS(0x1d)
|
||||
#define M2P_CTMU_CH_CFG M2P_MESSAGE_ACCESS(0x1e)
|
||||
#define M2P_CTMU_CH_WAKEUP_EN M2P_MESSAGE_ACCESS(0x1f)
|
||||
#define M2P_CTMU_EARTCH_CH M2P_MESSAGE_ACCESS(0x20)
|
||||
#define M2P_CTMU_TIME_BASE M2P_MESSAGE_ACCESS(0x21)
|
||||
|
||||
#define M2P_CTMU_LONG_TIMEL M2P_MESSAGE_ACCESS(0x22)
|
||||
#define M2P_CTMU_LONG_TIMEH M2P_MESSAGE_ACCESS(0x23)
|
||||
#define M2P_CTMU_HOLD_TIMEL M2P_MESSAGE_ACCESS(0x24)
|
||||
#define M2P_CTMU_HOLD_TIMEH M2P_MESSAGE_ACCESS(0x25)
|
||||
#define M2P_CTMU_SOFTOFF_LONG_TIMEL M2P_MESSAGE_ACCESS(0x26)
|
||||
#define M2P_CTMU_SOFTOFF_LONG_TIMEH M2P_MESSAGE_ACCESS(0x27)
|
||||
#define M2P_CTMU_LONG_PRESS_RESET_TIME_VALUE_L M2P_MESSAGE_ACCESS(0x28)//长按复位
|
||||
#define M2P_CTMU_LONG_PRESS_RESET_TIME_VALUE_H M2P_MESSAGE_ACCESS(0x29)//长按复位
|
||||
|
||||
#define M2P_CTMU_INEAR_VALUE_L M2P_MESSAGE_ACCESS(0x2a)
|
||||
#define M2P_CTMU_INEAR_VALUE_H M2P_MESSAGE_ACCESS(0x2b)
|
||||
#define M2P_CTMU_OUTEAR_VALUE_L M2P_MESSAGE_ACCESS(0x2c)
|
||||
#define M2P_CTMU_OUTEAR_VALUE_H M2P_MESSAGE_ACCESS(0x2d)
|
||||
#define M2P_CTMU_EARTCH_TRIM_VALUE_L M2P_MESSAGE_ACCESS(0x2e)
|
||||
#define M2P_CTMU_EARTCH_TRIM_VALUE_H M2P_MESSAGE_ACCESS(0x2f)
|
||||
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG0L 0x30
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG0H 0x31
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG1L 0x32
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG1H 0x33
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG2L 0x34
|
||||
#define M2P_MASSAGE_CTMU_CH0_CFG2H 0x35
|
||||
|
||||
#define M2P_CTMU_CH0_CFG0L M2P_MESSAGE_ACCESS(0x30)
|
||||
#define M2P_CTMU_CH0_CFG0H M2P_MESSAGE_ACCESS(0x31)
|
||||
#define M2P_CTMU_CH0_CFG1L M2P_MESSAGE_ACCESS(0x32)
|
||||
#define M2P_CTMU_CH0_CFG1H M2P_MESSAGE_ACCESS(0x33)
|
||||
#define M2P_CTMU_CH0_CFG2L M2P_MESSAGE_ACCESS(0x34)
|
||||
#define M2P_CTMU_CH0_CFG2H M2P_MESSAGE_ACCESS(0x35)
|
||||
|
||||
#define M2P_CTMU_CH1_CFG0L M2P_MESSAGE_ACCESS(0x38)
|
||||
#define M2P_CTMU_CH1_CFG0H M2P_MESSAGE_ACCESS(0x39)
|
||||
#define M2P_CTMU_CH1_CFG1L M2P_MESSAGE_ACCESS(0x3a)
|
||||
#define M2P_CTMU_CH1_CFG1H M2P_MESSAGE_ACCESS(0x3b)
|
||||
#define M2P_CTMU_CH1_CFG2L M2P_MESSAGE_ACCESS(0x3c)
|
||||
#define M2P_CTMU_CH1_CFG2H M2P_MESSAGE_ACCESS(0x3d)
|
||||
|
||||
#define M2P_CTMU_CH2_CFG0L M2P_MESSAGE_ACCESS(0x40)
|
||||
#define M2P_CTMU_CH2_CFG0H M2P_MESSAGE_ACCESS(0x41)
|
||||
#define M2P_CTMU_CH2_CFG1L M2P_MESSAGE_ACCESS(0x42)
|
||||
#define M2P_CTMU_CH2_CFG1H M2P_MESSAGE_ACCESS(0x43)
|
||||
#define M2P_CTMU_CH2_CFG2L M2P_MESSAGE_ACCESS(0x44)
|
||||
#define M2P_CTMU_CH2_CFG2H M2P_MESSAGE_ACCESS(0x45)
|
||||
|
||||
#define M2P_CTMU_CH3_CFG0L M2P_MESSAGE_ACCESS(0x48)
|
||||
#define M2P_CTMU_CH3_CFG0H M2P_MESSAGE_ACCESS(0x49)
|
||||
#define M2P_CTMU_CH3_CFG1L M2P_MESSAGE_ACCESS(0x4a)
|
||||
#define M2P_CTMU_CH3_CFG1H M2P_MESSAGE_ACCESS(0x4b)
|
||||
#define M2P_CTMU_CH3_CFG2L M2P_MESSAGE_ACCESS(0x4c)
|
||||
#define M2P_CTMU_CH3_CFG2H M2P_MESSAGE_ACCESS(0x4d)
|
||||
|
||||
#define M2P_CTMU_CH4_CFG0L M2P_MESSAGE_ACCESS(0x50)
|
||||
#define M2P_CTMU_CH4_CFG0H M2P_MESSAGE_ACCESS(0x51)
|
||||
#define M2P_CTMU_CH4_CFG1L M2P_MESSAGE_ACCESS(0x52)
|
||||
#define M2P_CTMU_CH4_CFG1H M2P_MESSAGE_ACCESS(0x53)
|
||||
#define M2P_CTMU_CH4_CFG2L M2P_MESSAGE_ACCESS(0x54)
|
||||
#define M2P_CTMU_CH4_CFG2H M2P_MESSAGE_ACCESS(0x55)
|
||||
#define M2P_RVD2PVDD_EN M2P_MESSAGE_ACCESS(0x56)
|
||||
#define M2P_PVDD_EXTERN_DCDC M2P_MESSAGE_ACCESS(0x57)
|
||||
|
||||
#define M2P_USER_PEND (0x58)
|
||||
#define M2P_USER_MSG_TYPE (0x59)
|
||||
#define M2P_USER_MSG_LEN0 (0x5a)
|
||||
#define M2P_USER_MSG_LEN1 (0x5b)
|
||||
#define M2P_USER_ADDR0 (0x5c)
|
||||
#define M2P_USER_ADDR1 (0x5d)
|
||||
#define M2P_USER_ADDR2 (0x5e)
|
||||
#define M2P_USER_ADDR3 (0x5f)
|
||||
|
||||
enum {
|
||||
CLOSE_P33_INTERRUPT = 1,
|
||||
OPEN_P33_INTERRUPT,
|
||||
LOWPOWER_PREPARE,
|
||||
M2P_SPIN_LOCK,
|
||||
M2P_SPIN_UNLOCK,
|
||||
P2M_SPIN_LOCK,
|
||||
P2M_SPIN_UNLOCK,
|
||||
M2P_WDT_CLEAR,
|
||||
|
||||
P2M_RESERVED_CMD = 0xFF,
|
||||
};
|
||||
|
||||
//=================================P2M===========================================
|
||||
//P2M中断索引
|
||||
enum {
|
||||
P2M_LP_INDEX = 0,
|
||||
P2M_PF_INDEX,
|
||||
P2M_LLP_INDEX,
|
||||
P2M_WK_INDEX,
|
||||
P2M_WDT_INDEX,
|
||||
P2M_LP_INDEX2,
|
||||
P2M_CTMU_INDEX,
|
||||
P2M_CTMU_POWUP,
|
||||
P2M_REPLY_CCMD_INDEX, //reply common cmd
|
||||
P2M_VAD_INDEX,
|
||||
P2M_USER_INDEX,
|
||||
P2M_BANK_INDEX,
|
||||
P2M_REPLY_SYNC_INDEX,
|
||||
P2M_APP_INDEX,
|
||||
};
|
||||
|
||||
#define P2M_WKUP_SRC P2M_MESSAGE_ACCESS(0x000)
|
||||
#define P2M_WKUP_PND0 P2M_MESSAGE_ACCESS(0x001)
|
||||
#define P2M_WKUP_PND1 P2M_MESSAGE_ACCESS(0x002)
|
||||
#define P2M_REPLY_SYNC_CMD P2M_MESSAGE_ACCESS(0x003)
|
||||
#define P2M_MESSAGE_VAD_CMD P2M_MESSAGE_ACCESS(0x004)
|
||||
#define P2M_MESSAGE_VAD_CBUF_WPTR P2M_MESSAGE_ACCESS(0x005)
|
||||
#define P2M_MESSAGE_BANK_ADR_L P2M_MESSAGE_ACCESS(0x006)
|
||||
#define P2M_MESSAGE_BANK_ADR_H P2M_MESSAGE_ACCESS(0x007)
|
||||
#define P2M_MESSAGE_BANK_INDEX P2M_MESSAGE_ACCESS(0x008)
|
||||
#define P2M_MESSAGE_BANK_ACK P2M_MESSAGE_ACCESS(0x009)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_L P2M_MESSAGE_ACCESS(0x00A)
|
||||
#define P2M_P11_HEAP_BEGIN_ADDR_H P2M_MESSAGE_ACCESS(0x00B)
|
||||
#define P2M_P11_HEAP_SIZE_L P2M_MESSAGE_ACCESS(0x00C)
|
||||
#define P2M_P11_HEAP_SIZE_H P2M_MESSAGE_ACCESS(0x00D)
|
||||
|
||||
#define P2M_CTMU_KEY_EVENT P2M_MESSAGE_ACCESS(0x010)
|
||||
#define P2M_CTMU_KEY_CNT P2M_MESSAGE_ACCESS(0x011)
|
||||
#define P2M_CTMU_WKUP_MSG P2M_MESSAGE_ACCESS(0x012)
|
||||
#define P2M_CTMU_EARTCH_EVENT P2M_MESSAGE_ACCESS(0x013)
|
||||
|
||||
#define P2M_MASSAGE_CTMU_CH0_L_RES 0x014
|
||||
#define P2M_MASSAGE_CTMU_CH0_H_RES 0x015
|
||||
#define P2M_CTMU_CH0_L_RES P2M_MESSAGE_ACCESS(0x014)
|
||||
#define P2M_CTMU_CH0_H_RES P2M_MESSAGE_ACCESS(0x015)
|
||||
#define P2M_CTMU_CH1_L_RES P2M_MESSAGE_ACCESS(0x016)
|
||||
#define P2M_CTMU_CH1_H_RES P2M_MESSAGE_ACCESS(0x017)
|
||||
#define P2M_CTMU_CH2_L_RES P2M_MESSAGE_ACCESS(0x018)
|
||||
#define P2M_CTMU_CH2_H_RES P2M_MESSAGE_ACCESS(0x019)
|
||||
#define P2M_CTMU_CH3_L_RES P2M_MESSAGE_ACCESS(0x01a)
|
||||
#define P2M_CTMU_CH3_H_RES P2M_MESSAGE_ACCESS(0x01b)
|
||||
#define P2M_CTMU_CH4_L_RES P2M_MESSAGE_ACCESS(0x01c)
|
||||
#define P2M_CTMU_CH4_H_RES P2M_MESSAGE_ACCESS(0x01d)
|
||||
|
||||
#define P2M_CTMU_EARTCH_L_IIR_VALUE P2M_MESSAGE_ACCESS(0x01e)
|
||||
#define P2M_CTMU_EARTCH_H_IIR_VALUE P2M_MESSAGE_ACCESS(0x01f)
|
||||
#define P2M_CTMU_EARTCH_L_TRIM_VALUE P2M_MESSAGE_ACCESS(0x020)
|
||||
#define P2M_CTMU_EARTCH_H_TRIM_VALUE P2M_MESSAGE_ACCESS(0x021)
|
||||
#define P2M_CTMU_EARTCH_L_DIFF_VALUE P2M_MESSAGE_ACCESS(0x022)
|
||||
#define P2M_CTMU_EARTCH_H_DIFF_VALUE P2M_MESSAGE_ACCESS(0x023)
|
||||
|
||||
#define P2M_AWKUP_P_PND P2M_MESSAGE_ACCESS(0x024)
|
||||
#define P2M_AWKUP_N_PND P2M_MESSAGE_ACCESS(0x025)
|
||||
#define P2M_WKUP_RTC P2M_MESSAGE_ACCESS(0x026)
|
||||
|
||||
#define P2M_CBUF_ADDR0 P2M_MESSAGE_ACCESS(0x027)
|
||||
#define P2M_CBUF_ADDR1 P2M_MESSAGE_ACCESS(0x028)
|
||||
#define P2M_CBUF_ADDR2 P2M_MESSAGE_ACCESS(0x029)
|
||||
#define P2M_CBUF_ADDR3 P2M_MESSAGE_ACCESS(0x02a)
|
||||
|
||||
#define P2M_CBUF1_ADDR0 P2M_MESSAGE_ACCESS(0x02b)
|
||||
#define P2M_CBUF1_ADDR1 P2M_MESSAGE_ACCESS(0x02c)
|
||||
#define P2M_CBUF1_ADDR2 P2M_MESSAGE_ACCESS(0x02d)
|
||||
#define P2M_CBUF1_ADDR3 P2M_MESSAGE_ACCESS(0x02e)
|
||||
|
||||
#define P2M_USER_PEND (0x038)//传感器使用或者开放客户使用
|
||||
#define P2M_USER_MSG_TYPE (0x039)
|
||||
#define P2M_USER_MSG_LEN0 (0x03a)
|
||||
#define P2M_USER_MSG_LEN1 (0x03b)
|
||||
#define P2M_USER_ADDR0 (0x03c)
|
||||
#define P2M_USER_ADDR1 (0x03d)
|
||||
#define P2M_USER_ADDR2 (0x03e)
|
||||
#define P2M_USER_ADDR3 (0x040)
|
||||
|
||||
#include "m2p_msg.h"
|
||||
#include "p2m_msg.h"
|
||||
|
||||
|
||||
void msys_to_p11_sync_cmd(u8 cmd);
|
||||
|
||||
void lp_ipc_init();
|
||||
|
||||
#endif
|
||||
89
include_lib/driver/cpu/br28/asm/power/m2p_msg.h
Normal file
89
include_lib/driver/cpu/br28/asm/power/m2p_msg.h
Normal file
@ -0,0 +1,89 @@
|
||||
#ifndef __M2P_MSG_H__
|
||||
#define __M2P_MSG_H__
|
||||
|
||||
//m2p用户消息类型
|
||||
enum {
|
||||
M2P_MSG_ACK = BIT(0),
|
||||
M2P_MSG_TEST = BIT(1),
|
||||
M2P_MSG_COMMOM = BIT(2),
|
||||
M2P_MSG_CTMU = BIT(3),
|
||||
M2P_MSG_SENSOR = BIT(4),
|
||||
M2P_MSG_VAD = BIT(5),
|
||||
};
|
||||
|
||||
//测试
|
||||
struct m2p_msg_test {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//测试
|
||||
struct m2p_msg_ack {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//公共消息
|
||||
struct m2p_msg_common {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//触摸消息
|
||||
struct m2p_msg_ctmu {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//vad
|
||||
struct m2p_msg_vad {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//m2p用户消息格式
|
||||
struct m2p_msg_head {
|
||||
u16 type :
|
||||
MSG_TYPE_BIT_LEN;
|
||||
u16 len :
|
||||
MSG_PARAM_BIT_LEN;
|
||||
u8 index :
|
||||
MSG_INDEX_BIT;
|
||||
u8 ack :
|
||||
MSG_ACK_BIT;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct m2p_msg {
|
||||
struct m2p_msg_head head;
|
||||
union {
|
||||
struct m2p_msg_ack ack;
|
||||
struct m2p_msg_test test;
|
||||
struct m2p_msg_common com;
|
||||
struct m2p_msg_ctmu ctmu;
|
||||
struct m2p_msg_vad vad;
|
||||
} u;
|
||||
} __attribute__((packed));
|
||||
|
||||
//m2p用户消息对应处理
|
||||
struct m2p_msg_handler {
|
||||
u8 type;
|
||||
void (*handler)(struct m2p_msg *);
|
||||
} __attribute__((packed));
|
||||
|
||||
#define REGISTER_M2P_MSG_HANDLER(_type, fn, pri) \
|
||||
const struct m2p_msg_handler _##fn SEC_USED(.m2p_msg_handler)= { \
|
||||
.type = _type, \
|
||||
.handler = fn, \
|
||||
}
|
||||
|
||||
extern struct m2p_msg_handler m2p_msg_handler_begin[];
|
||||
extern struct m2p_msg_handler m2p_msg_handler_end[];
|
||||
|
||||
#define list_for_each_m2p_msg_handler(p) \
|
||||
for (p = m2p_msg_handler_begin; p < m2p_msg_handler_end; p++)
|
||||
|
||||
int m2p_get_msg(int len, struct m2p_msg *msg);
|
||||
|
||||
int m2p_post_msg(int len, struct m2p_msg *msg);
|
||||
|
||||
int m2p_post_sync_msg(int len, struct m2p_msg *msg, u8 abandon, int timeout);
|
||||
|
||||
void msys_to_p11_sys_cmd(u8 cmd);
|
||||
|
||||
|
||||
#endif
|
||||
23
include_lib/driver/cpu/br28/asm/power/p11.h
Normal file
23
include_lib/driver/cpu/br28/asm/power/p11.h
Normal file
@ -0,0 +1,23 @@
|
||||
/*********************************************************************************************
|
||||
* Filename : p11.h
|
||||
|
||||
* Description :
|
||||
|
||||
* Author : Bingquan
|
||||
|
||||
* Email : caibingquan@zh-jieli.com
|
||||
|
||||
* Last modifiled : 2019-12-09 10:21
|
||||
|
||||
* Copyright:(c)JIELI 2011-2019 @ , All Rights Reserved.
|
||||
*********************************************************************************************/
|
||||
#ifndef __P11_H__
|
||||
#define __P11_H__
|
||||
|
||||
#include "p11_csfr.h"
|
||||
#include "p11_sfr.h"
|
||||
#include "p11_app.h"
|
||||
|
||||
#endif /* #ifndef __P11_H__ */
|
||||
|
||||
|
||||
239
include_lib/driver/cpu/br28/asm/power/p11_app.h
Normal file
239
include_lib/driver/cpu/br28/asm/power/p11_app.h
Normal file
@ -0,0 +1,239 @@
|
||||
/*********************************************************************************************
|
||||
* Filename : p11_app.h
|
||||
|
||||
* Description : 本文件基于p11.h文件封装应用的接口
|
||||
|
||||
* Author : MoZhiYe
|
||||
|
||||
* Email : mozhiye@zh-jieli.com
|
||||
|
||||
* Last modifiled : 2021-04-19 09:00
|
||||
|
||||
* Copyright:(c)JIELI 2021-2029 @ , All Rights Reserved.
|
||||
*********************************************************************************************/
|
||||
#ifndef __P11_APP_H__
|
||||
#define __P11_APP_H__
|
||||
|
||||
#include "p11.h"
|
||||
|
||||
/*
|
||||
|
||||
_______________ <-----P11 Message Acess End
|
||||
| poweroff boot |
|
||||
|_______________|
|
||||
| m2p msg(0x40) |
|
||||
|_______________|
|
||||
| p2m msg(0x40) |
|
||||
|_______________|<-----P11 Message Acess Begin
|
||||
| |
|
||||
| p11 use |
|
||||
|_______________|__
|
||||
|
||||
*/
|
||||
#define P11_RAM_BASE 0xF20000
|
||||
#define P11_RAM_SIZE (0x8000)
|
||||
#define P11_RAM_END (P11_RAM_BASE + P11_RAM_SIZE)
|
||||
|
||||
#define P11_POWEROFF_RAM_SIZE (0x14 + 0xc)
|
||||
#define P11_POWEROFF_RAM_BEGIN (P11_RAM_END - P11_POWEROFF_RAM_SIZE)
|
||||
|
||||
#define P2M_MESSAGE_SIZE 0x40
|
||||
#define M2P_MESSAGE_SIZE 0x60
|
||||
|
||||
#define M2P_MESSAGE_RAM_BEGIN (P11_POWEROFF_RAM_BEGIN - M2P_MESSAGE_SIZE)
|
||||
#define P2M_MESSAGE_RAM_BEGIN (M2P_MESSAGE_RAM_BEGIN - P2M_MESSAGE_SIZE)
|
||||
|
||||
#define P11_MESSAGE_RAM_BEGIN (P2M_MESSAGE_RAM_BEGIN)
|
||||
|
||||
#define P11_RAM_ACCESS(x) (*(volatile u8 *)(x))
|
||||
|
||||
#define P2M_MESSAGE_ACCESS(x) P11_RAM_ACCESS(P2M_MESSAGE_RAM_BEGIN + x)
|
||||
#define M2P_MESSAGE_ACCESS(x) P11_RAM_ACCESS(M2P_MESSAGE_RAM_BEGIN + x)
|
||||
|
||||
//==========================================================//
|
||||
// P11_VAD_RAM //
|
||||
//==========================================================//
|
||||
//-------------------------- VAD CBUF-----------------------//
|
||||
#define VAD_POINT_PER_FRAME (160)
|
||||
#define VAD_FRAME_SIZE (160 * 2)
|
||||
#define VAD_CBUF_FRAME_CNT (6)
|
||||
#define VAD_CBUF_TAG_SIZE (0)
|
||||
#define VAD_CBUF_FRAME_SIZE (VAD_FRAME_SIZE + VAD_CBUF_TAG_SIZE)
|
||||
#define CONFIG_P11_CBUF_SIZE (VAD_CBUF_FRAME_SIZE * VAD_CBUF_FRAME_CNT)
|
||||
#define VAD_CBUF_END (P11_MESSAGE_RAM_BEGIN - 0x20)
|
||||
#define VAD_CBUF_BEGIN (VAD_CBUF_END - CONFIG_P11_CBUF_SIZE)
|
||||
|
||||
//------------------------ VAD CONFIG-----------------------//
|
||||
#define CONFIG_P2M_AVAD_CONFIG_SIZE (20 * 4) //sizeof(int)
|
||||
#define CONFIG_P2M_DVAD_CONFIG_SIZE (20 * 4) //sizeof(int)
|
||||
#define CONFIG_VAD_CONFIG_SIZE (CONFIG_P2M_AVAD_CONFIG_SIZE + CONFIG_P2M_DVAD_CONFIG_SIZE)
|
||||
#define VAD_AVAD_CONFIG_BEGIN (VAD_CBUF_BEGIN - CONFIG_P2M_AVAD_CONFIG_SIZE)
|
||||
#define VAD_DVAD_CONFIG_BEGIN (VAD_AVAD_CONFIG_BEGIN - CONFIG_P2M_DVAD_CONFIG_SIZE)
|
||||
|
||||
#define P11_HEAP_BEGIN (P11_RAM_BASE + ((P2M_P11_HEAP_BEGIN_ADDR_H << 8) | P2M_P11_HEAP_BEGIN_ADDR_L))
|
||||
#define P11_HEAP_SIZE ((P2M_P11_HEAP_SIZE_H << 8) | P2M_P11_HEAP_SIZE_L)
|
||||
|
||||
#define P11_RAM_PROTECT_END (P11_HEAP_BEGIN)
|
||||
|
||||
|
||||
#define P11_PWR_CON P11_CLOCK->PWR_CON
|
||||
|
||||
/*
|
||||
*------------------- P11_CLOCK->CLK_CON
|
||||
*/
|
||||
|
||||
#define P11_CLK_CON0 P11_CLOCK->CLK_CON0
|
||||
enum P11_SYS_CLK_TABLE {
|
||||
P11_SYS_CLK_RC250K = 0,
|
||||
P11_SYS_CLK_RC16M,
|
||||
P11_SYS_CLK_LRC_OSC,
|
||||
P11_SYS_CLK_BTOSC_24M,
|
||||
P11_SYS_CLK_BTOSC_48M,
|
||||
P11_SYS_CLK_PLL_SYS_CLK,
|
||||
P11_SYS_CLK_CLK_X2,
|
||||
};
|
||||
//#define P11_SYS_CLK_SEL(x) SFR(P11_CLOCK->CLK_CON0, 0, 3, x)
|
||||
#define P11_SYS_CLK_SEL(x) (P11_CLOCK->CLK_CON0 = x)
|
||||
|
||||
|
||||
//p11 btosc use d2sh
|
||||
#define CLOCK_KEEP(en) \
|
||||
if(en){ \
|
||||
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
|
||||
P11_CLOCK->CLK_CON1 |= BIT(14); \
|
||||
P11_CLOCK->CLK_CON1 |= (2<<15); \
|
||||
}else{ \
|
||||
P11_CLOCK->CLK_CON1 &= ~(3<<15); \
|
||||
P11_CLOCK->CLK_CON1 &= ~BIT(14); \
|
||||
}
|
||||
|
||||
#define P11_P2M_CLK_CON0 P11_SYSTEM->P2M_CLK_CON0
|
||||
#define P11_SYSTEM_CON0 P11_SYSTEM->P11_SYS_CON0
|
||||
#define P11_SYSTEM_CON1 P11_SYSTEM->P11_SYS_CON1
|
||||
#define P11_P11_SYS_CON0 P11_SYSTEM_CON0
|
||||
#define P11_P11_SYS_CON1 P11_SYSTEM_CON1
|
||||
#define P11_RST_SRC P11_CLOCK->RST_SRC
|
||||
|
||||
#define LED_CLK_SEL(x) P11_SYSTEM->P2M_CLK_CON0 = ((P11_SYSTEM->P2M_CLK_CON0 & ~0xe0) | (x) << 5)
|
||||
#define GET_LED_CLK_SEL(x) (P11_SYSTEM->P2M_CLK_CON0 & 0xe0)
|
||||
|
||||
#define P11_WDT_CON P11_WDT->CON
|
||||
|
||||
#define P11_P2M_INT_IE P11_SYSTEM->P2M_INT_IE
|
||||
#define P11_M2P_INT_IE P11_SYSTEM->M2P_INT_IE
|
||||
#define P11_M2P_INT_SET P11_SYSTEM->M2P_INT_SET
|
||||
#define P11_P2M_INT_SET P11_SYSTEM->P2M_INT_SET
|
||||
#define P11_P2M_INT_CLR P11_SYSTEM->P2M_INT_CLR
|
||||
#define P11_P2M_INT_PND P11_SYSTEM->P2M_INT_PND //?
|
||||
#define P11_M2P_INT_PND P11_SYSTEM->M2P_INT_PND //?
|
||||
|
||||
#define P11_TMR0_CON0 P11_LPTMR0->CON0
|
||||
#define P11_TMR0_CON1 P11_LPTMR0->CON1
|
||||
#define P11_TMR0_CON2 P11_LPTMR0->CON2
|
||||
#define P11_TMR0_CNT P11_LPTMR0->CNT
|
||||
#define P11_TMR0_PRD P11_LPTMR0->PRD
|
||||
#define P11_TMR0_RSC P11_LPTMR0->RSC
|
||||
|
||||
#define P11_TMR1_CON0 P11_LPTMR1->CON0
|
||||
#define P11_TMR1_CON1 P11_LPTMR1->CON1
|
||||
#define P11_TMR1_CON2 P11_LPTMR1->CON2
|
||||
#define P11_TMR1_CNT P11_LPTMR1->CNT
|
||||
#define P11_TMR1_PRD P11_LPTMR1->PRD
|
||||
#define P11_TMR1_RSC P11_LPTMR1->RSC
|
||||
|
||||
#define P11_TMR2_CON0 P11_LPTMR2->CON0
|
||||
#define P11_TMR2_CON1 P11_LPTMR2->CON1
|
||||
#define P11_TMR2_CON2 P11_LPTMR2->CON2
|
||||
#define P11_TMR2_CNT P11_LPTMR2->CNT
|
||||
#define P11_TMR2_PRD P11_LPTMR2->PRD
|
||||
#define P11_TMR2_RSC P11_LPTMR2->RSC
|
||||
|
||||
#define P11_TMR3_CON0 P11_LPTMR3->CON0
|
||||
#define P11_TMR3_CON1 P11_LPTMR3->CON1
|
||||
#define P11_TMR3_CON2 P11_LPTMR3->CON2
|
||||
#define P11_TMR3_CNT P11_LPTMR3->CNT
|
||||
#define P11_TMR3_PRD P11_LPTMR3->PRD
|
||||
#define P11_TMR3_RSC P11_LPTMR3->RSC
|
||||
|
||||
#define GET_P11_SYS_RST_SRC() P11_RST_SRC
|
||||
|
||||
#define LP_PWR_IDLE(x) SFR(P11_PWR_CON, 0, 1, x)
|
||||
#define LP_PWR_STANDBY(x) SFR(P11_PWR_CON, 1, 1, x)
|
||||
#define LP_PWR_SLEEP(x) SFR(P11_PWR_CON, 2, 1, x)
|
||||
#define LP_PWR_SSMODE(x) SFR(P11_PWR_CON, 3, 1, x)
|
||||
#define LP_PWR_SOFT_RESET(x) SFR(P11_PWR_CON, 4, 1, x)
|
||||
#define LP_PWR_INIT_FLAG() (P11_PWR_CON & BIT(5))
|
||||
#define LP_PWR_RST_FLAG_CLR(x) SFR(P11_PWR_CON, 6, 1, x)
|
||||
#define LP_PWR_RST_FLAG() (P11_PWR_CON & BIT(7))
|
||||
|
||||
#define P33_TEST_ENABLE() P11_P11_SYS_CON0 |= BIT(5)
|
||||
#define P33_TEST_DISABLE() P11_P11_SYS_CON0 &= ~BIT(5)
|
||||
|
||||
#define P11_TX_DISABLE(x) P11_SYSTEM->P11_SYS_CON1 |= BIT(2)
|
||||
#define P11_TX_ENABLE(x) P11_SYSTEM->P11_SYS_CON1 &= ~BIT(2)
|
||||
|
||||
#define MSYS_IO_LATCH_ENABLE() P11_SYSTEM->P11_SYS_CON1 |= BIT(7)
|
||||
#define MSYS_IO_LATCH_DISABLE() P11_SYSTEM->P11_SYS_CON1 &= ~BIT(7)
|
||||
|
||||
#define LP_TMR0_EN(x) SFR(P11_TMR0_CON0, 0, 1, x)
|
||||
#define LP_TMR0_CTU(x) SFR(P11_TMR0_CON0, 1, 1, x)
|
||||
#define LP_TMR0_P11_WKUP_IE(x) SFR(P11_TMR0_CON0, 2, 1, x)
|
||||
#define LP_TMR0_P11_TO_IE(x) SFR(P11_TMR0_CON0, 3, 1, x)
|
||||
#define LP_TMR0_CLR_P11_WKUP(x) SFR(P11_TMR0_CON0, 4, 1, x)
|
||||
#define LP_TMR0_P11_WKUP(x) (P11_TMR0_CON0 & BIT(5))
|
||||
#define LP_TMR0_CLR_P11_TO(x) SFR(P11_TMR0_CON0, 6, 1, x)
|
||||
#define LP_TMR0_P11_TO(x) (P11_TMR0_CON0 & BIT(7))
|
||||
|
||||
#define LP_TMR0_SW_KICK_START_EN(x) SFR(P11_TMR0_CON1, 0, 1, x)
|
||||
#define LP_TMR0_HW_KICK_START_EN(x) SFR(P11_TMR0_CON1, 1, 1, x)
|
||||
#define LP_TMR0_WKUP_IE(x) SFR(P11_TMR0_CON1, 2, 1, x)
|
||||
#define LP_TMR0_TO_IE(x) SFR(P11_TMR0_CON1, 3, 1, x)
|
||||
#define LP_TMR0_CLR_MSYS_WKUP(x) SFR(P11_TMR0_CON1, 4, 1, x)
|
||||
#define LP_TMR0_MSYS_WKUP(x) (P11_TMR0_CON1 & BIT(5))
|
||||
#define LP_TMR0_CLR_MSYS_TO(x) SFR(P11_TMR0_CON1, 6, 1, x)
|
||||
#define LP_TMR0_MSYS_TO(x) (P11_TMR0_CON1 & BIT(7))
|
||||
|
||||
#define LP_TMR0_CLK_SEL(x) SFR(P11_TMR0_CON2, 0, 4, x)
|
||||
#define LP_TMR0_CLK_DIV(x) SFR(P11_TMR0_CON2, 4, 4, x)
|
||||
#define LP_TMR0_KST(x) SFR(P11_TMR0_CON2, 8, 1, x)
|
||||
#define LP_TMR0_RUN() (P11_TMR0_CON2 & BIT(9))
|
||||
|
||||
#define P11_M2P_RESET_MASK(x) SFR(P11_P11_SYS_CON1 , 4, 1, x)
|
||||
|
||||
//MEM_PWR_CON
|
||||
#define MEM_PWR_CPU_CON BIT(0)
|
||||
#define MEM_PWR_RAM0_RAM3_CON BIT(1)
|
||||
#define MEM_PWR_RAM4_RAM5_CON BIT(2)
|
||||
#define MEM_PWR_RAM6_RAM7_CON BIT(3)
|
||||
#define MEM_PWR_RAM8_RAM9_CON BIT(4)
|
||||
#define MEM_PWR_PERIPH_CON BIT(5)
|
||||
|
||||
#define MEM_PWR_RAM_SET(a) (((1 << a) - 1) - 1)
|
||||
|
||||
#define LRC_Hz_DEFAULT (200 * 1000L)
|
||||
|
||||
#define LRC_CON0_INIT \
|
||||
/* */ (0 << 7) |\
|
||||
/* */ (0 << 6) |\
|
||||
/*RC32K_RPPS_S1_33v */ (1 << 5) |\
|
||||
/*RC32K_RPPS_S0_33v */ (0 << 4) |\
|
||||
/* */ (0 << 3) |\
|
||||
/* */ (0 << 2) |\
|
||||
/*RC32K_RN_TRIM_33v */ (0 << 1) |\
|
||||
/*RC32K_EN_33v */ (1 << 0)
|
||||
|
||||
#define LRC_CON1_INIT \
|
||||
/* */ (0 << 7) |\
|
||||
/*RC32K_CAP_S2_33v */ (1 << 6) |\
|
||||
/*RC32K_CAP_S1_33v */ (0 << 5) |\
|
||||
/*RC32K_CAP_S0_33v */ (0 << 4) |\
|
||||
/* 2bit */ (0 << 2) |\
|
||||
/*RC32K_RNPS_S1_33v */ (0 << 1) |\
|
||||
/*RC32K_RNPS_S0_33v */ (1 << 0)
|
||||
|
||||
void wdt_isr(void);
|
||||
u8 p11_run_query(void);
|
||||
|
||||
#endif /* #ifndef __P11_APP_H__ */
|
||||
|
||||
|
||||
176
include_lib/driver/cpu/br28/asm/power/p11_csfr.h
Normal file
176
include_lib/driver/cpu/br28/asm/power/p11_csfr.h
Normal file
@ -0,0 +1,176 @@
|
||||
//*********************************************************************************//
|
||||
// Module name : csfr.h //
|
||||
// Description : q32small core sfr define //
|
||||
// By Designer : zequan_liu //
|
||||
// Dat changed : //
|
||||
//*********************************************************************************//
|
||||
|
||||
#ifndef __P11_Q32S_CSFR__
|
||||
#define __P11_Q32S_CSFR__
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small define
|
||||
//---------------------------------------------//
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define p11_q32s_sfr_base 0x00a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#else
|
||||
#define p11_q32s_sfr_base 0xf2a000
|
||||
#define p11_q32s_sfr_offset 0x000000 // multi_core used
|
||||
#endif
|
||||
|
||||
#define p11_q32s_cpu_base (p11_q32s_sfr_base + 0x00)
|
||||
#define p11_q32s_mpu_base (p11_q32s_sfr_base + 0x80)
|
||||
|
||||
#define p11_q32s(n) ((JL_TypeDef_p11_q32s *)(p11_q32s_sfr_base + p11_q32s_sfr_offset*n))
|
||||
#define p11_q32s_mpu(n) ((JL_TypeDef_p11_q32s_MPU *)(p11_q32s_mpu_base + p11_q32s_sfr_offset*n))
|
||||
|
||||
//---------------------------------------------//
|
||||
// q32small core sfr
|
||||
//---------------------------------------------//
|
||||
|
||||
typedef struct {
|
||||
/* 00 */ __RO __u32 DR00;
|
||||
/* 01 */ __RO __u32 DR01;
|
||||
/* 02 */ __RO __u32 DR02;
|
||||
/* 03 */ __RO __u32 DR03;
|
||||
/* 04 */ __RO __u32 DR04;
|
||||
/* 05 */ __RO __u32 DR05;
|
||||
/* 06 */ __RO __u32 DR06;
|
||||
/* 07 */ __RO __u32 DR07;
|
||||
/* 08 */ __RO __u32 DR08;
|
||||
/* 09 */ __RO __u32 DR09;
|
||||
/* 0a */ __RO __u32 DR10;
|
||||
/* 0b */ __RO __u32 DR11;
|
||||
/* 0c */ __RO __u32 DR12;
|
||||
/* 0d */ __RO __u32 DR13;
|
||||
/* 0e */ __RO __u32 DR14;
|
||||
/* 0f */ __RO __u32 DR15;
|
||||
|
||||
/* 10 */ __RO __u32 RETI;
|
||||
/* 11 */ __RO __u32 RETE;
|
||||
/* 12 */ __RO __u32 RETX;
|
||||
/* 13 */ __RO __u32 RETS;
|
||||
/* 14 */ __RO __u32 SR04;
|
||||
/* 15 */ __RO __u32 PSR;
|
||||
/* 16 */ __RO __u32 CNUM;
|
||||
/* 17 */ __RO __u32 SR07;
|
||||
/* 18 */ __RO __u32 SR08;
|
||||
/* 19 */ __RO __u32 SR09;
|
||||
/* 1a */ __RO __u32 SR10;
|
||||
/* 1b */ __RO __u32 ICFG;
|
||||
/* 1c */ __RO __u32 USP;
|
||||
/* 1d */ __RO __u32 SSP;
|
||||
/* 1e */ __RO __u32 SP;
|
||||
/* 1f */ __RO __u32 PCRS;
|
||||
|
||||
/* 20 */ __RW __u32 BPCON;
|
||||
/* 21 */ __RW __u32 BSP;
|
||||
/* 22 */ __RW __u32 BP0;
|
||||
/* 23 */ __RW __u32 BP1;
|
||||
/* 24 */ __RW __u32 BP2;
|
||||
/* 25 */ __RW __u32 BP3;
|
||||
/* 26 */ __WO __u32 CMD_PAUSE;
|
||||
/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
|
||||
|
||||
/* 30 */ __RW __u32 PMU_CON;
|
||||
/* */ __RO __u32 REV_3b_30[0x3b - 0x30 - 1];
|
||||
/* 3b */ __RW __u8 TTMR_CON;
|
||||
/* 3c */ __RW __u32 TTMR_CNT;
|
||||
/* 3d */ __RW __u32 TTMR_PRD;
|
||||
/* 3e */ __RW __u32 BANK_CON;
|
||||
/* 3f */ __RW __u32 BANK_NUM;
|
||||
|
||||
/* 40 */ __RW __u32 ICFG00;
|
||||
/* 41 */ __RW __u32 ICFG01;
|
||||
/* 42 */ __RW __u32 ICFG02;
|
||||
/* 43 */ __RW __u32 ICFG03;
|
||||
/* 44 */ __RW __u32 ICFG04;
|
||||
/* 45 */ __RW __u32 ICFG05;
|
||||
/* 46 */ __RW __u32 ICFG06;
|
||||
/* 47 */ __RW __u32 ICFG07;
|
||||
/* 48 */ __RW __u32 ICFG08;
|
||||
/* 49 */ __RW __u32 ICFG09;
|
||||
/* 4a */ __RW __u32 ICFG10;
|
||||
/* 4b */ __RW __u32 ICFG11;
|
||||
/* 4c */ __RW __u32 ICFG12;
|
||||
/* 4d */ __RW __u32 ICFG13;
|
||||
/* 4e */ __RW __u32 ICFG14;
|
||||
/* 4f */ __RW __u32 ICFG15;
|
||||
|
||||
/* 50 */ __RW __u32 ICFG16;
|
||||
/* 51 */ __RW __u32 ICFG17;
|
||||
/* 52 */ __RW __u32 ICFG18;
|
||||
/* 53 */ __RW __u32 ICFG19;
|
||||
/* 54 */ __RW __u32 ICFG20;
|
||||
/* 55 */ __RW __u32 ICFG21;
|
||||
/* 56 */ __RW __u32 ICFG22;
|
||||
/* 57 */ __RW __u32 ICFG23;
|
||||
/* 58 */ __RW __u32 ICFG24;
|
||||
/* 59 */ __RW __u32 ICFG25;
|
||||
/* 5a */ __RW __u32 ICFG26;
|
||||
/* 5b */ __RW __u32 ICFG27;
|
||||
/* 5c */ __RW __u32 ICFG28;
|
||||
/* 5d */ __RW __u32 ICFG29;
|
||||
/* 5e */ __RW __u32 ICFG30;
|
||||
/* 5f */ __RW __u32 ICFG31;
|
||||
|
||||
/* 60 */ __RO __u32 IPND0;
|
||||
/* 61 */ __RO __u32 IPND1;
|
||||
/* 62 */ __RO __u32 IPND2;
|
||||
/* 63 */ __RO __u32 IPND3;
|
||||
/* 64 */ __RO __u32 IPND4;
|
||||
/* 65 */ __RO __u32 IPND5;
|
||||
/* 66 */ __RO __u32 IPND6;
|
||||
/* 67 */ __RO __u32 IPND7;
|
||||
/* 68 */ __WO __u32 ILAT_SET;
|
||||
/* 69 */ __WO __u32 ILAT_CLR;
|
||||
/* 6a */ __RW __u32 IPMASK;
|
||||
/* 6b */ __RW __u32 GIEMASK;
|
||||
/* 6c */ __RW __u32 IWKUP_NUM;
|
||||
/* */ __RO __u32 REV_70_6c[0x70 - 0x6c - 1];
|
||||
|
||||
/* 70 */ __RW __u32 ETM_CON;
|
||||
/* 71 */ __RO __u32 ETM_PC0;
|
||||
/* 72 */ __RO __u32 ETM_PC1;
|
||||
/* 73 */ __RO __u32 ETM_PC2;
|
||||
/* 74 */ __RO __u32 ETM_PC3;
|
||||
/* 75 */ __RW __u32 WP0_ADRH;
|
||||
/* 76 */ __RW __u32 WP0_ADRL;
|
||||
/* 77 */ __RW __u32 WP0_DATH;
|
||||
/* 78 */ __RW __u32 WP0_DATL;
|
||||
/* 79 */ __RW __u32 WP0_PC;
|
||||
|
||||
/* */ __RO __u32 REV_80_79[0x80 - 0x79 - 1];
|
||||
/* 80 */ __RW __u32 EMU_CON;
|
||||
/* 81 */ __RW __u32 EMU_MSG;
|
||||
/* 82 */ __RO __u32 EMU_SSP_H;
|
||||
/* 83 */ __RO __u32 EMU_SSP_L;
|
||||
/* 84 */ __RO __u32 EMU_USP_H;
|
||||
/* 85 */ __RO __u32 EMU_USP_L;
|
||||
} JL_TypeDef_p11_q32s;
|
||||
|
||||
#undef __RW
|
||||
#undef __RO
|
||||
#undef __WO
|
||||
|
||||
#undef __u8
|
||||
#undef __u16
|
||||
#undef __u32
|
||||
|
||||
#endif
|
||||
|
||||
//*********************************************************************************//
|
||||
// //
|
||||
// end of this module //
|
||||
// //
|
||||
//*********************************************************************************//
|
||||
38
include_lib/driver/cpu/br28/asm/power/p11_io_imap.h
Normal file
38
include_lib/driver/cpu/br28/asm/power/p11_io_imap.h
Normal file
@ -0,0 +1,38 @@
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// input IO define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_PB0_IN 1
|
||||
#define P11_PB1_IN 2
|
||||
#define P11_PB2_IN 3
|
||||
#define P11_PB3_IN 4
|
||||
#define P11_PB4_IN 5
|
||||
#define P11_PB5_IN 6
|
||||
#define P11_PB6_IN 7
|
||||
#define P11_PB7_IN 8
|
||||
#define P11_PB8_IN 9
|
||||
#define P11_PB9_IN 10
|
||||
#define P11_PB10_IN 11
|
||||
#define P11_PB11_IN 12
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// function input select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_FI_GP_ICH0;
|
||||
__RW __u8 P11_FI_GP_ICH1;
|
||||
__RW __u8 P11_FI_GP_ICH2;
|
||||
__RW __u8 P11_FI_UART0_RX;
|
||||
__RW __u8 P11_FI_SPI_DI;
|
||||
__RW __u8 P11_FI_IIC_SCL;
|
||||
__RW __u8 P11_FI_IIC_SDA;
|
||||
__RW __u8 P11_FI_DMIC_DAT;
|
||||
} P11_IMAP_TypeDef;
|
||||
|
||||
#define P11_IMAP_BASE (p11_sfr_base + map_adr(0x16, 0x00))
|
||||
#define P11_IMAP ((P11_IMAP_TypeDef *)P11_IMAP_BASE)
|
||||
40
include_lib/driver/cpu/br28/asm/power/p11_io_omap.h
Normal file
40
include_lib/driver/cpu/br28/asm/power/p11_io_omap.h
Normal file
@ -0,0 +1,40 @@
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// output function define
|
||||
//
|
||||
//===============================================================================//
|
||||
#define P11_FO_GP_OCH0 ((0 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH1 ((1 << 2)|BIT(1))
|
||||
#define P11_FO_GP_OCH2 ((2 << 2)|BIT(1))
|
||||
#define P11_FO_UART0_TX ((3 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_UART1_TX ((4 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_CLK ((5 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_SPI_DO ((6 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SCL ((7 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_IIC_SDA ((8 << 2)|BIT(1)|BIT(0))
|
||||
#define P11_FO_DMIC_CLK ((9 << 2)|BIT(1)|BIT(0))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// IO output select sfr
|
||||
//
|
||||
//===============================================================================//
|
||||
typedef struct {
|
||||
__RW __u8 P11_PB0_OUT;
|
||||
__RW __u8 P11_PB1_OUT;
|
||||
__RW __u8 P11_PB2_OUT;
|
||||
__RW __u8 P11_PB3_OUT;
|
||||
__RW __u8 P11_PB4_OUT;
|
||||
__RW __u8 P11_PB5_OUT;
|
||||
__RW __u8 P11_PB6_OUT;
|
||||
__RW __u8 P11_PB7_OUT;
|
||||
__RW __u8 P11_PB8_OUT;
|
||||
__RW __u8 P11_PB9_OUT;
|
||||
__RW __u8 P11_PB10_OUT;
|
||||
__RW __u8 P11_PB11_OUT;
|
||||
} P11_OMAP_TypeDef;
|
||||
|
||||
#define P11_OMAP_BASE (p11_sfr_base + map_adr(0x15, 0x00))
|
||||
#define P11_OMAP ((P11_OMAP_TypeDef *)P11_OMAP_BASE)
|
||||
244
include_lib/driver/cpu/br28/asm/power/p11_sfr.h
Normal file
244
include_lib/driver/cpu/br28/asm/power/p11_sfr.h
Normal file
@ -0,0 +1,244 @@
|
||||
#ifndef __P11__
|
||||
#define __P11__
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define p11_base 0x000000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0x00a000
|
||||
#else
|
||||
#define p11_base 0xf20000
|
||||
#define p11_ram_base p11_base
|
||||
#define p11_sfr_base 0xf2a000
|
||||
#endif
|
||||
|
||||
#define __RW volatile // read write
|
||||
#define __RO volatile const // only read
|
||||
#define __WO volatile // only write
|
||||
|
||||
#define __u8 unsigned int // u8 to u32 special for struct
|
||||
#define __u16 unsigned int // u16 to u32 special for struct
|
||||
#define __u32 unsigned int
|
||||
|
||||
#define __s8(x) char(x); char(reserved_1_##x); char(reserved_2_##x); char(reserved_3_##x)
|
||||
#define __s16(x) short(x); short(reserved_1_##x)
|
||||
#define __s32(x) int(x)
|
||||
|
||||
#define map_adr(grp, adr) ((64 * grp + adr) * 4) // grp(0x0-0xff), adr(0x0-0x3f)
|
||||
#define P11_ACCESS(x) (*(volatile u32 *)(p11_base + x))
|
||||
#define P11_RAM(x) (*(volatile u32 *)(p11_ram_base + x))
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// sfr address define
|
||||
//
|
||||
//===============================================================================//
|
||||
|
||||
//............. 0x0000 - 0x03ff............ for cpu
|
||||
|
||||
// #include ../core/csfr.h
|
||||
|
||||
//............. 0x0400 - 0x04ff............ for clock
|
||||
typedef struct {
|
||||
__RW __u32 PWR_CON;
|
||||
__RW __u32 RST_SRC;
|
||||
__RW __u32 WKUP_EN;
|
||||
__RW __u32 WKUP_SRC;
|
||||
__RW __u32 SYS_DIV;
|
||||
__RW __u32 CLK_CON0;
|
||||
__RW __u32 CLK_CON1;
|
||||
__RW __u32 CLK_CON2;
|
||||
__RW __u32 CLK_CON3;
|
||||
} P11_CLOCK_TypeDef;
|
||||
|
||||
#define P11_CLOCK_BASE (p11_sfr_base + map_adr(0x04, 0x00))
|
||||
#define P11_CLOCK ((P11_CLOCK_TypeDef *)P11_CLOCK_BASE)
|
||||
|
||||
//............. 0x0500 - 0x05ff............ for memory control
|
||||
typedef struct {
|
||||
__RW __u32 MPC0;
|
||||
__RW __u32 MPC1;
|
||||
__RW __u32 MSC;
|
||||
} P11_MEM_CTL_TypeDef;
|
||||
|
||||
#define P11_MEM_CTL_BASE (p11_sfr_base + map_adr(0x05, 0x00))
|
||||
#define P11_MEM_CTL ((P11_MEM_CTL_TypeDef *)P11_MEM_CTL_BASE)
|
||||
|
||||
//............. 0x0600 - 0x06ff............ for system
|
||||
typedef struct {
|
||||
__RW __u32 P2M_INT_IE;
|
||||
__RW __u32 P2M_INT_SET;
|
||||
__RW __u32 P2M_INT_CLR;
|
||||
__RO __u32 P2M_INT_PND;
|
||||
__RW __u32 P2M_CLK_CON0;
|
||||
__RW __u32 M2P_INT_IE;
|
||||
__RW __u32 M2P_INT_SET;
|
||||
__RW __u32 M2P_INT_CLR;
|
||||
__RO __u32 M2P_INT_PND;
|
||||
__RW __u32 P11_SYS_CON0;
|
||||
__RW __u32 P11_SYS_CON1;
|
||||
__RW __u32 MEM_PWR_CON;
|
||||
} P11_SYSTEM_TypeDef;
|
||||
|
||||
#define P11_SYSTEM_BASE (p11_sfr_base + map_adr(0x06, 0x00))
|
||||
#define P11_SYSTEM ((P11_SYSTEM_TypeDef *)P11_SYSTEM_BASE)
|
||||
|
||||
//............. 0x0800 - 0x08ff............ for watch dog
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 KEY;
|
||||
__RW __u32 DUMMY;
|
||||
} P11_WDT_TypeDef;
|
||||
|
||||
#define P11_WDT_BASE (p11_sfr_base + map_adr(0x08, 0x00))
|
||||
#define P11_WDT ((P11_WDT_TypeDef *)P11_WDT_BASE)
|
||||
|
||||
//............. 0x0900 - 0x0cff............ for lp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 RSC;
|
||||
__RO __u32 CNT;
|
||||
} P11_LPTMR_TypeDef;
|
||||
|
||||
#define P11_LPTMR0_BASE (p11_sfr_base + map_adr(0x09, 0x00))
|
||||
#define P11_LPTMR1_BASE (p11_sfr_base + map_adr(0x0a, 0x00))
|
||||
#define P11_LPTMR2_BASE (p11_sfr_base + map_adr(0x0b, 0x00))
|
||||
#define P11_LPTMR3_BASE (p11_sfr_base + map_adr(0x0c, 0x00))
|
||||
|
||||
#define P11_LPTMR0 ((P11_LPTMR_TypeDef *)P11_LPTMR0_BASE)
|
||||
#define P11_LPTMR1 ((P11_LPTMR_TypeDef *)P11_LPTMR1_BASE)
|
||||
#define P11_LPTMR2 ((P11_LPTMR_TypeDef *)P11_LPTMR2_BASE)
|
||||
#define P11_LPTMR3 ((P11_LPTMR_TypeDef *)P11_LPTMR3_BASE)
|
||||
|
||||
//............. 0x0d00 - 0x0dff............ for irflt
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
} P11_IRFLT_TypeDef;
|
||||
|
||||
#define P11_IRFLT_BASE (p11_sfr_base + map_adr(0x0d, 0x00))
|
||||
#define P11_IRFLT ((P11_IRFLT_TypeDef *)P11_IRFLT_BASE)
|
||||
|
||||
//............. 0x0e00 - 0x0eff............ for spi
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__WO __u32 BAUD;
|
||||
__RW __u32 BUF;
|
||||
//__WO __u32 ADR;
|
||||
//__WO __u32 CNT;
|
||||
} P11_SPI_TypeDef;
|
||||
|
||||
#define P11_SPI_BASE (p11_sfr_base + map_adr(0x0e, 0x00))
|
||||
#define P11_SPI ((P11_SPI_TypeDef *)P11_SPI_BASE)
|
||||
|
||||
//............. 0x0f00 - 0x10ff............ for uart
|
||||
typedef struct {
|
||||
__RW __u16 CON0;
|
||||
//__RW __u16 CON1;
|
||||
__WO __u16 BAUD;
|
||||
__RW __u8 BUF;
|
||||
__RW __u32 OTCNT;
|
||||
//__RW __u32 TXADR;
|
||||
//__WO __u16 TXCNT;
|
||||
//__RW __u32 RXSADR;
|
||||
//__RW __u32 RXEADR;
|
||||
//__RW __u32 RXCNT;
|
||||
//__RO __u16 HRXCNT;
|
||||
__RW __u16 CON2;
|
||||
} P11_UART_TypeDef;
|
||||
|
||||
#define P11_UART0_BASE (p11_sfr_base + map_adr(0x0f, 0x00))
|
||||
#define P11_UART1_BASE (p11_sfr_base + map_adr(0x10, 0x00))
|
||||
|
||||
#define P11_UART0 ((P11_UART_TypeDef *)P11_UART0_BASE)
|
||||
#define P11_UART1 ((P11_UART_TypeDef *)P11_UART1_BASE)
|
||||
|
||||
//............. 0x1100 - 0x11ff............ for iic
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 BAUD;
|
||||
__RW __u32 BUF;
|
||||
} P11_IIC_TypeDef;
|
||||
|
||||
#define P11_IIC_BASE (p11_sfr_base + map_adr(0x11, 0x00))
|
||||
#define P11_IIC ((P11_IIC_TypeDef *)P11_IIC_BASE)
|
||||
|
||||
//............. 0x1200 - 0x12ff............ for port
|
||||
typedef struct {
|
||||
__RW __u32 OCH_CON0 ;
|
||||
__RW __u32 ICH_CON0 ;
|
||||
__RW __u32 P33_PORT ;
|
||||
__RW __u32 PB_SEL ;
|
||||
__RW __u32 PB_PU ;
|
||||
__RW __u32 PB_PD ;
|
||||
__RW __u32 PB_DIR ;
|
||||
__RW __u32 PB_DIE ;
|
||||
__RW __u32 PB_DIEH ;
|
||||
__RW __u32 PB_OUT ;
|
||||
__RO __u32 PB_IN ;
|
||||
} P11_PORT_TypeDef;
|
||||
|
||||
#define P11_PORT_BASE (p11_sfr_base + map_adr(0x12, 0x00))
|
||||
#define P11_PORT ((P11_PORT_TypeDef *)P11_PORT_BASE)
|
||||
|
||||
//............. 0x1300 - 0x13ff............ for lp ctmu
|
||||
typedef struct {
|
||||
__RW __u32 CON0;
|
||||
__RW __u32 CON1;
|
||||
__RW __u32 CON2;
|
||||
__RW __u32 CON3;
|
||||
__RW __u32 ANA0;
|
||||
__RW __u32 ANA1;
|
||||
__RW __u32 RES;
|
||||
} P11_LPCTM_TypeDef;
|
||||
|
||||
#define P11_LPCTM_BASE (p11_sfr_base + map_adr(0x13, 0x00))
|
||||
#define P11_LPCTM ((P11_LPCTM_TypeDef *)P11_LPCTM_BASE)
|
||||
|
||||
//............. 0x1400 - 0x14ff............ for lpvad
|
||||
typedef struct {
|
||||
__RW __u32 VAD_CON;
|
||||
__RW __u32 VAD_ACON0;
|
||||
__RW __u32 VAD_ACON1;
|
||||
__RW __u32 AVAD_CON;
|
||||
__RW __u32 AVAD_DATA;
|
||||
__RW __u32 DVAD_CON0;
|
||||
__RW __u32 DVAD_CON1;
|
||||
__RW __u32 DMA_BADR;
|
||||
__RW __u32 DMA_LEN;
|
||||
__RW __u32 DMA_HPTR;
|
||||
__RW __u32 DMA_SPTR;
|
||||
__RW __u32 DMA_SPN;
|
||||
__RW __u32 DMA_SHN;
|
||||
} P11_LPVAD_TypeDef;
|
||||
|
||||
#define P11_LPVAD_BASE (p11_sfr_base + map_adr(0x14, 0x00))
|
||||
#define P11_LPVAD ((P11_LPVAD_TypeDef *)P11_LPVAD_BASE)
|
||||
|
||||
//............. 0x1500 - 0x16ff............ for crossbar
|
||||
#include "p11_io_omap.h"
|
||||
#include "p11_io_imap.h"
|
||||
|
||||
//............. 0x1700 - 0x18ff............ for gp timer
|
||||
typedef struct {
|
||||
__RW __u32 CON;
|
||||
__RW __u32 CNT;
|
||||
__RW __u32 PRD;
|
||||
__RW __u32 PWM;
|
||||
} P11_GPTMR_TypeDef;
|
||||
|
||||
#define P11_GPTMR0_BASE (p11_sfr_base + map_adr(0x17, 0x00))
|
||||
#define P11_GPTMR1_BASE (p11_sfr_base + map_adr(0x18, 0x00))
|
||||
|
||||
#define P11_GPTMR0 ((P11_GPTMR_TypeDef *)P11_GPTMR0_BASE)
|
||||
#define P11_GPTMR1 ((P11_GPTMR_TypeDef *)P11_GPTMR1_BASE)
|
||||
|
||||
#endif
|
||||
89
include_lib/driver/cpu/br28/asm/power/p2m_msg.h
Normal file
89
include_lib/driver/cpu/br28/asm/power/p2m_msg.h
Normal file
@ -0,0 +1,89 @@
|
||||
#ifndef __P2M_MSG_H__
|
||||
#define __P2M_MSG_H__
|
||||
|
||||
//p2m用户消息实例
|
||||
enum {
|
||||
P2M_MSG_ACK = BIT(0),
|
||||
P2M_MSG_TEST = BIT(1),
|
||||
P2M_MSG_COMMOM = BIT(2),
|
||||
P2M_MSG_CTMU = BIT(3),
|
||||
P2M_MSG_SENSOR = BIT(4),
|
||||
P2M_MSG_VAD = BIT(5),
|
||||
|
||||
};
|
||||
|
||||
//测试
|
||||
struct p2m_msg_test {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//测试
|
||||
struct p2m_msg_ack {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//公共消息
|
||||
struct p2m_msg_common {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//触摸消息
|
||||
struct p2m_msg_ctmu {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//vad
|
||||
struct p2m_msg_vad {
|
||||
u8 dat;
|
||||
};
|
||||
|
||||
//p2m用户消息格式
|
||||
struct p2m_msg_head {
|
||||
u16 type :
|
||||
MSG_TYPE_BIT_LEN;
|
||||
u16 len :
|
||||
MSG_PARAM_BIT_LEN;
|
||||
u8 index :
|
||||
MSG_INDEX_BIT;
|
||||
u8 ack :
|
||||
MSG_ACK_BIT;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct p2m_msg {
|
||||
struct p2m_msg_head head;
|
||||
union {
|
||||
struct p2m_msg_ack ack;
|
||||
struct p2m_msg_test test;
|
||||
struct p2m_msg_common com;
|
||||
struct p2m_msg_ctmu ctmu;
|
||||
struct p2m_msg_vad vad;
|
||||
} u;
|
||||
} __attribute__((packed));
|
||||
|
||||
//p2m用户消息对应处理
|
||||
struct p2m_msg_handler {
|
||||
u8 type;
|
||||
void (*handler)(struct p2m_msg *);
|
||||
};
|
||||
|
||||
#define REGISTER_P2M_MSG_HANDLER(_type, fn, pri) \
|
||||
const struct p2m_msg_handler _##fn sec(.p2m_msg_handler)= { \
|
||||
.type = _type, \
|
||||
.handler = fn, \
|
||||
}
|
||||
|
||||
extern struct p2m_msg_handler p2m_msg_handler_begin[];
|
||||
extern struct p2m_msg_handler p2m_msg_handler_end[];
|
||||
|
||||
#define list_for_each_p2m_msg_handler(p) \
|
||||
for (p = p2m_msg_handler_begin; p < p2m_msg_handler_end; p++)
|
||||
|
||||
|
||||
|
||||
int p2m_get_msg(int len, struct p2m_msg *msg);
|
||||
|
||||
int p2m_post_msg(int len, struct p2m_msg *msg);
|
||||
|
||||
int p2m_post_sync_msg(int len, struct p2m_msg *msg, u8 abandon, int timeout);
|
||||
|
||||
#endif
|
||||
26
include_lib/driver/cpu/br28/asm/power/p33.h
Normal file
26
include_lib/driver/cpu/br28/asm/power/p33.h
Normal file
@ -0,0 +1,26 @@
|
||||
/*********************************************************************************************
|
||||
* Filename : p33.h
|
||||
|
||||
* Description :
|
||||
|
||||
* Author : Bingquan
|
||||
|
||||
* Email : caibingquan@zh-jieli.com
|
||||
|
||||
* Last modifiled : 2019-12-09 10:42
|
||||
|
||||
* Copyright:(c)JIELI 2011-2019 @ , All Rights Reserved.
|
||||
*********************************************************************************************/
|
||||
|
||||
#ifndef __P33_H__
|
||||
#define __P33_H__
|
||||
|
||||
#include "p33_sfr.h"
|
||||
|
||||
#include "p33_app.h"
|
||||
|
||||
#include "p33_io_app.h"
|
||||
|
||||
#include "rtc_app.h"
|
||||
|
||||
#endif
|
||||
796
include_lib/driver/cpu/br28/asm/power/p33_app.h
Normal file
796
include_lib/driver/cpu/br28/asm/power/p33_app.h
Normal file
@ -0,0 +1,796 @@
|
||||
#ifndef __P33_APP_H__
|
||||
#define __P33_APP_H__
|
||||
|
||||
//ROM
|
||||
u8 p33_buf(u8 buf);
|
||||
|
||||
// void p33_xor_1byte(u16 addr, u8 data0);
|
||||
#define p33_xor_1byte(addr, data0) (*((volatile u8 *)&addr + 0x300*4) = data0)
|
||||
// #define p33_xor_1byte(addr, data0) addr ^= (data0)
|
||||
|
||||
// void p33_and_1byte(u16 addr, u8 data0);
|
||||
#define p33_and_1byte(addr, data0) (*((volatile u8 *)&addr + 0x100*4) = (data0))
|
||||
//#define p33_and_1byte(addr, data0) addr &= (data0)
|
||||
|
||||
// void p33_or_1byte(u16 addr, u8 data0);
|
||||
#define p33_or_1byte(addr, data0) (*((volatile u8 *)&addr + 0x200*4) = data0)
|
||||
// #define p33_or_1byte(addr, data0) addr |= (data0)
|
||||
|
||||
// void p33_tx_1byte(u16 addr, u8 data0);
|
||||
#define p33_tx_1byte(addr, data0) addr = data0
|
||||
|
||||
// u8 p33_rx_1byte(u16 addr);
|
||||
#define p33_rx_1byte(addr) addr
|
||||
|
||||
#define P33_CON_SET(sfr, start, len, data) (sfr = (sfr & ~((~(0xff << (len))) << (start))) | \
|
||||
(((data) & (~(0xff << (len)))) << (start)))
|
||||
|
||||
#define P33_CON_GET(sfr) sfr
|
||||
|
||||
#define P33_ANA_CHECK(reg) (((reg & reg##_MASK) == reg##_RV) ? 1:0)
|
||||
|
||||
|
||||
#if 1
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
p33_or_1byte(reg, (data)); \
|
||||
} else { \
|
||||
p33_and_1byte(reg, ~(data)); \
|
||||
} \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define p33_fast_access(reg, data, en) \
|
||||
{ \
|
||||
if (en) { \
|
||||
reg |= (data); \
|
||||
} else { \
|
||||
reg &= ~(data); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
//
|
||||
// for p33_analog.doc
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_ANA_CON0*****************************/
|
||||
#define VDD13TO12_SYS_EN(en) P33_CON_SET(P3_ANA_CON0, 0, 1, en)
|
||||
|
||||
#define VDD13TO12_RVD_EN(en) P33_CON_SET(P3_ANA_CON0, 1, 1, en)
|
||||
|
||||
#define LDO13_EN(en) P33_CON_SET(P3_ANA_CON0, 2, 1, en)
|
||||
|
||||
#define DCDC13_EN(en) P33_CON_SET(P3_ANA_CON0, 3, 1, en)
|
||||
|
||||
#define GET_DCDC13_EN() ((P33_CON_GET(P3_ANA_CON0) & BIT(3)) ? 1:0)
|
||||
|
||||
#define PVDD_EN(en) P33_CON_SET(P3_ANA_CON0, 4, 1, en)
|
||||
|
||||
#define MVIO_VBAT_EN(en) P33_CON_SET(P3_ANA_CON0, 5, 1, en)
|
||||
|
||||
#define MVIO_VPWR_EN(en) P33_CON_SET(P3_ANA_CON0, 6, 1, en)
|
||||
|
||||
#define MBG_EN(en) P33_CON_SET(P3_ANA_CON0, 7, 1, en)
|
||||
|
||||
#define P3_ANA_CON0_MASK 0b11110011
|
||||
#define P3_ANA_CON0_RV 0b11110011
|
||||
|
||||
/************************P3_ANA_KEEP*****************************/
|
||||
#define CLOSE_ANA_KEEP() P33_CON_SET(P3_ANA_KEEP, 0, 8, 0)
|
||||
|
||||
#define P3_ANA_KEEP_MASK 0b11111111
|
||||
#define P3_ANA_KEEP_RV 0b00000000
|
||||
|
||||
/************************P3_ANA_KEEP1****************************/
|
||||
#define VIO2_EN_KEEP(en) P33_CON_SET(P3_ANA_KEEP1, 0, 1, en)
|
||||
|
||||
#define P3_ANA_KEEP1_MASK 0b00000001
|
||||
#define P3_ANA_KEEP1_RV 0b00000000
|
||||
|
||||
/**************************P3_ANA_CON1*********************************/
|
||||
#define RVDD_BYPASS_EN(en) P33_CON_SET(P3_ANA_CON1, 0, 1, en)
|
||||
|
||||
#define WVDD_SHORT_RVDD(en) P33_CON_SET(P3_ANA_CON1, 1, 1, en)
|
||||
|
||||
#define WVDD_SHORT_SVDD(en) P33_CON_SET(P3_ANA_CON1, 2, 1, en)
|
||||
|
||||
#define WLDO06_EN(en) P33_CON_SET(P3_ANA_CON1, 3, 1, en)
|
||||
|
||||
#define WLDO06_OE(en) P33_CON_SET(P3_ANA_CON1, 4, 1, en)
|
||||
|
||||
#define EVD_EN(en) P33_CON_SET(P3_ANA_CON1, 5, 1, en)
|
||||
|
||||
#define EVD_SHORT_PB8(en) P33_CON_SET(P3_ANA_CON1, 6, 1, en)
|
||||
|
||||
#define PVD_SHORT_PB8(en) P33_CON_SET(P3_ANA_CON1, 7, 1, en)
|
||||
|
||||
#define P3_ANA_CON1_MASK 0b10011111
|
||||
#define P3_ANA_CON1_RV 0b00000100
|
||||
|
||||
/************************P3_ANA_CON2*****************************/
|
||||
#define VCM_DET_EN(en) P33_CON_SET(P3_ANA_CON2, 3, 1, en)
|
||||
|
||||
#define MVIO_VBAT_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 4, 1, en)
|
||||
|
||||
#define MVIO_VPWR_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 5, 1, en)
|
||||
|
||||
#define DCVD_ILMT_EN(en) P33_CON_SET(P3_ANA_CON2, 6, 1, en)
|
||||
|
||||
#define CURRENT_LIMIT_DISABLE() (P3_ANA_CON2 &= ~(BIT(4) | BIT(5) | BIT(6)))
|
||||
|
||||
#define P3_ANA_CON2_MASK 0b01110000
|
||||
#define P3_ANA_CON2_RV 0b01110000
|
||||
|
||||
/************************P3_ANA_CON3*****************************/
|
||||
#define MVBG_SEL(en) P33_CON_SET(P3_ANA_CON3, 0, 4, en)
|
||||
|
||||
#define MVBG_GET() (P33_CON_GET(P3_ANA_CON3) & 0x0f)
|
||||
|
||||
#define WVBG_SEL(en) P33_CON_SET(P3_ANA_CON3, 4, 4, en)
|
||||
|
||||
#define P3_ANA_CON3_MASK 0b00000000
|
||||
#define P3_ANA_CON3_RV 0b00000000
|
||||
|
||||
/************************P3_ANA_CON4*****************************/
|
||||
#define PMU_DET_EN(en) P33_CON_SET(P3_ANA_CON4, 0, 1, en)
|
||||
|
||||
#define ADC_CHANNEL_SEL(ch) P33_CON_SET(P3_ANA_CON4, 1, 4, ch)
|
||||
|
||||
#define PMU_DET_BG_BUF_EN(en) P33_CON_SET(P3_ANA_CON4, 5, 1, en)
|
||||
|
||||
#define VBG_TEST_EN(en) P33_CON_SET(P3_ANA_CON4, 6, 1, en)
|
||||
|
||||
#define VBG_TEST_SEL(en) P33_CON_SET(P3_ANA_CON4, 7, 1, en)
|
||||
|
||||
#define P3_ANA_CON4_MASK 0b11100001
|
||||
#define P3_ANA_CON4_RV 0b11100001
|
||||
|
||||
/************************P3_ANA_CON5*****************************/
|
||||
//vddiom_lev
|
||||
enum {
|
||||
VDDIOM_VOL_20V = 0,
|
||||
VDDIOM_VOL_22V,
|
||||
VDDIOM_VOL_24V,
|
||||
VDDIOM_VOL_26V,
|
||||
VDDIOM_VOL_28V,
|
||||
VDDIOM_VOL_30V, //default
|
||||
VDDIOM_VOL_32V,
|
||||
VDDIOM_VOL_34V,
|
||||
};
|
||||
|
||||
#define VDDIOM_VOL_SEL(lev) P33_CON_SET(P3_ANA_CON5, 0, 3, lev)
|
||||
|
||||
#define GET_VDDIOM_VOL() (P33_CON_GET(P3_ANA_CON5) & 0x7)
|
||||
|
||||
//vddiow_lev
|
||||
enum {
|
||||
VDDIOW_VOL_20V = 0,
|
||||
VDDIOW_VOL_22V,
|
||||
VDDIOW_VOL_24V,
|
||||
VDDIOW_VOL_26V,
|
||||
VDDIOW_VOL_28V,
|
||||
VDDIOW_VOL_30V,
|
||||
VDDIOW_VOL_32V,
|
||||
VDDIOW_VOL_34V,
|
||||
};
|
||||
|
||||
#define VDDIOW_VOL_SEL(lev) P33_CON_SET(P3_ANA_CON5, 3, 3, lev)
|
||||
|
||||
#define GET_VDDIOW_VOL() (P33_CON_GET(P3_ANA_CON5)>>3 & 0x7)
|
||||
|
||||
#define VDDIO_HD_SEL(cur) P33_CON_SET(P3_ANA_CON5, 6, 2, cur)
|
||||
|
||||
#define P3_ANA_CON5_MASK 0b11000000
|
||||
#define P3_ANA_CON5_RV 0b01000000
|
||||
|
||||
/************************P3_ANA_CON6*****************************/
|
||||
#define VDC13_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON6, 0, 4, sel)
|
||||
//Macro for VDC13_VOL_SEL
|
||||
enum {
|
||||
VDC13_VOL_SEL_100V = 0,
|
||||
VDC13_VOL_SEL_105V,
|
||||
VDC13_VOL_SEL_1075V,
|
||||
VDC13_VOL_SEL_110V,
|
||||
VDC13_VOL_SEL_1125V,
|
||||
VDC13_VOL_SEL_115V,
|
||||
VDC13_VOL_SEL_1175V,
|
||||
VDC13_VOL_SEL_120V,
|
||||
VDC13_VOL_SEL_1225V,
|
||||
VDC13_VOL_SEL_125V,
|
||||
VDC13_VOL_SEL_1275V,
|
||||
VDC13_VOL_SEL_130V,
|
||||
VDC13_VOL_SEL_1325V,
|
||||
VDC13_VOL_SEL_135V,
|
||||
VDC13_VOL_SEL_1375V,
|
||||
VDC13_VOL_SEL_140V,
|
||||
};
|
||||
|
||||
#define VD13_DEFAULT_VOL VDC13_VOL_SEL_125V
|
||||
|
||||
#define GET_VD13_VOL_SEL() (P33_CON_GET(P3_ANA_CON6) & 0xf)
|
||||
|
||||
#define VD13_HD_SEL(sel) P33_CON_SET(P3_ANA_CON6, 4, 2, sel)
|
||||
|
||||
#define VD13_CAP_EN(en) P33_CON_SET(P3_ANA_CON6, 6, 1, en)
|
||||
|
||||
#define VD13_DESHOT_EN(en) P33_CON_SET(P3_ANA_CON6, 7, 1, en)
|
||||
|
||||
#define P3_ANA_CON6_MASK 0b11111111
|
||||
#define P3_ANA_CON6_RV 0b11011010
|
||||
|
||||
/************************P3_ANA_CON7*****************************/
|
||||
#define BTDCDC_PFM_MODE(en) P33_CON_SET(P3_ANA_CON7, 0, 1, en)
|
||||
|
||||
#define GET_BTDCDC_PFM_MODE() (P33_CON_GET(P3_ANA_CON7) & BIT(0) ? 1 : 0)
|
||||
|
||||
#define BTDCDC_RAMP_SHORT(en) P33_CON_SET(P3_ANA_CON7, 1, 1, en)
|
||||
|
||||
#define BTDCDC_V17_TEST_OE(en) P33_CON_SET(P3_ANA_CON7, 2, 1, en);
|
||||
|
||||
#define BTDCDC_DUTY_SEL(sel) P33_CON_SET(P3_ANA_CON7, 3, 2, sel)
|
||||
|
||||
#define BTDCDC_OSC_SEL(sel) P33_CON_SET(P3_ANA_CON7, 5, 3, sel)
|
||||
//Macro for BTDCDC_OSC_SEL
|
||||
enum {
|
||||
BTDCDC_OSC_SEL0520KHz = 0,
|
||||
BTDCDC_OSC_SEL0762KHz,
|
||||
BTDCDC_OSC_SEL0997KHz,
|
||||
BTDCDC_OSC_SEL1220KHz,
|
||||
BTDCDC_OSC_SEL1640KHz,
|
||||
BTDCDC_OSC_SEL1840KHz,
|
||||
BTDCDC_OSC_SEL2040KHz,
|
||||
BTDCDC_OSC_SEL2220MHz,
|
||||
};
|
||||
|
||||
#define P3_ANA_CON7_MASK 0b11111111
|
||||
#define P3_ANA_CON7_RV 0b01001001
|
||||
|
||||
/************************P3_ANA_CON8*****************************/
|
||||
#define BTDCDC_V21_RES_S(sel) P33_CON_SET(P3_ANA_CON8, 0, 2, sel)
|
||||
|
||||
#define BTDCDC_DT_S(sel) P33_CON_SET(P3_ANA_CON8, 2, 2, sel)
|
||||
|
||||
#define BTDCDC_ISENSE_HD(sel) P33_CON_SET(P3_ANA_CON8, 4, 2, sel)
|
||||
|
||||
#define BTDCDC_COMP_HD(sel) P33_CON_SET(P3_ANA_CON8, 6, 2, sel)
|
||||
|
||||
#define P3_ANA_CON8_MASK 0b11111111
|
||||
#define P3_ANA_CON8_RV 0b01100110
|
||||
|
||||
/************************P3_ANA_CON9*****************************/
|
||||
#define BTDCDC_NMOS_S(sel) P33_CON_SET(P3_ANA_CON9, 1, 3, sel)
|
||||
|
||||
#define BTDCDC_PMOS_S(sel) P33_CON_SET(P3_ANA_CON9, 5, 3, sel)
|
||||
|
||||
#define P3_ANA_CON9_MASK 0b11101110
|
||||
#define P3_ANA_CON9_RV 0b01101110
|
||||
|
||||
/************************P3_ANA_CON10*****************************/
|
||||
|
||||
#define BTDCDC_OSC_TEST_OE(en) P33_CON_SET(P3_ANA_CON10, 7, 1, en)
|
||||
|
||||
#define BTDCDC_HD_BIAS_SEL(sel) P33_CON_SET(P3_ANA_CON10, 5, 2, sel)
|
||||
|
||||
#define BTDCDC_CLK_SEL(sel) P33_CON_SET(P3_ANA_CON10, 4, 1, sel)
|
||||
|
||||
#define GET_BTDCDC_CLK_SEL() (P33_CON_GET(P3_ANA_CON10) & BIT(4) ? 1 : 0)
|
||||
|
||||
#define BTDCDC_ZCD_RES(sel) P33_CON_SET(P3_ANA_CON10, 2, 2, sel)
|
||||
|
||||
#define BTDCDC_ZCD_EN(en) P33_CON_SET(P3_ANA_CON10, 0, 1, en)
|
||||
|
||||
#define P3_ANA_CON10_MASK 0b11111101
|
||||
#define P3_ANA_CON10_RV 0b00110001
|
||||
|
||||
/************************P3_ANA_CON11*****************************/
|
||||
#define SYSVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON11, 0, 4, sel)
|
||||
//Macro for SYSVDD_VOL_SEL
|
||||
enum {
|
||||
SYSVDD_VOL_SEL_081V = 0,
|
||||
SYSVDD_VOL_SEL_084V,
|
||||
SYSVDD_VOL_SEL_087V,
|
||||
SYSVDD_VOL_SEL_090V,
|
||||
SYSVDD_VOL_SEL_093V,
|
||||
SYSVDD_VOL_SEL_096V,
|
||||
SYSVDD_VOL_SEL_099V,
|
||||
SYSVDD_VOL_SEL_102V,
|
||||
SYSVDD_VOL_SEL_105V,
|
||||
SYSVDD_VOL_SEL_108V,
|
||||
SYSVDD_VOL_SEL_111V,
|
||||
SYSVDD_VOL_SEL_114V,
|
||||
SYSVDD_VOL_SEL_117V,
|
||||
SYSVDD_VOL_SEL_120V,
|
||||
SYSVDD_VOL_SEL_123V,
|
||||
SYSVDD_VOL_SEL_126V,
|
||||
};
|
||||
|
||||
#define SYSVDD_DEFAULT_VOL SYSVDD_VOL_SEL_105V
|
||||
|
||||
#define GET_SYSVDD_VOL_SEL() (P33_CON_GET(P3_ANA_CON11) & 0xf)
|
||||
|
||||
#define SYSVDD_VOL_HD_SEL(sel) P33_CON_SET(P3_ANA_CON11, 4, 2, sel)
|
||||
|
||||
#define SYSVDD_CAP_EN(en) P33_CON_SET(P3_ANA_CON11, 6, 1, en)
|
||||
|
||||
#define P3_ANA_CON11_MASK 0b01110000
|
||||
#define P3_ANA_CON11_RV 0b00010000
|
||||
|
||||
/************************P3_ANA_CON12*****************************/
|
||||
#define RVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON12, 0, 4, sel)
|
||||
//Macro for SYSVDD_VOL_SEL
|
||||
enum {
|
||||
RVDD_VOL_SEL_081V = 0,
|
||||
RVDD_VOL_SEL_084V,
|
||||
RVDD_VOL_SEL_087V,
|
||||
RVDD_VOL_SEL_090V,
|
||||
RVDD_VOL_SEL_093V,
|
||||
RVDD_VOL_SEL_096V,
|
||||
RVDD_VOL_SEL_099V,
|
||||
RVDD_VOL_SEL_102V,
|
||||
RVDD_VOL_SEL_105V,
|
||||
RVDD_VOL_SEL_108V,
|
||||
RVDD_VOL_SEL_111V,
|
||||
RVDD_VOL_SEL_114V,
|
||||
RVDD_VOL_SEL_117V,
|
||||
RVDD_VOL_SEL_120V,
|
||||
RVDD_VOL_SEL_123V,
|
||||
RVDD_VOL_SEL_126V,
|
||||
};
|
||||
|
||||
#define RVDD_DEFAULT_VOL RVDD_VOL_SEL_105V
|
||||
|
||||
#define GET_RVDD_VOL_SEL() (P33_CON_GET(P3_ANA_CON12) & 0xf)
|
||||
|
||||
#define RVDD_VOL_HD_SEL(en) P33_CON_SET(P3_ANA_CON12, 4, 2, en)
|
||||
|
||||
#define RVDD_CAP_EN(en) P33_CON_SET(P3_ANA_CON12, 6, 1, en)
|
||||
|
||||
#define P3_ANA_CON12_MASK 0b01110000
|
||||
#define P3_ANA_CON12_RV 0b00010000
|
||||
|
||||
/************************P3_ANA_CON13*****************************/
|
||||
#define WVDD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON13, 0, 4, sel)
|
||||
//Macro for WVDD_VOL_SEL
|
||||
enum {
|
||||
WVDD_VOL_SEL_050V = 0,
|
||||
WVDD_VOL_SEL_055V,
|
||||
WVDD_VOL_SEL_060V,
|
||||
WVDD_VOL_SEL_065V,
|
||||
WVDD_VOL_SEL_070V,
|
||||
WVDD_VOL_SEL_075V,
|
||||
WVDD_VOL_SEL_080V,
|
||||
WVDD_VOL_SEL_085V,
|
||||
WVDD_VOL_SEL_090V,
|
||||
WVDD_VOL_SEL_095V,
|
||||
WVDD_VOL_SEL_100V,
|
||||
WVDD_VOL_SEL_105V,
|
||||
WVDD_VOL_SEL_110V,
|
||||
WVDD_VOL_SEL_115V,
|
||||
WVDD_VOL_SEL_120V,
|
||||
WVDD_VOL_SEL_125V,
|
||||
};
|
||||
|
||||
#define WVDD_VOL_MIN 500
|
||||
#define VWDD_VOL_MAX 1250
|
||||
#define WVDD_VOL_TRIM 800//mv
|
||||
#define WVDD_VOL_STEP 50
|
||||
#define WVDD_LEVEL_MAX 0xf
|
||||
#define WVDD_LEVEL_ERR 0xff
|
||||
|
||||
#define WVDD_VOL_TRIM_LED 850
|
||||
|
||||
#define WVDD_LEVEL_DEFAULT ((WVDD_VOL_TRIM-WVDD_VOL_MIN)/WVDD_VOL_STEP + 2)
|
||||
|
||||
#define WVDD_LOAD_EN(en) P33_CON_SET(P3_ANA_CON13, 4, 1, en)
|
||||
|
||||
#define WVDDIO_FBRES_AUTO(en) P33_CON_SET(P3_ANA_CON13, 6, 1, en)
|
||||
|
||||
#define WVDDIO_FBRES_SEL_W(en) P33_CON_SET(P3_ANA_CON13, 7, 1, en)
|
||||
|
||||
#define P3_ANA_CON13_MASK 0b11110000
|
||||
#define P3_ANA_CON13_RV 0b10000000
|
||||
|
||||
/************************P3_ANA_CON14*****************************/
|
||||
#define RVD2PVD_SHORT_EN(en) P33_CON_SET(P3_ANA_CON14, 4, 1, en)
|
||||
|
||||
#define GET_RVD2PVD_SHORT_EN() (P33_CON_GET(P3_ANA_CON14) & BIT(4) ? 1:0)
|
||||
|
||||
#define PVD_DEUDSHT_EN(en) P33_CON_SET(P3_ANA_CON14, 3, 1, en)
|
||||
|
||||
#define GET_PVD_DEUDST_EN() ((P33_CON_GET(P3_ANA_CON14) & BIT(3)) ? 1:0)
|
||||
|
||||
#define PVD_HD_SEL(sel) P33_CON_SET(P3_ANA_CON14, 0, 3, sel)
|
||||
|
||||
#define GET_PVD_HD_SEL() (P33_CON_GET(P3_ANA_CON14) & 0x7)
|
||||
|
||||
#define P3_ANA_CON14_MASK 0b00011111
|
||||
#define P3_ANA_CON14_RV 0b00000100
|
||||
|
||||
/************************P3_ANA_CON15*****************************/
|
||||
#define EVD_VOL_SEL(sel) P33_CON_SET(P3_ANA_CON15, 0, 2, sel)
|
||||
enum {
|
||||
EVD_VOL_SEL_100V = 0,
|
||||
EVD_VOL_SEL_105V,
|
||||
EVD_VOL_SEL_110V,
|
||||
EVD_VOL_SEL_115V,
|
||||
};
|
||||
|
||||
#define EVD_HD_SEL(sel) P33_CON_SET(P3_ANA_CON15, 2, 2, sel)
|
||||
|
||||
#define EVD_CAP_EN(en) P33_CON_SET(P3_ANA_CON15, 4, 1, en)
|
||||
|
||||
#define P3_ANA_CON15_MASK 0b00001100
|
||||
#define P3_ANA_CON15_RV 0b00000100
|
||||
|
||||
/************************P3_PVDD0_AUTO*****************************/
|
||||
#define PVDD_LEVEL_LOW(sel) P33_CON_SET(P3_PVDD0_AUTO, 0, 4, sel)
|
||||
|
||||
#define GET_PVDD_LEVEL_LOW() (P33_CON_GET(P3_PVDD0_AUTO) & 0xf)
|
||||
|
||||
#define PVDD_LEVEL_AUTO(en) P33_CON_SET(P3_PVDD0_AUTO, 4, 1, en)
|
||||
|
||||
#define GET_PVDD_LEVEL_AUTO() ((P33_CON_GET(P3_PVDD0_AUTO) & BIT(4)) ? 1:0)
|
||||
|
||||
#define PVDD_AUTO_PRD(sel) P33_CON_SET(P3_PVDD0_AUTO, 5, 3, sel)
|
||||
|
||||
#define GET_PVDD_AUTO_PRD() ((P33_CON_GET(P3_PVDD0_AUTO) & (0x7<<5)) >> 5)
|
||||
|
||||
enum {
|
||||
PVDD_VOL_SEL_050V = 0,
|
||||
PVDD_VOL_SEL_055V,
|
||||
PVDD_VOL_SEL_060V,
|
||||
PVDD_VOL_SEL_065V,
|
||||
PVDD_VOL_SEL_070V,
|
||||
PVDD_VOL_SEL_075V,
|
||||
PVDD_VOL_SEL_080V,
|
||||
PVDD_VOL_SEL_085V,
|
||||
PVDD_VOL_SEL_090V,
|
||||
PVDD_VOL_SEL_095V,
|
||||
PVDD_VOL_SEL_100V,
|
||||
PVDD_VOL_SEL_105V,
|
||||
PVDD_VOL_SEL_110V,
|
||||
PVDD_VOL_SEL_115V,
|
||||
PVDD_VOL_SEL_120V,
|
||||
PVDD_VOL_SEL_125V,
|
||||
};
|
||||
|
||||
#define PVDD_VOL_MIN 500
|
||||
#define PVDD_VOL_MAX 1250
|
||||
#define PVDD_VOL_STEP 50
|
||||
#define PVDD_LEVEL_MAX 0xf
|
||||
#define PVDD_LEVEL_ERR 0xff
|
||||
#define PVDD_LEVEL_DEFAULT 0xc
|
||||
|
||||
#define PVDD_LEVEL_REF PVDD_VOL_SEL_115V
|
||||
#define PVDD_VOL_REF 1150//mV
|
||||
|
||||
#define PVDD_VOL_CLOCK_SET 1200
|
||||
|
||||
#define PVDD_VOL_HIGH_NOW 1100
|
||||
|
||||
#ifdef CONFIG_WATCH_CASE_ENABLE
|
||||
#define PVDD_LEVEL_SLEEP PVDD_VOL_SEL_090V
|
||||
#define PVDD_VOL_SLEEP 900
|
||||
|
||||
#else
|
||||
#define PVDD_LEVEL_SLEEP PVDD_VOL_SEL_095V
|
||||
#define PVDD_VOL_SLEEP 950
|
||||
|
||||
#endif
|
||||
|
||||
#define P3_PVDD0_AUTO_MASK 0b11110000
|
||||
#define P3_PVDD0_AUTO_RV 0b01110000
|
||||
|
||||
/************************P3_PVDD1_AUTO*****************************/
|
||||
#define PVDD_LEVEL_HIGH_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 8, (sel<<4)|sel);
|
||||
|
||||
#define PVDD_LEVEL_HIGH(sel) P33_CON_SET(P3_PVDD1_AUTO, 4, 4, sel)
|
||||
|
||||
#define GET_PVDD_LEVEL_HIGH() ((P33_CON_GET(P3_PVDD1_AUTO) & 0xf0)>>4)
|
||||
|
||||
#define PVDD_LEVEL_NOW(sel) P33_CON_SET(P3_PVDD1_AUTO, 0, 4, sel)
|
||||
|
||||
#define GET_PVDD_LEVEL_NOW() (P33_CON_GET(P3_PVDD1_AUTO) & 0x0f)
|
||||
|
||||
#define P3_PVDD1_AUTO_MASK 0b00000000
|
||||
#define P3_PVDD1_AUTO_RV 0b00000000
|
||||
|
||||
/************************P3_PVDD2_AUTO*****************************/
|
||||
#define GET_PVDD_DRV_AUTO() (P33_CON_GET(P3_PVDD2_AUTO) & BIT(0))
|
||||
|
||||
#define P3_PVDD2_AUTO_MASK 0b00000001
|
||||
#define P3_PVDD2_AUTO_RV 0b00000001
|
||||
|
||||
/************************P3_CHG_CON0*****************************/
|
||||
#define CHARGE_EN(en) P33_CON_SET(P3_CHG_CON0, 0, 1, en)
|
||||
|
||||
#define CHGGO_EN(en) P33_CON_SET(P3_CHG_CON0, 1, 1, en)
|
||||
|
||||
#define IS_CHARGE_EN() ((P33_CON_GET(P3_CHG_CON0) & BIT(0)) ? 1: 0 )
|
||||
|
||||
#define CHG_HV_MODE(mode) P33_CON_SET(P3_CHG_CON0, 2, 1, mode)
|
||||
|
||||
#define CHG_TRICKLE_EN(en) P33_CON_SET(P3_CHG_CON0, 3, 1, en)
|
||||
|
||||
#define CHG_CCLOOP_EN(en) P33_CON_SET(P3_CHG_CON0, 4, 1, en)
|
||||
|
||||
#define CHG_VILOOP_EN(en) P33_CON_SET(P3_CHG_CON0, 5, 1, en)
|
||||
|
||||
#define CHG_VINLOOP_SLT(sel) P33_CON_SET(P3_CHG_CON0, 6, 1, sel)
|
||||
|
||||
#define CHG_SEL_CHG_FULL 0
|
||||
#define CHG_SEL_VBAT_DET 1
|
||||
#define CHG_SSEL(sel) P33_CON_SET(P3_CHG_CON0, 7, 1, sel)
|
||||
|
||||
#define P3_CHG_CON0_MASK 0
|
||||
#define P3_CHG_CON0_RV 0
|
||||
|
||||
/************************P3_CHG_CON1*****************************/
|
||||
#define CHARGE_FULL_V_SEL(a) P33_CON_SET(P3_CHG_CON1, 0, 4, a)
|
||||
|
||||
#define CHARGE_mA_SEL(a) P33_CON_SET(P3_CHG_CON1, 4, 4, a)
|
||||
|
||||
#define P3_CHG_CON1_MASK 0
|
||||
#define P3_CHG_CON1_RV 0
|
||||
|
||||
/************************P3_CHG_CON2*****************************/
|
||||
#define CHARGE_FULL_mA_SEL(a) P33_CON_SET(P3_CHG_CON2, 4, 3, a)
|
||||
|
||||
enum {
|
||||
CHARGE_DET_VOL_365V,
|
||||
CHARGE_DET_VOL_375V,
|
||||
CHARGE_DET_VOL_385V,
|
||||
CHARGE_DET_VOL_395V,
|
||||
};
|
||||
#define CHARGE_DET_VOL(a) P33_CON_SET(P3_CHG_CON2, 1, 2, a)
|
||||
|
||||
#define CHARGE_DET_EN(en) P33_CON_SET(P3_CHG_CON2, 0, 1, en)
|
||||
|
||||
#define P3_CHG_CON2_MASK 0
|
||||
#define P3_CHG_CON2_RV 0
|
||||
|
||||
/************************P3_L5V_CON0*****************************/
|
||||
#define L5V_LOAD_EN(a) P33_CON_SET(P3_L5V_CON0, 0, 1, a)
|
||||
|
||||
#define L5V_IO_MODE(a) P33_CON_SET(P3_L5V_CON0, 2, 1, a)
|
||||
|
||||
#define IS_L5V_LOAD_EN() ((P33_CON_GET(P3_L5V_CON0) & BIT(0)) ? 1: 0 )
|
||||
|
||||
#define GET_L5V_RES_DET_S_SEL() (P33_CON_GET(P3_L5V_CON1) & 0x03)
|
||||
|
||||
#define P3_L5V_CON0_MASK 0
|
||||
#define P3_L5V_CON0_RV 0
|
||||
|
||||
/************************P3_L5V_CON1*****************************/
|
||||
#define L5V_RES_DET_S_SEL(a) P33_CON_SET(P3_L5V_CON1, 0, 2, a)
|
||||
|
||||
#define P3_L5V_CON1_MASK 0
|
||||
#define P3_L5V_CON1_RV 0
|
||||
|
||||
/************************P3_VLVD_CON*****************************/
|
||||
#define P33_VLVD_EN(en) P33_CON_SET(P3_VLVD_CON, 0, 1, en)
|
||||
|
||||
#define GET_VLVD_EN() (P33_CON_GET(P3_VLVD_CON) & BIT(0))
|
||||
|
||||
#define P33_VLVD_PS(en) P33_CON_SET(P3_VLVD_CON, 1, 1, en)
|
||||
|
||||
#define P33_VLVD_OE(en) P33_CON_SET(P3_VLVD_CON, 2, 1, en)
|
||||
|
||||
#define GET_VLVD_OE() ((P33_CON_GET(P3_VLVD_CON) & BIT(2)) ? 1:0)
|
||||
|
||||
#define VLVD_SEL(lev) P33_CON_SET(P3_VLVD_CON, 3, 3, lev)
|
||||
|
||||
#define GET_VLVD_SEL() ((P33_CON_GET(P3_VLVD_CON) & (0x7<<3))>>3)
|
||||
//Macro for VLVD_SEL
|
||||
enum {
|
||||
VLVD_SEL_18V = 0,
|
||||
VLVD_SEL_19V,
|
||||
VLVD_SEL_20V,
|
||||
VLVD_SEL_21V,
|
||||
VLVD_SEL_22V,
|
||||
VLVD_SEL_23V,
|
||||
VLVD_SEL_24V,
|
||||
VLVD_SEL_25V,
|
||||
};
|
||||
|
||||
#define VLVD_PND_CLR() P33_CON_SET(P3_VLVD_CON, 6, 1, 1)
|
||||
|
||||
#define VLVD_PND() ((P33_CON_GET(P3_VLVD_CON) & BIT(7)) ? 1 : 0)
|
||||
|
||||
#define P3_VLVD_CON_MASK 0
|
||||
#define P3_VLVD_CON_RV 0
|
||||
|
||||
/************************P3_VLVD_FLT*****************************/
|
||||
#define VLVD_FLT(sel) P33_CON_SET(P3_VLVD_FLT, 0, 2, sel);
|
||||
|
||||
#define P3_VLVD_FLT_MASK 0b00000011
|
||||
#define P3_VLVD_FLT_RV 0b00000010
|
||||
|
||||
/************************P3_RST_CON0*****************************/
|
||||
#define DPOR_MASK(en) P33_CON_SET(P3_RST_CON0, 0, 1, en)
|
||||
|
||||
#define VLVD_RST_EN(en) P33_CON_SET(P3_RST_CON0, 2, 1, en)
|
||||
|
||||
#define VLVD_WKUP_EN(en) P33_CON_SET(P3_RST_CON0, 3, 1, en)
|
||||
|
||||
#define PPOR_MASK(en) P33_CON_SET(P3_RST_CON0, 4, 1, en)
|
||||
|
||||
#define P11_TO_P33_RST_MASK(en) P33_CON_SET(P3_RST_CON0, 5, 1, en)
|
||||
|
||||
#define DVDDOK_OE(en) P33_CON_SET(P3_RST_CON0, 6, 1, en)
|
||||
|
||||
#define PVDDOK_OE(en) P33_CON_SET(P3_RST_CON0, 7, 1, en)
|
||||
|
||||
#define P3_RST_CON0_MASK 0b11111101
|
||||
#define P3_RST_CON0_RV 0b00000100
|
||||
|
||||
/************************P3_LRC_CON0*****************************/
|
||||
#define RC32K_EN(en) P33_CON_SET(P3_LRC_CON0, 0, 1, en)
|
||||
|
||||
#define RC32K_RN_TRIM(en) P33_CON_SET(P3_LRC_CON0, 1, 1, en)
|
||||
|
||||
#define RC32K_RPPS_SEL(sel) P33_CON_SET(P3_LRC_CON0, 4, 2, sel)
|
||||
|
||||
#define P3_LRC_CON0_MASK 0b00110011
|
||||
#define P3_LRC_CON0_RV 0b00100001
|
||||
|
||||
/************************P3_LRC_CON1*****************************/
|
||||
#define RC32K_PNPS_SEL(sel) P33_CON_SET(P3_LRC_CON1, 0, 2, sel)
|
||||
|
||||
#define RC32K_CAP_SEL(sel) P33_CON_SET(P3_LRC_CON1, 4, 3, sel)
|
||||
|
||||
#define CLOSE_LRC() P33_CON_SET(P3_LRC_CON0, 0, 8, 0);\
|
||||
P33_CON_SET(P3_LRC_CON1, 0, 8, 0)
|
||||
|
||||
#define P3_LRC_CON1_MASK 0b01110011
|
||||
#define P3_LRC_CON1_RV 0b01000001
|
||||
|
||||
/************************P3_CLK_CON0*****************************/
|
||||
#define RC_250K_EN(a) P33_CON_SET(P3_CLK_CON0, 0, 1, a)
|
||||
|
||||
#define P3_CLK_CON0_MASK 0b00000001
|
||||
#define P3_CLK_CON0_RV 0b00000000
|
||||
|
||||
/************************P3_VLD_KEEP*****************************/
|
||||
#define RTC_WKUP_KEEP(a) P33_CON_SET(P3_VLD_KEEP, 1, 1, a)
|
||||
|
||||
#define P33_WKUP_P11_EN(a) P33_CON_SET(P3_VLD_KEEP, 2, 1, a)
|
||||
|
||||
#define P3_VLD_KEEP_MASK 0b00000110
|
||||
#define P3_VLD_KEEP_RV 0b00000110
|
||||
|
||||
/************************P3_PMU_CON0*****************************/
|
||||
#define GET_P33_SYS_POWER_FLAG() ((P33_CON_GET(P3_PMU_CON0) & BIT(7)) ? 1 : 0)
|
||||
|
||||
#define P33_SYS_POWERUP_CLEAR() P33_CON_SET(P3_PMU_CON0, 6, 1, 1);
|
||||
|
||||
#define P3_PMU_CON0_MASK 0b00000000
|
||||
#define P3_PMU_CON0_RV 0b00000000
|
||||
|
||||
/************************P3_PMU_DBG_CON*****************************/
|
||||
#define P3_PMU_DBG_CON_MASK 0b00000000
|
||||
#define P3_PMU_DBG_CON_RV 0b00000000
|
||||
|
||||
/************************P3_IOV2_CON*****************************/
|
||||
#define GET_IOV2_VOL() ((P33_CON_GET(P3_IOV2_CON) & (0x7<<3)) >> 3)
|
||||
|
||||
#define GET_IOV2_IFULL() ((P33_CON_GET(P3_IOV2_CON) & BIT(2)) ? 1:0)
|
||||
|
||||
#define GET_IOV2_BYPASS() ((P33_CON_GET(P3_IOV2_CON) & BIT(1)) ? 1:0)
|
||||
|
||||
#define GET_IOV2_EN() ((P33_CON_GET(P3_IOV2_CON) & BIT(0)) ? 1:0)
|
||||
|
||||
#define P3_IOV2_CON_MASK 0
|
||||
#define P3_IOV2_CON_RV 0
|
||||
|
||||
/************************P3_RVD_CON*****************************/
|
||||
#define RVDD_CMP_EN(en) P33_CON_SET(P3_RVD_CON, 4, 1, en)
|
||||
|
||||
#define PVDD_DCDC_LEV_SEL(sel) P33_CON_SET(P3_RVD_CON, 0, 4, sel)
|
||||
|
||||
#define GET_PVDD_DCDC_LEV_SEL() (P33_CON_GET(P3_RVD_CON) & 0xf)
|
||||
|
||||
#define P3_RVD_CON_MASK 0b00000000
|
||||
#define P3_RVD_CON_RV 0b00000000
|
||||
|
||||
/************************P3_CHG_WKUP*****************************/
|
||||
#define CHARGE_LEVEL_DETECT_EN(a) P33_CON_SET(P3_CHG_WKUP, 0, 1, a)
|
||||
|
||||
#define CHARGE_EDGE_DETECT_EN(a) P33_CON_SET(P3_CHG_WKUP, 1, 1, a)
|
||||
|
||||
#define CHARGE_WKUP_SOURCE_SEL(a) P33_CON_SET(P3_CHG_WKUP, 2, 2, a)
|
||||
|
||||
#define CHARGE_WKUP_EN(a) P33_CON_SET(P3_CHG_WKUP, 4, 1, a)
|
||||
|
||||
#define CHARGE_WKUP_EDGE_SEL(a) P33_CON_SET(P3_CHG_WKUP, 5, 1, a)
|
||||
|
||||
#define CHARGE_WKUP_PND_CLR() P33_CON_SET(P3_CHG_WKUP, 6, 1, 1)
|
||||
|
||||
/************************P3_AWKUP_LEVEL*****************************/
|
||||
#define CHARGE_FULL_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(2)) ? 1: 0)
|
||||
|
||||
#define LVCMP_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(1)) ? 1: 0)
|
||||
|
||||
#define LDO5V_DET_FILTER_GET() ((P33_CON_GET(P3_AWKUP_LEVEL) & BIT(0)) ? 1: 0)
|
||||
|
||||
/************************P3_ANA_READ*****************************/
|
||||
#define CHARGE_FULL_FLAG_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(0)) ? 1: 0 )
|
||||
|
||||
#define LVCMP_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(1)) ? 1: 0 )
|
||||
|
||||
#define LDO5V_DET_GET() ((P33_CON_GET(P3_ANA_READ) & BIT(2)) ? 1: 0 )
|
||||
//
|
||||
//
|
||||
// for ANA_control.doc
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_LS_XX*****************************/
|
||||
#define PVDD_ANA_LAT_EN(en) \
|
||||
if(en){ \
|
||||
P3_LS_P11 = 0x01; \
|
||||
P3_LS_P11 = 0x03; \
|
||||
}else{ \
|
||||
P3_LS_P11 = 0x0; \
|
||||
}
|
||||
|
||||
#define DVDD_ANA_LAT_EN(en) \
|
||||
if(en){ \
|
||||
P3_LS_IO_DLY = 0x1; \
|
||||
P3_LS_IO_ROM = 0x1; \
|
||||
P3_LS_ADC = 0x1; \
|
||||
P3_LS_AUDIO = 0x1; \
|
||||
P3_LS_RF = 0x1; \
|
||||
P3_LS_PLL = 0x1; \
|
||||
P3_LS_IO_DLY = 0x3; \
|
||||
P3_LS_IO_ROM = 0x3; \
|
||||
P3_LS_ADC = 0x3; \
|
||||
P3_LS_AUDIO = 0x3; \
|
||||
P3_LS_RF = 0x3; \
|
||||
P3_LS_PLL = 0x3; \
|
||||
}else{ \
|
||||
P3_LS_IO_DLY = 0x0; \
|
||||
P3_LS_IO_ROM = 0x0; \
|
||||
P3_LS_ADC = 0x0; \
|
||||
P3_LS_AUDIO = 0x0; \
|
||||
P3_LS_RF = 0x0; \
|
||||
P3_LS_PLL = 0x0;\
|
||||
}
|
||||
|
||||
#define DVDD_ANA_ROM_LAT_EN(en) \
|
||||
if(en){ \
|
||||
P3_LS_IO_ROM = 1; \
|
||||
P3_LS_PLL = 1; \
|
||||
P3_LS_RF = 1; \
|
||||
P3_LS_IO_ROM = 3; \
|
||||
P3_LS_PLL = 3; \
|
||||
P3_LS_RF = 3; \
|
||||
}else{ \
|
||||
P3_LS_IO_ROM = 0; \
|
||||
P3_LS_PLL = 0; \
|
||||
P3_LS_RF = 0; \
|
||||
}
|
||||
//
|
||||
//
|
||||
// for reset_source.doc
|
||||
//
|
||||
//
|
||||
//
|
||||
/************************P3_PR_PWR*****************************/
|
||||
#define P3_SOFT_RESET() P33_CON_SET(P3_PR_PWR, 4, 2, 3)
|
||||
|
||||
/************************P3_IVS_CLR*****************************/
|
||||
#define P33_SF_KICK_START() P33_CON_SET(P3_IVS_CLR, 0, 8, 0b10101000)
|
||||
|
||||
/************************P3_RST_SRC*****************************/
|
||||
#define GET_P33_SYS_RST_SRC() P33_CON_GET(P3_RST_SRC)
|
||||
|
||||
|
||||
#endif
|
||||
140
include_lib/driver/cpu/br28/asm/power/p33_io_app.h
Normal file
140
include_lib/driver/cpu/br28/asm/power/p33_io_app.h
Normal file
@ -0,0 +1,140 @@
|
||||
#ifndef __P33_IO_APP_H__
|
||||
#define __P33_IO_APP_H__
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/*
|
||||
*-------------------P3_WKUP_DLY
|
||||
*/
|
||||
|
||||
#define P3_WKUP_DLY_SET(val) P33_CON_SET(P3_WKUP_DLY, 0, 3, val)
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/*
|
||||
*-------------------P3_PCNT_CON
|
||||
*/
|
||||
|
||||
#define PCNT_PND_CLR() P33_CON_SET(P3_PCNT_CON, 6, 1, 1)
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/*
|
||||
*-------------------P3_PCNT_SET
|
||||
*/
|
||||
|
||||
#define SET_EXCEPTION_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xb)
|
||||
#define SET_ASSERT_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xc)
|
||||
#define SET_XOSC_RESUME_ERR_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xd)
|
||||
#define SET_LPTMR_TIMEOUT_FLAG() P33_CON_SET(P3_PCNT_SET0, 0, 7, 0xe)
|
||||
#define SET_LVD_FLAG(en) P33_CON_SET(P3_PCNT_SET0, 7, 1, en)
|
||||
|
||||
#define GET_EXCEPTION_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xb) ? 1 : 0)
|
||||
#define GET_ASSERT_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xc) ? 1 : 0)
|
||||
#define GET_XOSC_RESUME_ERR_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xd) ? 1 : 0)
|
||||
#define GET_LPTMR_TIMEOUT_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x7f) == 0xe) ? 1 : 0)
|
||||
#define GET_LVD_FLAG() (((P33_CON_GET(P3_PCNT_SET0)&0x80) == 0x80) ? 1 : 0)
|
||||
|
||||
#define SOFT_RESET_FLAG_CLEAR() (P33_CON_SET(P3_PCNT_SET0, 0, 8, 0))
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/*
|
||||
*-------------------P3_WKUP_XX
|
||||
*/
|
||||
|
||||
#define MAX_WAKEUP_PORT 12 //最大同时支持数字io输入个数
|
||||
|
||||
#define MAX_WAKEUP_ANA_PORT 3 //最大同时支持模拟io输入个数
|
||||
|
||||
typedef enum {
|
||||
RISING_EDGE = 0,
|
||||
FALLING_EDGE,
|
||||
BOTH_EDGE,
|
||||
} POWER_WKUP_EDGE;
|
||||
|
||||
typedef enum {
|
||||
PORT_FLT_NULL = 0,
|
||||
PORT_FLT_256us,
|
||||
PORT_FLT_512us,
|
||||
PORT_FLT_1ms,
|
||||
PORT_FLT_2ms,
|
||||
PORT_FLT_4ms,
|
||||
PORT_FLT_8ms,
|
||||
PORT_FLT_16ms,
|
||||
} POWER_WKUP_FLT;
|
||||
|
||||
//en
|
||||
#define P33_SET_WKUP_EN(data) P33_CON_SET(P3_WKUP_EN0, 0, 8, data & 0xff); \
|
||||
P33_CON_SET(P3_WKUP_EN1, 0, 8, (data >> 8) & 0xff)
|
||||
|
||||
#define P33_OR_WKUP_EN(data) p33_fast_access(P3_WKUP_EN0, data & 0xff, 1); \
|
||||
p33_fast_access(P3_WKUP_EN1, (data >> 8) & 0xff, 1)
|
||||
|
||||
#define P33_AND_WKUP_EN(data) p33_fast_access(P3_WKUP_EN0, data & 0xff, 0); \
|
||||
p33_fast_access(P3_WKUP_EN1, (data >> 8) & 0xff, 0)
|
||||
|
||||
//edge
|
||||
#define P33_SET_WKUP_EDGE(data) P33_CON_SET(P3_WKUP_EDGE0, 0, 8, data & 0xff); \
|
||||
P33_CON_SET(P3_WKUP_EDGE1, 0, 8, (data >> 8) & 0xff)
|
||||
|
||||
#define P33_OR_WKUP_EDGE(data) p33_fast_access(P3_WKUP_EDGE0, data & 0xff, 1); \
|
||||
p33_fast_access(P3_WKUP_EDGE1, (data >> 8) & 0xff, 1)
|
||||
|
||||
#define P33_AND_WKUP_EDGE(data) p33_fast_access(P3_WKUP_EDGE0, data & 0xff, 0); \
|
||||
p33_fast_access(P3_WKUP_EDGE1, (data >> 8) & 0xff, 0)
|
||||
|
||||
//cpnd
|
||||
#define P33_SET_WKUP_CPND(data) p33_fast_access(P3_WKUP_CPND0, data & 0xff, 1); \
|
||||
p33_fast_access(P3_WKUP_CPND1, (data >> 8) & 0xff, 1)
|
||||
|
||||
//pnd
|
||||
#define P33_GET_WKUP_PND() (P33_CON_GET(P3_WKUP_PND0) | (P33_CON_GET(P3_WKUP_PND1)<<8))
|
||||
|
||||
//akwup_en
|
||||
#define P33_SET_AWKUP_EN(data) P33_CON_SET(P3_AWKUP_EN, 0, 8, data & 0xff)
|
||||
|
||||
#define P33_OR_AWKUP_EN(data) p33_fast_access(P3_AWKUP_EN, data & 0xff, 1)
|
||||
|
||||
//awkup_p_pnd
|
||||
#define P33_GET_AWKUP_P_PND() (P33_CON_GET(P3_AWKUP_P_PND))
|
||||
|
||||
//awkup_n_pnd
|
||||
#define P33_GET_AWKUP_N_PND() (P33_CON_GET(P3_AWKUP_N_PND))
|
||||
|
||||
//awkup_p_cpnd
|
||||
#define P33_SET_AWKUP_P_CPND(data) p33_fast_access(P3_AWKUP_P_CPND, data & 0xff, 1)
|
||||
|
||||
//awkup_n_cpnd
|
||||
#define P33_SET_AWKUP_N_CPND(data) p33_fast_access(P3_AWKUP_N_CPND, data & 0xff, 1)
|
||||
|
||||
//awkup_p_ie
|
||||
#define P33_SET_AWKUP_P_IE(data) P33_CON_SET(P3_AWKUP_P_IE, 0, 8, data & 0xff)
|
||||
#define P33_OR_AWKUP_P_IE(data) p33_fast_access(P3_AWKUP_P_IE, data & 0xff, 1)
|
||||
#define P33_AND_AWKUP_P_IE(data) p33_fast_access(P3_AWKUP_P_IE, data & 0xff, 0)
|
||||
|
||||
//awkup_n_ie
|
||||
#define P33_SET_AWAKEUP_N_IE(data) P33_CON_SET(P3_AWKUP_N_IE, 0, 8, data & 0xff)
|
||||
#define P33_OR_AWKUP_N_IE(data) p33_fast_access(P3_AWKUP_N_IE, data & 0xff, 1)
|
||||
#define P33_AND_AWKUP_N_IE(data) p33_fast_access(P3_AWKUP_N_IE, data & 0xff, 0)
|
||||
|
||||
#define CLEAN_GPIO_WAKEUP_PENDING() P33_SET_AWKUP_P_CPND(0xff); \
|
||||
P33_SET_AWKUP_N_CPND(0xff); \
|
||||
P33_SET_WKUP_CPND(0xffff);
|
||||
|
||||
#define CLEAN_P33_WKUP_PENDING() P33_SET_AWKUP_P_CPND(0xff); \
|
||||
P33_SET_AWKUP_N_CPND(0xff); \
|
||||
P33_SET_WKUP_CPND(0xffff); \
|
||||
VLVD_PND_CLR(); \
|
||||
PCNT_PND_CLR()
|
||||
|
||||
enum {
|
||||
P3_WKUP_SRC_PCNT_OVF = 0,
|
||||
P3_WKUP_SRC_PORT_EDGE,
|
||||
P3_WKUP_SRC_ANA_EDGE,
|
||||
P3_WKUP_SRC_VDDIO_LVD = 4,
|
||||
};
|
||||
|
||||
#define P33_GET_WKUP_SRC() P33_CON_GET(P3_WKUP_SRC)
|
||||
|
||||
#endif
|
||||
249
include_lib/driver/cpu/br28/asm/power/p33_sfr.h
Normal file
249
include_lib/driver/cpu/br28/asm/power/p33_sfr.h
Normal file
@ -0,0 +1,249 @@
|
||||
#ifndef __BR28_P33__
|
||||
#define __BR28_P33__
|
||||
////////////////////////////////
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xc000 + x*4))
|
||||
#else
|
||||
#define P33_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xc000 + x*4))
|
||||
#endif
|
||||
|
||||
#ifdef PMU_SYSTEM
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xd000 + x*4))
|
||||
#else
|
||||
#define RTC_ACCESS(x) (*(volatile u32 *)(0xf20000 + 0xd000 + x*4))
|
||||
#endif
|
||||
|
||||
//===========
|
||||
//===============================================================================//
|
||||
//
|
||||
//
|
||||
//
|
||||
//===============================================================================//
|
||||
//............. 0x0000 - 0x000f............
|
||||
#define P3_IOV2_CON P33_ACCESS(0x00)
|
||||
|
||||
//............. 0x0010 - 0x001f............ for analog others
|
||||
#define P3_OSL_CON P33_ACCESS(0x10)
|
||||
#define P3_VLVD_CON P33_ACCESS(0x11)
|
||||
#define P3_RST_SRC P33_ACCESS(0x12)
|
||||
#define P3_LRC_CON0 P33_ACCESS(0x13)
|
||||
#define P3_LRC_CON1 P33_ACCESS(0x14)
|
||||
#define P3_RST_CON0 P33_ACCESS(0x15)
|
||||
#define P3_ANA_KEEP P33_ACCESS(0x16)
|
||||
#define P3_VLD_KEEP P33_ACCESS(0x17)
|
||||
#define P3_CLK_CON0 P33_ACCESS(0x18)
|
||||
#define P3_ANA_READ P33_ACCESS(0x19)
|
||||
#define P3_CHG_CON0 P33_ACCESS(0x1a)
|
||||
#define P3_CHG_CON1 P33_ACCESS(0x1b)
|
||||
#define P3_CHG_CON2 P33_ACCESS(0x1c)
|
||||
#define P3_CHG_CON3 P33_ACCESS(0x1d)
|
||||
|
||||
//............. 0x0020 - 0x002f............ for PWM LED
|
||||
//#define P3_PWM_CON0 P33_ACCESS(0x20)
|
||||
//#define P3_PWM_CON1 P33_ACCESS(0x21)
|
||||
//#define P3_PWM_CON2 P33_ACCESS(0x22)
|
||||
//#define P3_PWM_CON3 P33_ACCESS(0x23)
|
||||
//#define P3_PWM_BRI_PRDL P33_ACCESS(0x24)
|
||||
//#define P3_PWM_BRI_PRDH P33_ACCESS(0x25)
|
||||
//#define P3_PWM_BRI_DUTY0L P33_ACCESS(0x26)
|
||||
//#define P3_PWM_BRI_DUTY0H P33_ACCESS(0x27)
|
||||
//#define P3_PWM_BRI_DUTY1L P33_ACCESS(0x28)
|
||||
//#define P3_PWM_BRI_DUTY1H P33_ACCESS(0x29)
|
||||
//#define P3_PWM_PRD_DIVL P33_ACCESS(0x2a)
|
||||
//#define P3_PWM_DUTY0 P33_ACCESS(0x2b)
|
||||
//#define P3_PWM_DUTY1 P33_ACCESS(0x2c)
|
||||
//#define P3_PWM_DUTY2 P33_ACCESS(0x2d)
|
||||
//#define P3_PWM_DUTY3 P33_ACCESS(0x2e)
|
||||
//#define P3_PWM_CNT_RD P33_ACCESS(0x2f)
|
||||
|
||||
//............. 0x0030 - 0x003f............ for PMU manager
|
||||
#define P3_PMU_CON0 P33_ACCESS(0x30)
|
||||
|
||||
#define P3_SFLAG0 P33_ACCESS(0x38)
|
||||
#define P3_SFLAG1 P33_ACCESS(0x39)
|
||||
#define P3_SFLAG2 P33_ACCESS(0x3a)
|
||||
#define P3_SFLAG3 P33_ACCESS(0x3b)
|
||||
//#define P3_SFLAG4 P33_ACCESS(0x3c)
|
||||
//#define P3_SFLAG5 P33_ACCESS(0x3d)
|
||||
//#define P3_SFLAG6 P33_ACCESS(0x3e)
|
||||
//#define P3_SFLAG7 P33_ACCESS(0x3f)
|
||||
|
||||
//............. 0x0040 - 0x004f............ for
|
||||
#define P3_IVS_RD P33_ACCESS(0x40)
|
||||
#define P3_IVS_SET P33_ACCESS(0x41)
|
||||
#define P3_IVS_CLR P33_ACCESS(0x42)
|
||||
#define P3_PVDD0_AUTO P33_ACCESS(0x43)
|
||||
#define P3_PVDD1_AUTO P33_ACCESS(0x44)
|
||||
#define P3_WKUP_DLY P33_ACCESS(0x45)
|
||||
#define P3_VLVD_FLT P33_ACCESS(0x46)
|
||||
#define P3_PINR_CON1 P33_ACCESS(0x47)
|
||||
#define P3_PINR_CON P33_ACCESS(0x48)
|
||||
#define P3_PCNT_CON P33_ACCESS(0x49)
|
||||
#define P3_PCNT_SET0 P33_ACCESS(0x4a)
|
||||
#define P3_PCNT_SET1 P33_ACCESS(0x4b)
|
||||
#define P3_PCNT_DAT0 P33_ACCESS(0x4c)
|
||||
#define P3_PCNT_DAT1 P33_ACCESS(0x4d)
|
||||
#define P3_PVDD2_AUTO P33_ACCESS(0x4e)
|
||||
|
||||
//............. 0x0050 - 0x005f............ for port wake up
|
||||
#define P3_WKUP_EN0 P33_ACCESS(0x50)
|
||||
#define P3_WKUP_EN1 P33_ACCESS(0x51)
|
||||
#define P3_WKUP_EDGE0 P33_ACCESS(0x52)
|
||||
#define P3_WKUP_EDGE1 P33_ACCESS(0x53)
|
||||
#define P3_WKUP_LEVEL0 P33_ACCESS(0x54)
|
||||
#define P3_WKUP_LEVEL1 P33_ACCESS(0x55)
|
||||
#define P3_WKUP_PND0 P33_ACCESS(0x56)
|
||||
#define P3_WKUP_PND1 P33_ACCESS(0x57)
|
||||
#define P3_WKUP_CPND0 P33_ACCESS(0x58)
|
||||
#define P3_WKUP_CPND1 P33_ACCESS(0x59)
|
||||
|
||||
//............. 0x0060 - 0x006f............ for
|
||||
#define P3_AWKUP_EN P33_ACCESS(0x60)
|
||||
#define P3_AWKUP_P_IE P33_ACCESS(0x61)
|
||||
#define P3_AWKUP_N_IE P33_ACCESS(0x62)
|
||||
#define P3_AWKUP_LEVEL P33_ACCESS(0x63)
|
||||
#define P3_AWKUP_INSEL P33_ACCESS(0x64)
|
||||
#define P3_AWKUP_P_PND P33_ACCESS(0x65)
|
||||
#define P3_AWKUP_N_PND P33_ACCESS(0x66)
|
||||
#define P3_AWKUP_P_CPND P33_ACCESS(0x67)
|
||||
#define P3_AWKUP_N_CPND P33_ACCESS(0x68)
|
||||
|
||||
//............. 0x0070 - 0x007f............ for power gate
|
||||
//#define P3_PGDR_CON0 P33_ACCESS(0x70)
|
||||
//#define P3_PGDR_CON1 P33_ACCESS(0x71)
|
||||
#define P3_PGSD_CON P33_ACCESS(0x72)
|
||||
//#define P3_PGFS_CON P33_ACCESS(0x73)
|
||||
|
||||
//............. 0x0080 - 0x008f............ for
|
||||
#define P3_AWKUP_FLT0 P33_ACCESS(0x80)
|
||||
#define P3_AWKUP_FLT1 P33_ACCESS(0x81)
|
||||
#define P3_AWKUP_FLT2 P33_ACCESS(0x82)
|
||||
|
||||
#define P3_APORT_SEL0 P33_ACCESS(0x88)
|
||||
#define P3_APORT_SEL1 P33_ACCESS(0x89)
|
||||
#define P3_APORT_SEL2 P33_ACCESS(0x8a)
|
||||
|
||||
//............. 0x0090 - 0x009f............ for analog control
|
||||
#define P3_ANA_CON0 P33_ACCESS(0x90)
|
||||
#define P3_ANA_CON1 P33_ACCESS(0x91)
|
||||
#define P3_ANA_CON2 P33_ACCESS(0x92)
|
||||
#define P3_ANA_CON3 P33_ACCESS(0x93)
|
||||
#define P3_ANA_CON4 P33_ACCESS(0x94)
|
||||
#define P3_ANA_CON5 P33_ACCESS(0x95)
|
||||
#define P3_ANA_CON6 P33_ACCESS(0x96)
|
||||
#define P3_ANA_CON7 P33_ACCESS(0x97)
|
||||
#define P3_ANA_CON8 P33_ACCESS(0x98)
|
||||
#define P3_ANA_CON9 P33_ACCESS(0x99)
|
||||
#define P3_ANA_CON10 P33_ACCESS(0x9a)
|
||||
#define P3_ANA_CON11 P33_ACCESS(0x9b)
|
||||
#define P3_ANA_CON12 P33_ACCESS(0x9c)
|
||||
#define P3_ANA_CON13 P33_ACCESS(0x9d)
|
||||
#define P3_ANA_CON14 P33_ACCESS(0x9e)
|
||||
#define P3_ANA_CON15 P33_ACCESS(0x9f)
|
||||
|
||||
//............. 0x00a0 - 0x00af............
|
||||
#define P3_PR_PWR P33_ACCESS(0xa0)
|
||||
#define P3_L5V_CON0 P33_ACCESS(0xa1)
|
||||
#define P3_L5V_CON1 P33_ACCESS(0xa2)
|
||||
|
||||
#define P3_LS_P11 P33_ACCESS(0xa4)
|
||||
|
||||
#define P3_RVD_CON P33_ACCESS(0xa7)
|
||||
#define P3_WKUP_SRC P33_ACCESS(0xa8)
|
||||
|
||||
#define P3_PMU_DBG_CON P33_ACCESS(0xaa)
|
||||
#define P3_ANA_KEEP1 P33_ACCESS(0xab)
|
||||
|
||||
//............. 0x00b0 - 0x00bf............ for EFUSE
|
||||
#define P3_EFUSE_CON0 P33_ACCESS(0xb0)
|
||||
#define P3_EFUSE_CON1 P33_ACCESS(0xb1)
|
||||
#define P3_EFUSE_RDAT P33_ACCESS(0xb2)
|
||||
|
||||
#define P3_FUNC_EN P33_ACCESS(0xb8)
|
||||
|
||||
//............. 0x00c0 - 0x00cf............ for port input select
|
||||
#define P3_PORT_SEL0 P33_ACCESS(0xc0)
|
||||
#define P3_PORT_SEL1 P33_ACCESS(0xc1)
|
||||
#define P3_PORT_SEL2 P33_ACCESS(0xc2)
|
||||
#define P3_PORT_SEL3 P33_ACCESS(0xc3)
|
||||
#define P3_PORT_SEL4 P33_ACCESS(0xc4)
|
||||
#define P3_PORT_SEL5 P33_ACCESS(0xc5)
|
||||
#define P3_PORT_SEL6 P33_ACCESS(0xc6)
|
||||
#define P3_PORT_SEL7 P33_ACCESS(0xc7)
|
||||
#define P3_PORT_SEL8 P33_ACCESS(0xc8)
|
||||
#define P3_PORT_SEL9 P33_ACCESS(0xc9)
|
||||
#define P3_PORT_SEL10 P33_ACCESS(0xca)
|
||||
#define P3_PORT_SEL11 P33_ACCESS(0xcb)
|
||||
#define P3_PORT_SEL12 P33_ACCESS(0xcc)
|
||||
#define P3_PORT_SEL13 P33_ACCESS(0xcd)
|
||||
#define P3_PORT_SEL14 P33_ACCESS(0xce)
|
||||
#define P3_PORT_SEL15 P33_ACCESS(0xcf)
|
||||
|
||||
//............. 0x00d0 - 0x00df............
|
||||
#define P3_LS_IO_DLY P33_ACCESS(0xd0) //TODO: check sync with verilog head file chip_def.v LEVEL_SHIFTER
|
||||
#define P3_LS_IO_ROM P33_ACCESS(0xd1)
|
||||
#define P3_LS_ADC P33_ACCESS(0xd2)
|
||||
#define P3_LS_AUDIO P33_ACCESS(0xd3)
|
||||
#define P3_LS_RF P33_ACCESS(0xd4)
|
||||
#define P3_LS_PLL P33_ACCESS(0xd5)
|
||||
|
||||
|
||||
//===============================================================================//
|
||||
//
|
||||
// p33 rtcvdd
|
||||
//
|
||||
//===============================================================================//
|
||||
//#define RTC_SFR_BEGIN 0x1000
|
||||
|
||||
|
||||
|
||||
//............. 0x0080 - 0x008f............ for RTC
|
||||
#define R3_ALM_CON RTC_ACCESS((0x80))
|
||||
|
||||
#define R3_RTC_CON0 RTC_ACCESS((0x84))
|
||||
#define R3_RTC_CON1 RTC_ACCESS((0x85))
|
||||
#define R3_RTC_DAT0 RTC_ACCESS((0x86))
|
||||
#define R3_RTC_DAT1 RTC_ACCESS((0x87))
|
||||
#define R3_RTC_DAT2 RTC_ACCESS((0x88))
|
||||
#define R3_RTC_DAT3 RTC_ACCESS((0x89))
|
||||
#define R3_RTC_DAT4 RTC_ACCESS((0x8a))
|
||||
#define R3_ALM_DAT0 RTC_ACCESS((0x8b))
|
||||
#define R3_ALM_DAT1 RTC_ACCESS((0x8c))
|
||||
#define R3_ALM_DAT2 RTC_ACCESS((0x8d))
|
||||
#define R3_ALM_DAT3 RTC_ACCESS((0x8e))
|
||||
#define R3_ALM_DAT4 RTC_ACCESS((0x8f))
|
||||
|
||||
//............. 0x0090 - 0x009f............ for PORT control
|
||||
#define R3_WKUP_EN RTC_ACCESS((0x90))
|
||||
#define R3_WKUP_EDGE RTC_ACCESS((0x91))
|
||||
#define R3_WKUP_CPND RTC_ACCESS((0x92))
|
||||
#define R3_WKUP_PND RTC_ACCESS((0x93))
|
||||
#define R3_WKUP_FLEN RTC_ACCESS((0x94))
|
||||
#define R3_PORT_FLT RTC_ACCESS((0x95))
|
||||
|
||||
#define R3_PR_IN RTC_ACCESS((0x98))
|
||||
#define R3_PR_OUT RTC_ACCESS((0x99))
|
||||
#define R3_PR_DIR RTC_ACCESS((0x9a))
|
||||
#define R3_PR_DIE RTC_ACCESS((0x9b))
|
||||
#define R3_PR_PU RTC_ACCESS((0x9c))
|
||||
#define R3_PR_PD RTC_ACCESS((0x9d))
|
||||
#define R3_PR_HD RTC_ACCESS((0x9e))
|
||||
|
||||
//............. 0x00a0 - 0x00af............ for system
|
||||
#define R3_TIME_CON RTC_ACCESS((0xa0))
|
||||
#define R3_TIME_CPND RTC_ACCESS((0xa1))
|
||||
#define R3_TIME_PND RTC_ACCESS((0xa2))
|
||||
|
||||
#define R3_ADC_CON RTC_ACCESS((0xa4))
|
||||
#define R3_OSL_CON RTC_ACCESS((0xa5))
|
||||
|
||||
#define R3_WKUP_SRC RTC_ACCESS((0xa8))
|
||||
#define R3_RST_SRC RTC_ACCESS((0xa9))
|
||||
|
||||
#define R3_RST_CON RTC_ACCESS((0xab))
|
||||
#define R3_CLK_CON RTC_ACCESS((0xac))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
336
include_lib/driver/cpu/br28/asm/power/power_api.h
Normal file
336
include_lib/driver/cpu/br28/asm/power/power_api.h
Normal file
@ -0,0 +1,336 @@
|
||||
#ifndef __POWER_API_H__
|
||||
#define __POWER_API_H__
|
||||
|
||||
#define PMU_NEW_FLOW 0
|
||||
#define TRIM_WVDD BIT(0)
|
||||
#define TRIM_PVDD BIT(1)
|
||||
#define TRIM_IOVDD BIT(2)
|
||||
|
||||
//=========================电源参数配置==================================
|
||||
struct low_power_param {
|
||||
u8 config; //低功耗使能，蓝牙&&系统空闲可进入低功耗
|
||||
u8 osc_type; //低功耗晶振类型，btosc/lrc
|
||||
u32 btosc_hz; //蓝牙晶振频率
|
||||
|
||||
//vddiow_lev不需要配置，sleep、softoff模式会保持电压，除非配置使用nkeep_vddio(功耗相差不大)
|
||||
u8 vddiom_lev; //vddiom
|
||||
u8 vddiow_lev; //vddiow
|
||||
u8 nkeep_vddio; //softoff模式下不保持vddio
|
||||
|
||||
u32 osc_delay_us; //低功耗晶振起振延时，为预留配置。
|
||||
u8 rtc_clk; //rtc时钟源，softoff模式根据此配置是否保持住相应时钟
|
||||
u8 lpctmu_en; //低功耗触摸，softoff模式根据此配置是否保持住该模块
|
||||
|
||||
u8 mem_init_con; //初始化ram电源
|
||||
u8 mem_lowpower_con; //低功耗ram电源
|
||||
u8 rvdd2pvdd; //低功耗外接dcdc
|
||||
u8 pvdd_dcdc_port;
|
||||
|
||||
u8 lptmr_flow; //低功耗参数由用户配置
|
||||
u32 t1;
|
||||
u32 t2;
|
||||
u32 t3_lrc;
|
||||
u32 t4_lrc;
|
||||
u32 t3_btosc;
|
||||
u32 t4_btosc;
|
||||
|
||||
u8 flash_pg; //iomc: 外置flash power gate
|
||||
|
||||
u8 btosc_disable;
|
||||
u8 delay_us;
|
||||
|
||||
u8 vddio_keep_type_pd; //sleep keep vddio使用类型
|
||||
u8 vddio_keep_type_sf; //soff keep vddio使用类型
|
||||
};
|
||||
|
||||
//config
|
||||
#define SLEEP_EN BIT(0)
|
||||
#define DEEP_SLEEP_EN BIT(1)
|
||||
|
||||
enum {
|
||||
VDDIO_KEEP_TYPE_TRIM = 0,//vddio keep使用trim值：默认
|
||||
VDDIO_KEEP_TYPE_PG, //vddio keep使用 mvvdio：功耗代价100ua
|
||||
};
|
||||
|
||||
//osc_type
|
||||
enum {
|
||||
OSC_TYPE_LRC = 0,
|
||||
OSC_TYPE_BT_OSC,
|
||||
};
|
||||
|
||||
//DCVDD电源模式
|
||||
enum {
|
||||
PWR_LDO15,
|
||||
PWR_DCDC15,
|
||||
};
|
||||
|
||||
//PVDD电源模式
|
||||
enum PVDD_MODE {
|
||||
PWR_PVDD_LDO,
|
||||
PWR_PVDD_DCDC,
|
||||
};
|
||||
|
||||
//==============================软关机参数配置============================
|
||||
//软关机会复位寄存器，该参数为传给rom配置的参数。
|
||||
struct soft_flag0_t {
|
||||
u8 wdt_dis: 1;
|
||||
u8 poweroff: 1;
|
||||
u8 is_port_b: 1;
|
||||
u8 lvd_en: 1;
|
||||
u8 pmu_en: 1;
|
||||
u8 iov2_ldomode: 1;
|
||||
u8 res: 2;
|
||||
};
|
||||
|
||||
struct soft_flag1_t {
|
||||
u8 usbdp: 2;
|
||||
u8 usbdm: 2;
|
||||
u8 uart_key_port: 1;
|
||||
u8 ldoin: 3;
|
||||
};
|
||||
|
||||
struct soft_flag2_t {
|
||||
u8 pg2: 4;
|
||||
u8 pg3: 4;
|
||||
};
|
||||
|
||||
struct soft_flag3_t {
|
||||
u8 pg4: 4;
|
||||
u8 res: 4;
|
||||
};
|
||||
|
||||
struct soft_flag4_t {
|
||||
u8 fast_boot: 1;
|
||||
u8 flash_stable_delay_sel: 2;
|
||||
u8 res: 5;
|
||||
};
|
||||
|
||||
struct soft_flag5_t {
|
||||
u8 mvddio: 3;
|
||||
u8 wvbg: 4;
|
||||
u8 res: 1;
|
||||
};
|
||||
|
||||
struct boot_soft_flag_t {
|
||||
union {
|
||||
struct soft_flag0_t boot_ctrl;
|
||||
u8 value;
|
||||
} flag0;
|
||||
union {
|
||||
struct soft_flag1_t misc;
|
||||
u8 value;
|
||||
} flag1;
|
||||
union {
|
||||
struct soft_flag2_t pg2_pg3;
|
||||
u8 value;
|
||||
} flag2;
|
||||
union {
|
||||
struct soft_flag3_t pg4_res;
|
||||
u8 value;
|
||||
} flag3;
|
||||
union {
|
||||
struct soft_flag4_t fast_boot_ctrl;
|
||||
u8 value;
|
||||
} flag4;
|
||||
union {
|
||||
struct soft_flag5_t level;
|
||||
u8 value;
|
||||
} flag5;
|
||||
};
|
||||
|
||||
enum soft_flag_io_stage {
|
||||
SOFTFLAG_HIGH_RESISTANCE,
|
||||
SOFTFLAG_PU,
|
||||
SOFTFLAG_PD,
|
||||
|
||||
SOFTFLAG_OUT0,
|
||||
SOFTFLAG_OUT0_HD0,
|
||||
SOFTFLAG_OUT0_HD,
|
||||
SOFTFLAG_OUT0_HD0_HD,
|
||||
|
||||
SOFTFLAG_OUT1,
|
||||
SOFTFLAG_OUT1_HD0,
|
||||
SOFTFLAG_OUT1_HD,
|
||||
SOFTFLAG_OUT1_HD0_HD,
|
||||
};
|
||||
|
||||
//==============================电源接口============================
|
||||
|
||||
#define AT_VOLATILE_RAM_CODE_POWER AT(.power_driver.text.cache.L1)
|
||||
#define AT_VOLATILE_CACHE_CODE_POWER AT(.power_driver.text.cache.L2)
|
||||
|
||||
void power_set_mode(u8 mode);
|
||||
|
||||
void power_set_pvdd_mode(enum PVDD_MODE mode);
|
||||
|
||||
u8 get_pvdd_dcdc_cfg();
|
||||
|
||||
void power_init(const struct low_power_param *param);
|
||||
|
||||
void power_keep_dacvdd_en(u8 en);
|
||||
|
||||
void sdpg_config(int enable);
|
||||
|
||||
void p11_init(void);
|
||||
|
||||
u8 get_wvdd_trim_level();
|
||||
|
||||
u8 get_pvdd_level();
|
||||
|
||||
u8 get_pvdd_trim_level();
|
||||
|
||||
u8 get_miovdd_trim_level();
|
||||
|
||||
u8 get_wiovdd_trim_level();
|
||||
|
||||
void store_pmu_trim_value_to_vm(u8 wvdd_level, u8 pvdd_level, u8 miovdd_lev, u8 wiovdd_lev);
|
||||
|
||||
u8 load_pmu_trim_value_from_vm();
|
||||
|
||||
void volatage_trim_init();
|
||||
|
||||
//==============================sleep接口============================
|
||||
//注意：所有接口在临界区被调用，请勿使用阻塞操作
|
||||
//sleep模式介绍
|
||||
//1.所有数字模块停止，包括cpu、periph、audio、rf等
|
||||
//2.所有模拟模块停止，包括pll、btosc、rc等
|
||||
//3.只保留pmu模块
|
||||
|
||||
//light_sleep: 不切电源域
|
||||
//normal_sleep: dvdd低电
|
||||
//deepsleep：dvdd掉电
|
||||
|
||||
//----------------低功耗线程查询是否满足低功耗状态, 被动等待------------
|
||||
struct low_power_operation {
|
||||
|
||||
const char *name;
|
||||
|
||||
u32(*get_timeout)(void *priv);
|
||||
|
||||
void (*suspend_probe)(void *priv);
|
||||
|
||||
void (*suspend_post)(void *priv, u32 usec);
|
||||
|
||||
void (*resume)(void *priv, u32 usec);
|
||||
|
||||
void (*resume_post)(void *priv, u32 usec);
|
||||
};
|
||||
|
||||
enum LOW_POWER_LEVEL {
|
||||
LOW_POWER_MODE_LIGHT_SLEEP = 1,
|
||||
LOW_POWER_MODE_SLEEP,
|
||||
LOW_POWER_MODE_DEEP_SLEEP,
|
||||
};
|
||||
|
||||
typedef u8(*idle_handler_t)(void);
|
||||
typedef enum LOW_POWER_LEVEL(*level_handler_t)(void);
|
||||
|
||||
typedef u8(*idle_handler_t)(void);
|
||||
|
||||
struct lp_target {
|
||||
char *name;
|
||||
level_handler_t level;
|
||||
idle_handler_t is_idle;
|
||||
};
|
||||
|
||||
#define REGISTER_LP_TARGET(target) \
|
||||
const struct lp_target target sec(.lp_target)
|
||||
|
||||
|
||||
extern const struct lp_target lp_target_begin[];
|
||||
extern const struct lp_target lp_target_end[];
|
||||
|
||||
#define list_for_each_lp_target(p) \
|
||||
for (p = lp_target_begin; p < lp_target_end; p++)
|
||||
|
||||
|
||||
//--------------低功耗线程请求进入低功耗, 主动发出------------
|
||||
struct lp_request {
|
||||
char *name;
|
||||
u8(*request_enter)(u32 timeout);
|
||||
u8(*request_exit)(u32 timeout);
|
||||
};
|
||||
|
||||
#define REGISTER_LP_REQUEST(target) \
|
||||
const struct lp_request target sec(.lp_request)
|
||||
|
||||
extern const struct lp_request lp_request_begin[];
|
||||
extern const struct lp_request lp_request_end[];
|
||||
|
||||
#define list_for_each_lp_request(p) \
|
||||
for (p = lp_request_begin; p < lp_request_end; p++)
|
||||
|
||||
//-----------------------深度睡眠处理--------------------------
|
||||
struct deepsleep_target {
|
||||
char *name;
|
||||
u8(*enter)(void);
|
||||
u8(*exit)(void);
|
||||
};
|
||||
|
||||
#define DEEPSLEEP_TARGET_REGISTER(target) \
|
||||
const struct deepsleep_target target sec(.deepsleep_target)
|
||||
|
||||
|
||||
extern const struct deepsleep_target deepsleep_target_begin[];
|
||||
extern const struct deepsleep_target deepsleep_target_end[];
|
||||
|
||||
#define list_for_each_deepsleep_target(p) \
|
||||
for (p = deepsleep_target_begin; p < deepsleep_target_end; p++)
|
||||
|
||||
|
||||
#define NEW_BASEBAND_COMPENSATION 0
|
||||
|
||||
u32 __tus_carry(u32 x);
|
||||
|
||||
#define power_is_poweroff_post() 0
|
||||
|
||||
void *low_power_get(void *priv, const struct low_power_operation *ops);
|
||||
|
||||
void low_power_put(void *priv);
|
||||
|
||||
void low_power_sys_request(void *priv);
|
||||
|
||||
void *low_power_sys_get(void *priv, const struct low_power_operation *ops);
|
||||
|
||||
void low_power_sys_put(void *priv);
|
||||
|
||||
u8 is_low_power_mode(enum LOW_POWER_LEVEL level);
|
||||
|
||||
u8 low_power_sys_is_idle(void);
|
||||
|
||||
s32 low_power_trace_drift(u32 usec);
|
||||
|
||||
void low_power_reset_osc_type(u8 type);
|
||||
|
||||
u8 low_power_get_default_osc_type(void);
|
||||
|
||||
u8 low_power_get_osc_type(void);
|
||||
|
||||
void low_power_on(void);
|
||||
|
||||
void low_power_request(void);
|
||||
|
||||
u8 low_power_sys_request_enter(u32 timeout);
|
||||
|
||||
u8 low_power_sys_request_exit(u32 timeout);
|
||||
|
||||
u32 get_rch_hz();
|
||||
|
||||
void cap_rch_enable();
|
||||
|
||||
void cap_rch_disable();
|
||||
|
||||
//==============================soft接口============================
|
||||
|
||||
|
||||
void power_set_soft_poweroff();
|
||||
|
||||
void power_set_soft_poweroff_advance();
|
||||
|
||||
void mask_softflag_config(const struct boot_soft_flag_t *softflag);
|
||||
|
||||
void power_set_callback(u8 mode, void (*powerdown_enter)(u8 step), void (*powerdown_exit)(u32), void (*soft_poweroff_enter)(void));
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
8
include_lib/driver/cpu/br28/asm/power/power_compat.h
Normal file
8
include_lib/driver/cpu/br28/asm/power/power_compat.h
Normal file
@ -0,0 +1,8 @@
|
||||
#ifndef __POWER_COMPAT_H__
|
||||
#define __POWER_COMPAT_H__
|
||||
|
||||
//compatibility
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
154
include_lib/driver/cpu/br28/asm/power/power_port.h
Normal file
154
include_lib/driver/cpu/br28/asm/power/power_port.h
Normal file
@ -0,0 +1,154 @@
|
||||
#ifndef __POWER_PORT_H__
|
||||
#define __POWER_PORT_H__
|
||||
|
||||
#define NO_CONFIG_PORT (-1)
|
||||
enum {
|
||||
PORTA_GROUP = 0,
|
||||
PORTB_GROUP,
|
||||
PORTC_GROUP,
|
||||
PORTD_GROUP,
|
||||
PORTE_GROUP,
|
||||
PORTG_GROUP,
|
||||
PORTP_GROUP,
|
||||
};
|
||||
|
||||
struct gpio_value {
|
||||
u16 gpioa;
|
||||
u16 gpiob;
|
||||
u16 gpioc;
|
||||
u16 gpiod;
|
||||
u16 gpioe;
|
||||
u16 gpiog;
|
||||
u16 gpiop;
|
||||
u16 gpiousb;
|
||||
};
|
||||
|
||||
#define _PORT(p) JL_PORT##p
|
||||
#define SPI_PORT(p) _PORT(p)
|
||||
|
||||
|
||||
|
||||
// | func\port | A | B | C |
|
||||
// |-----------|------|------|------|
|
||||
// | CS | PD3 | PG4 | PC3 |
|
||||
// | CLK | PD0 | PD0 | PC1 |
|
||||
// | DO(D0) | PD1 | PD1 | PC2 |
|
||||
// | DI(D1) | PD2 | PG3 | PC4 |
|
||||
// | WP(D2) | PD5 | PG2 | PC5 |
|
||||
// | HOLD(D3) | PD6 | PD6 | PC0 |
|
||||
|
||||
#define PORT_SPI0_PWRA D
|
||||
#define SPI0_PWRA 4
|
||||
|
||||
#define PORT_SPI0_CSA D
|
||||
#define SPI0_CSA 3
|
||||
|
||||
#define PORT_SPI0_CLKA D
|
||||
#define SPI0_CLKA 0
|
||||
|
||||
#define PORT_SPI0_DOA D
|
||||
#define SPI0_DOA 1
|
||||
|
||||
#define PORT_SPI0_DIA D
|
||||
#define SPI0_DIA 2
|
||||
|
||||
#define PORT_SPI0_D2A D
|
||||
#define SPI0_D2A 5
|
||||
|
||||
#define PORT_SPI0_D3A D
|
||||
#define SPI0_D3A 6
|
||||
|
||||
#define SPI0_PWR_A IO_PORTD_04
|
||||
#define SPI0_CS_A IO_PORTD_03
|
||||
#define SPI0_CLK_A IO_PORTD_00
|
||||
#define SPI0_DO_D0_A IO_PORTD_01
|
||||
#define SPI0_DI_D1_A IO_PORTD_02
|
||||
#define SPI0_WP_D2_A IO_PORTD_05
|
||||
#define SPI0_HOLD_D3_A IO_PORTD_06
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define PORT_SPI0_PWRB D
|
||||
#define SPI0_PWRB 4
|
||||
|
||||
#define PORT_SPI0_CSB G
|
||||
#define SPI0_CSB 4
|
||||
|
||||
#define PORT_SPI0_CLKB D
|
||||
#define SPI0_CLKB 0
|
||||
|
||||
#define PORT_SPI0_DOB D
|
||||
#define SPI0_DOB 1
|
||||
|
||||
#define PORT_SPI0_DIB G
|
||||
#define SPI0_DIB 3
|
||||
|
||||
#define PORT_SPI0_D2B G
|
||||
#define SPI0_D2B 2
|
||||
|
||||
#define PORT_SPI0_D3B D
|
||||
#define SPI0_D3B 6
|
||||
|
||||
#define SPI0_PWR_B IO_PORTD_04
|
||||
#define SPI0_CS_B IO_PORTG_04
|
||||
#define SPI0_CLK_B IO_PORTD_00
|
||||
#define SPI0_DO_D0_B IO_PORTD_01
|
||||
#define SPI0_DI_D1_B IO_PORTG_03
|
||||
#define SPI0_WP_D2_B IO_PORTG_02
|
||||
#define SPI0_HOLD_D3_B IO_PORTD_06
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#define PORT_SPI0_PWRC C
|
||||
#define SPI0_PWRC 8
|
||||
|
||||
#define PORT_SPI0_CSC C
|
||||
#define SPI0_CSC 3
|
||||
|
||||
#define PORT_SPI0_CLKC C
|
||||
#define SPI0_CLKC 1
|
||||
|
||||
#define PORT_SPI0_DOC C
|
||||
#define SPI0_DOC 2
|
||||
|
||||
#define PORT_SPI0_DIC C
|
||||
#define SPI0_DIC 4
|
||||
|
||||
#define PORT_SPI0_D2C C
|
||||
#define SPI0_D2C 5
|
||||
|
||||
#define PORT_SPI0_D3C C
|
||||
#define SPI0_D3C 0
|
||||
|
||||
#define SPI0_PWR_C IO_PORTC_08
|
||||
#define SPI0_CS_C IO_PORTC_03
|
||||
#define SPI0_CLK_C IO_PORTC_01
|
||||
#define SPI0_DO_D0_C IO_PORTC_02
|
||||
#define SPI0_DI_D1_C IO_PORTC_04
|
||||
#define SPI0_WP_D2_C IO_PORTC_05
|
||||
#define SPI0_HOLD_D3_C IO_PORTC_00
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define PSRAM_D0A IO_PORTE_00
|
||||
#define PSRAM_D1A IO_PORTE_01
|
||||
#define PSRAM_D2A IO_PORTE_02
|
||||
#define PSRAM_D3A IO_PORTE_05
|
||||
|
||||
u32 get_sfc_port(void);
|
||||
u8 get_sfc_bit_mode();
|
||||
u8 get_sfc1_bit_mode();
|
||||
void port_init(void);
|
||||
void port_protect(u16 *port_group, u32 port_num);
|
||||
|
||||
u8 WSIG_to_PANA(u8 wsig);
|
||||
u8 PANA_to_WSIG(u8 iomap);
|
||||
|
||||
void soff_gpio_protect(u32 gpio);
|
||||
void board_set_soft_poweroff_common(void *priv);
|
||||
|
||||
void sleep_gpio_protect(u32 gpio);
|
||||
void sleep_enter_callback_common(void *priv);
|
||||
void sleep_exit_callback_common(void *priv);
|
||||
|
||||
#endif
|
||||
|
||||
59
include_lib/driver/cpu/br28/asm/power/power_reset.h
Normal file
59
include_lib/driver/cpu/br28/asm/power/power_reset.h
Normal file
@ -0,0 +1,59 @@
|
||||
#ifndef __POWER_RESET_H__
|
||||
#define __POWER_RESET_H__
|
||||
|
||||
/*
|
||||
*复位原因包括两种
|
||||
1.系统复位源: p33 p11 主系统
|
||||
2.自定义复位源：断言、异常等
|
||||
*/
|
||||
enum RST_REASON {
|
||||
/*主系统*/
|
||||
MSYS_P11_RST, //P11复位
|
||||
MSYS_DVDD_POR_RST, //DVDD上电
|
||||
MSYS_SOFT_RST, //主系统软件复位
|
||||
MSYS_P2M_RST, //低功耗唤醒复位(softoff advance && deepsleep)
|
||||
MSYS_POWER_RETURN, //主系统未被复位
|
||||
|
||||
/*P11*/
|
||||
P11_PVDD_POR_RST, //pvdd上电
|
||||
P11_IVS_RST, //低功耗唤醒复位(softoff legacy)
|
||||
P11_P33_RST, //p33复位
|
||||
P11_WDT_RST, //看门狗复位
|
||||
P11_SOFT_RST, //软件复位
|
||||
P11_MSYS_RST, //主系统复位P11
|
||||
P11_POWER_RETURN, //P11系统未被复位
|
||||
|
||||
/*P33*/
|
||||
P33_VDDIO_POR_RST, //vddio上电复位(电池/vpwr供电)
|
||||
P33_VDDIO_LVD_RST, //vddio低压复位、上电复位(电池/vpwr供电)
|
||||
P33_VCM_RST, //vcm高电平短接复位
|
||||
P33_PPINR_RST, //数字io输入长按复位
|
||||
P33_P11_RST, //p11系统复位p33，rset_mask=0
|
||||
P33_SOFT_RST, //p33软件复位，一般软件复位指此系统复位源，所有系统会直接复位。
|
||||
P33_PPINR1_RST, //模拟io输入长按复位，包括charge_full、vatch、ldoint、vabt_det
|
||||
P33_POWER_RETURN, //p33系统未被复位。
|
||||
|
||||
//SUB
|
||||
P33_EXCEPTION_SOFT_RST, //异常软件复位
|
||||
P33_ASSERT_SOFT_RST, //断言软件复位
|
||||
P33_XOSC_RESUME_ERR_RST, //快速起振恢复失败软件复位
|
||||
P33_LPTMR_TIMEOUT_RST, //LPTMR软件复位
|
||||
};
|
||||
|
||||
void power_reset_close();
|
||||
|
||||
void reset_source_dump(void);
|
||||
|
||||
void p33_soft_reset(void);
|
||||
|
||||
void set_reset_source_value(enum RST_REASON index);
|
||||
|
||||
u32 get_reset_source_value(void);
|
||||
|
||||
u8 is_reset_source(enum RST_REASON index);
|
||||
|
||||
int cpu_reset_by_soft();
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
74
include_lib/driver/cpu/br28/asm/power/power_wakeup.h
Normal file
74
include_lib/driver/cpu/br28/asm/power/power_wakeup.h
Normal file
@ -0,0 +1,74 @@
|
||||
#ifndef __POWER_WAKEUP_H__
|
||||
#define __POWER_WAKEUP_H__
|
||||
|
||||
enum WAKEUP_REASON {
|
||||
//WAKEUP
|
||||
PWR_WK_REASON_PLUSE_CNT_OVERFLOW, //pcnt唤醒复位
|
||||
PWR_WK_REASON_P11, //P11唤醒复位
|
||||
PWR_WK_REASON_LPCTMU, //触摸唤醒复位
|
||||
PWR_WK_REASON_PORT_EDGE, //数字io输入边沿唤醒复位
|
||||
PWR_WK_REASON_ANA_EDGE, //模拟io输入边沿唤醒复位
|
||||
PWR_WK_REASON_VDDIO_LVD, //vddio lvd唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX0, //p33 index0 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX1, //p33 index1 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX2, //p33 index2 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX3, //p33 index3 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX4, //p33 index4 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX5, //p33 index5 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX6, //p33 index6 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX7, //p33 index7 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX8, //p33 index8 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX9, //p33 index9 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX10, //p33 index10 io唤醒复位
|
||||
PWR_WK_REASON_EDGE_INDEX11, //p33 index11 io唤醒复位
|
||||
PWR_ANA_WK_REASON_FALLINIG_EDGE_LDOIN, //LDO5V上升沿唤醒复位
|
||||
PWR_ANA_WK_REASON_RISING_EDGE_LDOIN, //LDO5V下降沿唤醒复位
|
||||
PWR_ANA_WK_REASON_FALLING_EDGE_VBATCH, //VBATCH上升降沿唤醒复位
|
||||
PWR_ANA_WK_REASON_RISING_EDGE_VBATCH, //VBATCH下降沿唤醒复位
|
||||
PWR_RTC_WK_REASON_ALM, //RTC闹钟唤醒复位
|
||||
PWR_RTC_WK_REASON_256HZ, //RTC 256Hz时基唤醒复位
|
||||
PWR_RTC_WK_REASON_64HZ, //RTC 64Hz时基唤醒复位
|
||||
PWR_RTC_WK_REASON_2HZ, //RTC 2Hz时基唤醒复位
|
||||
PWR_RTC_WK_REASON_1HZ, //RTC 1Hz时基唤醒复位
|
||||
};
|
||||
|
||||
//=========================唤醒参数配置==================================
|
||||
|
||||
struct port_wakeup {
|
||||
u8 iomap; //唤醒io
|
||||
u8 pullup_down_enable; //上下拉是否使能
|
||||
POWER_WKUP_EDGE edge; //唤醒边沿条件
|
||||
POWER_WKUP_FLT filter; //滤波参数，数字io输入没有滤波可配制
|
||||
};
|
||||
|
||||
struct wakeup_param {
|
||||
//数字io输入
|
||||
const struct port_wakeup *port[MAX_WAKEUP_PORT];
|
||||
//模拟io输入
|
||||
const struct port_wakeup *aport[MAX_WAKEUP_ANA_PORT];
|
||||
};
|
||||
|
||||
//=========================唤醒接口==================================
|
||||
void power_wakeup_index_enable(u8 index, u8 enable);
|
||||
void power_wakeup_gpio_enable(u8 gpio, u8 enable);
|
||||
void power_wakeup_gpio_edge(u8 gpio, POWER_WKUP_EDGE edge);
|
||||
|
||||
void power_awakeup_index_enable(u8 index, u8 enable);
|
||||
void power_awakeup_gpio_enable(u8 gpio, u8 enable);
|
||||
void power_awakeup_gpio_edge(u8 gpio, POWER_WKUP_EDGE edge);
|
||||
|
||||
void power_wakeup_set_callback(void (*wakeup_callback)(u8 index, u8 gpio));
|
||||
void power_awakeup_set_callback(void (*wakeup_callback)(u8 index, u8 gpio, POWER_WKUP_EDGE edge));
|
||||
|
||||
void port_edge_wkup_set_callback_by_index(u8 index, void (*wakeup_callback)(u8 index, u8 gpio));
|
||||
void aport_edge_wkup_set_callback_by_index(u8 index, void (*wakeup_callback)(u8 index, u8 gpio, POWER_WKUP_EDGE edge));
|
||||
|
||||
void power_wakeup_init(const struct wakeup_param *param);
|
||||
|
||||
u8 is_wakeup_source(enum WAKEUP_REASON index);
|
||||
|
||||
void power_wakeup_reason_dump();
|
||||
|
||||
u8 is_ldo5v_wakeup(void);
|
||||
|
||||
#endif
|
||||
55
include_lib/driver/cpu/br28/asm/power/rtc_app.h
Normal file
55
include_lib/driver/cpu/br28/asm/power/rtc_app.h
Normal file
@ -0,0 +1,55 @@
|
||||
#ifndef __RTC_APP_H__
|
||||
#define __RTC_APP_H__
|
||||
|
||||
enum {
|
||||
R3_WKUP_SRC_ALM = 0,
|
||||
R3_WKUP_SRC_256HZ = 4,
|
||||
R3_WKUP_SRC_64HZ,
|
||||
R3_WKUP_SRC_2HZ,
|
||||
R3_WKUP_SRC_1HZ,
|
||||
};
|
||||
|
||||
|
||||
/************************R3_ALM_CON*****************************/
|
||||
#define ALM_ALMOUT(a) P33_CON_SET(R3_ALM_CON, 7, 1, a)
|
||||
|
||||
#define ALM_CLK_SEL(a) P33_CON_SET(R3_ALM_CON, 2, 3, a)
|
||||
|
||||
#define ALM_ALMEN(a) P33_CON_SET(R3_ALM_CON, 0, 1, a)
|
||||
|
||||
//Macro for CLK_SEL
|
||||
enum {
|
||||
CLK_SEL_32K = 1,
|
||||
CLK_SEL_12M,
|
||||
CLK_SEL_24M,
|
||||
CLK_SEL_LRC,
|
||||
};
|
||||
|
||||
/************************R3_RTC_CON0*****************************/
|
||||
#define RTC_ALM_RDEN(a) P33_CON_SET(R3_RTC_CON0, 5, 1, a)
|
||||
|
||||
#define RTC_RTC_RDEN(a) P33_CON_SET(R3_RTC_CON0, 4, 1, a)
|
||||
|
||||
#define RTC_ALM_WREN(a) P33_CON_SET(R3_RTC_CON0, 1, 1, a)
|
||||
|
||||
#define RTC_RTC_WREN(a) P33_CON_SET(R3_RTC_CON0, 0, 1, a)
|
||||
|
||||
/************************R3_OSL_CON*****************************/
|
||||
#define OSL_X32XS(a) P33_CON_SET(R3_OSL_CON, 4, 2, a)
|
||||
|
||||
#define OSL_X32TS(a) P33_CON_SET(R3_OSL_CON, 2, 1, a)
|
||||
|
||||
#define OSL_X32OS(a) P33_CON_SET(R3_OSL_CON, 1, 1, a)
|
||||
|
||||
#define OSL_X32ES(a) P33_CON_SET(R3_OSL_CON, 0, 1, a)
|
||||
|
||||
/************************R3_TIME_CPND*****************************/
|
||||
#define TIME_256HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 0, 1, a)
|
||||
|
||||
#define TIME_64HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 1, 1, a)
|
||||
|
||||
#define TIME_2HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 2, 1, a)
|
||||
|
||||
#define TIME_1HZ_CPND(a) P33_CON_SET(R3_TIME_CPND, 3, 1, a)
|
||||
|
||||
#endif
|
||||
23
include_lib/driver/cpu/br28/asm/power_interface.h
Normal file
23
include_lib/driver/cpu/br28/asm/power_interface.h
Normal file
@ -0,0 +1,23 @@
|
||||
#ifndef POWER_INTERFACE_H
|
||||
#define POWER_INTERFACE_H
|
||||
|
||||
#include "generic/typedef.h"
|
||||
|
||||
#include "asm/power/p33.h"
|
||||
|
||||
#include "asm/power/p11.h"
|
||||
|
||||
#include "asm/power/power_api.h"
|
||||
|
||||
#include "asm/power/power_port.h"
|
||||
|
||||
#include "asm/power/power_wakeup.h"
|
||||
|
||||
#include "asm/power/power_reset.h"
|
||||
|
||||
#include "asm/power/power_compat.h"
|
||||
|
||||
#include "asm/power/lp_ipc.h"
|
||||
|
||||
|
||||
#endif
|
||||
233
include_lib/driver/cpu/br28/asm/pwm_led.h
Normal file
233
include_lib/driver/cpu/br28/asm/pwm_led.h
Normal file
@ -0,0 +1,233 @@
|
||||
#ifndef _PWM_LED_H_
|
||||
#define _PWM_LED_H_
|
||||
|
||||
/*******************************************************************
|
||||
* 本文件为LED灯配置的接口头文件
|
||||
*
|
||||
* 约定:
|
||||
* 1)两盏灯为单IO双LED接法;
|
||||
* 2)LED0: RLED, 蓝色, 低电平亮灯;
|
||||
* 3)LED1: BLED, 红色, 高电平亮灯;
|
||||
*********************************************************************/
|
||||
|
||||
// LED实现的效果有:
|
||||
// 1.两盏LED全亮;
|
||||
// 2.LED单独亮灭;
|
||||
// 3.LED单独慢闪和快闪;
|
||||
// 4.LED 5s内单独闪一次和两次;
|
||||
// 5.LED交替快闪和慢闪;
|
||||
// 6.LED单独呼吸;
|
||||
// 7.LED交替呼吸
|
||||
|
||||
/*
|
||||
* LED各个效果可供配置以下参数, 请按照参数后面的注释说明的范围进行配置
|
||||
*/
|
||||
|
||||
//#define PWM_LED_TWO_IO_SUPPORT //定义该宏会支持两个IO推灯模式, 默认关闭
|
||||
|
||||
#define CFG_LED0_LIGHT 200 //10 ~ 500, 值越大, (红灯)亮度越高
|
||||
#define CFG_LED1_LIGHT 200 //10 ~ 500, 值越大, (蓝灯)亮度越高
|
||||
|
||||
#define CFG_SINGLE_FAST_FLASH_FREQ 500 //LED单独快闪速度, ms闪烁一次(100 ~ 1000)
|
||||
#define CFG_SINGLE_FAST_LIGHT_TIME 100 //单灯快闪灯亮持续时间, 单位ms
|
||||
|
||||
#define CFG_SINGLE_SLOW_FLASH_FREQ 2000 //LED单独慢闪速度, ms闪烁一次(1000 ~ 20000)
|
||||
#define CFG_SINGLE_SLOW_LIGHT_TIME 100 //单灯慢闪灯亮持续时间, 单位ms
|
||||
|
||||
#define CFG_DOUBLE_FAST_FLASH_FREQ 500 //LED交替快闪速度, ms闪烁一次(100 ~ 1000)
|
||||
#define CFG_DOUBLE_SLOW_FLASH_FREQ 2000 //LED交替慢闪速度, ms闪烁一次(1000 ~ 20000)
|
||||
|
||||
/***************** LED0/LED1单独每隔5S单闪时, 可供调节参数 ********************/
|
||||
#define CFG_LED_5S_FLASH_LIGHT_TIME 100 //LED 5S 闪烁时灯亮持续时间, 单位ms
|
||||
|
||||
/***************** 呼吸模式配置参数, 可供调节参数 ********************/
|
||||
#define CFG_LED_BREATH_TIME 1000 //呼吸时间灭->亮->灭, 单位ms
|
||||
#define CFG_LED0_BREATH_BRIGHT 300 //呼吸亮度, 范围: 0 ~ 500
|
||||
#define CFG_LED1_BREATH_BRIGHT 300 //呼吸亮度, 范围: 0 ~ 500
|
||||
#define CFG_LED_BREATH_BLINK_TIME 1000 //灭灯延时, 单位ms
|
||||
|
||||
|
||||
enum pwm_led_clk_source {
|
||||
PWM_LED_CLK_RESERVED0, //PWM_LED_CLK_OSC32K, no use
|
||||
PWM_LED_CLK_RC32K, //use
|
||||
PWM_LED_CLK_RESERVED1, //PWM_LED_CLK_BTOSC_12M, no use
|
||||
PWM_LED_CLK_RESERVED2, //PWM_LED_CLK_RCLK_250K, no use
|
||||
PWM_LED_CLK_BTOSC_24M, //use
|
||||
};
|
||||
|
||||
enum pwm_led_mode {
|
||||
PWM_LED_MODE_START,
|
||||
|
||||
PWM_LED_ALL_OFF, //mode1: 全灭
|
||||
PWM_LED_ALL_ON, //mode2: 全亮
|
||||
|
||||
PWM_LED0_ON, //mode3: 蓝亮
|
||||
PWM_LED0_OFF, //mode4: 蓝灭
|
||||
PWM_LED0_SLOW_FLASH, //mode5: 蓝慢闪
|
||||
PWM_LED0_FAST_FLASH, //mode6: 蓝快闪
|
||||
PWM_LED0_DOUBLE_FLASH_5S, //mode7: 蓝灯5秒连闪两下
|
||||
PWM_LED0_ONE_FLASH_5S, //mode8: 蓝灯5秒连闪1下
|
||||
|
||||
PWM_LED1_ON, //mode9: 红亮
|
||||
PWM_LED1_OFF, //mode10: 红灭
|
||||
PWM_LED1_SLOW_FLASH, //mode11: 红慢闪
|
||||
PWM_LED1_FAST_FLASH, //mode12: 红快闪
|
||||
PWM_LED1_DOUBLE_FLASH_5S, //mode13: 红灯5秒连闪两下
|
||||
PWM_LED1_ONE_FLASH_5S, //mode14: 红灯5秒闪1下
|
||||
|
||||
PWM_LED0_LED1_FAST_FLASH, //mode15: 红蓝交替闪（快闪）
|
||||
PWM_LED0_LED1_SLOW_FLASH, //mode16: 红蓝交替闪（慢闪）
|
||||
|
||||
PWM_LED0_BREATHE, //mode17: 蓝灯呼吸灯模式
|
||||
PWM_LED1_BREATHE, //mode18: 红灯呼吸灯模式
|
||||
PWM_LED0_LED1_BREATHE, //mode19: 红蓝交替呼吸灯模式
|
||||
|
||||
PWM_LED_MODE_END,
|
||||
|
||||
PWM_LED1_FLASH_THREE, //自定义状态，不能通过pmd_led_mode去设置
|
||||
PWM_LED0_FLASH_THREE, //自定义状态，不能通过pmd_led_mode去设置
|
||||
|
||||
PWM_LED_USER_DEFINE_BEGIN = 0x50,
|
||||
PWM_LED_USER_DEFINE_MODE0, //用户自定义模式0:
|
||||
PWM_LED_USER_DEFINE_END,
|
||||
|
||||
PWM_LED_NULL = 0xFF,
|
||||
};
|
||||
|
||||
struct pwm_led_two_io_mode {
|
||||
u8 two_io_mode_enable;
|
||||
u8 led0_pin;
|
||||
u8 led1_pin;
|
||||
};
|
||||
enum led_io_mode {
|
||||
LED_ONE_IO_MODE,
|
||||
LED_TWO_IO_MODE,
|
||||
};
|
||||
|
||||
struct one_io_cfg {
|
||||
u8 pin;
|
||||
};
|
||||
|
||||
struct two_io_cfg {
|
||||
u8 pin0;
|
||||
u8 pin1;
|
||||
};
|
||||
|
||||
union io_mode_cfg {
|
||||
struct one_io_cfg one_io;
|
||||
struct two_io_cfg two_io;
|
||||
};
|
||||
|
||||
struct led_platform_data {
|
||||
enum led_io_mode io_mode;
|
||||
union io_mode_cfg io_cfg;
|
||||
};
|
||||
|
||||
#define LED_PLATFORM_DATA_BEGIN(data) \
|
||||
const struct led_platform_data data = {
|
||||
|
||||
#define LED_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
/*********************** LED 初始化 ******************************/
|
||||
void pwm_led_init(const struct led_platform_data *user_data);
|
||||
|
||||
/********************** LED 闪烁模式切换 ************************/
|
||||
void pwm_led_mode_set(u8 fre_mode);
|
||||
|
||||
/*****************************************************************
|
||||
LED时钟源切换, support:
|
||||
PWM_LED_CLK_RC32K
|
||||
PWM_LED_CLK_BTOSC_24M
|
||||
*********************************************************************/
|
||||
void pwm_led_clk_set(enum pwm_led_clk_source src);
|
||||
|
||||
/***************** 闪烁状态复位, 重新开始一个周期 ******************/
|
||||
void pwm_led_display_mode_reset(void);
|
||||
|
||||
/***************** 获取led当前的闪烁模式 ***************************/
|
||||
enum pwm_led_mode pwm_led_display_mode_get(void);
|
||||
|
||||
/********************************************************************
|
||||
修改LED灯IO口驱动能力, 挡位: 0 ~ 3
|
||||
0: 2.4mA(8mA mos + 120Ωres)
|
||||
1: 8mA(8mA mos)
|
||||
2: 18.4mA(24mA mos + 120Ωres)
|
||||
3: 24mA(24mA mos)
|
||||
*********************************************************************/
|
||||
void pwm_led_io_max_drive_set(u8 strength);
|
||||
|
||||
/******************* PWM 模块开关 *********************/
|
||||
void pwm_led_set_on(void);
|
||||
void pwm_led_set_off(void);
|
||||
void led_module_on();
|
||||
void led_module_off();
|
||||
|
||||
|
||||
/******************* PWM 模块是否开启 *********************/
|
||||
u8 is_pwm_led_on(void);
|
||||
bool is_led_module_on();
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: 自定义设置单灯闪状态
|
||||
//@input: void
|
||||
// led_index: 0: led0, 1:led1, 2:led0 & led1(互闪)
|
||||
// led0_bright, LED0亮度: 0 ~ 500
|
||||
// led1_bright, LED1亮度: 0 ~ 500
|
||||
// led1_bright: led1亮度,
|
||||
// period: 闪灯周期(ms), 多少ms闪一下,
|
||||
// start_light_time: 在周期中开始亮灯的时间, -1: 周期最后亮灯
|
||||
// light_time: 灯亮持续时间,
|
||||
//@return: void
|
||||
//@note:
|
||||
//=================================================================================//
|
||||
void pwm_led_one_flash_display(u8 led_index, u16 led0_bright, u16 led1_bright,
|
||||
u32 period, u32 start_light_time, u32 light_time);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: 自定义设置单灯双闪状态
|
||||
//@input:
|
||||
// led_index: 0: led0, 1:led1, 3:led0 & led1(互闪)
|
||||
// led0_bright, LED0亮度: 0 ~ 500
|
||||
// led1_bright, LED1亮度: 0 ~ 500
|
||||
// period: 闪灯周期(ms), 多少ms闪一下
|
||||
// first_light_time: 第一次亮灯持续时间,
|
||||
// second_light_time: 第二次亮灯持续时间,
|
||||
// gap_time: 两次亮灯时间间隔,
|
||||
//@return: void
|
||||
//@note:
|
||||
//=================================================================================//
|
||||
void pwm_led_double_flash_display(u8 led_index, u16 led0_bright, u16 led1_bright,
|
||||
u32 period, u32 first_light_time, u32 gap_time, u32 second_light_time);
|
||||
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: 自定义设置呼吸模式
|
||||
//@input:
|
||||
// led_index: 0: led0, 1:led1, 2:led0 & led1(交互呼吸)
|
||||
// breathe_time: 呼吸周期(灭->最亮->灭), 设置范围: 500ms以上;
|
||||
// led0_bright: led0呼吸到最亮的亮度(0 ~ 500);
|
||||
// led1_bright: led1呼吸到最亮的亮度(0 ~ 500);
|
||||
// led0_light_delay_time: led0最高亮度延时(0 ~ 100ms);
|
||||
// led1_light_delay_time: led1最高亮度延时(0 ~ 100ms);
|
||||
// led_blink_delay_time: led0和led1灭灯延时(0 ~ 20000ms), 0 ~ 20S;
|
||||
//@return: void
|
||||
//@note:
|
||||
//=================================================================================//
|
||||
void pwm_led_breathe_display(u8 led_index, u16 breathe_time, u16 led0_bright, u16 led1_bright,
|
||||
u32 led0_light_delay_time, u32 led1_light_delay_time, u32 led_blink_delay_time);
|
||||
|
||||
//=================================================================================//
|
||||
//@brief: 注册LED周期中断函数, 每个LED周期结束后会调用一次, 可以统计指定状态闪烁多少次
|
||||
//@input:
|
||||
//@return: void
|
||||
//@note:
|
||||
//=================================================================================//
|
||||
void pwm_led_register_irq(void (*func)(void));
|
||||
|
||||
void led_module_enter_sniff_mode();
|
||||
void led_module_exit_sniff_mode();
|
||||
|
||||
#endif //_PWM_LED_H_
|
||||
|
||||
|
||||
37
include_lib/driver/cpu/br28/asm/rdec.h
Normal file
37
include_lib/driver/cpu/br28/asm/rdec.h
Normal file
@ -0,0 +1,37 @@
|
||||
#ifndef _RDEC_H_
|
||||
#define _RDEC_H_
|
||||
|
||||
#define DEVICE_EVENT_FROM_RDEC (('R' << 24) | ('D' << 16) | ('E' << 8) | '\0')
|
||||
|
||||
enum rdec_index {
|
||||
RDEC0,
|
||||
RDEC1,
|
||||
RDEC2,
|
||||
};
|
||||
|
||||
struct rdec_device {
|
||||
enum rdec_index index;
|
||||
u8 sin_port0; //采样信号端口0
|
||||
u8 sin_port1; //采样信号端口1
|
||||
u8 key_value0; //键值1
|
||||
u8 key_value1; //键值2
|
||||
};
|
||||
|
||||
struct rdec_platform_data {
|
||||
u8 enable;
|
||||
u8 num; //rdec数量
|
||||
const struct rdec_device *rdec;
|
||||
};
|
||||
|
||||
#define RDEC_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct rdec_platform_data data = {
|
||||
|
||||
#define RDEC_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
/*********************** rdec 初始化 ******************************/
|
||||
int rdec_init(const struct rdec_platform_data *user_data);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
39
include_lib/driver/cpu/br28/asm/rtc.h
Normal file
39
include_lib/driver/cpu/br28/asm/rtc.h
Normal file
@ -0,0 +1,39 @@
|
||||
|
||||
#ifndef __RTC_H__
|
||||
#define __RTC_H__
|
||||
|
||||
#include "typedef.h"
|
||||
#include "system/sys_time.h"
|
||||
|
||||
|
||||
struct rtc_dev_platform_data {
|
||||
const struct sys_time *default_sys_time;
|
||||
const struct sys_time *default_alarm;
|
||||
void (*cbfun)(u8);
|
||||
u8 clk_sel;
|
||||
u8 x32xs;
|
||||
};
|
||||
|
||||
#define RTC_DEV_PLATFORM_DATA_BEGIN(data) \
|
||||
const struct rtc_dev_platform_data data = {
|
||||
|
||||
#define RTC_DEV_PLATFORM_DATA_END() \
|
||||
.x32xs = 0, \
|
||||
};
|
||||
|
||||
extern const struct device_operations rtc_dev_ops;
|
||||
|
||||
int rtc_init(const struct rtc_dev_platform_data *arg);
|
||||
int rtc_ioctl(u32 cmd, u32 arg);
|
||||
void set_alarm_ctrl(u8 set_alarm);
|
||||
void write_sys_time(struct sys_time *curr_time);
|
||||
void read_sys_time(struct sys_time *curr_time);
|
||||
void write_alarm(struct sys_time *alarm_time);
|
||||
void read_alarm(struct sys_time *alarm_time);
|
||||
|
||||
u16 month_to_day(u16 year, u8 month);
|
||||
void day_to_ymd(u16 day, struct sys_time *sys_time);
|
||||
u16 ymd_to_day(struct sys_time *time);
|
||||
u8 caculate_weekday_by_time(struct sys_time *r_time);
|
||||
|
||||
#endif // __RTC_API_H__
|
||||
50
include_lib/driver/cpu/br28/asm/sdmmc.h
Normal file
50
include_lib/driver/cpu/br28/asm/sdmmc.h
Normal file
@ -0,0 +1,50 @@
|
||||
#ifndef ARCH_SDMMC_H
|
||||
#define ARCH_SDMMC_H
|
||||
|
||||
|
||||
#include "device/sdmmc.h"
|
||||
|
||||
struct sdmmc_platform_data {
|
||||
char port[6];
|
||||
u8 irq;
|
||||
u8 data_width;
|
||||
u8 priority;
|
||||
u8 detect_mode;
|
||||
u8 detect_io;
|
||||
u8 detect_io_level;
|
||||
u8 detect_time_interval;
|
||||
u32 detect_timeout;
|
||||
u32 speed;
|
||||
volatile u16 *sfr;
|
||||
int (*detect_func)(const struct sdmmc_platform_data *);
|
||||
void (*port_init)(const struct sdmmc_platform_data *, int mode);
|
||||
void (*power)(int on);
|
||||
};
|
||||
|
||||
#define SD0_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct sdmmc_platform_data data = {
|
||||
|
||||
|
||||
#define SD0_PLATFORM_DATA_END() \
|
||||
.irq = IRQ_SD0_IDX, \
|
||||
.sfr = (volatile u16 *)JL_SD0, \
|
||||
.port_init = sdmmc_0_port_init, \
|
||||
.detect_time_interval = 250, \
|
||||
.detect_timeout = 1000, \
|
||||
};
|
||||
|
||||
extern const struct device_operations sd_dev_ops;
|
||||
|
||||
extern void sdmmc_0_port_init(const struct sdmmc_platform_data *, int mode);
|
||||
|
||||
extern int sdmmc_0_clk_detect(const struct sdmmc_platform_data *);
|
||||
extern int sdmmc_0_io_detect(const struct sdmmc_platform_data *);
|
||||
extern int sdmmc_0_cmd_detect(const struct sdmmc_platform_data *);
|
||||
extern int sdmmc_cmd_detect(const struct sdmmc_platform_data *data);
|
||||
|
||||
extern void sd_set_power(u8 enable);
|
||||
|
||||
|
||||
extern const struct device_operations sd_dev_ops;
|
||||
#endif
|
||||
|
||||
13
include_lib/driver/cpu/br28/asm/sfc_norflash_api.h
Normal file
13
include_lib/driver/cpu/br28/asm/sfc_norflash_api.h
Normal file
@ -0,0 +1,13 @@
|
||||
#ifndef __SFC_NORFLASH_API_H__
|
||||
#define __SFC_NORFLASH_API_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
int norflash_init(const struct dev_node *node, void *arg);
|
||||
int norflash_open(const char *name, struct device **device, void *arg);
|
||||
int norflash_read(struct device *device, void *buf, u32 len, u32 offset);
|
||||
int norflash_write(struct device *device, void *buf, u32 len, u32 offset);
|
||||
int norflash_ioctl(struct device *device, u32 cmd, u32 arg);
|
||||
|
||||
|
||||
#endif
|
||||
47
include_lib/driver/cpu/br28/asm/sfc_spi.h
Normal file
47
include_lib/driver/cpu/br28/asm/sfc_spi.h
Normal file
@ -0,0 +1,47 @@
|
||||
#ifndef _SFC1_INTERFACE_H_
|
||||
#define _SFC1_INTERFACE_H_
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
enum SFC_DATA_WIDTH {
|
||||
SFC_DATA_WIDTH_2 = 2,
|
||||
SFC_DATA_WIDTH_4 = 4,
|
||||
};
|
||||
|
||||
enum SFC_READ_MODE {
|
||||
SFC_RD_OUTPUT = 0,
|
||||
SFC_RD_IO,
|
||||
SFC_RD_IO_CONTINUE,
|
||||
};
|
||||
|
||||
struct sfc_spi_platform_data {
|
||||
u8 spi_hw_index;
|
||||
enum SFC_DATA_WIDTH sfc_data_width;
|
||||
enum SFC_READ_MODE sfc_read_mode;
|
||||
u8 sfc_encry; //是否加密
|
||||
u16 sfc_clk_div; //时钟分频: sfc_fre = sys_clk / div;
|
||||
u32 unencry_start_addr; //不加密起始地址
|
||||
u32 unencry_size; //不加密大小
|
||||
};
|
||||
|
||||
#define SFC_SPI_PLATFORM_DATA_BEGIN(data) \
|
||||
const struct sfc_spi_platform_data data = {
|
||||
|
||||
#define SFC_SPI_PLATFORM_DATA_END() \
|
||||
};
|
||||
|
||||
|
||||
//sfc1 API:
|
||||
int sfc_spi_init(struct sfc_spi_platform_data *sfc_spi_data);
|
||||
int sfc_spi_open(void *sfc_spi_data);
|
||||
int sfc_spi_close(void);
|
||||
u32 sfc_spi_read_id(void);
|
||||
int sfc_spi_read(u32 addr, void *buf, u32 len);
|
||||
int sfc_spi_write_pages(u32 addr, void *buf, u32 len);
|
||||
int sfc_spi_eraser(u32 cmd, u32 addr);
|
||||
u32 sfc1_flash_addr2cpu_addr(u32 offset);
|
||||
u32 sfc1_cpu_addr2flash_addr(u32 offset);
|
||||
|
||||
void sfc_suspend(u32 enable_spi);
|
||||
void sfc1_suspend();
|
||||
#endif /* #ifndef _SFC1_INTERFACE_H_ */
|
||||
77
include_lib/driver/cpu/br28/asm/spi.h
Normal file
77
include_lib/driver/cpu/br28/asm/spi.h
Normal file
@ -0,0 +1,77 @@
|
||||
#ifndef _SPI_INTERFACE_H_
|
||||
#define _SPI_INTERFACE_H_
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
|
||||
/*enum spi_mode {
|
||||
SPI_2WIRE_MODE,
|
||||
SPI_ODD_MODE,
|
||||
SPI_DUAL_MODE,
|
||||
SPI_QUAD_MODE,
|
||||
};*/
|
||||
enum spi_mode {
|
||||
SPI_MODE_BIDIR_1BIT, //支持SPIx(x=0,1,2)，全双工，di接收，do发送
|
||||
SPI_MODE_UNIDIR_1BIT, //支持SPIx(x=0,1,2)，半双工，do分时发送/接收
|
||||
SPI_MODE_UNIDIR_2BIT, //支持SPIx(x=0)，半双工，di & do共2bit分时发送/接收
|
||||
SPI_MODE_UNIDIR_4BIT, //支持SPIx(x=0)，半双工，di & do & wp & hold 共4bit分时发送/接收
|
||||
};
|
||||
|
||||
enum {
|
||||
SPI0,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI_MAX_HW_NUM,
|
||||
};
|
||||
|
||||
#define SPI_MAX_IO_GROUP 2
|
||||
|
||||
struct spi_io {
|
||||
u8 cs_pin;
|
||||
u8 di_pin;
|
||||
u8 do_pin;
|
||||
u8 clk_pin;
|
||||
u8 d2_pin;
|
||||
u8 d3_pin;
|
||||
};
|
||||
|
||||
struct spi_io_mapping {
|
||||
u32 num; //可选端口数量
|
||||
struct spi_io io[SPI_MAX_IO_GROUP];
|
||||
};
|
||||
|
||||
enum spi_role {
|
||||
SPI_ROLE_MASTER,
|
||||
SPI_ROLE_SLAVE,
|
||||
};
|
||||
|
||||
struct spi_platform_data {
|
||||
u8 port[5];//CLK, DO, DI D2(wp) D3(hold)
|
||||
u8 mode; //模式，选项为enum spi_mode中的枚举常量
|
||||
u8 role; //角色，选项为enum spi_role中的枚举常量
|
||||
u32 clk; //波特率
|
||||
};
|
||||
|
||||
extern const struct spi_platform_data spi1_p_data;
|
||||
extern const struct spi_platform_data spi2_p_data;
|
||||
|
||||
typedef const int spi_dev;
|
||||
|
||||
int spi_open(spi_dev spi);
|
||||
int spi_dma_recv(spi_dev spi, void *buf, u32 len);
|
||||
int spi_dma_send(spi_dev spi, const void *buf, u32 len);
|
||||
void spi_dma_set_addr_for_isr(spi_dev spi, void *buf, u32 len, u8 rw);
|
||||
void spi_set_ie(spi_dev spi, u8 en);
|
||||
u8 spi_get_pending(spi_dev spi);
|
||||
void spi_clear_pending(spi_dev spi);
|
||||
void spi_set_bit_mode(spi_dev spi, int mode);
|
||||
u8 spi_recv_byte(spi_dev spi, int *err);
|
||||
u8 spi_recv_byte_for_isr(spi_dev spi);
|
||||
int spi_send_byte(spi_dev spi, u8 byte);
|
||||
void spi_send_byte_for_isr(spi_dev spi, u8 byte);
|
||||
u8 spi_send_recv_byte(spi_dev spi, u8 byte, int *err);
|
||||
int spi_set_baud(spi_dev spi, u32 baud);
|
||||
u32 spi_get_baud(spi_dev spi);
|
||||
void spi_close(spi_dev spi);
|
||||
|
||||
#endif
|
||||
29
include_lib/driver/cpu/br28/asm/spiflash.h
Normal file
29
include_lib/driver/cpu/br28/asm/spiflash.h
Normal file
@ -0,0 +1,29 @@
|
||||
#ifndef ASM_SPIFLASH_H
|
||||
#define ASM_SPIFLASH_H
|
||||
|
||||
|
||||
|
||||
#include "device/device.h"
|
||||
#include "device/spiflash.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern const struct device_operations spiflash_dev_ops;
|
||||
extern const struct device_operations sfcflash_dev_ops;
|
||||
extern const struct device_operations sdfile_dev_ops;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
12
include_lib/driver/cpu/br28/asm/timer.h
Normal file
12
include_lib/driver/cpu/br28/asm/timer.h
Normal file
@ -0,0 +1,12 @@
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
void udelay(u32 us);
|
||||
void mdelay(u32 us);
|
||||
void delay_2ms(int cnt);
|
||||
u32 timer_get_sec(void);
|
||||
u32 timer_get_ms(void);
|
||||
|
||||
#endif
|
||||
56
include_lib/driver/cpu/br28/asm/uart.h
Normal file
56
include_lib/driver/cpu/br28/asm/uart.h
Normal file
@ -0,0 +1,56 @@
|
||||
#ifndef ASM_UART_H
|
||||
#define ASM_UART_H
|
||||
|
||||
|
||||
#define UART_NUM 3
|
||||
#define UART_OUTPORT_NUM 4
|
||||
|
||||
|
||||
#include "device/uart.h"
|
||||
#include "device/device.h"
|
||||
|
||||
#define UART0_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct uart_platform_data data = {
|
||||
|
||||
|
||||
#define UART0_PLATFORM_DATA_END() \
|
||||
.irq = IRQ_UART0_IDX, \
|
||||
};
|
||||
|
||||
|
||||
#define UART1_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct uart_platform_data data = {
|
||||
|
||||
|
||||
#define UART1_PLATFORM_DATA_END() \
|
||||
.irq = IRQ_UART1_IDX, \
|
||||
};
|
||||
|
||||
|
||||
#define UART2_PLATFORM_DATA_BEGIN(data) \
|
||||
static const struct uart_platform_data data = {
|
||||
|
||||
#define UART2_PLATFORM_DATA_END() \
|
||||
.irq = IRQ_UART2_IDX, \
|
||||
};
|
||||
|
||||
|
||||
// #define UART3_PLATFORM_DATA_BEGIN(data) \
|
||||
// static const struct uart_platform_data data = {
|
||||
|
||||
// #define UART3_PLATFORM_DATA_END() \
|
||||
// .irq = UART3_INT, \
|
||||
// };
|
||||
|
||||
|
||||
|
||||
|
||||
extern const struct device_operations uart_dev_ops;
|
||||
|
||||
|
||||
extern int uart_init(const struct uart_platform_data *);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
176
include_lib/driver/cpu/br28/asm/uart_dev.h
Normal file
176
include_lib/driver/cpu/br28/asm/uart_dev.h
Normal file
@ -0,0 +1,176 @@
|
||||
#ifndef _UART_DEV_H_
|
||||
#define _UART_DEV_H_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "os/os_api.h"
|
||||
#include "jiffies.h"
|
||||
#include "irq.h"
|
||||
/* #include "jtime.h" */
|
||||
|
||||
#define CONFIG_ENABLE_UART_SEM 1
|
||||
#define SET_INTERRUPT ___interrupt
|
||||
#define irq_disable(x) bit_clr_ie(x)
|
||||
#define irq_enable(x) bit_set_ie(x)
|
||||
|
||||
#ifndef time_after
|
||||
#define time_after(a,b) (((long)(b) - (long)(a)) < 0)
|
||||
#endif
|
||||
|
||||
#ifndef time_before
|
||||
#define time_before(a,b) time_after(b,a)
|
||||
#endif
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
static inline u32 ut_get_jiffies(void)
|
||||
{
|
||||
#if 1
|
||||
return jiffies;
|
||||
#endif
|
||||
#if 0
|
||||
return Jtime_updata_jiffies();
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline u32 ut_msecs_to_jiffies(u32 msecs)
|
||||
{
|
||||
if (msecs >= 10) {
|
||||
msecs /= 10;
|
||||
} else if (msecs) {
|
||||
msecs = 1;
|
||||
}
|
||||
return msecs;
|
||||
}
|
||||
|
||||
#if CONFIG_ENABLE_UART_SEM
|
||||
typedef OS_SEM UT_Semaphore ;
|
||||
static inline void UT_OSSemCreate(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
os_sem_create(sem, count);
|
||||
}
|
||||
static inline void UT_OSSemPost(UT_Semaphore *sem)
|
||||
{
|
||||
os_sem_post(sem);
|
||||
}
|
||||
static inline u32 UT_OSSemPend(UT_Semaphore *sem, u32 timeout)
|
||||
{
|
||||
return os_sem_pend(sem, timeout);
|
||||
}
|
||||
static inline void UT_OSSemSet(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
os_sem_set(sem, count);
|
||||
}
|
||||
static inline void UT_OSSemClose(UT_Semaphore *sem)
|
||||
{
|
||||
|
||||
}
|
||||
static inline void ut_sleep()
|
||||
{
|
||||
os_time_dly(1);
|
||||
}
|
||||
|
||||
#else
|
||||
typedef volatile u32 UT_Semaphore;
|
||||
static inline void UT_OSSemCreate(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
*sem = count;
|
||||
}
|
||||
static inline void UT_OSSemPost(UT_Semaphore *sem)
|
||||
{
|
||||
(*sem)++;
|
||||
}
|
||||
static inline u32 UT_OSSemPend(UT_Semaphore *sem, u32 timeout)
|
||||
{
|
||||
u32 _timeout = timeout + ut_get_jiffies();
|
||||
extern void clr_wdt();
|
||||
while (1) {
|
||||
if (*sem) {
|
||||
(*sem) --;
|
||||
break;
|
||||
}
|
||||
if ((timeout != 0) && time_before(_timeout, ut_get_jiffies())) {
|
||||
return -1;
|
||||
}
|
||||
clr_wdt();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
static inline void UT_OSSemSet(UT_Semaphore *sem, u32 count)
|
||||
{
|
||||
*sem = count;
|
||||
}
|
||||
static inline void UT_OSSemClose(UT_Semaphore *sem)
|
||||
{
|
||||
|
||||
}
|
||||
static inline void ut_sleep()
|
||||
{
|
||||
extern void clr_wdt();
|
||||
clr_wdt();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
typedef void (*ut_isr_cbfun)(void *ut_bus, u32 status);
|
||||
struct uart_platform_data_t {
|
||||
u8 tx_pin; ///< 作为发送引脚的引脚号，可从参考gpio.h枚举中选，当引脚为空时，则填 -1
|
||||
u8 rx_pin; ///< 作为接收引脚的引脚号，可从参考gpio.h枚举中选，当引脚为空时，则填 -1
|
||||
void *rx_cbuf; ///< 如果使用中断DMA接收，则写入循环buf的首地址，ut中断使能；如果不使用，则写入NULL，无中断
|
||||
u32 rx_cbuf_size; ///< 循环buf的大小,必须为2的多少几次幂，如果不用循环buf，该值无效，可写NULL
|
||||
u32 frame_length; ///< 产生RT中断的字节数，如无中断，该值无效
|
||||
u32 rx_timeout; ///< 产生OT中断的时间值，单位ms，如无中断，该值无效
|
||||
ut_isr_cbfun isr_cbfun; ///< ut中断的回调函数句柄，不用回调函数则写入NULL，如无中断，句柄无效
|
||||
void *argv; ///< ut中断的回调函数的一个扩展形参，可供用户设定，如无回调函数，此参数无效
|
||||
u32 is_9bit: 1; ///< ut九位模式使能位，0：关闭；1：使能
|
||||
u32 baud: 24; ///< ut的波特率
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief 循环buf结构体类型定义
|
||||
*/
|
||||
typedef struct {
|
||||
u8 *buffer; ///<循环buf的首地址
|
||||
u32 buf_size; ///<循环buf的大小
|
||||
u32 buf_in; ///<循环buf的写偏移量
|
||||
u32 buf_out; ///<循环buf的读偏移量
|
||||
} KFIFO;
|
||||
|
||||
enum {
|
||||
UT_TX = 1,
|
||||
UT_RX,
|
||||
UT_RX_OT
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief ut初始化函数的返回结构体，含各函数指针，供外部使用
|
||||
*/
|
||||
typedef struct {
|
||||
ut_isr_cbfun isr_cbfun; ///< ut中断的回调函数句柄，不用回调函数则写入NULL，如无中断，句柄无效
|
||||
void *argv; ///< ut中断的回调函数的一个扩展形参,在此返回
|
||||
void (*putbyte)(char a); ///< ut发送一个byte
|
||||
u8(*getbyte)(u8 *buf, u32 timeout); ///< ut接收一个byte，buf：字节存放地址；timeout：超时时间，单位ms；返回0：失败；返回1：成功
|
||||
u32(*read)(u8 *inbuf, u32 len, u32 timeout); ///< ut接收一个字符串，inbuf：字符串存放首地址；len：预接收长度；timeout：超时时间，单位ms；返回实际接收的长度
|
||||
void (*write)(const u8 *outbuf, u32 len); ///< ut发送一个字符串，outbuf：字符串首地址；len：发送的字符串长度；
|
||||
void (*set_baud)(u32 baud); ///< ut设置波特率，baud：波特率值
|
||||
u32 frame_length;
|
||||
u32 rx_timeout;
|
||||
KFIFO kfifo; ///< ut用的循环buf结构体的指针
|
||||
UT_Semaphore sem_rx;
|
||||
UT_Semaphore sem_tx;
|
||||
u32(*get_data_len)(void);
|
||||
} uart_bus_t;
|
||||
|
||||
|
||||
const uart_bus_t *uart_dev_open(const struct uart_platform_data_t *arg);
|
||||
u32 uart_dev_close(uart_bus_t *ut);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
#endif
|
||||
|
||||
|
||||
19
include_lib/driver/cpu/br28/asm/umidigi_chargestore.h
Normal file
19
include_lib/driver/cpu/br28/asm/umidigi_chargestore.h
Normal file
@ -0,0 +1,19 @@
|
||||
#ifndef _UIMIDIGI_
|
||||
#define _UIMIDIGI_
|
||||
|
||||
#include "typedef.h"
|
||||
#include "system/event.h"
|
||||
|
||||
void ldo_port_wakeup_to_cmessage(void);
|
||||
void umidigi_chargestore_message_callback(void (*app_umidigi_chargetore_message_deal)(u16 message));
|
||||
|
||||
/*
|
||||
* 收集数据定时器采集周期根据充电舱发送波形设置
|
||||
* 充电舱发送波形有40ms/bit和20ms/bit两种
|
||||
*
|
||||
* #define _20MS_BIT 21
|
||||
* #define _40MS_BIT 41
|
||||
* #define TIMER2CMESSAGE _20MS_BIT
|
||||
*/
|
||||
|
||||
#endif
|
||||
185
include_lib/driver/cpu/br28/asm/usb.h
Normal file
185
include_lib/driver/cpu/br28/asm/usb.h
Normal file
@ -0,0 +1,185 @@
|
||||
#ifndef _USB_H_
|
||||
#define _USB_H_
|
||||
#include "typedef.h"
|
||||
#include "generic/ioctl.h"
|
||||
|
||||
|
||||
#ifndef min
|
||||
#define min(a,b) ((a)<(b) ? (a) : (b))
|
||||
#endif
|
||||
#ifndef USB_DIR_OUT
|
||||
#define USB_DIR_OUT 0 /* to device */
|
||||
#endif
|
||||
#ifndef USB_DIR_IN
|
||||
#define USB_DIR_IN 0x80 /* to host */
|
||||
#endif
|
||||
|
||||
#define FUSB_MODE 1
|
||||
#define EP0_SETUP_LEN 0x40
|
||||
#define USB_MAX_HW_EPNUM 5
|
||||
|
||||
/* #define ep_regs JL_USB_EP_TypeDef */
|
||||
typedef struct {
|
||||
volatile u32 TXMAXP;
|
||||
volatile u32 TXCSR1;
|
||||
volatile u32 TXCSR2;
|
||||
volatile u32 RXMAXP;
|
||||
volatile u32 RXCSR1;
|
||||
volatile u32 RXCSR2;
|
||||
volatile const u32 RXCOUNT1;
|
||||
volatile const u32 RXCOUNT2;
|
||||
volatile u32 TXTYPE;
|
||||
volatile u32 TXINTERVAL;
|
||||
volatile u32 RXTYPE;
|
||||
volatile u32 RXINTERVAL;
|
||||
u32 RESERVED[0xd0 / 4];
|
||||
} ep_regs;
|
||||
|
||||
|
||||
|
||||
#define PHY_ON 0
|
||||
#define LOW_SPEED 1
|
||||
#define USB_NRST 2
|
||||
#define TM1 3
|
||||
#define CID 4
|
||||
#define VBUS 5
|
||||
#define USB_TEST 6
|
||||
#define PDCHKDP 9
|
||||
#define SOFIE 10
|
||||
#define SIEIE 11
|
||||
#define CLR_SOF_PND 12
|
||||
#define SOF_PND 13
|
||||
#define SIE_PND 14
|
||||
#define CHKDPO 15
|
||||
#define DM_SE 16
|
||||
#define DP_SE 17
|
||||
|
||||
#define MC_RNW 14
|
||||
#define MACK 15
|
||||
|
||||
#define DPOUT 0
|
||||
#define DMOUT 1
|
||||
#define DPIE 2
|
||||
#define DMIE 3
|
||||
#define DPPU 4
|
||||
#define DMPU 5
|
||||
#define DPPD 6
|
||||
#define DMPD 7
|
||||
#define DPDIE 8
|
||||
#define DMDIE 9
|
||||
#define DPDIEH 10
|
||||
#define DMDIEH 11
|
||||
#define IO_MODE 12
|
||||
#define SR 13
|
||||
#define IO_PU_MODE 14
|
||||
|
||||
|
||||
|
||||
enum {
|
||||
USB0,
|
||||
};
|
||||
#define USB_MAX_HW_NUM 1
|
||||
|
||||
|
||||
struct usb_ep_addr_t {
|
||||
u32 ep0_addr;
|
||||
u32 ep_usage;
|
||||
const u8 *ep_taddr[4];
|
||||
const u8 *ep_dual_taddr[4];
|
||||
u8 *ep_raddr[4];
|
||||
u8 *ep_dual_raddr[4];
|
||||
u32 ep_tsize[4];
|
||||
u32 ep_rsize[4];
|
||||
} __attribute__((aligned(4)));
|
||||
|
||||
|
||||
typedef u8 usb_dev;
|
||||
|
||||
u16 usb_read_sofframe(const usb_dev id);
|
||||
u32 usb_dev_con0(const usb_dev usb_id);
|
||||
void usb_sie_enable(const usb_dev usb_id);
|
||||
void usb_sie_disable(const usb_dev id);
|
||||
void usb_write_ep_cnt(const usb_dev usb_id, u32 ep, u32 len);
|
||||
u32 usb_g_dev_status(const usb_dev usb_id);
|
||||
u32 usb_h_dev_status(const usb_dev usb_id);
|
||||
void usb_set_low_speed(const usb_dev usb_id, u8 flag);
|
||||
void usb_write_ep0(const usb_dev usb_id, const u8 *ptr, u32 len);
|
||||
void usb_read_ep0(const usb_dev usb_id, u8 *ptr, u32 len);
|
||||
void *usb_get_dma_taddr(const usb_dev usb_id, u32 ep);
|
||||
u32 usb_get_dma_size(const usb_dev usb_id, u32 ep);
|
||||
void usb_set_dma_tsize(const usb_dev usb_id, u32 ep, u32 size);
|
||||
void usb_set_dma_rsize(const usb_dev usb_id, u32 ep, u32 size);
|
||||
void usb_set_dma_taddr(const usb_dev usb_id, u32 ep, const void *ptr);
|
||||
void *usb_get_dma_raddr(const usb_dev usb_id, u32 ep);
|
||||
void usb_set_dma_raddr(const usb_dev usb_id, u32 ep, void *ptr);
|
||||
void usb_set_dma_dual_raddr(const usb_dev usb_id, u32 ep, void *ptr);
|
||||
void musb_write_index(const usb_dev usb_id, u32 endpoint);
|
||||
void usb_write_power(const usb_dev usb_id, u32 value);
|
||||
u32 usb_read_power(const usb_dev usb_id);
|
||||
u32 usb_read_devctl(const usb_dev usb_id);
|
||||
void usb_write_devctl(const usb_dev usb_id, u32 value);
|
||||
u32 usb_read_csr0(const usb_dev usb_id);
|
||||
void usb_write_csr0(const usb_dev usb_id, u32 csr0);
|
||||
void usb_ep0_ClrRxPktRdy(const usb_dev usb_id);
|
||||
void usb_ep0_TxPktEnd(const usb_dev usb_id);
|
||||
void usb_ep0_RxPktEnd(const usb_dev usb_id);
|
||||
void usb_ep0_Set_Stall(const usb_dev usb_id);
|
||||
u32 usb_read_count0(const usb_dev usb_id);
|
||||
void usb_read_intre(const usb_dev usb_id,
|
||||
u32 *const intr_usbe,
|
||||
u32 *const intr_txe,
|
||||
u32 *const intr_rxe);
|
||||
|
||||
void usb_read_intr(const usb_dev usb_id,
|
||||
u32 *const intr_usb,
|
||||
u32 *const intr_tx,
|
||||
u32 *const intr_rx);
|
||||
void usb_write_intr_usbe(const usb_dev usb_id, u32 intr_usbe);
|
||||
void usb_set_intr_txe(const usb_dev usb_id, const u32 ep);
|
||||
void usb_clr_intr_txe(const usb_dev usb_id, const u32 ep);
|
||||
void usb_set_intr_rxe(const usb_dev usb_id, const u32 ep);
|
||||
void usb_clr_intr_rxe(const usb_dev usb_id, const u32 ep);
|
||||
void usb_write_faddr(const usb_dev usb_id, u32 addr);
|
||||
void usb_write_txcsr(const usb_dev usb_id, const u32 ep, u32 txcsr);
|
||||
u32 usb_read_txcsr(const usb_dev usb_id, const u32 ep);
|
||||
void usb_write_rxcsr(const usb_dev usb_id, const u32 ep, u32 rxcsr);
|
||||
u32 usb_read_rxcsr(const usb_dev usb_id, const u32 ep);
|
||||
void usb_write_rxmaxp(const usb_dev usb_id, const u32 ep, u32 value);
|
||||
void usb_write_txmaxp(const usb_dev usb_id, const u32 ep, u32 value);
|
||||
void usb_write_rxtype(const usb_dev usb_id, const u32 ep, u32 value);
|
||||
void usb_write_txtype(const usb_dev usb_id, const u32 ep, u32 value);
|
||||
u32 usb_read_rxcount(const usb_dev usb_id, u32 ep);
|
||||
u32 usb_g_ep_config(const usb_dev usb_id, const u32 ep, u32 type, u32 ie, u8 *ptr, u32 dma_size);
|
||||
u32 usb_g_ep_read64byte_fast(const usb_dev usb_id, const u32 ep, u8 *ptr, u32 len);
|
||||
u32 usb_g_ep_read(const usb_dev usb_id, const u32 ep, u8 *ptr, u32 len, u32 block);
|
||||
u32 usb_g_ep_write(const usb_dev usb_id, u32 ep, const u8 *ptr, u32 len);
|
||||
u32 usb_g_ep_config(const usb_dev usb_id, u32 ep, u32 type, u32 ie, u8 *ptr, u32 dma_size);
|
||||
void usb_g_sie_init(const usb_dev usb_id);
|
||||
void usb_g_hold(const usb_dev usb_id);
|
||||
u32 usb_get_ep_num(const usb_dev usb_id, u32 ep_dir, u32 type);
|
||||
u32 usb_h_ep_config(const usb_dev usb_id, u32 ep, u32 type, u32 ie, u32 interval, u8 *ptr, u32 dma_size);
|
||||
void usb_mdelay(unsigned int ms);
|
||||
u32 usb_h_ep_write(const usb_dev usb_id, u8 host_ep, u16 txmaxp, u8 target_ep, const u8 *ptr, u32 len, u32 xfer);
|
||||
int usb_h_ep_write_async(const usb_dev id, u8 host_ep, u16 txmaxp, u8 target_ep, const u8 *ptr, u32 len, u32 xfer, u32 kstart);
|
||||
u32 usb_h_ep_read(const usb_dev usb_id, u8 host_ep, u16 rxmaxp, u8 target_ep, u8 *ptr, u32 len, u32 xfer);
|
||||
int usb_h_ep_read_async(const usb_dev id, u8 host_ep, u8 target_ep, u8 *ptr, u32 len, u32 xfer, u32 kstart);
|
||||
void usb_h_sie_init(const usb_dev usb_id);
|
||||
void usb_h_sie_close(const usb_dev usb_id);
|
||||
u32 usb_h_chirp_and_reset(const usb_dev id, u32 reset_delay, u32 timeout);
|
||||
void usb_h_sie_reset(const usb_dev usb_id);
|
||||
void usb_hotplug_disable(const usb_dev usb_id);
|
||||
void usb_hotplug_enable(const usb_dev usb_id, u32 mode);
|
||||
void usb_sie_close(const usb_dev usb_id);
|
||||
void usb_sie_close_all(void);
|
||||
void usb_var_init(const usb_dev usb_id, void *ptr);
|
||||
void usb_var_release(const usb_dev usb_id);
|
||||
void usb_enable_ep(const usb_dev usb_id, u32 eps);
|
||||
void usb_disable_ep(const usb_dev usb_id, u32 eps);
|
||||
u32 usb_get_ep_status(const usb_dev usb_id, u32 epx);
|
||||
|
||||
void usb_sofie_enable(const usb_dev id);
|
||||
void usb_sofie_disable(const usb_dev id);
|
||||
void usb_sof_clr_pnd(const usb_dev id);
|
||||
void usb_ep0_Set_ignore(const usb_dev id, u32 addr);
|
||||
void usb_recover_io_status(const usb_dev id);
|
||||
#endif
|
||||
32
include_lib/driver/cpu/br28/asm/wdt.h
Normal file
32
include_lib/driver/cpu/br28/asm/wdt.h
Normal file
@ -0,0 +1,32 @@
|
||||
#ifndef __BR22_WDT_H__
|
||||
#define __BR22_WDT_H__
|
||||
|
||||
#define WDT_1MS 0x00
|
||||
#define WDT_2MS 0x01
|
||||
#define WDT_4MS 0x02
|
||||
#define WDT_8MS 0x03
|
||||
#define WDT_16MS 0x04
|
||||
#define WDT_32MS 0x05
|
||||
#define WDT_64MS 0x06
|
||||
#define WDT_128MS 0x07
|
||||
#define WDT_256MS 0x08
|
||||
#define WDT_512MS 0x09
|
||||
#define WDT_1S 0x0A
|
||||
#define WDT_2S 0x0B
|
||||
#define WDT_4S 0x0C
|
||||
#define WDT_8S 0x0D
|
||||
#define WDT_16S 0x0E
|
||||
#define WDT_32S 0x0F
|
||||
#define WDT_64S 0x10
|
||||
#define WDT_128S 0x11
|
||||
|
||||
void wdt_init(u8 time);
|
||||
void wdt_close(void);
|
||||
void wdt_clear(void);
|
||||
|
||||
void wdt_enable(void);
|
||||
void wdt_disable(void);
|
||||
|
||||
u32 wdt_get_time(void);//ms
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user